MC10EP195, MC100EP195 3.3V ECL Programmable Delay Chip The MC10/100EP195 is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. http://onsemi.com The delay section consists of a programmable matrix of gates and multiplexers as shown in the logic diagram, Figure 2. The delay increment of the EP195 has a digitally selectable resolution of about MARKING DIAGRAM* 10 ps and a net range of up to 10.2 ns. The required delay is selected by the 10 data select inputs D[9:0] values and controlled by the LEN (pin 10). A LOW level on LEN allows a transparent LOAD mode of MCXXX real time delay values by D[9:0]. A LOW to HIGH transition on LEN EP195 will LOCK and HOLD current values present against any subsequent AWLYYWW changes in D[10:0]. The approximate delay values for varying tap 32 LQFP−32 numbers correlating to D0 (LSB) through D9 (MSB) are shown in FA SUFFIX Table 6 and Figure 3. 1 CASE 873A Because the EP195 is designed using a chain of multiplexers it has a fixed minimum delay of 2.2 ns. An additional pin D10 is provided for controlling Pins 14 and 15, CASCADE and CASCADE, also latched XXX = 10 or 100 by LEN, in cascading multiple PDCs for increased programmable A = Assembly Location WL = Wafer Lot range. The cascade logic allows full control of multiple PDCs. YY = Year Switching devices from all “1” states on D[0:9] with SETMAX LOW WW = Work Week to all “0” states on D[0:9] with SETMAX HIGH will increase the delay equivalent to “D0”, the minimum increment. *For additional marking information, refer to Select input pins D[10:0] may be threshold controlled by Application Note AND8002/D. combinations of interconnects between VEF (pin 7) and VCF (pin 8) for LVCMOS, ECL, or LVTTL level signals. For LVCMOS input ORDERING INFORMATION levels, leave VCF and VEF open. For ECL operation, short VCF and See detailed ordering and shipping information in the package VEF (pins 7 and 8). For LVTTL level operation, connect a 1.5 V dimensions section on page 17 of this data sheet. supply reference to VCF and leave open VEF pin. The 1.5 V reference voltage to VCF pin can be accomplished by placing a 2.2 k resistor between VCF and VEE for a 3.3 V power supply. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The 100 Series contains temperature compensation. • Maximum Input Clock Frequency >1.2 GHz Typical • Open Input Default State • Programmable Range: 0 ns to 10 ns • Safety Clamp on Inputs • Delay Range: 2.2 ns to 12.2 ns • A Logic High on the EN Pin Will Force Q to Logic Low • 10 ps Increments • D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL • PECL Mode Operating Range: Inputs VCC = 3.0 V to 3.6 V with VEE = 0 V • VBB Output Reference Voltage • NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −3.6 V Semiconductor Components Industries, LLC, 2004 October, 2004 − Rev. 13 1 Publication Order Number: MC10EP195/D MC10EP195, MC100EP195 VEE D0 VCC Q 24 23 22 21 Q VCC VCC NC 20 19 18 17 D1 25 16 EN D2 26 15 CASCADE D3 27 14 CASCADE VEE 28 13 VCC D4 29 12 SETMAX D5 30 11 SETMIN D6 31 10 LEN D7 32 9 VEE MC10EP195 MC100EP195 1 D8 2 3 4 D9 D10 IN 5 6 7 8 IN VBB VEF VCF Figure 1. 32−Lead LQFP Pinout (Top View) http://onsemi.com 2 MC10EP195, MC100EP195 Table 1. PIN DESCRIPTION Pin Name I/O Default State Description 23, 25, 26, 27, 29, 30, 31, 32, 1, 2 D[0:9] LVCMOS, LVTTL, ECL Input Low Single−Ended Parallel Data Inputs [0:9]. Internal 75 k to VEE. (Note 1) 3 D[10] LVCMOS, LVTTL, ECL Input Low Single−Ended CASCADE/CASCADE Control Input. Internal 75 k to VEE. (Note 1) 4 IN ECL Input Low Noninverted Differential Input. Internal 75 k to VEE. 5 IN ECL Input High Inverted Differential Input. Internal 75 k to VEE and 36.5 k to VCC. 6 VBB − − ECL Reference Voltage Output 7 VEF − − Reference Voltage for ECL Mode Connection 8 VCF − − LVCMOS, ECL, OR LVTTL Input Mode Select 9, 24, 28 VEE − − Negative Supply Voltage. All VEE Pins must be Externally Connected to Power Supply to Guarantee Proper Operation. (Note 2) 13, 18, 19, 22 VCC − − Positive Supply Voltage. All VCC Pins must be externally Connected to Power Supply to Guarantee Proper Operation. (Note 2) 10 LEN ECL Input Low Single−ended D pins LOAD / HOLD input. Internal 75 k to VEE. 11 SETMIN ECL Input Low Single−ended Minimum Delay Set Logic Input. Internal 75 k to VEE. (Note 1) 12 SETMAX ECL Input Low Single−ended Maximum Delay Set Logic Input. Internal 75 k to VEE. (Note 1) 14 CASCADE ECL Output − Inverted Differential Cascade Output for D[10]. Typically Terminated with 50 to VTT = VCC − 2 V. 15 CASCADE ECL Output − Noninverted Differential Cascade Output. for D[10] Typically Terminated with 50 to VTT = VCC − 2 V. 16 EN ECL Input Low 17 NC − − No Connect. The NC Pin is Electrically Connected to the Die and ”MUST BE” Left Open 21 Q ECL Output − Noninverted Differential Output. Typically Terminated with 50 to VTT = VCC − 2 V. 20 Q ECL Output − Inverted Differential Output. Typically Terminated with 50 to VTT = VCC − 2 V. Single−ended Output Enable Pin. Internal 75 k to VEE. 1. SETMIN will override SETMAX if both are high. SETMAX and SETMIN will override all D[0:10] inputs. 2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. http://onsemi.com 3 MC10EP195, MC100EP195 Table 2. CONTROL PIN Pin State EN LOW (Note 3) Function Input Signal is Propagated to the Output HIGH LEN Output Holds Logic Low State LOW (Note 3) Transparent or LOAD mode for real time delay values present on D[0:10]. HIGH SETMIN SETMAX D10 LOCK and HOLD mode for delay values on D[0:10]; further changes on D[0:10] are not recognized and do not affect delay. LOW (Note 3) Output Delay set by D[0:10] HIGH Set Minimum Output Delay LOW (Note 3) Output Delay set by D[0:10] HIGH Set Maximum Output Delay LOW (Note 3) CASCADE Output LOW, CASCADE Output HIGH HIGH CASCADE Output LOW, CASCADE Output HIGH 3. Internal pulldown resistor will provide a logic LOW if pin is left unconnected. Table 3. CONTROL D[0:10] INTERFACE VCF VEF Pin (Note 4) VCF No Connect VCF 1.5 V 100 mV ECL Mode LVCMOS Mode LVTTL Mode (Note 5) 4. Short VCF (pin 8) and VEF (pin 7). 5. When Operating in LVTTL Mode, the reference voltage can be provided by connecting an external resistor, RCF (suggested resistor value is 2.2 k 5%), between VCF and VEE pins. Table 4. DATA INPUT ALLOWED OPERATING VOLTAGE MODE TABLE CONTROL DATA SELECT INPUTS PINS (D [0:10]) POWER SUPPLY LVCMOS LVTTL LVPECL LVNECL PECL Mode Operating Range YES YES YES N/A NECL Mode Operating Range N/A N/A N/A YES Table 5. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor ESD Protection (R1) Human Body Model Machine Model Charged Device Model Moisture Sensitivity (Note 6) Flammability Rating 75 k > 2 kV > 100 V > 2 kV Level 2 Oxygen Index: 28 to 34 Transistor Count UL 94 V−0 @ 0.125 in 1217 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 6. For additional information, see Application Note AND8003/D. http://onsemi.com 4 0 IN 0 0 0 0 0 0 0 0 0 0 R1 IN R1 EN 1 256 GD* 1 128 GD* 1 64 GD* 1 32 GD* 16 GD* 1 1 8 GD* 1 4 GD* 1 2 GD* 1 1 GD* 1 5 http://onsemi.com Figure 2. Logic Diagram R1 LEN R1 SET MIN 10 BIT LATCH R1 SET MAX R1 VBB R1 D9 R1 D8 R1 D7 R1 D6 R1 D5 R1 D4 R1 D3 R1 D2 R1 D1 VCF VEF VEE CASCADE Latch D10 CASCADE R1 *GD = (GATE DELAY) APPROXIMATELY 10 ps DELAY PER GATE (MINIMUM FIXED DELAY APPROX. 2.2 ns) D0 R1 1 GD* 1 Q Q MC10EP195, MC100EP195 512 GD* MC10EP195, MC100EP195 Table 6. THEORETICAL DELAY VALUES D(9:0) Value SETMIN SETMAX Programmable Delay* XXXXXXXXXX H L 0 ps 0000000000 L L 0 ps 0000000001 L L 10 ps 0000000010 L L 20 ps 0000000011 L L 30 ps 0000000100 L L 40 ps 0000000101 L L 50 ps 0000000110 L L 60 ps 0000000111 L L 70 ps 0000001000 L L 80 ps 0000010000 L L 160 ps 0000100000 L L 320 ps 0001000000 L L 640 ps 0010000000 L L 1280 ps 0100000000 L L 2560 ps 1000000000 L L 5120 ps 1111111111 L L 10230 ps XXXXXXXXXX L H 10240 ps *Fixed minimum delay not included. http://onsemi.com 6 MC10EP195, MC100EP195 14000.0 13000.0 85°C 12000.0 11000.0 25°C −40°C DELAY ( ps) 10000.0 9000.0 VCC = 0 V 8000.0 VEE = −3.3 V 7000.0 6000.0 5000.0 4000.0 3000.0 2000.0 1000.0 0.0 0.0 100.0 200.0 300.0 400.0 500.0 600.0 700.0 800.0 900.0 1000.0 Decimal Value of Select Inputs (D[9:0]) Figure 3. Measured Delay vs. Select Inputs Table 7. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit 6 V −6 V 6 −6 V V 50 100 mA mA ±0.5 mA VCC Positive Mode Power Supply VEE = 0 V VEE Negative Mode Power Supply VCC = 0 V VI Positive Mode Input Voltage Negative Mode Input Voltage VEE = 0 V VCC = 0 V Iout Output Current Continuous Surge IBB VBB Sink/Source TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C JA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm LQFP−23 LQFP−23 80 55 °C/W °C/W JC Thermal Resistance (Junction−to−Case) Standard Board LQFP−23 12 to 17 °C/W Tsol Wave Solder < 2 to 3 sec @ 248°C 265 °C VI ≤ VCC VI ≥ VEE Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. http://onsemi.com 7 MC10EP195, MC100EP195 Table 8. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 7) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit IEE Negative Power Supply Current 100 145 175 100 150 180 100 150 180 mA VOH Output HIGH Voltage (Note 8) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV VOL Output LOW Voltage (Note 8) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV VIH Input HIGH Voltage (Single−Ended) VIL mV LVPECL LVCMOS LVTTL 2090 2000 2000 2415 3300 3300 2155 2000 2000 2480 3300 3300 2215 2000 2000 2540 3300 3300 LVPECL LVCMOS LVTTL 1365 0 0 1690 800 800 1430 0 0 1755 800 800 1490 0 0 1815 800 800 Input LOW Voltage (Single−Ended) mV VBB ECL Output Voltage Reference VCF LVTTL Mode Input Detect Voltage VEF Reference Voltage for ECL Mode Connection VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 9) IIH Input HIGH Current (@ VIH) IIL Input LOW Current (@ VIL) 1790 1890 1990 1855 1955 2055 1915 2015 2115 mV 1.4 1.5 1.6 1.4 1.5 1.6 1.4 1.5 1.6 V 1915 2020 2120 1940 2080 2190 1985 2130 2265 mV 3.3 2.0 3.3 2.0 3.3 V 150 A 2.0 150 IN IN 0.5 −150 150 0.5 −150 0.5 −150 A NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −0.3 V. 8. All loading with 50 to VCC − 2.0 V. 9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 8 MC10EP195, MC100EP195 Table 9. 10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −3.3 V to −3.0 V (Note 10) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit IEE Negative Power Supply Current 100 145 175 100 150 180 100 150 180 mA VOH Output HIGH Voltage (Note 11) −1135 −1010 −885 −1070 −945 −820 −1010 −885 −760 mV VOL Output LOW Voltage (Note 11) −1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560 mV VIH Input HIGH Voltage (Single−Ended) LVNECL −1210 −885 −1145 −820 −1085 −760 Input LOW Voltage (Single−Ended) LVNECL −1935 −1610 −1870 −1545 −1810 −1485 VBB ECL Output Voltage Reference −1510 −1410 −1310 −1445 −1345 −1245 −1385 −1285 −1185 mV VEF Reference Voltage for ECL Mode Connection −1385 −1280 −1180 −1360 −1220 −1110 −1315 −1170 −1035 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 12) 0.0 V IIH Input HIGH Current (@ VIH) 150 A IIL Input LOW Current (@ VIL) VIL mV mV VEE+2.0 0.0 VEE+2.0 150 IN IN 0.5 −150 0.0 VEE+2.0 150 0.5 −150 0.5 −150 A NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −0.3 V. 11. All loading with 50 to VCC − 2.0 V. 12. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 9 MC10EP195, MC100EP195 Table 10. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 13) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit IEE Negative Power Supply Current 100 135 160 100 140 170 100 145 175 mA VOH Output HIGH Voltage (Note 14) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 14) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV VIH Input HIGH Voltage (Single−Ended) VIL mV LVPECL CMOS TTL 2075 2000 2000 2420 3300 3300 2075 2000 2000 2420 3300 3300 2075 2000 2000 2420 3300 3300 LVPECL CMOS TTL 1355 0 0 1675 800 800 1490 0 0 1675 800 800 1490 0 0 1675 800 800 Input LOW Voltage (Single−Ended) mV VBB ECL Output Voltage Reference VCF LVTTL Mode Input Detect Voltage VEF Reference Voltage for ECL Mode Connection VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 15) IIH Input HIGH Current (@ VIH) IIL Input LOW Current (@ VIL) 1775 1875 1975 1775 1875 1975 1775 1875 1975 mV 1.4 1.5 1.6 1.4 1.5 1.6 1.4 1.5 1.6 V 1915 2020 2120 1940 2080 2190 1985 2130 2265 mV 3.3 2.0 3.3 2.0 3.3 V 150 A 2.0 150 IN IN 0.5 −150 150 0.5 −150 0.5 −150 A NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 13. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −0.3 V. 14. All loading with 50 to VCC − 2.0 V. 15. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 10 MC10EP195, MC100EP195 Table 11. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −3.3 V (Note 16) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 100 135 160 100 140 170 100 145 175 mA IEE Negative Power Supply Current (Note 17) VOH Output HIGH Voltage (Note 18) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV VOL Output LOW Voltage (Note 18) −1945 −1820 −1695 −1945 −1820 −1695 −1945 −1820 −1695 mV VIH Input HIGH Voltage (Single−Ended) LVNECL −1225 −880 −1225 −880 −1225 −880 Input LOW Voltage (Single−Ended) LVNECL −1945 −1625 −1945 −1625 −1945 −1625 VBB ECL Output Voltage Reference −1525 −1425 −1325 −1525 −1425 −1325 −1525 −1425 −1325 mV VEF Reference Voltage for ECL Mode Connection −1385 −1280 −1180 −1360 −1220 −1110 −1315 −1170 −1035 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 19) 0.0 V IIH Input HIGH Current (@ VIH) 150 A IIL Input LOW Current (@ VIL) VIL mV mV VEE+2.0 0.0 VEE+2.0 150 IN IN 0.5 −150 0.0 VEE+2.0 150 0.5 −150 0.5 −150 A NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 16. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −0.3 V. 17. Required 500 lfpm air flow when using +5 V power supply. For (VCC − VEE) > 3.3 V, 5 to 10 in line with VEE required for maximum thermal protection at elevated temperatures. Recommend VCC − VEE operation at ≤ 3.8 V. 18. All loading with 50 to VCC − 2.0 V. 19. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 11 MC10EP195, MC100EP195 Table 12. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −3.6 V or VCC = 3.0 V to 3.6 V; VEE = 0 V (Note 20) −40°C Symbol Min Characteristic Typ Max fmax Maximum Frequency tPLH tPHL Propagation Delay IN to Q; D(0−10) = 0 IN to Q; D(0−10) = 1023 EN to Q; D(0−10) = 0 D0 to CASCADE 1650 9500 1600 300 2050 11500 2150 420 tRANGE Programmable Range tPD (max) − tPD (min) 7850 9450 t Max Min 1.2 Typ Max 1.2 Unit GHz 2450 13500 2600 500 1800 10000 1800 350 2200 12200 2300 450 8200 10000 2600 14000 2800 550 1950 10800 2000 425 2350 13300 2500 525 8850 10950 2750 15800 3000 625 ps Step Delay (Note 21) Monotonicity (Note 27) tSKEW Duty Cycle Skew (Note 22) ps 13 27 44 90 130 312 590 1100 2250 4500 14 30 47 97 140 335 650 1180 2400 4800 41 100 145 360 690 1300 2650 5300 TBD ps 25 |tPHL−tPLH| tR Typ 85°C ps mono th Min 1.2 D0 High D1 High D2 High D3 High D4 High D5 High D6 High D7 High D8 High D9 High ts 25°C 25 25 Setup Time ps D to LEN D to IN (Note 23) EN to IN (Note 24) 200 300 300 0 140 150 200 300 300 0 160 170 200 300 300 0 180 180 LEN to D IN to EN (Note 25) 200 400 60 250 200 400 100 280 200 400 80 300 EN to IN (Note 26) SET MAX to LEN SET MIN to LEN 150 400 350 −25 200 275 150 400 350 −75 250 200 150 400 350 −50 300 225 Hold Time ps Release Time ps tjitter RMS Random Clock Jitter @ 1.2 GHz VPP Input Voltage Swing (Differential Configuration) tr tf Output Rise/Fall Time @ 50 MHz 20−80% (Q) 20−80% (CASCADE) 3 3 3 ps 150 800 1200 150 800 1200 150 800 1200 85 100 100 140 135 200 85 110 110 150 135 200 95 130 125 170 155 220 mV ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 20. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC − 2.0 V. 21. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range. 22. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output. 23. This setup time defines the amount of time prior to the input signal the delay tap of the device must be set. 24. This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than ±75 mV to that IN/IN transition. 25. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response greater than ±75 mV to that IN/IN transition. 26. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets the specified IN to Q propagation delay and transition times. 27. The monotonicity indicates the increasing delay value for each binary count increment on the control inputs D[9:0]. http://onsemi.com 12 MC10EP195, MC100EP195 IN VINPP = VIH(D) − VIL(D) IN Q VOUTPP = VOH(Q) − VOL(Q) Q tPHL tPLH Figure 4. AC Reference Measurement Cascading Multiple EP195s To increase the programmable range of the EP195, internal cascade circuitry has been included. This circuitry allows for the cascading of multiple EP195s without the need for any external gating. Furthermore, this capability requires only one more address line per added E195. Obviously, cascading multiple programmable delay chips will result in a larger programmable range: however, this increase is at the expense of a longer minimum delay. Figure 5 illustrates the interconnect scheme for cascading two EP195s. As can be seen, this scheme can easily be expanded for larger EP195 chains. The D10 input of the EP195 is the CASCADE control pin. With the interconnect scheme of Figure 5 when D10 is asserted, it signals the need for a larger programmable range than is achievable with a single device and switches output pin CASCADE HIGH and pin CASCADE LOW. The A11 address can be added to generate a cascade output for the next EP195. For a 2−device configuration, A11 is not required. Need if Chip #3 is used ADDRESS BUS A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 VEE D3 D2 D1 D7 D6 D5 D4 VEE D3 D2 D1 D8 VEE D8 VEE D9 D0 D9 D0 VCC D10 D10 EP195 IN Q IN Q IN VCC EP195 Q INPUT OUTPUT Figure 5. Cascading Interconnect Architecture http://onsemi.com 13 NC EN CASCADE VCF CASCADE NC VCC VCC VCC VEF SETMAX VCC CHIP #1 SETMIN VBB VEE CASCADE CASCADE VCC SETMAX LEN VEE VCF SETMIN VEF VCC EN CHIP #2 VBB Q LEN IN MC10EP195, MC100EP195 (1111111111 on the A0—A9 address bus) D10 will be asserted to signal the need to cascade the delay to the next EP195 device. When D10 is asserted, the SET MIN pin of chip #2 will be deasserted and SET MAX pin asserted resulting in the device delay to be the maximum delay. Table 13 shows the delay time of two EP195 chips in cascade. To expand this cascading scheme to more devices, one simply needs to connect the D10 pin from the next chip to the address bus and CASCADE outputs to the next chip in the same manner as pictured in Figure 5. The only addition to the logic is the increase of one line to the address bus for cascade control of the second programmable delay chip. An expansion of the latch section of the block diagram is pictured in Figure 6. Use of this diagram will simplify the explanation of how the cascade circuitry works. When D10 of chip #1 in Figure 5 is LOW this device’s CASCADE output will also be low while the CASCADE output will be high. In this condition the SET MIN pin of chip #2 will be asserted HIGH and thus all of the latches of chip #2 will be reset and the device will be set at its minimum delay. Chip #1, on the other hand, will have both SET MIN and SET MAX deasserted so that its delay will be controlled entirely by the address bus A0—A9. If the delay needed is greater than can be achieved with 1023 gate delays TO SELECT MULTIPLEXERS SET MIN BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 D8 Q8 D9 Q9 LEN LEN LEN LEN LEN LEN LEN LEN LEN LEN Set Reset Set Reset Set Reset Set Reset Set Reset Set Reset Set Reset Set Reset Set Reset Set Reset SET MAX Figure 6. Expansion of the Latch Section of the EP195 Block Diagram http://onsemi.com 14 MC10EP195, MC100EP195 Table 13. Delay Value of Two EP195 Cascaded VARIABLE INPUT TO CHIP #1 AND SETMIN FOR CHIP #2 INPUT FOR CHIP #1 Total D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Delay Value Delay Value 0 0 0 0 0 0 0 0 0 0 0 0 ps 4400 ps 0 0 0 0 0 0 0 0 0 0 1 10 ps 4410 ps 0 0 0 0 0 0 0 0 0 1 0 20 ps 4420 ps 0 0 0 0 0 0 0 0 0 1 1 30 ps 4430 ps 0 0 0 0 0 0 0 0 1 0 0 40 ps 4440 ps 0 0 0 0 0 0 0 0 1 0 1 50 ps 4450 ps 0 0 0 0 0 0 0 0 1 1 0 60 ps 4460 ps 0 0 0 0 0 0 0 0 1 1 1 70 ps 4470 ps 0 0 0 0 0 0 0 1 0 0 0 80 ps 4480 ps 0 0 0 0 0 0 1 0 0 0 0 160 ps 4560 ps 0 0 0 0 0 1 0 0 0 0 0 220 ps 4720 ps 0 0 0 0 1 0 0 0 0 0 0 640 ps 5040 ps 0 0 0 1 0 0 0 0 0 0 0 1280 ps 5680 ps 0 0 1 0 0 0 0 0 0 0 0 2560 ps 6960 ps 0 1 0 0 0 0 0 0 0 0 0 5120 ps 9520 ps 0 1 1 1 1 1 1 1 1 1 1 10230 ps 14630 ps VARIABLE INPUT TO CHIP #1 AND SETMAX FOR CHIP #2 INPUT FOR CHIP #1 Total D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 0 0 0 0 0 10240 ps 14640 ps 1 0 0 0 0 0 0 0 0 0 1 10250 ps 14650 ps 1 0 0 0 0 0 0 0 0 1 0 10260 ps 14660 ps 1 0 0 0 0 0 0 0 0 1 1 10270 ps 14670 ps 1 0 0 0 0 0 0 0 1 0 0 10280 ps 14680 ps 1 0 0 0 0 0 0 0 1 0 1 10290 ps 14690 ps 1 0 0 0 0 0 0 0 1 1 0 10300 ps 14700 ps 1 0 0 0 0 0 0 0 1 1 1 10310 ps 14710 ps 1 0 0 0 0 0 0 1 0 0 0 10320 ps 14720 ps 1 0 0 0 0 0 1 0 0 0 0 10400 ps 14800 ps 1 0 0 0 0 1 0 0 0 0 0 10560 ps 14960 ps 1 0 0 0 1 0 0 0 0 0 0 10880 ps 15280 ps 1 0 0 1 0 0 0 0 0 0 0 11520 ps 15920 ps 1 0 1 0 0 0 0 0 0 0 0 12800 ps 17200 ps 1 1 0 0 0 0 0 0 0 0 0 15360 ps 19760 ps 1 1 1 1 1 1 1 1 1 1 1 20470 ps 24870 ps http://onsemi.com 15 Delay Value Delay Value MC10EP195, MC100EP195 Multi−Channel Deskewing be sent through each EP195 as shown in Figure 7. One signal channel can be used as reference and the other EP195s can be used to adjust the delay to eliminate the timing skews. Nearly any high−speed system can be fine−tuned (as small as 10 ps) to reduce the skew to extremely tight tolerances. The most practical application for EP195 is in multiple channel delay matching. Slight differences in impedance and cable length can create large timing skews within a high−speed system. To deskew multiple signal channels, each channel can EP195 IN IN Q Q #1 EP195 IN IN Q Q #2 EP195 IN IN Q Q #N Control Logic Digital Data Figure 7. Multiple Channel Deskewing Diagram Measure Unknown High Speed Device Delays If the programmed delay through the second EP195 is too long, the flip−flop output will be at logic high. On the other hand, if the programmed delay through the second EP195 is too short, the flip−flop output will be at a logic low. If the programmed delay is correctly fine−tuned in the second EP195, the flip−flop will bounce between logic high and logic low. The digital code in the second EP195 can be directly correlated into an accurate device delay. EP195s provide a possible solution to measure the unknown delay of a device with a high degree of precision. By combining two EP195s and EP31 as shown in Figure 8, the delay can be measured. The first EP195 can be set to SETMIN and its output is used to drive the unknown delay device, which in turn drives the input of a D flip−flop of EP31. The second EP195 is triggered along with the first EP195 and its output provides a clock signal for EP31. The programmed delay of the second EP195 is varied to detect the output edge from the unknown delay device. EP195 CLOCK IN IN CLOCK Q Q Unknown Delay Device #1 D Q EP31 CLK EP195 IN IN Q Q #2 Control Logic Figure 8. Multiple Channel Deskewing Diagram http://onsemi.com 16 Q MC10EP195, MC100EP195 Zo = 50 Q D Receiver Device Driver Device Zo = 50 Q D 50 50 VTT VTT = VCC − 2.0 V Figure 9. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device Shipping† Package MC10EP195FA LQFP−32 250 Units / Tray MC10EP195FAR2 LQFP−32 2000 / Tape & Reel MC100EP195FA LQFP−32 250 Units / Tray MC100EP195FAR2 LQFP−32 2000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 17 MC10EP195, MC100EP195 Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPS I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1642/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 18 MC10EP195, MC100EP195 PACKAGE DIMENSIONS A 32 A1 −T−, −U−, −Z− 32 LEAD LQFP CASE 873A−02 ISSUE B 4X 25 0.20 (0.008) AB T−U Z 1 AE −U− −T− B P V 17 8 BASE METAL DETAIL Y V1 ÉÉ ÉÉ ÉÉ −Z− 9 S1 4X 0.20 (0.008) AC T−U Z F S 8X M J R D DETAIL AD G SECTION AE−AE −AB− C E −AC− H W K X DETAIL AD NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE −AB− IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS −T−, −U−, AND −Z− TO BE DETERMINED AT DATUM PLANE −AB−. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE −AC−. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE −AB−. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X http://onsemi.com 19 MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12 REF 0.090 0.160 0.400 BSC 1 5 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12 REF 0.004 0.006 0.016 BSC 1 5 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF Q 0.250 (0.010) 0.10 (0.004) AC GAUGE PLANE SEATING PLANE M N 9 0.20 (0.008) DETAIL Y AC T−U Z AE B1 MC10EP195, MC100EP195 ECLinPS is a trademark of Semiconductor Components Industries, LLC. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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