PD - 96186A
IRFS4010PbF
IRFSL4010PbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
D
G
S
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
VDSS
RDS(on) typ.
max.
ID
100V
3.9m:
4.7m:
180A
D
D
S
G
G
D2Pak
IRFS4010PbF
D
S
TO-262
IRFSL4010PbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
Parameter
Max.
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
c
Pulsed Drain Current
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
e
dv/dt
TJ
TSTG
Avalanche Characteristics
EAS (Thermally limited)
IAR
EAR
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
c
d
Units
180
127
720
375
2.5
± 20
31
-55 to + 175
A
W
W/°C
V
V/ns
°C
300
318
See Fig. 14, 15, 22a, 22b,
f
mJ
A
mJ
Thermal Resistance
Symbol
RθJC
RθJA
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Parameter
jk
Junction-to-Case
Junction-to-Ambient (PCB Mount)
i
Typ.
Max.
Units
–––
0.40
40
°C/W
–––
1
07/07/11
IRFS/SL4010PbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
V(BR)DSS
ΔV(BR)DSS/ΔTJ
RDS(on)
VGS(th)
IDSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
IGSS
RG(int)
Min. Typ. Max. Units
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
100
–––
–––
2.0
–––
–––
–––
–––
–––
0.10
3.9
–––
–––
–––
–––
–––
–––
–––
4.7
4.0
20
250
100
-100
Internal Gate Resistance
–––
2.0
–––
Conditions
V VGS = 0V, ID = 250μA
V/°C Reference to 25°C, ID = 5mA
mΩ VGS = 10V, ID = 106A
V VDS = VGS, ID = 250μA
VDS = 100V, VGS = 0V
μA
VDS = 100V, VGS = 0V, TJ = 125°C
VGS = 20V
nA
VGS = -20V
c
f
Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
Qsync
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss eff. (ER)
Coss eff. (TR)
Parameter
Min. Typ. Max. Units
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
h
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
g
189
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
143
38
50
93
21
86
100
77
9575
660
270
757
1112
–––
215
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
S
nC
ns
Conditions
VDS = 25V, ID = 106A
ID = 106A
VDS = 50V
VGS = 10V
ID = 106A, VDS =0V, VGS = 10V
VDD = 65V
ID = 106A
RG = 2.7Ω
VGS = 10V
VGS = 0V
VDS = 50V
ƒ = 1.0MHz See Fig.5
VGS = 0V, VDS = 0V to 80V See Fig.11
VGS = 0V, VDS = 0V to 80V
f
f
pF
h
g
Diode Characteristics
Symbol
IS
Parameter
Continuous Source Current
VSD
trr
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
ISM
c
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.057mH
RG = 25Ω, IAS = 106A, VGS =10V. Part not recommended for use
above this value .
ISD ≤ 106A, di/dt ≤ 1319A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400μs; duty cycle ≤ 2%.
2
Min. Typ. Max. Units
–––
–––
180
A
–––
–––
720
Conditions
MOSFET symbol
showing the
integral reverse
D
G
p-n junction diode.
TJ = 25°C, IS = 106A, VGS = 0V
TJ = 25°C
VR = 85V,
TJ = 125°C
IF = 106A
di/dt = 100A/μs
TJ = 25°C
f
S
––– –––
1.3
V
–––
72
–––
ns
–––
81
–––
––– 210 –––
nC
TJ = 125°C
––– 268 –––
–––
5.3
–––
A TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
f
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering echniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C
RθJC value shown is at time zero
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IRFS/SL4010PbF
1000
1000
VGS
15V
10V
8.0V
7.0V
5.0V
4.5V
4.3V
4.0V
100
BOTTOM
BOTTOM
100
10
1
≤60μs PULSE WIDTH
Tj = 25°C
4.0V
4.0V
0.1
0.1
10
1
10
0.1
100
Fig 1. Typical Output Characteristics
Tj = 175°C
1
10
100
Fig 2. Typical Output Characteristics
2.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
1000
ID, Drain-to-Source Current (A)
≤60μs PULSE WIDTH
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
100
TJ = 175°C
T J = 25°C
10
1
VDS = 50V
≤60μs PULSE WIDTH
0.1
2
3
4
5
6
1.0
-60 -40 -20 0 20 40 60 80 100120140160180
Fig 4. Normalized On-Resistance vs. Temperature
14.0
VGS, Gate-to-Source Voltage (V)
C oss = C ds + C gd
Ciss
Coss
1000
1.5
T J , Junction Temperature (°C)
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
10000
2.0
0.5
Fig 3. Typical Transfer Characteristics
100000
ID = 106A
VGS = 10V
7
VGS, Gate-to-Source Voltage (V)
C, Capacitance (pF)
VGS
15V
10V
8.0V
7.0V
5.0V
4.5V
4.3V
4.0V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
Crss
100
ID= 106A
12.0
10.0
VDS= 80V
VDS= 50V
8.0
6.0
4.0
2.0
0.0
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
www.irf.com
0
25
50
75 100 125 150 175 200 225
QG, Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
3
IRFS/SL4010PbF
10000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
T J = 175°C
100
T J = 25°C
10
OPERATION IN THIS AREA
LIMITED BY RDS(on)
1000
100μsec
100
1msec
10
10msec
1
VGS = 0V
0.01
1.0
0.2
0.6
1.0
1.4
0.1
1.8
180
ID, Drain Current (A)
160
140
120
100
80
60
40
20
0
75
100
125
150
175
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
200
50
100
1000
130
Id = 5mA
125
120
115
110
105
100
95
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Temperature ( °C )
T C , Case Temperature (°C)
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Drain-to-Source Breakdown Voltage
4.0
EAS , Single Pulse Avalanche Energy (mJ)
1400
3.5
ID
12.5A
17A
BOTTOM 106A
1200
3.0
Energy (μJ)
10
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
25
1
VDS, Drain-to-Source Voltage (V)
VSD, Source-to-Drain Voltage (V)
TOP
1000
2.5
2.0
1.5
1.0
0.5
0.0
800
600
400
200
0
0
20
40
60
80
100
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy
4
DC
Tc = 25°C
Tj = 175°C
Single Pulse
0.1
120
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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IRFS/SL4010PbF
Thermal Response ( Z thJC ) °C/W
1
D = 0.50
0.1
0.20
0.10
0.05
0.02
0.01
0.01
τJ
R1
R1
τJ
τ1
0.001
τC
τ2
τ1
τ2
Ci= τi/Ri
Ci i/Ri
SINGLE PULSE
( THERMAL RESPONSE )
0.0001
1E-006
R2
R2
1E-005
0.0001
τ
Ri (°C/W)
0.17537
0.22547
τi (sec)
0.000343
0.006073
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Avalanche Current (A)
Duty Cycle = Single Pulse
100
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
10
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
350
300
EAR , Avalanche Energy (mJ)
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 22a, 22b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 106A
250
200
150
100
50
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
4.5
35
4.0
30
3.5
25
3.0
20
2.5
ID = 250μA
2.0
ID = 1.0A
IRR (A)
VGS(th) , Gate threshold Voltage (V)
IRFS/SL4010PbF
ID = 1.0mA
IF = 70A
V R = 85V
TJ = 25°C
TJ = 125°C
15
10
1.5
5
1.0
0
-75 -50 -25
0
25 50 75 100 125 150 175
0
200
T J , Temperature ( °C )
600
800
1000
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
1100
35
IF = 106A
V R = 85V
30
IF = 70A
V R = 85V
1000
900
TJ = 25°C
TJ = 125°C
25
TJ = 25°C
TJ = 125°C
800
20
QRR (A)
IRR (A)
400
diF /dt (A/μs)
15
700
600
500
400
10
300
5
200
100
0
0
200
400
600
800
0
1000
200
400
600
800
1000
diF /dt (A/μs)
diF /dt (A/μs)
Fig. 19 - Typical Stored Charge vs. dif/dt
Fig. 18 - Typical Recovery Current vs. dif/dt
1100
IF = 106A
V R = 85V
1000
900
TJ = 25°C
TJ = 125°C
QRR (A)
800
700
600
500
400
300
200
0
200
400
600
800
1000
diF /dt (A/μs)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFS/SL4010PbF
Driver Gate Drive
D.U.T
-
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D=
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V(BR)DSS
15V
DRIVER
L
VDS
tp
D.U.T
RG
VGS
20V
+
V
- DD
IAS
A
0.01Ω
tp
I AS
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
Fig 22b. Unclamped Inductive Waveforms
VDS
90%
VGS
D.U.T.
RG
+
- VDD
V10V
GS
10%
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
td(on)
Fig 23a. Switching Time Test Circuit
tr
t d(off)
Fig 23b. Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
12V
tf
.2μF
.3μF
D.U.T.
+
V
- DS
Vgs(th)
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
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Qgs1 Qgs2
Qgd
Qgodr
Fig 24b. Gate Charge Waveform
7
IRFS/SL4010PbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
EXAMPLE: T HIS IS AN IRL3103L
LOT CODE 1789
AS S EMBLED ON WW 19, 1997
IN THE AS S EMBLY LINE "C"
PART NUMBER
INT ERNATIONAL
RECTIFIER
LOGO
DAT E CODE
YEAR 7 = 1997
WEEK 19
LINE C
AS S EMBLY
LOT CODE
OR
INT ERNAT IONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
PART NUMBER
DAT E CODE
P = DES IGNAT ES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 7 = 1997
WEEK 19
A = ASS EMBLY S IT E CODE
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
8
www.irf.com
IRFS/SL4010PbF
D2Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
D2Pak (TO-263AB) Part Marking Information
T HIS IS AN IRF 530S WIT H
LOT CODE 8024
ASS EMBLED ON WW 02, 2000
IN T HE ASS EMBLY LINE "L"
INT ERNAT IONAL
RECT IFIER
LOGO
PART NUMBER
F 530S
DAT E CODE
YEAR 0 = 2000
WEEK 02
LINE L
AS SEMBLY
LOT CODE
OR
INT ERNAT IONAL
RECT IFIER
LOGO
ASS EMBLY
LOT CODE
PART NUMBER
F530S
DAT E CODE
P = DESIGNAT ES LEAD - F REE
PRODUCT (OPT IONAL)
YEAR 0 = 2000
WEEK 02
A = ASS EMBLY S IT E CODE
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
www.irf.com
9
IRFS/SL4010PbF
D2Pak (TO-263AB) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
1.60 (.063)
1.50 (.059)
11.60 (.457)
11.40 (.449)
1.65 (.065)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
3
30.40 (1.197)
MAX.
4
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
10
IR WORLD HEADQUARTERS: 101N.Sepulveda blvd, El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 07/2011
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