Holtek HT49C10 8-bit microcontroller Datasheet

HT49C10
8-Bit Microcontroller
Features
·
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·
·
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Operating voltage: 2.2V~5.2V
Eight bidirectional I/O lines
Six input lines
Two external interrupt input
8-bit programmable timer/event counter
withPFD(programmablefrequencydivider)
Watchdog timer
On-chip crystal and RC oscillator
1K´14 program memory ROM
64´8 data memory RAM
Real Time Clock (RTC)
8-bit prescaler for RTC
·
·
·
·
·
·
·
·
·
·
Buzzer output
Halt function and wake-up feature reduce
power consumption
LCD driver with 19´3 or 18´4 segments
4-level subroutine nesting
Bit manipulation instruction
14-bit table read instruction
Up to 1ms instruction cycle with 4MHz
system clock
63 powerful instructions
All instructions in 1 or 2 machine cycles
48-pin SSOP package
General Description
The HT49C10 is an 8-bit high performance single
chip microcontroller. Its single-cycle instruction
and two-stage pipeline architecture make it suitable for high speed applications. The device is
also suited for multiple LCD low power applications among which are calculators, clock timers,
games, scales, leisure products, other hand held
LCD products, and battery systems in particular.
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September 28, 1999
HT49C10
Block Diagram
T im e r C L K
In te rru p t
C ir c u it
P ro g ra m
R O M
P ro g ra m
C o u n te r
M
T M R
S T A C K
IN T C
M
M P
U
X
D A T A
M e m o ry
S Y S C L K /4
M
W D T
M U X
In s tr u c tio n
D e c o d e r
S h ifte r
P O R T A
S
S
P A
A C C
C 1
L C D
M e m o ry
D
R T C O S C
X
O S C 3
O S C 4
P B 0 /IN T 0
P B 1 /IN T 1
P B 2 /T M R
P B 3 ~ P B 5
P B
B P
U
W D T O S C
P O R T B
S T A T U S
A L U
O S
R E
V D
V S
T M R
R T C
T im e B a s e
O S C 2
X
T M R C
In s tr u c tio n
R e g is te r
T im in g
G e n e ra to r
U
P A 0
P A 1
P A 2
P A 3
P A 4
/B Z
/B Z
/P F D
~ P A 7
L C D D R IV E R
C O M 0 ~
C O M 2
C O M 3 /
S E G 1 8
S E G 0 ~
S E G 1 7
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September 28, 1999
HT49C10
Pin Assignment
P A 0 /B Z
1
4 8
R E S
P A 1 /B Z
2
4 7
O S C 1
P A 2
3
4 6
O S C 2
P A 3 /P F D
4
4 5
V D D
P A 4
5
4 4
O S C 3
P A 5
6
4 3
O S C 4
P A 6
7
4 2
S E G 0
P A 7
8
4 1
S E G 1
P B 0 /IN T 0
9
4 0
S E G 2
P B 1 /IN T 1
1 0
3 9
S E G 3
P B 2 /T M R
1 1
3 8
S E G 4
P B 3
1 2
3 7
S E G 5
P B 4
1 3
3 6
S E G 6
P B 5
1 4
3 5
S E G 7
V S S
1 5
3 4
S E G 8
V L C D
1 6
3 3
S E G 9
V 1
1 7
3 2
S E G 1 0
V 2
1 8
3 1
S E G 1 1
C 1
1 9
3 0
S E G 1 2
C 2
2 0
2 9
S E G 1 3
C O M 0
2 1
2 8
S E G 1 4
C O M 1
2 2
2 7
S E G 1 5
C O M 2
2 3
2 6
S E G 1 6
S E G 1 8 /C O M 3
2 4
2 5
S E G 1 7
H T 4 9 C 1 0
4 8 S S O P
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September 28, 1999
HT49C10
Pad Assignment
OSC2
VDD
48 47 46 45 44
OSC1
RES
PA0/BZ
3
PA1/BZ
2
PA6
PA2
PA5
PA3/PFD
PA4
1
43
42
41
40
OSC3
39
OSC4
PA7
4
38
SEG0
PB0/INT0
5
37
SEG1
PB1/INT1
6
36
SEG2
PB2/TMR
7
35
SEG3
PB3
8
34
SEG4
PB4
9
33
SEG5
PB5
10
32
SEG6
VSS
11
31
SEG7
30
SEG8
29
SEG9
28
SEG10
VLCD
V1
(0,0)
12
13
25 26
27
V2
C2
COM1
SEG18/COM3
SEG16
SEG15
SEG13
SEG11
SEG12
23 24
SEG14
22
SEG17
20 21
COM2
18 19
COM0
16 17
C1
14 15
* The IC substrate should be connected to VSS in the PCB layout artwork.
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September 28, 1999
HT49C10
Pad Description
Pad No.
45
46
47
48
1~4
Pad Name
PA0/BZ
PA1/BZ
PA2
PA3/PFD
PA4~PA7
I/O
I/O
Mask
Option
Description
Wake-up
Pull-high
or None
CMOS or
NMOS
PA0~PA7 constitute an 8-bit bidirectional input/ output port with Schmitt trigger input capability. Each
bit on port can be configured as wake-up input by
mask option. PA0~PA3 can be configured as CMOS
(output) or NMOS (input/output) and with or without
pull-high resistor by mask option, PA4~PA7 always
pull-high and NMOS (input/output). Of the eight bits,
PA0~PA1 can be set as I/O pins or buzzer outputs by
mask option. PA3 can be set as an I/O pin or a PFD
output also by mask option.
5
6
7
8~10
PB0/INT0
PB1/INT1
PB2/TMR
PB3~PB5
I
¾
PB0~PB5 constitute a 6-bit Schmitt trigger input
port. Each bit on port are pull-high resistor. Of the six
bits, PB0 can be set as input pin or external interrupt
control pin (INT0) by software application. PB1 can be
set as input pin or an external interrupt control pin
(INT1) by software application. While PB2 can be set
as input pin or timer/event counter input pin also by
software application.
11
VSS
I
¾
Negative power supply, GND
12
VLCD
I
¾
LCD power supply
13~16
V1,V2,C1,C2
I
¾
Voltage pump
20
19~17
SEG18/COM3
COM2~COM0
O
1/3 or 1/4
Duty
21~38
SEG17~SEG0
O
¾
LCD driver outputs for LCD panel segments
39
40
OSC4
OSC3
O
I
¾
Real time clock oscillators
41
VDD
¾
¾
Positive power supply
42
43
OSC2
OSC1
O
I
44
RES
I
SEG18 can be set as segment or common output driver
for LCD panel by mask option. COM2~COM0 are outputs for LCD panel plate.
OSC1 and OSC2 are connected to an RC network or a
Crystal or crystal (by mask option) for the internal system clock.
RC
In the case of RC operation, OSC2 is the output terminal for 1/4 system clock.
¾
Schmitt trigger reset input, active low
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September 28, 1999
HT49C10
Absolute Maximum Ratings
Supply Voltage..............................-0.3V to 5.5V
Storage Temperature.................-50°C to 125°C
Input Voltage .................VSS-0.3V to VDD+0.3V
Operating Temperature ..............-25°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
Min.
Typ.
Max.
Unit
2.2
¾
5.2
V
No load,
fSYS=4MHz
¾
0.7
1.5
mA
¾
2
3
mA
No load,
fSYS=2MHz
¾
0.5
1
mA
¾
1
2
mA
No load,
system Halt
¾
¾
5
mA
¾
¾
10
mA
¾
¾
1
mA
¾
¾
2
mA
VDD
Conditions
¾
VDD
Operating Voltage
¾
IDD1
Operating Current
(Crystal OSC)
3V
IDD2
Operating Current
(RC OSC)
3V
ISTB1
Standby Current
(RTC Enable, LCD On)
3V
ISTB2
Standby Current
(RTC Disable, LCD Off)
VIL
Input Low Voltage for I/O Ports
VIH
Input High Voltage for I/O
Ports
VIL1
Input Low Voltage
(RES, INT0, INT1, TMR)
VIH1
Input High Voltage
(RES, INT0, INT1, TMR)
IOL
I/O Ports Sink Current
IOH
I/O Ports Source Current
RPH
Pull-high Resistance of I/O
Ports and INT0, INT1
5V
5V
5V
3V
No load,
system Halt
5V
3V
¾
0
¾
0.9
V
5V
¾
0
¾
1.5
V
3V
¾
2.1
¾
3
V
5V
¾
3.5
¾
5
V
3V
RES=0.5VDD
INT0/1=0.3VDD
TMR=0.3VDD
0
¾
1.5/0.9
V
0
¾
2.5/1.5
V
2.4
¾
3
V
4.0
¾
5
V
5V
3V
0.8VDD
5V
3V
VOL=0.3V
1.5
2.5
¾
mA
5V
VOL=0.5V
4
6
¾
mA
3V
VOH=2.7V
-1
-1.5
¾
mA
5V
VOH=4.5V
-2
-3
¾
mA
3V
¾
40
60
80
kW
5V
¾
10
30
50
kW
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September 28, 1999
HT49C10
A.C. Characteristics
Symbol
Parameter
fSYS1
System Clock (Crystal OSC)
fSYS2
System Clock (RC OSC)
fTIMER
Timer I/P Frequency (TMR)
tWDTOSC Watchdog Oscillator
Ta=25°C
Test Conditions
Min.
Typ.
Max.
Unit
¾
455
¾
4000
kHz
5V
¾
455
¾
4000
kHz
3V
¾
400
¾
2000
kHz
5V
¾
400
¾
3000
kHz
3V
¾
0
¾
4000
kHz
5V
¾
0
¾
4000
kHz
3V
¾
45
90
180
ms
5V
¾
35
65
130
ms
VDD
Conditions
3V
tRES
External Reset Low Pulse
Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer
Period
¾
Power-up or
wake-up from halt
¾
1024
¾
tSYS
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
Note: tSYS=1/fSYS
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September 28, 1999
HT49C10
Functional Description
The conditional skip is activated by instructions.
Once the condition is met, the next instruction,
fetched during the current instruction execution, is discarded and a dummy cycle replaces it
to get a proper instruction; otherwise proceed
with the next instruction.
Execution flow
The system clock is derived from either a crystal or an RC oscillator. It is internally divided
into four non-overlapping clocks. One instruction
cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined
in such a way that a fetch takes one instruction
cycle while decoding and execution takes the
next instruction cycle. The pipelining scheme
causes each instruction to effectively execute in
a cycle. If an instruction changes the value of
the program counter, two cycles are required to
complete the instruction.
The lower byte of the PC (PCL) is a readable
and writeable register (06H). Moving data into
the PCL performs a short jump. The destination is within 256 locations.
Program counter - PC
The program memory (ROM) is used to store
the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 1024´14 bits
which are addressed by the PC and table
pointer.
When a control transfer takes place, an additional dummy cycle is required.
Program memory - ROM
The 10-bit program counter (PC) controls the
sequence in which the instructions stored in the
program ROM are executed. The contents of
the PC can specify a maximum of 1024 addresses.
Certain locations in the ROM are reserved for
special usage:
After accessing a program memory word to fetch
an instruction code, the value of the PC is incremented by one. The PC then points to the memory word containing the next instruction code.
· Location 000H
Location 000H is reserved for program initialization. After chip reset, the program always
begins execution at this location.
When executing a jump instruction, conditional
skip execution, loading a PCL register, a subroutine call, an initial reset, an internal interrupt, an external interrupt, or returning from a
subroutine, the PC manipulates program
transfer by loading the address corresponding
to each instruction.
S y s te m
C lo c k
T 1
T 2
T 3
T 4
· Location 004H
Location 004H is reserved for the external interrupt service program. If the INT0 input
pin is activated, and the interrupt is enabled,
and the stack is not full, the program begins
execution at location 004H.
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
O S C 2 ( R C o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
P C + 2
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution flow
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September 28, 1999
HT49C10
· Location 008H
0 0 0 H
Location 008H is reserved for the external interrupt service program. If the INT1 input pin
is activated, and the interrupt is enabled, and
the stack is not full, the program begins execution at location 008H.
D e v ic e in itia liz a tio n p r o g r a m
0 0 4 H
E x te r n a l in te r r u p t0 s u b r o u tin e
0 0 8 H
E x te r n a l in te r r u p t1 s u b r o u tin e
0 0 C H
T im e r /e v e n t c o u n te r in te r r u p t s u b r o u tin e
0 1 0 H
· Location 00CH
Location 00CH is reserved for the timer/event
counter interrupt service program. If a timer
interrupt resulting from a timer/event counter overflow, and if the interrupt is enabled
and the stack is not full, the program begins
execution at location 00CH.
P ro g ra m
R O M
T im e b a s e in te r r u p t
0 1 4 H
R T C in te r r u p t
n 0 0 H
L o o k - u p ta b le ( 2 5 6 w o r d s )
n F F H
· Location 010H
Location 010H is reserved for the time base
interrupt service program. If a time base interrupt occurs, and the interrupt is enabled,
and the stack is not full, the program begins
execution at location 010H.
1 4 b its
N o te : n ra n g e s fro m
0 to 3
Program memory
· Location 014H
· Table location
Location 014H is reserved for the real time
clock interrupt service program. If a real time
clock interrupt occurs, and the interrupt is enabled, and the stack is not full, the program
begins execution at location 014H.
Mode
L o o k - u p ta b le ( 2 5 6 w o r d s )
3 F F H
Any location in the ROM can be used as a
look-up table. The instructions ²TABRDC [m]²
(the current page, 1 page=256 words) and
²TABRDL [m]² (the last page) transfer the conProgram Counter
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial reset
0
0
0
0
0
0
0
0
0
0
External interrupt 0
0
0
0
0
0
0
0
1
0
0
External interrupt 1
0
0
0
0
0
0
1
0
0
0
Timer/event Counter overflow
0
0
0
0
0
0
1
1
0
0
Time Base Interrupt
0
0
0
0
0
1
0
0
0
0
RTC Interrupt
0
0
0
0
0
1
0
1
0
0
Skip
PC+2
Loading PCL
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return From Subroutine
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program counter
Note: *9~*0: Program counter bits
#9~#0: Instruction code bits
S9~S0: Stack register bits
@7~@0: PCL bits
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September 28, 1999
HT49C10
terrupt is serviced. This feature prevents stack
overflow, allowing the programmer to use the
structure easily. Likewise, if the stack is full,
and a ²CALL² is subsequently executed, a stack
overflow occurs and the first entry is lost (only
the most recent four return addresses are stored).
tents of the lower-order byte to the specified
data memory, and the contents of the
higher-order byte to TBLH (table higher-order
byte register) (08H). Only the destination of
t h e l ow er - or d er b y te i n t he t a b l e i s
well-defined; the other bits of the table word
are all transferred to the lower portion of
TBLH, and the remaining two bits are both
read as ²0². The TBLH is read only, and the table pointer (TBLP) is a read/write register
(07H), indicating the table location. Before accessing the table, the location should be placed
in TBLP. All the table related instructions require two cycles to complete the operation.
These areas may function as a normal ROM
dependingupontherequirements.
Data memory - RAM
The data memory (RAM) is designed with 81´8
bits, and is divided into two functional groups,
namely special function registers and general
purpose data memory, most of which are readable/writeable, although some are read only.
Of the two types of functional groups, the special
function registers consist of an indirect addressing
register 0 (00H), a memory pointer register 0
(MP0; 01H), an indirect addressing register 1 (02H),
a memory pointer register 1 (MP1;03H), a bank
pointer (BP;04H), an accumulator (ACC;05H), a
program counter lower-order byte register
(PCL;06H), a table pointer (TBLP;07H), a table
higher-order byte register (TBLH;08H), a real
time clock control register (RTCC;09H), a status
register (STATUS;0AH), an interrupt control register 0 (INTC0;0BH), a timer/event counter
(TMR;0DH), a timer/event counter control register
(TMRC; 0EH), I/O registers (PA;12H, PB;14H),
and interrupt control register 1 (INTC1;1EH). On
the other hand, the general purpose data memory,
addressed from 20H to 5FH, is used for data and
control information under instruction commands.
Stack register - STACK
The stack register is a special part of the memory used to save the contents of the PC. The
stack is organized into four levels and is neither
part of the data nor part of the program, and is
neither readable nor writeable. Its activated
level is indexed by a stack pointer (SP) and is
neither readable nor writeable. At a commencement of a subroutine call or an interrupt acknowledgment, the contents of the PC is
pushed onto the stack. At the end of the subroutine or interrupt routine, signaled by a return
instruction (RET or RETI), the contents of the
PC is restored to its previous value from the
stack. After chip reset, the SP will point to the
top of the stack.
The areas in the RAM can directly handle
arithmetic, logic, increment, decrement, and
rotate operations. Except for some dedicated
bits, each bit in the RAM can be set and reset by
²SET [m].i² and ²CLR [m].i². They are also indirectly accessible through the memory pointer
If the stack is full and a non-masked interrupt
takes place, the interrupt request flag is recorded
but the acknowledgment is still inhibited. Once
the SP is decremented (by RET or RETI), the inInstruction(s)
Table Location
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table location
Note: *9~*0: Table location bits
P9~P8: Current program counter bits
@7~@0: Table pointer bits
10
September 28, 1999
HT49C10
MP1 (03H) respectively. Reading location 00H
or 02H indirectly returns the result 00H, while,
writing it leads to no operation.
register 0 (MP0;01H) or the memory pointer register 1 (MP1;03H).
0 1 H
In d ir e c t A d d r e s s in g R e g is te r 0
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 0 H
0 3 H
M P 1
0 4 H
B P
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
T B L H
0 8 H
The function of data movement between two indirect addressing registers is not supported.
The memory pointer registers, MP0 and MP1,
are both 7-bit registers used to access the RAM
by combining corresponding indirect addressing registers. The bit 7 of MP0 and MP1 are undefined and reading will return the result 1 .
Any writing operation to MP0 and MP1 will
only transfer the lower 7-bit data.
0 9 H
R T C C
0 A H
S T A T U S
0 B H
IN T C 0
Only MP0 can be applied to data memory, while
MP1 can be applied to data memory and LCD
display memory.
0 C H
0 D H
T M R
0 E H
T M R C
0 F H
Accumulator - ACC
The accumulator (ACC) is related to ALU operations. It is also mapped to location 05H of the
RAM and is capable of carrying out immediate
data operations. The data movement between
two data memory locations has to pass through
the ACC.
S p e c ia l P u r p o s e
D a ta M e m o ry
1 0 H
1 1 H
1 2 H
P A
1 3 H
1 4 H
P B
1 5 H
1 6 H
Arithmetic and logic unit - ALU
1 7 H
This circuit performs 8-bit arithmetic and logic
operations and provides the following functions:
1 8 H
1 9 H
1 A H
· Arithmetic operations
1 B H
(ADD, ADC, SUB, SBC, DAA)
1 C H
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
1 D H
1 E H
IN T C 1
1 F H
2 0 H
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ etc.)
: U n u s e d
G e n e ra l P u rp o s e
D a ta M e m o ry
(6 4 B y te s )
The ALU not only saves the results of a data operation but also changes the status register.
R e a d a s "0 0 "
Status register - STATUS
The status register (0AH) is 8-bit wide and contains a carry flag (C), an auxiliary carry flag
(AC), a zero flag (Z), an overflow flag (OV), a
power down flag (PD), and a watchdog time-out
flag (TO). It also records the status information
and controls the operation sequence.
5 F H
RAM mapping
Indirect addressing register
Location 00H and 02H are indirect addressing
registers that are not physically implemented.
Any read/write operation of [00H] and [02H] accesses the RAM pointed to by MP0 (01H) and
Except for the TO and PD flags, bits in the status
register can be altered by instructions, similar to
other registers. Data written into the status reg11
September 28, 1999
HT49C10
Labels
Bits
Function
C
0
C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
AC
1
AC is set if the operation results in a carry out of the low nibbles in addition or no
borrow from the high nibble into the low nibble in subtraction; otherwise AC is
cleared.
Z
2
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is
cleared.
OV
3
OV is set if the operation results in a carry into the highest-order bit but not a
carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
PD
4
PD is cleared by either a system power-up or executing the ²CLR WDT² instruction. PD is set by executing the ²HALT² instruction.
TO
5
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is set by a WDT time-out.
¾
6, 7
Undefined, read as ²0²
STATUS register
interrupts are all blocked (by clearing the EMI
bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may
take place during this interval, but only the interrupt request flag will be recorded. If a certain interrupt requires servicing within the
service routine, the programmer may set the
EMI bit and the corresponding bit of INTC0 or of
INTC1 in order to allow interrupt nesting. Once
the stack is full, the interrupt request will not be
acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate
service is desired, the stack should be prevented
from becoming full.
ister does not alter the TO or PD flags. Operations related to the status register, however, may
yield different results from those intended. The
TO and PD flags can only be changed by a watchdog timer overflow, chip power-up, or clearing the
watchdog timer and executing the ²HALT² instruction. The Z, OV, AC, and C flags reflect the
status of the latest operations.
On entering the interrupt sequence or executing the subroutine call, the status register will
not be pushed onto the stack automatically. If
the contents of the status is important, and if
the subroutine is likely to corrupt the status
register, precautions should be taken to save it
properly.
All these interrupts have the wake-up capability.
When an interrupt is serviced, a control transfer occurs by pushing the PC onto the stack, followed by a branch to subroutines at the
specified locations in the ROM. Only the PC is
pushed onto the stack. If the contents of the register or of the status register (STATUS) is altered by the interrupt service program which
corrupts the desired control sequence, the contents should be saved first.
Interrupts
The HT49C10 provides two external interrupts,
an internal timer/event counter interrupt, an
internal time base interrupt, and an internal
real time clock interrupt. The interrupt control
register 0 (INTC0;0BH) and interrupt control
register 1 (INTC1;1EH) both contain the interrupt control bits that are used to set the enable/disable status and interrupt request flags.
External interrupts are triggered by a high to
low transition of INT0 or INT1, and the related
Once an interrupt subroutine is serviced, other
12
September 28, 1999
HT49C10
Register
INTC0
(0BH)
INTC1
(1EH)
Bit No.
Label
Function
0
EMI
Control the master (global) interrupt
(1= enabled; 0= disabled)
1
EEI0
Control the external interrupt 0
(1= enabled; 0= disabled)
2
EEI1
Control the external interrupt 1
(1= enabled; 0= disabled)
3
ETI
Control the timer/event counter interrupt
(1= enabled; 0= disabled)
4
EIF0
External interrupt 0 request flag
(1= active; 0= inactive)
5
EIF1
External interrupt 1 request flag
(1= active; 0= inactive)
6
TF
Internal timer/event counter request flag
(1= active; 0= inactive)
7
¾
Unused bit, read as ²0²
0
ETBI
Control the time base interrupt
(1= enabled; 0= disabled)
1
ERTI
Control the real time clock interrupt
(1= enabled; 0= disabled)
2, 3
¾
Unused bit, read as ²0²
4
TBF
Time base request flag
(1= active; 0= inactive)
5
RTF
Real time clock request flag
(1= active; 0= inactive)
6, 7
¾
Unused bit, read as ²0²
INTC register
(TF) is reset, and the EMI bit is cleared to disable further interrupts.
interrupt request flag (EIF0; bit 4 of INTC0,
EIF1; bit 5 of INTC0) is set as well. After the interrupt is enabled, and the stack is not full, and
the external interrupt is active, a subroutine
call to location 04H or 08H occurs. The interrupt request flag (EIF0 or EIF1) and EMI bits
are all cleared to disable other interrupts.
The time base interrupt is initialized by setting
the time base interrupt request flag (TBF; bit 4
of INTC1), that is caused by a regular time base
signal. After the interrupt is enabled, and the
stack is not full, and the TBF bit is set, a subroutine call to location 10H occurs. The related
interrupt request flag (TBF) is reset and the
EMI bit is cleared to disable further interrupts.
The internal timer/event counter interrupt is
initialized by setting the timer/event counter
interrupt request flag (TF; bit 6 of INTC0), that
is caused by a timer overflow. After the interrupt is enabled, and the stack is not full, and
the TF bit is set, a subroutine call to location
0CH occurs. The related interrupt request flag
The real time clock interrupt is initialized by
setting the real time clock interrupt request
flag (RTF; bit 5 of INTC1), that is caused by a
13
September 28, 1999
HT49C10
status of the interrupts. These bits prevent the
requested interrupt from being serviced. Once
the interrupt request flags (RTF, TBF, TF,
EIF1, EIF0) are all set, they remain in the
INTC1 or INTC0 respectively until the interrupts are serviced or cleared by a software instruction.
regular real time clock signal. After the interrupt is enabled, and the stack is not full, and
the RTF bit is set, a subroutine call to location
14H occurs. The related interrupt request flag
(RTF) is reset and the EMI bit is cleared to disable further interrupts.
During the execution of an interrupt subroutine,
other interrupt acknowledgments are all held
until the ²RETI² instruction is executed or the
EMI bit and the related interrupt control bit are
set both to 1 (if the stack is not full). To return
from the interrupt subroutine, ²RET² or ²RETI²
may be invoked. RETI sets the EMI bit and enables an interrupt service, but RET does not.
It is recommended that a program not use the
²CALL subroutine² within the interrupt subroutine. It¢s because interrupts often occur in
an unpredictable manner or require to be serviced immediately in some applications. At this
time, if only one stack is left, and enabling the
interrupt is not well controlled, operation of the
²call subroutine² in the interrupt subroutine
may damage the original control sequence.
Interrupts occurring in the interval between
the rising edges of two consecutive T2 pulses
are serviced on the latter of the two T2 pulses if
the corresponding interrupts are enabled. In
the case of simultaneous requests, the following
table shows the priority that is applied. These
can be masked by resetting the EMI bit.
Oscillator configuration
The HT49C10 provides two oscillator circuits
for system clocks, i.e., RC oscillator and crystal
oscillator, determined by mask option. No matter what type of oscillator is selected, the signal
is used for the system clock. The HALT mode
stops the system oscillator and ignores an external signal to conserve power.
No. Interrupt Source Priority Vector
a
External interrupt 0
1
04H
b
External interrupt 1
2
08H
c
Timer/event
counter overflow
3
0CH
d
Time base interrupt
4
10H
e
Real time clock
interrupt
5
14H
Of the two oscillators, if the RC oscillator is
used, an external resistor between OSC1 and
VSS is required, and the range of the resistance
should be from 51kW to 1MW. The system clock,
O S C 1
O S C 1
V
The timer/event counter interrupt request flag
(TF), external interrupt 1 request flag (EIF1),
external interrupt 0 request flag (EIF0), enable
timer/event counter interrupt bit (ETI), enable
external interrupt 1 bit (EEI1), enable external
interrupt 0 bit (EEI0), and enable master interrupt bit (EMI) make up of the interrupt control
register (INTC0) which is located at 0BH in the
RAM. The real time clock interrupt request flag
(RTF), time base interrupt request flag (TBF),
enable real time clock interrupt bit (ERTI), and
enable time base interrupt bit (ETBI), on the
other hand, constitute the other interrupt control register (INTC1) which is located at 1EH in
the RAM. EMI, EEI0, EEI1, ETI, ETBI, and
ERTI are all used to control the enable/disable
O S C 2
fS
Y S
D D
O S C 2
/4
C r y s ta l O s c illa to r
R C
O s c illa to r
System oscillator
O S C 3
O S C 4
RTC oscillator
14
September 28, 1999
HT49C10
divided by 4, is available on OSC2 with
pull-high resistor, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However,
the frequency of the oscillation may vary with
VDD, temperature, and the chip itself due to
process variations. It is, therefore, not suitable
for timing sensitive operations where accurate
oscillator frequency is desired.
Watchdog timer - WDT
The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or an instruction clock (system clock/4) or a real time
clock oscillator (RTC oscillator). The timer is
designed to prevent a software malfunction or
sequence from jumping to an unknown location
with unpredictable results. The WDT can be
disabled by mask option. But if the WDT is disabled, all executions related to the WDT lead to
no operation.
On the other hand, if the crystal oscillator is selected, a crystal across OSC1 and OSC2 is
needed to provide the feedback and phase shift
required for the oscillator, and no other external
components are required. A resonator may be
connected between OSC1 and OSC2 to replace
the crystal and to get a frequency reference, but
two external capacitors in OSC1 and OSC2 are
needed.
After the WDT clock source is selected, it
time-out period is fs/215~fs/216.
If the WDT clock source chooses the internal
WDT oscillator, the time-out period may vary
with temperature, VDD, and process variations. On the other hand, if the clock source selects the instruction clock and the ²halt²
instruction is executed, WDT may stop counting and lose its protecting purpose, and the
logic can only be restarted by external logic.
There is another oscillator circuit designed for
the real time clock. In this case, only the
32.768kHz crystal oscillator can be applied. The
crystal should be connected between OSC3 and
OSC4, and two external capacitors along with
one external resistor are required for the oscillator circuit in order to get a stable frequency.
When the device operates in a noisy environment, using the on-chip RC oscillator (WDT
OSC) is strongly recommended, since the HALT
can stop the system clock.
The RTC oscillator circuit can be controlled to
oscillate quickly by setting ²QOSC² bit (bit 4 of
RTCC). It is recommended to turn on the quick
oscillating function upon power on, and turn it
off after two seconds.
The WDT overflow under normal operation
initializes a ²chip reset² and sets the status bit
²TO². In the HALT mode, the overflow
initializes a ²warm reset², and only the PC and
SP are reset to zero. To clear the contents of the
WDT, there are three methods to be adopted,
i.e., external reset (a low level to RES), software
instruction, and ²HALT² instruction. There are
two sets of software instructions, ²CLR WDT²
and the other set - ²CLR WDT1² and ²CLR
WDT2². Of these two types of instructions, only
one type of instruction can be active at a time
depending on the mask option - ²CLR WDT
The WDT oscillator is a free running on-chip
RC oscillator, and no external components are
required. Although the system enters the power
down mode, the system clock stops, and the
WDT oscillator still works with a period of approximately 78 ms. The WDT oscillator can be
disabled by mask option to conserve power.
S y s te m
C lo c k /4
R T C
O S C 3 2 7 6 8 H z
W D T
O S C
M a s k
O p tio n
S e le c t
fs
D iv id e r
P r e s c a le r
C K
T
C K
T
R
T im e - o u t
R e s e t fs /2
1 5
~ fs /2
1 6
W D T C le a r
1 2 k H z
Watchdog timer
15
September 28, 1999
HT49C10
time-out period ranges from fs/28 to fs/215 by
software programming (recommand use 212~215).
Writing data to RT2, RT1 and RT0 (bits 2, 1, 0 of
RTCC;09H) yields various time-out periods. If
the RTC time-out occurs, the related interrupt request flag (RTF; bit 5 of INTC1) is set. But if the
interrupt is enabled, and the stack is not full, a
subroutine call to location 14H occurs. The real
time clock time-out signal can also be applied as a
clock source of the timer/event counter to get a
longer time-out period.
times selection option². If the ²CLR WDT² is selected (i.e., CLR WDT times equal one), any execution of the ²CLR WDT² instruction clears
the WDT. In the case that ²CLR WDT1² and
²CLR WDT2² are chosen (i.e., CLR WDT times
equal two), these two instructions have to be executed to clear the WDT; otherwise, the WDT
may reset the chip because of time-out.
Multi-function timer
The HT49C10 provides a multi-function timer
for WDT, time base and RTC but with different
time-out periods. The multi-function timer consists of a 7-stage divider and an 8-bit prescaler,
with the clock source coming from the WDT
OSC or RTC OSC or the instruction clock (i.e.,
system clock divided by 4). The multi-function
timer also provides a selectable frequency signal (ranges from fs/22 to fs/28) for LCD driver
circuits, and a selectable frequency signal
(ranges from fs/22 to fs/29) for buzzer output by
mask option. It is recommended to select a
4kHz signal for LCD driver circuits for proper
display.
RT2
RT1
RT0
RTC Clock Divided
Factor
0
0
0
28
0
0
1
29
0
1
0
210
0
1
1
211
1
0
0
212
1
0
1
213
1
1
0
214
1
1
1
215
Time base
The time base offers a periodic time-out period to
generate a regular internal interrupt. Its
time-out period ranges from fs/212 to fs/215 selected by mask option. If time base time-out occurs, the related interrupt request flag (TBF; bit 4
of INTC1) is set. But if the interrupt is enabled,
and the stack is not full, a subroutine call to location 10H occurs.
Power down operation - HALT
The HALT mode is initialized by the ²HALT² instruction and results in the following.
· The system oscillator turns off but the WDT
oscillator keeps running (if the WDT oscillator or the real time clock is selected).
· The contents of the on-chip RAM and of the
registers remain unchanged.
Real time clock - RTC
· The WDT is cleared and start recounting (if the
The real time clock (RTC) is operated in the
same manner as the time base that is used to
supply a regular internal interrupt. Its
fs
WDT clock source is from the WDT oscillator or
the real time clock oscillator).
D iv id e r
P r e s c a le r
M a s k
O p tio n
M a s k O p tio n
2
8
T im e B a s e In te r r u p t
fs /2 1 2~ fs /2 1 5
L C D D r iv e r ( fs /2 ~ fs /2 )
2
9
B u z z e r (fs /2 ~ fs /2 )
Time base
16
September 28, 1999
HT49C10
· All I/O ports maintain their original status.
acknowledgment, the actual interrupt subroutine execution is delayed by more than one cycle. However, if the wake-up results in the next
instruction execution, the execution will be performed immediately after the dummy period is
finished.
· The PD flag is set but the TO flag is cleared.
· LCD driver is still running (if the WDT OSC
or RTC OSC is selected).
The system quits the HALT mode by an external
reset, an interrupt, an external falling edge signal on port A, or a WDT overflow. An external reset causes device initialization, and the WDT
overflow performs a ²warm reset². After examining the TO and PD flags, the reason for chip reset can be determined. The PD flag is cleared by
system power-up or by executing the ²CLR
WDT² instruction, and is set by executing the
²HALT² instruction. On the other hand, the TO
flag is set if WDT time-out occurs, and causes a
wake-up that only resets the PC (Program Counter) and SP, and leaves the others at their original state.
To minimize power consumption, all the I/O
pins should be carefully managed before entering the HALT status.
Reset
There are three ways in which a reset may occur.
· RES is reset during normal operation
· RES is reset during HALT
· WDT time-out is reset during normal operation
The WDT time-out during HALT differs from
other chip reset conditions, for it can perform a
²warm reset² that resets only the PC and SP
and leaves the other circuits at their original
state. Some registers remain unaffected during
any other reset conditions. Most registers are
reset to the ²initial condition² once the reset
conditions are met. Examining the PD and TO
flags, the program can distinguish between different ²chip resets².
The port A wake-up and interrupt methods can
be considered as a continuation of normal execution. Each bit in port A can be independently
selected to wake up the device by mask option.
Awakening from an I/O port stimulus, the program resumes execution of the next instruction.
On the other hand, awakening from an interrupt, two sequences may occur. If the related interrupt is disabled or the interrupt is enabled,
but the stack is full, the program resumes execution at the next instruction. But if the interrupt is enabled, and the stack is not full, the
regular interrupt response takes place.
TO
PD
0
0
RES reset during power-up
u
u
When an interrupt request flag is set before entering the ²halt² status, the system cannot be
awaken using that interrupt.
RES reset during normal
operation
0
1
RES wake-up HALT
If a wake-up event occurs, it takes 1024 tSYS
(system clock period) to resume normal operation. In other words, a dummy period is inserted. If the wake-up results from an interrupt
1
u
WDT time-out during normal
operation
1
1
WDT wake-up HALT
fs
RESET Conditions
Note: ²u² means ²unchanged²
D iv id e r
P r e s c a le r
R T 2
R T 1
R T 0
8 to 1
M u x .
8
1 5
(fs /2 ~ fs /2 )
R T C In te rru p t
Real time clock
17
September 28, 1999
HT49C10
The functional unit chip reset status are shown
below.
V D D
R E S
tS
S T
S S T T im e - o u t
C h ip
R e s e t
Reset timing chart
V
D D
R E S
PC
000H
Interrupt
Disabled
Prescaler, divider
Cleared
WDT, RTC, time base
Clear. After master reset, begins counting
Timer/event counter
Off
Input/output ports
Input mode
SP
Points to the top of the
stack
Reset circuit
H A L T
W a rm
W D T
E x te rn a l
R E S
O S C 1
R e s e t
W D T
T im e - o u t
R e s e t
S S T
1 0 - b it R ip p le
C o u n te r
C o ld
R e s e t
P o w e r - o n D e te c tio n
Reset configuration
To guarantee that the crystal oscillator is
started and stabilized, the SST (System
Start-up Timer) provides an extra-delay of 1024
system clock pulses when the system powers up
or awakes from the HALT state. Awaking from
the HALT state or system power-up, the SST
delay is added.
An extra SST delay is added during the
power-up period, and any wake-up from HALT
may enable the SST delay only.
18
September 28, 1999
HT49C10
The states of the registers are summarized below.
Reset
(Power On)
WDT Time-out
(Normal
Operation)
RES Reset
(Normal
Operation)
RES Reset
(HALT)
WDT
Time-out
(HALT)
TMR
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMRC
0000 1---
0000 1---
0000 1---
0000 1---
uuuu u---
000H
000H
000H
000H
000H*
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
--xx xxxx
--uu uuuu
--uu uuuu
--uu uuuu
--uu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
INTC1
--00 --00
--00 --00
--00 --00
--00 --00
--uu --uu
RTCC
--00 0111
--00 0111
--00 0111
--00 0111
--uu uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
--11 1111
--11 1111
--11 1111
--11 1111
--uu uuuu
Register
Program Counter
Note: ²*² means ²warm reset²
²u² means ²unchanged²
²x² means ²unknown²
19
September 28, 1999
HT49C10
In the event count or timer mode, the
timer/event counter starts counting at the current contents in the timer/event counter and
ends at FFH. Once an overflow occurs, the
counter is reloaded from the timer/event counter preload register, and generates an interrupt
request flag (TF; bit 6 of INTC0).
Timer/event counter
A timer/event counter (TMR) is implemented in
the HT49C10. The timer/event counter contains
an 8-bit programmable count-up counter, and the
clock source may come from the system clock or
instruction clock (system clock/4) or RTC time-out
signal or external source. System clock source or
instruction clock is selected by mask option.
In the pulse width measurement mode with
the values of the TON and TE bits equal to
one, after the TMR has received a transient
from low to high (or high to low if the TE bit is
²0²), it will start counting until the TMR returns to the original level and resets the
TON. The measured result remains in the
timer/event counter even if the activated
transient occurs again. In other words, only
one cycle measurement can be done. Until setting the TON, the cycle measurement will
re-function as long as it receives further transient pulse. In this operation mode, the
timer/event counter begins counting according
not to the logic level but to the transient edges.
In the case of counter overflows, the counter is
reloaded from the timer/event counter preload
register and issues an interrupt request, as in
the other two modes, i.e., event and timer
modes.
The external clock input allows the user to
count external events, measure time intervals
or pulse widths, or generate an accurate time
base.
There are two registers related to the timer/event
counter, i.e., TMR ([0DH]) and TMRC ([0EH]).
And two physical registers are mapped to TMR
location; writing TMR locates the starting value
in the timer/event counter preload register, while
reading it yields the contents of the timer/event
counter. The TMRC is a timer/event counter control register which defines some options.
The TN0 and TN1 bits define the operation
mode. The event count mode is used to count external events, which means that the clock
source is from an external (TMR) pin. The timer
mode functions as a normal timer with the
clock source coming from the internal selected
clock source. Finally, the pulse width measurement mode can be used to count the high or low
level duration of the external signal (TMR), and
the counting is based on the internal selected
clock source.
S y s te m
S y s te m
C lo c k
C lo c k /4
M a s k
O p tio n
S e le c t
To enable the counting operation, the Timer ON
bit (TON; bit 4 of TMRC) should be set to 1. In
the pulse width measurement mode, the TON
is automatically cleared after the measurement
cycle is completed. But in the other two modes,
M
U
X
D a ta B u s
R T C O u t
T N 1
T N 0
T N 2
T M R
T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T E
T N 1
T N 0
T O N
T im e r /E v e n t
C o u n te r
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
T
O v e r flo w
T o In te rru p t
Q
P F D O u t
P A 3 D a ta C T R L
Timer/event counter
20
September 28, 1999
HT49C10
Label (TMRC)
Bits
Function
¾
0~2
Unused bits, read as ²0²
TE
3
Defines the TMR active edge of the timer/event counter
(0=active on low to high; 1=active on high to low)
TON
4
Enable/disable timer counting
(0=disabled; 1=enabled)
TN2
5
Two to one multiplexer control inputs to select the timer/event counter
clock source (0=RTC output; 1=system clock or system clock/4)
7, 6
Defines the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse Width measurement mode (external clock)
00=Unused
TN0, TN1
TMRC register
Input/output ports
the TON can only be reset by instructions. The
overflow of the timer/event counter is one of the
wake-up sources and can also be applied to a
PFD (Programmable Frequency Divider) output at PA3 by mask option. No matter what the
operation mode is, writing a 0 to ETI disables the
interrupt service. When the PFD function is selected, executing ²CLR [PA].3² instruction to enable PFD output and executing ²SET [PA].3²
instruction to disable the PFD output.
There is an 8-bit bidirectional input/output port
and a 6-bit input port in the HT49C10, labeled
PA and PB, which are mapped to [12H] and
[14H] of the RAM, respectively. PA0~PA3 can
be configured as CMOS (output) or NMOS (input/output) and with or without pull-high resistor by mask option, PA4~PA7 always pull-high
and NMOS (input/output). PB can only be used
for input operation, and each bit on the port
with pull-high resistor. Both are for the input
operation, these ports are non-latched, that is,
the inputs should be ready at the T2 rising edge
of the instruction ²MOV A, [m]² (m=12H or
14H). For PA output operation, all data are
latched and remain unchanged until the output
latch is rewritten.
In the case of timer/event counter OFF
condition, writing data to the timer/event counter
preload register also reloads that data to the
timer/event counter. But if the timer/event counter is t u r n e d o n , d a t a w r i t t e n t o t h e
timer/event counter is kept only in the
timer/event counter preload register. The
timer/event counter still goes on operating until an overflow occurs.
When the structures of PA are open drain
NMOS type, it should be noted that, before
reading data from the pads, a ²1² should be
written to the related bits to disable the NMOS
device. That is executing first the instruction
²SET [m].i² (i=0~7 for PA) to disable any related
NMOS device, and then ²MOV A, [m]² to get
stable data.
When the timer/event counter (reading TMR)
is read, the clock is blocked to avoid errors. As
this may results in a counting error, this
should be taken into account by the programmer.
It is strongly recommended to load first a specific value into the TMR register, then turn on
the timer/event counter for proper operation.
Because the initial value of TMR is unknown.
21
September 28, 1999
HT49C10
V
V
D D
D D
W E A K
P u ll- u p
D
D a ta B u s
Q
C K
W r ite
M a
O p
(o n
P A
S
s k
tio n
ly
0 ~ P A 3 )
M a s k O p tio n
( o n ly P A 0 ~ P A 3 )
P A 0 ~ P A 7
Q
C h ip R e s e t
R e a d I/O
W a k e -u p
S y s te m
M a s k O p tio n
PA input/output port
V
Some instructions first input data and then follow the output operations. For example, ²SET
[m].i², ²CLR [m].i², ²CPL [m]², ²CPLA [m]² read
the entire port states into the CPU, execute the
defined operations (bit-operation), and then
write the results back to the latches or to the accumulator.
D D
W E A K
P u ll- u p
C h ip R e s e t
P B 0 ~ P B 5
R e a d I/O
PB input lines
LCD display memory
After chip reset, these input lines remain at a
high level or are left floating (by mask option).
Each bit of these output latches can be set or
cleared by the ²SET [m].i² and ²CLR [m].i²
(m=12H) instructions.
4 0 H
C O M
4 1 H
4 2 H
The HT49C10 provides an area of embedded
data memory for LCD display. This area is located from 40H to 52H of the RAM at Bank 1.
Bank pointer (BP; located at 04H of the RAM) is
the switch between the RAM and the LCD display memory. When the BP is set ²1², any data
4 3 H
5 0 H
5 1 H
5 2 H
0
B it
S E G M E N T
0
1
1
2
2
3
3
0
1
2
3
1 6
1 7
1 8
Display memory
22
September 28, 1999
HT49C10
Register Bit No. Label Read/Write Reset
0~2
RTCC
(09H)
RT0
RT1
RT2
Function
R/W
0
8 to 1 multiplexer control inputs to select the
real time clock prescaler output
3
¾
¾
¾
Unused bits, read as ²0²
4
QOSC
R/W
0
Control the RTC OSC to oscillate quickly.
²0² enable
²1² disable
¾
¾
¾
Unused bits, read as ²0²
5~7
RTCC register
written into 40H~52H will affect the LCD display. When the BP is cleared ²0², any data written into 40H~52H means to access the general
purpose data memory. The LCD display memory can be read and written to, only by indirect
addressing mode using MP1. When data is
writxten into the display data area it is automatically read by the LCD driver which then
generates the corresponding LCD driving signals. To turn the display On or Off, a ²1² or a ²0²
is written to the corresponding bit of the display
memory, respectively. The figure illustrates the
mapping between the display memory and LCD
pattern for the HT49C10.
²R² bias type is selected, no external capacitor
is required. If the ²C² bias type is selected, a capacitor mounted between C1 and C2 pins is
needed. The bias voltage of LCD driver can be
1/2 bias or 1/3 bias by mask option. If 1/2 bias is
selected, a capacitor mounted between V2 pin
and the ground is required. If 1/3 bias is selected, two capacitors are needed for V1 and V2
pins. Please refer to the application diagram.
Buzzer
HT49C10 provides a pair of buzzer output BZ and
BZ, which share pins with PA0 and PA1 respectively, as determined by mask option. Its output
frequency can be selected by mask option.
LCD driver output
When the buzzer function is selected, setting
PA.0 and PA.1 ²0² simultaneously will enable
the buzzer output and setting PA.0 ²1² will disable the buzzer output.
The output number of the HT49C10 LCD driver
can be 19´2 or 19´3 or 18´4 by mask option (i.e.,
1/2 duty or 1/3 duty or 1/4 duty). The bias type of
LCD driver can be ²R² type or ²C² type. If the
23
September 28, 1999
HT49C10
D u r in g a R e s e t P u ls e :
C O M 0 ,C O M 1 ,C O M 2
A ll L C D d r iv e r o u tp u ts
N o r m a l O p e r a tio n M o d e :
C O M 0
C O M 1
C O M 2
L C D s e g m e n ts o n C O M
0 ,1 ,2 s id e s b e in g u n lit
O n ly L C D s e g m e n ts o n
C O M 0 s id e b e in g lit
O n ly L C D s e g m e n ts o n
C O M 1 s id e b e in g lit
O n ly L C D s e g m e n ts o n
C O M 2 s id e b e in g lit
L C D s e g m e n ts o n
C O M 0 ,1 s id e s b e in g lit
L C D s e g m e n ts o n
C O M 0 ,2 s id e s b e in g lit
L C D s e g m e n ts o n
C O M 1 ,2 s id e s b e in g lit
L C D s e g m e n ts o n
C O M 0 ,1 ,2 s id e s b e in g lit
H a lt M o d e :
C O M 0 ,C O M 1 ,C O M 2
A ll L C D d r iv e r o u tp u ts
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
C D
V L
1 /2
V S
V D
1 /2
V S
C D
S
C D
S
C D
S
C D
S
C D
S
C D
S
C D
S
C D
S
C D
S
C D
S
C D
S
C D
S
C D
S
S
D
S
V L C D
V L C D
V L C D
V L C D
V L C D
V L C D
V L C D
V L C D
V L C D
V L C D
V L C D
V L C D
V L C D
V L C D
V L C D
LCD driver output (1/3 duty, 1/2 bias, R/C type)
24
September 28, 1999
HT49C10
3 /2 V L C D
V L C D
1 /2 V L C D
C O M 0
V S S
3 /2 V L C D
V L C D
1 /2 V L C D
C O M 1
V S S
3 /2 V L C D
V L C D
1 /2 V L C D
C O M 2
V S S
3 /2 V L C D
V L C D
C O M 3
1 /2 V L C D
V S S
3 /2 V L C D
V L C D
1 /2 V L C D
L C D s e g m e n ts O N
C O M 2 s id e lig h te d
V S S
LCD driver output (1/4 duty, 1/3 bias, C type)
25
September 28, 1999
HT49C10
Mask option
The following shows 16 kinds of mask options in the HT49C10. All these options should be defined in
order to ensure proper system functioning.
No.
Mask Option
1
OSC type selection. This option is to decide if an RC or crystal oscillator is selected as system clock.
2
Clock source selection of WDT, RTC and Time Base. There are three types of selection: system clock/4 or RTC OSC or WDT OSC.
3
WDT enable/disable selection. WDT can be enabled or disabled by mask option.
4
CLR WDT times selection. This option defines how to clear the WDT by instruction. One
time means that the ²CLR WDT² can clear the WDT. ²Two times² means only if both of the
²CLR WDT1² and ²CLR WDT2² have been executed, the WDT can be cleared.
5
Time Base time-out period selection. The Time Base time-out period ranges from fs/2
15
fs/2 . ²fs² means the clock source selected by mask option.
6
Buzzer output frequency selection. There are eight types frequency signals for buzzer out2
9
put: fs/2 ~fs/2 . ²fs² means the clock source selected by mask option.
7
Wake-up selection. This option defines the wake-up function activity. External I/O pins
(PA only) all have the capability to wake-up the chip from a HALT by a falling edge.
8
Pull-high selection. This option is to decide whether the pull-high resistance is viable or not
on the PA0~PA3.
9
PA CMOS or NMOS selection.
PA0~PA3 can be selected as CMOS or NMOS structure, but PA4~PA7 are always NMOS.
When the CMOS is selected, the related pins can only be used for output operations. When
the NMOS is selected, the related pins can be used for input or output operations.
10
Clock source selection of timer/event counter. There are two types of selection: system clock
or system clock/4.
11
I/O pins share with other functions selection.
PA0/BZ, PA1/BZ: PA0 and PA1 can be set as I/O pins or buzzer outputs.
PA3/PFD: PA3 can be set as I/O pins or PFD output.
12
LCD common selection. There are three types of selection: 2 commons (1/2 duty) or 3 commons (1/3 duty) or 4 commons (1/4 duty). If the 4 commons are selected, the segment output
pin ²SEG18² will be set as a common output.
13
LCD bias power supply selection.
There are two types of selection: 1/2 bias or 1/3 bias.
14
LCD bias type selection.
This option is to decide what kind of bias is selected, R type or C type.
15
LCD driver clock selection. There are seven types frequency signals for LCD driver circuits:
2
8
fs/2 ~fs/2 . ²fs² means the clock source selected by mask option.
12
26
to
September 28, 1999
HT49C10
Application Circuits
R C
o s c illa to r a p p lic a tio n
V
D D
C r y s ta l o s c illa to r a p p lic a tio n
O S C 1
O S C 1
S E G 0 ~ 1 7
C O M 0 ~ 3
L C D
P A N E L
S E G 0 ~ 1 7
C O M 0 ~ 3
L C D
P A N E L
O S C 2
fS
Y S
O S C 2
/4
V L C D
V
D D
V
L C D P o w e r
S u p p ly
C 1
C 2
R E S
H T 4 9 C 1 0
V 1
C 2
H T 4 9 C 1 0
0 .1 m F
V 1
0 .1 m F
0 .1 m F
O S C 3
V 2
O S C 4
V 2
0 .1 m F
O S C 4
IN T 0
P A 0 ~ P A 7
IN T 1
T M R
L C D P o w e r
S u p p ly
C 1
R E S
0 .1 m F
O S C 3
IN T 0
V L C D
D D
0 .1 m F
P A 0 ~ P A 7
IN T 1
T M R
P B 0 ~ P B 5
27
P B 0 ~ P B 5
September 28, 1999
HT49C10
Instruction Set Summary
Mnemonic
Description
Flag Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to register with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in
data memory
Decimal adjust ACC for addition with result in data memory
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
C
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
Z
Z
Z
Z
Increment &
Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
28
None
None
C
C
None
None
C
C
September 28, 1999
HT49C10
Mnemonic
Description
Flag Affected
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
None**
None
None
Bit Operation
CLR [m].i
SET [m].i
Clear bit of data memory
Set bit of data memory
None
None
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
None
None
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
No operation
Clear data memory
Set data memory
Clear Watchdog timer
Pre-clear watchdog timer
Pre-clear watchdog timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
None
None
None
TO,PD
TO*,PD*
TO*,PD*
None
None
TO,PD
**: For the old version of the E.V. chip, the zero
flag (Z) can be affected by executing the
MOV A,[M] instruction.
Note: x: 8-bit immediate data
m: 7 bits data memory address
A: accumulator
i: 0~7 number of bits
addr: 10-bit program memory address
Ö: Flag is affected
-: Flag is not affected
For the new version of the E.V. chip, the
zero flag cannot be changed by executing
the MOV A,[M] instruction.
*: Flag may be affected by the execution
status
29
September 28, 1999
HT49C10
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag
are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag
are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added.
The result is stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving
the result in the accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
30
September 28, 1999
HT49C10
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added.
The result is stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise
logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise
logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
31
September 28, 1999
HT49C10
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated
address. The program counter increments once to obtain the address of the
next instruction, and pushes this onto the stack. The indicated address is
then loaded. Program execution continues with the instruction at this address.
Operation
Stack ¬ PC+1
PC ¬ addr
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to zero.
Operation
[m] ¬ 00H
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to zero.
Operation
[m].i ¬ 0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR WDT
Clear watchdog timer
Description
The WDT is cleared (re-counting from zero). The power down bit (PD) and
time-out bit (TO) are cleared.
Operation
WDT ¬ 00H
PD and TO ¬ 0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0
0
¾
¾
¾
¾
32
September 28, 1999
HT49C10
CLR WDT1
Preclear watchdog timer
Description
The TD, PD flags and WDT are all cleared (re-counting from zero), if the
other preclear WDT instruction has been executed. Only execution of this instruction without the other preclear instruction sets the indicated flag which
implies that this instruction has been executed and the TO and PD flags remain unchanged.
Operation
WDT ¬ 00H*
PD and TO ¬ 0*
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear watchdog timer
Description
The TO, PD flags and WDT are cleared (re-counting from zero), if the other
preclear WDT instruction has been executed. Only execution of this instruction without the other preclear instruction sets the indicated flag which implies that this instruction has been executed and the TO and PD flags
remain unchanged.
Operation
WDT ¬ 00H*
PD and TO ¬ 0*
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits which previously contained a one are changed to zero and
vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
33
September 28, 1999
HT49C10
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits which previously contained a one are changed to zero and
vice-versa. The complemented result is stored in the accumulator and the
contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Code Decimal) code.
The accumulator is divided into two nibbles. Each nibble is adjusted to the
BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the
original value if the original value is greater than 9 or a carry (AC or C) is set;
otherwise the original value remains unchanged. The result is stored in the
data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0) ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by one.
Operation
[m] ¬ [m]-1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
34
September 28, 1999
HT49C10
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by one, leaving the result
in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The
contents of the RAM and registers are retained. The WDT and prescaler are
cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is
cleared.
Operation
PC ¬ PC+1
PD ¬ 1
TO ¬ 0
Affected flag(s)
INC [m]
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0
1
¾
¾
¾
¾
Increment data memory
Description
Data in the specified data memory is incremented by one.
Operation
[m] ¬ [m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by one, leaving the result
in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
35
September 28, 1999
HT49C10
JMP addr
Directly jump
Description
The contents of the program counter are replaced with the directly-specified
address unconditionally, and control is passed to this destination.
Operation
PC ¬ addr
Affected flag(s)
MOV A,[m]
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one
of the data memories).
Operation
[m] ¬ ACC
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
PC ¬ PC+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
36
September 28, 1999
HT49C10
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data
memories) perform a bitwise logical_OR operation. The result is stored in
the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR
operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator
perform a bitwise logical_OR operation. The result is stored in the data
memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a two-cycle instruction.
Operation
PC ¬ Stack
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
37
September 28, 1999
HT49C10
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded
with the specified 8-bit immediate data.
Operation
PC ¬ Stack
ACC ¬ x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled
by setting the EMI bit. EMI is the enable master (global) interrupt bit (bit 0;
register INTC).
Operation
PC ¬ Stack
EMI ¬ 1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated one bit left with bit 7
rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated one bit left with bit 7 rotated
into bit 0, leaving the rotated result in the accumulator. The contents of the
data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
38
September 28, 1999
HT49C10
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated one
bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the
bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated one bit left.
Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the
data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated one bit right with bit 0
rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
39
September 28, 1999
HT49C10
RRA [m]
Rotate right-place result in the accumulator
Description
Data in the specified data memory is rotated one bit right with bit 0 rotated
into bit 7, leaving the rotated result in the accumulator. The contents of the
data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated one bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
RRCA [m]
Rotate right through carry-place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated one bit
right. Bit 0 replaces the carry bit and the original carry flag is rotated into
the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
40
September 28, 1999
HT49C10
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag
aresubtractedfromtheaccumulator,leavingtheresultintheaccumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry
flag are subtracted from the accumulator, leaving the result in the data
memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is zero
Description
The contents of the specified data memory are decremented by one. If the result is zero, the next instruction is skipped. If the result is zero, the following
instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (two cycles). Otherwise proceed with the next instruction (one cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if zero
Description
The contents of the specified data memory are decremented by one. If the result is zero, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is zero, the
following instruction, fetched during the current instruction execution, is
discarded and a dummy cycle is replaced to get the proper instruction (two
cycles). Otherwise proceed with the next instruction (one cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
41
September 28, 1999
HT49C10
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to one.
Operation
[m] ¬ FFH
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SET [m].i
Set bit of data memory
Description
Biti of the specified data memory is set to one.
Operation
[m].i ¬ 1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is zero
Description
The contents of the specified data memory are incremented by one. If the result is zero, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (two cycles). Otherwise proceed with the next instruction (one cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if zero
Description
The contents of the specified data memory are incremented by one. If the result is zero, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is zero, the
following instruction, fetched during the current instruction execution, is
discarded and a dummy cycle is replaced to get the proper instruction (two
cycles). Otherwise proceed with the next instruction (one cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
42
September 28, 1999
HT49C10
SNZ [m].i
Skip if bit ²i² of the data memory is not zero
Description
If bit ²i² of the specified data memory is not zero, the next instruction is
skipped. If bit ²i² of the data memory is not zero, the following instruction,
fetched during the current instruction execution, is discarded and a dummy
cycle is replaced to get the proper instruction (two cycles). Otherwise proceed
with the next instruction (one cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of
the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
43
September 28, 1999
HT49C10
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (one of
the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory-place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data
memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SZ [m]
Skip if data memory is zero
Description
If the contents of the specified data memory are zero, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (two cycles). Otherwise
proceed with the next instruction (one cycle).
Operation
Skip if [m]=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if zero
Description
The contents of the specified data memory are copied to the accumulator. If
the contents is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (two cycles). Otherwise proceed with the next instruction
(one cycle).
Operation
Skip if [m]=0, ACC ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
44
September 28, 1999
HT49C10
SZ [m].i
Skip if bit ²i² of the data memory is zero
Description
If bit ²i² of the specified data memory is zero, the following instruction,
fetched during the current instruction execution, is discarded and a dummy
cycle is replaced to get the proper instruction (two cycles). Otherwise proceed
with the next instruction (one cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer
(TBLP) is moved to the specified data memory and the high byte transferred
to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP)
is moved to the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise
logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC XOR [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
45
September 28, 1999
HT49C10
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise
logical Exclusive_OR operation. The result is stored in the data memory. The
zero flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the the accumulator and the specified data perform a bitwise logical
Exclusive_OR operation. The result is stored in the accumulator. The zero
flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
46
September 28, 1999
HT49C10
Holtek Semiconductor Inc. (Headquarters)
No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C.
Tel: 886-3-563-1999
Fax: 886-3-563-1189
Holtek Semiconductor Inc. (Taipei Office)
5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C.
Tel: 886-2-2782-9635
Fax: 886-2-2782-9636
Fax: 886-2-2782-7128 (International sales hotline)
Holtek Microelectronics Enterprises Ltd.
RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657
Copyright Ó 1999 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek
assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are
used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications
will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior
notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
47
September 28, 1999