Maxim MAX7031 Low-cost, 308mhz, 315mhz, and 433.92mhz fsk transceiver with fractional-n pll Datasheet

19-3707; Rev 3; 11/10
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
Features
The MAX7031 crystal-based, fractional-N transceiver is
designed to transmit and receive FSK data at factorypreset carrier frequencies of 308MHz †, 315MHz, or
433.92MHz with data rates up to 33kbps (Manchester
encoded) or 66kbps (NRZ encoded). This device generates a typical output power of +10dBm into a 50Ω
load, and exhibits typical sensitivity of -110dBm. The
MAX7031 features separate transmit and receive pins
(PAOUT and LNAIN) and provides an internal RF switch
that can be used to connect the transmit and receive
pins to a common antenna.
o +2.1V to +3.6V or +4.5V to +5.5V Single-Supply
Operation
The MAX7031 transmit frequency is generated by a 16bit, fractional-N, phase-locked loop (PLL), while the
receiver’s local oscillator (LO) is generated by an integer-N PLL. This hybrid architecture eliminates the need
for separate transmit and receive crystal reference
oscillators because the fractional-N PLL is preset to be
10.7MHz above the receive LO. Retaining the fixed-N
PLL for the receiver avoids the higher current-drain
requirements of a fractional-N PLL and keeps the
receiver current drain as low as possible.
The fractional-N architecture of the MAX7031 transmit
PLL allows the transmit FSK signal to be preset for
exact frequency deviations, and completely eliminates
the problems associated with oscillator-pulling FSK signal generation. All frequency-generation components
are integrated on-chip, and only a crystal, a 10.7MHz IF
filter, and a few discrete components are required to
implement a complete antenna/digital data solution.
The MAX7031 is available in a small, 5mm x 5mm, 32pin, thin QFN package, and is specified to operate in
the automotive -40°C to +125°C temperature range.
†
Consult factory for availability.
o Integrated TX/RX Switch
Applications
o Single-Crystal Transceiver
o Factory-Preset Frequency (No Serial Interface
Required)
o FSK Modulation
o Factory-Preset FSK Frequency Deviation
o +10dBm Output Power into 50Ω Load
o Integrated Transmit and Receive PLL, VCO, and
Loop Filter
o > 45dB Image Rejection
o Typical RF Sensitivity*: -110dBm
o Selectable IF Bandwidth with External Filter
o RSSI Output with High Dynamic Range
o < 12.5mA Transmit-Mode Current
o < 6.7mA Receive-Mode Current
o < 800nA Shutdown Current
o Fast-On Startup Feature, < 250µs
o Small, 32-Pin, Thin QFN Package
*0.2% BER, 4kbps Manchester-encoded data, 280kHz IF BW
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
2-Way Remote Keyless Entry
MAX7031_ATJ__+
-40°C to +125°C
32 Thin QFN-EP**
Security Systems
+Denotes a lead(Pb)-free/RoHs-compliant package.
**EP = Exposed pad.
Note: The MAX7031 is available with factory-preset operating
frequencies. See the Selector Guide for complete part numbers.
Home Automation
Remote Controls
Remote Sensing
Smoke Alarms
Garage-Door Openers
Local Telemetry Systems
Pin Configuration, Selector Guide, Typical Application
Circuit, and Functional Diagram appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX7031
General Description
MAX7031
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
ABSOLUTE MAXIMUM RATINGS
HVIN to GND .........................................................-0.3V to +6.0V
PAVDD, AVDD, DVDD to GND..............................-0.3V to +4.0V
ENABLE, T/R, DATA, AGC0, AGC1,
AUTOCAL to GND ...............................-0.3V to (VHVIN + 0.3)V
All Other Pins to GND .............................-0.3V to (V_VDD + 0.3)V
Continuous Power Dissipation (TA = +70°C)
32-Pin Thin QFN (derate 21.3mW/°C
above +70°C).............................................................1702mW
Operating Temperature Range .........................-40°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, 50Ω system impedance, VPAVDD = VAVDD = VDVDD = VHVIN = +2.1V to +3.6V, fRF = 308MHz, 315MHz, or
433.92MHz, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VPAVDD = VAVDD = VDVDD = VHVIN = +2.7V,
TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
Supply Voltage (3V Mode)
VDD
Supply Voltage (5V Mode)
VHVIN
MIN
TYP
MAX
UNITS
HVIN, PAVDD, AVDD, and DVDD
connected to power supply
CONDITIONS
2.1
2.7
3.6
V
PAVDD, AVDD, and DVDD unconnected
from HVIN, but connected together
4.5
5.0
5.5
V
fRF = 315MHz
11.6
19.1
fRF = 434MHz
12.4
20.4
Receiver 315MHz
6.4
8.4
Transmit mode
(Note 2)
Supply Current
IDD
TA < +85°C,
typ at +25°C
(Note 3)
TA < +125°C,
typ at +125°C
(Note 2)
Voltage Regulator
VREG
Receiver 434MHz
6.7
8.7
Deep-sleep (3V mode)
0.8
8.8
Deep-sleep (5V mode)
2.4
10.9
Receiver 315MHz
6.8
8.7
Receiver 434MHz
7.0
8.8
Deep-sleep (3V mode)
8.0
34.2
Deep-sleep (5V mode)
14.9
39.3
VHVIN = 5V, ILOAD = 15mA
3.0
mA
µA
mA
µA
V
DIGITAL I/O
Input-High Threshold
VIH
(Note 2)
Input-Low Threshold
VIL
(Note 2)
AGC0-1, AUTOCAL, ENABLE, T/R, DATA
(VHVIN = 5.5V)
Pulldown Sink Current
Output Low Voltage
Output High Voltage
2
VOL
VOH
ISINK = 500µA
ISOURCE = 500µA
0.9 x
VHVIN
V
0.1 x
VHVIN
V
20
µA
0.15
V
VHVIN
- 0.26
V
_______________________________________________________________________________________
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
(Typical Application Circuit, 50Ω system impedance, VPAVDD = VAVDD = VDVDD = VHVIN = +2.1V to +3.6V, fRF = 308MHz, 315MHz. or
433.92MHz, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VPAVDD = VAVDD = VDVDD = VHVIN = +2.7V,
TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GENERAL CHARACTERISTICS
Frequency Range
Maximum Input Level
Transmit Efficiency (Note 5)
Power-On Time
fRF = 315MHz
308/315/433.92
0
32
fRF = 434MHz
30
ENABLE or T/R transition low to high,
transmitter frequency settled to within
50kHz of the desired carrier
200
ENABLE or T/R transition low to high,
transmitter frequency settled to within 5kHz
of the desired carrier
350
ENABLE transition low to high, or T/R
transition high to low, receiver startup time
(Note 4)
250
PRFIN
tON
MHz
dBm
%
µs
RECEIVER
0.2% BER, 4kbps
Manchester data rate,
280kHz IF BW, FSK
±50kHz deviation
Sensitivity
315MHz
-110
434MHz
-107
dBm
Image Rejection
46
dB
POWER AMPLIFIER
Output Power
POUT
Maximum Carrier Harmonics
TA = +25°C (Note 3)
4.6
10.0
TA = +125°C, VPAVDD = VAVDD = VDVDD =
VHVIN = +2.1V (Note 2)
3.9
6.7
15.5
dBm
TA = -40°C, VPAVDD = VAVDD = VDVDD =
VHVIN = +3.6V (Note 3)
13.1
With output matching network
-40
dBc
-50
dBc
Reference Spur
15.8
PHASE-LOCKED LOOP
Transmit VCO Gain
KVCO
Transmit PLL Phase Noise
340
10kHz offset, 200kHz loop BW
-68
1MHz offset, 200kHz loop BW
-98
Receive VCO Gain
340
Receive PLL Phase Noise
Loop Bandwidth
10kHz offset, 500kHz loop BW
-80
1MHz offset, 500kHz loop BW
-90
Transmit PLL
200
Receive PLL
500
MHz/V
dBc/Hz
MHz/V
dBc/Hz
kHz
_______________________________________________________________________________________
3
MAX7031
AC ELECTRICAL CHARACTERISTICS
MAX7031
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
AC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, 50Ω system impedance, VPAVDD = VAVDD = VDVDD = VHVIN = +2.1V to +3.6V, fRF = 308MHz, 315MHz. or
433.92MHz, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VPAVDD = VAVDD = VDVDD = VHVIN = +2.7V,
TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
Reference Frequency Input Level
MIN
TYP
0.5
MAX
UNITS
VP-P
LOW-NOISE AMPLIFIER/MIXER (Note 7)
LNA Input Impedance
ZINLNA
Normalized to 50Ω
High-gain state
Voltage-Conversion Gain
Low-gain state
Input-Referred 3rd-Order
Intercept Point
IIP3
fRF = 315MHz
1 - j4.7
fRF = 434MHz
1 - j3.3
fRF = 315MHz
50
fRF = 434MHz
45
fRF = 315MHz
13
fRF = 434MHz
dB
9
High-gain state
-42
Low-gain state
-6
dBm
Mixer Output Impedance
330
Ω
LO Signal Feedthrough to
Antenna
-100
dBm
RSSI
Input Impedance
Operating Frequency
fIF
330
Ω
10.7
MHz
3dB Bandwidth
10
MHz
Gain
15
mV/dB
2.0
mV/kHz
Maximum Data Filter Bandwidth
50
kHz
Maximum Data Slicer Bandwidth
100
kHz
Maximum Peak Detector
Bandwidth
50
kHz
FSK DEMODULATOR
Conversion Gain
ANALOG BASEBAND
Maximum Data Rate
Manchester coded
33
Nonreturn to zero (NRZ)
66
kbps
CRYSTAL OSCILLATOR
Crystal Frequency
fXTAL
Frequency Pulling by VDD
Crystal Load Capacitance
4
(Note 6)
(fRF - 10.7)
/ 24
MHz
2
ppm/V
4.5
pF
_______________________________________________________________________________________
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
(Typical Application Circuit, 50Ω system impedance, VPAVDD = VAVDD = VDVDD = VHVIN = +2.1V to +3.6V, fRF = 308MHz, 315MHz. or
433.92MHz, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VPAVDD = VAVDD = VDVDD = VHVIN = +2.7V,
TA = +25°C, unless otherwise noted.) (Note 1)
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Supply current, output power, and efficiency are greatly dependent on board layout and PAOUT match.
100% tested at TA = +125°C. Guaranteed by design and characterization over temperature.
Guaranteed by design and characterization. Not production tested.
Time for final signal detection; does not include baseband filter settling.
Efficiency = POUT/(VDD x IDD).
Dependent on PCB trace capacitance.
Input impedance is measured at the LNAIN pin. Note that the impedance at 315MHz includes the 12nH inductive degeneration from the LNA source to ground. The impedance at 434MHz includes a 10nH inductive degeneration connected from the
LNA source to ground. The equivalent input circuit is 50Ω in series with ~2.2pF. The voltage conversion is measured with
the LNA input-matching inductor, the degeneration inductor, and the LNA/mixer tank in place, and does not include the IF
filter insertion loss.
Typical Operating Characteristics
(Typical Operating Circuit, VPAVDD = VAVDD = VDVDD = VHVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz. 4kbps Manchester
encoded, 0.2% BER deviation = ±50kHz, TA = +25°C, unless otherwise noted.)
RECEIVER
SUPPLY CURRENT vs. RF FREQUENCY
FSK MODE
SUPPLY CURRENT (mA)
7.0
+85°C
6.8
6.6
+25°C
6.4
6.8
DEEP-SLEEP CURRENT vs. TEMPERATURE
+85°C
6.7
+25°C
6.6
-40°C
-40°C
6.2
6.5
6.0
6.4
18
MAX7031 toc03
MAX7030 toc02
+125°C
6.9
SUPPLY CURRENT (mA)
+125°C
7.2
7.0
MAX7031 toc01
7.4
16
DEEP-SLEEP CURRENT (µA)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
14
VCC = +3.6V
12
VCC = +3.0V
10
VCC = +2.1V
8
6
4
2
2.1
2.4
2.7
3.0
SUPPLY VOLTAGE (V)
3.3
3.6
0
300
325
350
375
400
RF FREQUENCY (MHz)
425
450
-40
-15
-10
35
60
85
110
TEMPERATURE (°C)
_______________________________________________________________________________________
5
MAX7031
AC ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VPAVDD = VAVDD = VDVDD = VHVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz. 4kbps Manchester
encoded, 0.2% BER deviation = ±50kHz, TA = +25°C, unless otherwise noted.)
RECEIVER
280kHz IF BW
0.2% BER
-102
0.2% BER
fRF = 434MHz
-104
-106
-108
-110
-108
-106
-40
-104
10
35
60
85
1
110
TEMPERATURE (°C)
RSSI vs. RF INPUT POWER
RSSI AND DELTA vs. IF INPUT POWER
RSSI (V)
AGC SWITCH
POINT
0.6
0.4
1.5
RSSI
1.2
0.5
0.9
-0.5
0.6
LOW-GAIN MODE
-1.5
DELTA
-2.5
0.3
0.2
AGC HYSTERESIS: 3dB
0
-3.5
0
-70
-50
-30
-10
10
-90
-70
RF INPUT POWER (dBm)
SYSTEM GAIN vs. IF FREQUENCY
0
10
15
20
IF FREQUENCY (MHz)
6
46
fRF = 315MHz
44
10.5
25
10.6
10.7
10.8
10.9
11.0
NORMALIZED IF GAIN vs. IF FREQUENCY
0
-4
-8
-12
-20
42
5
10.4
-16
-20
0
0
IF FREQUENCY (MHz)
LOWER SIDEBAND
-10
0.4
10
fRF = 434MHz
IMAGE REJECTION (dB)
FROM RFIN
TO MIXOUT
fRF = 434MHz
10
0.8
IMAGE REJECTION vs. TEMPERATURE
30
45dB IMAGE
REJECTION
-10
48
MAX7031 toc10
UPPER SIDEBAND
20
-30
1.2
IF INPUT POWER (dBm)
50
40
-50
NORMALIZED IF GAIN (dB)
-90
MAX7031 toc11
-130 -110
1.6
2.5
1.5
0.8
3.5
1.8
HIGH-GAIN MODE
1.0
FSK DEMODULATOR OUTPUT
vs. IF FREQUENCY
MAX7031 toc08
2.1
MAX7031 toc07
1.4
100
10
FREQUENCY DEVIATION (kHz)
AVERAGE INPUT POWER (dBm)
1.6
1.2
-15
MAX7031 toc12
-110
FSK DEMODULATOR OUTPUT (V)
-112
DELTA (%)
-114
1.8
RSSI (V)
-108
-112
-116
-102
-106
fRF = 315MHz
0.01
-100
-104
0.1
fRF = 315MHz
-98
MAX7031 toc09
1
280kHz IF BW
0.2% BER
-96
SENSITIVITY (dBm)
SENSITIVITY (dBm)
10
fRF = 434MHz
-94
MAX7031 toc05
-100
MAX7031 toc04
280kHz IF BW
BIT-ERROR RATE (%)
SENSITIVITY vs. FREQUENCY DEVIATION
SENSITIVITY vs. TEMPERATURE
100
MAX7031 toc06
BIT-ERROR RATE
vs. AVERAGE INPUT POWER
SYSTEM GAIN (dBm)
MAX7031
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
30
-40
-15
10
35
60
85
110
1
TEMPERATURE (°C)
_______________________________________________________________________________________
10
IF FREQUENCY (MHz)
100
Low-Cost, 308MHz, 315MHz, and 433.92MHz
ASK Transceiver with Fractional-N PLL
RECEIVER
S11 vs. RF FREQUENCY
MAX7031 toc13
MAX7031 toc14
S11 SMITH PLOT OF RFIN
0
S11 (dB)
-6
434MHz
-12
433.92MHz
-18
400MHz
500MHz
-24
200
250
300
350
400
450
500
RF FREQUENCY (MHz)
INPUT IMPEDANCE
vs. INDUCTIVE DEGENERATION
INPUT IMPEDANCE
vs. INDUCTIVE DEGENERATION
-220
90
-230
80
MAX7031 toc16
-240
60
-250
50
-260
40
-270
REAL IMPEDANCE
20
10
1
-160
IMAGINARY
IMPEDANCE
70
60
-180
50
-190
40
-200
-280
30
-290
20
REAL IMPEDANCE
-220
PHASE NOISE vs. OFFSET FREQUENCY
MAX7031 toc17
fRF = 315MHz
PHASE NOISE vs. OFFSET FREQUENCY
-50
-70
-80
-90
-100
-110
fRF = 434MHz
-60
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
100
INDUCTIVE DEGENERATION (nH)
INDUCTIVE DEGENERATION (nH)
-60
-210
10
1
100
-50
-170
MAX7031 toc18
30
REAL IMPEDANCE (Ω)
IMAGINARY
IMPEDANCE
70
IMAGINARY IMPEDANCE (Ω)
REAL IMPEDANCE (Ω)
80
-150
fRF = 434MHz
fRF = 315MHz
IMAGINARY IMPEDANCE (Ω)
MAX7031 toc15
90
-70
-80
-90
-100
-110
-120
-120
100
1k
10k
100k
OFFSET FREQUENCY (Hz)
1M
10M
100
1k
10k
100k
1M
10M
OFFSET FREQUENCY (Hz)
_______________________________________________________________________________________
7
MAX7031
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VPAVDD = VAVDD = VDVDD = VHVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz. 4kbps Manchester
encoded, 0.2% BER deviation = ±50kHz, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VPAVDD = VAVDD = VDVDD = VHVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz. 4kbps Manchester
encoded, 0.2% BER deviation = ±50kHz, TA = +25°C, unless otherwise noted.)
TRANSMITTER
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
TA = +85°C
TA = +125°C
TA = -40°C
TA = +25°C
10
TA = +85°C
TA = +125°C
13
TA = -40°C
11
3.0
3.3
2.4
SUPPLY CURRENT vs. OUTPUT POWER
2.7
3.0
3.3
3.6
-14
-10
OUTPUT POWER (dBm)
12
11
10
9
8
fRF = 315MHz
12
2
6
fRF = 434MHz
TA = -40°C
12
TA = -40°C
10
8
TA = +125°C
6
-2
10
OUTPUT POWER vs. SUPPLY VOLTAGE
14
TA = +25°C
7
-6
AVERAGE OUTPUT POWER (dBm)
OUTPUT POWER vs. SUPPLY VOLTAGE
14
MAX7031 toc22
fRF = 434MHz
13
7
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
14
8
4
2.1
3.6
OUTPUT POWER (dBm)
2.7
MAX7031 toc 23
2.4
9
5
TA = +25°C
2.1
10
6
9
8
fRF = 315MHz
11
15
MAX7031 toc21
fRF = 434MHz
SUPPLY CURRENT (mA)
14
SUPPLY CURRENT vs. OUTPUT POWER
12
MAX7030 toc24
MAX7031 toc19
fRF = 315MHz
12
17
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
16
MAX7031 toc20
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT (mA)
TA = +25°C
10
8
TA = +125°C
TA = +85°C
6
TA = +85°C
6
4
4
-14
-10
-6
-2
2
6
10
2.1
2.4
AVERAGE OUTPUT POWER (dBm)
2.7
3.0
3.3
TA = -40°C
35
3.0
EFFICIENCY vs. SUPPLY VOLTAGE
fRF = 434MHz
TA = -40°C
35
EFFFICIENCY (%)
TA = +25°C
30
25
2.7
SUPPLY VOLTAGE (V)
40
MAX7031 toc25
fRF = 315MHz
2.4
SUPPLY VOLTAGE (V)
EFFICIENCY vs. SUPPLY VOLTAGE
40
2.1
3.6
MAX7031 toc26
5
EFFFICIENCY (%)
MAX7031
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
TA = +85°C
TA = +25°C
30
TA = +85°C
25
TA = +125°C
TA = +125°C
20
20
2.1
2.4
2.7
3.0
SUPPLY VOLTAGE (V)
8
3.3
3.6
2.1
2.4
2.7
3.0
3.3
3.6
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
3.3
3.6
Low-Cost, 308MHz, 315MHz, and 433.92MHz
ASK Transceiver with Fractional-N PLL
TRANSMITTER
fRF = 315MHz
-50
-70
-80
-90
-100
-110
-60
-120
-70
-80
-90
-100
-110
-120
-130
-130
-140
-140
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
REFERENCE SPUR MAGNITUDE
vs. SUPPLY VOLTAGE
FREQUENCY STABILITY
vs. SUPPLY VOLTAGE
-45
434MHz
-50
315MHz
-55
-60
-65
10
10M
MAX7031 toc30
MAX7031 toc29
-40
8
FREQUENCY STABILITY (ppm)
100
REFERENCE SPUR MAGNITUDE (dBc)
fRF = 434MHz
-50
PHASE NOISE (dBc/Hz)
-60
PHASE NOISE (dBc/Hz)
-40
MAX7031 toc27
-40
PHASE NOISE vs. OFFSET FREQUENCY
(TRANSMIT MODE)
MAX7031 toc28
PHASE NOISE vs. OFFSET FREQUENCY
(TRANSMIT MODE)
6
fRF = 315MHz
4
2
0
-2
fRF = 434MHz
-4
-6
-8
-70
-10
2.1
2.4
2.7
3.0
SUPPLY VOLTAGE (V)
3.3
3.6
2.1
2.4
2.7
3.0
3.3
3.6
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
9
MAX7031
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VPAVDD = VAVDD = VDVDD = VHVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz. 4kbps Manchester
encoded, 0.2% BER deviation = ±50kHz, TA = +25°C, unless otherwise noted.)
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
MAX7031
Pin Description
10
PIN
NAME
1
PAVDD
FUNCTION
Power-Amplifier Supply Voltage. Bypass to GND with 0.01µF and 220pF capacitors placed as close
as possible to the pin.
2
ROUT
Envelope-Shaping Output. ROUT controls the power-amplifier envelope’s rise and fall times. Connect
ROUT to the PA pullup inductor or optional power-adjust resistor. Bypass the inductor to GND as
close as possible to the inductor with 680pF and 220pF capacitors as shown in the Typical
Application Circuit.
3
TX/RX1
Transmit/Receive Switch Throw. Drive T/R high to short TX/RX1 to TX/RX2. Drive T/R low to disconnect
TX/RX1 from TX/RX2. Functionally identical to TX/RX2.
4
TX/RX2
Transmit/Receive Switch Pole. Typically connected to ground. See the Typical Application Circuit.
5
PAOUT
Power-Amplifier Output. Requires a pullup inductor to the supply voltage (or ROUT if envelope
shaping is desired), which can be part of the output-matching network to an antenna.
6
AVDD
7
LNAIN
Analog Power-Supply Voltage. AVDD is connected to an on-chip +3.0V regulator in 5V operation.
Bypass AVDD to GND with a 0.1µF and 220pF capacitor placed as close as possible to the pin.
Low-Noise Amplifier Input. Must be AC-coupled.
8
LNASRC
Low-Noise Amplifier Source for External Inductive Degeneration. Connect an inductor to GND to set
the LNA input impedance.
9
LNAOUT
Low-Noise Amplifier Output. Must be connected to AVDD through a parallel LC tank filter. AC-couple
to MIXIN+.
10
MIXIN+
Noninverting Mixer Input. Must be AC-coupled to the LNA output.
11
MIXIN-
Inverting Mixer Input. Bypass to AVDD with a capacitor as close as possible to the LNA LC tank filter.
12
MIXOUT
13
IFIN-
Inverting 330Ω IF Limiter Amplifier Input. Bypass to GND with a capacitor.
14
IFIN+
Noninverting 330Ω IF Limiter Amplifier Input. Connect to the output of the 10.7MHz IF filter.
330Ω Mixer Output. Connect to the input of the 10.7MHz filter.
15
PDMIN
16
PDMAX
Minimum-Level Peak Detector for Demodulator Output
17
DS-
Inverting Data Slicer Input
18
DS+
Noninverting Data Slicer Input
19
OP+
20
DF
21
RSSI
Maximum-Level Peak Detector for Demodulator Output
Noninverting Op-Amp Input for the Sallen-Key Data Filter
Data-Filter Feedback Node. Input for the feedback capacitor of the Sallen-Key data filter.
Buffered Received-Signal-Strength-Indicator Output
Transmit/Receive. Drive high to put the device in transmit mode. Drive low or leave unconnected to
put the device in receive mode. It is internally pulled down.
22
T/R
23
ENABLE
24
DATA
25
N.C.
26
DVDD
Digital Power-Supply Voltage. Bypass to GND with a 0.01µF and 220pF capacitor placed as close as
possible to the pin.
27
HVIN
High-Voltage Supply Input. For 3V operation, connect HVIN to AVDD, PAVDD, and DVDD. For 5V
operation, connect only HVIN to 5V. Bypass HVIN to GND with a 0.01µF and 220pF capacitor placed
as close as possible to the pin.
Enable. Drive high for normal operation. Drive low or leave unconnected to put the device into
shutdown mode.
Receiver Data Output/Transmitter Data Input
No Connection. Do not connect to this pin.
______________________________________________________________________________________
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
PIN
NAME
28
AUTOCAL
FUNCTION
29
AGC1
AGC Enable/Dwell Time Control 1. See Table 1. Bypass to GND with a 10pF capacitor.
30
AGC0
AGC Enable/Dwell Time Control 0 (LSB). See Table 1. Bypass to GND with a 10pF capacitor.
31
XTAL1
Crystal Input 1. Bypass to GND if XTAL2 is driven by an AC-coupled external reference.
32
XTAL2
Crystal Input 2. XTAL2 can be driven from an external AC-coupled reference.
—
EP
Exposed Pad. Solder evenly to the board’s ground plane for proper operation.
Enable (Logic-High) to Allow FSK Demodulator Calibration. Bypass to GND with a 10pF capacitor.
Detailed Description
The MAX7031 308MHz, 315MHz, and 433.92MHz
CMOS transceiver and a few external components provide a complete transmit and receive chain from the
antenna to the digital data interface. This device is
designed for transmitting and receiving FSK data. All
transmit frequencies are generated by a fractional-Nbased synthesizer, allowing for very fine frequency
steps in increments of fXTAL/4096. The receive local
oscillator (LO) is generated by a traditional integer-Nbased synthesizer. Depending on component selection, data rates as high as 33kbps (Manchester
encoded) or 66kbps (NRZ encoded) can be achieved.
Receiver
Low-Noise Amplifier (LNA)
The LNA is a cascode amplifier with off-chip inductive
degeneration that achieves approximately 30dB of voltage gain that is dependent on both the antenna-matching network at the LNA input, and the LC tank network
between the LNA output and the mixer inputs.
The off-chip inductive degeneration is achieved by connecting an inductor from LNASRC to AGND. This inductor sets the real part of the input impedances at LNAIN,
allowing for a more flexible match for low-input impedances such as a PCB trace antenna. A nominal value
for this inductor with a 50Ω input impedance is 12nH at
315MHz and 10nH at 434MHz, but the inductance is
affected by PCB trace length. LNASRC can be shorted
to ground to increase sensitivity by approximately 1dB,
but the input match must then be reoptimized.
The LC tank filter connected to LNAOUT consists of L5
and C9 (see the Typical Application Circuit). Select L5
and C9 to resonate at the desired RF input frequency.
The resonant frequency is given by:
f=
where LTOTAL = L5 + LPARASITICS and CTOTAL = C9 +
CPARASITICS.
LPARASITICS and CPARASITICS include inductance and
capacitance of the PCB traces, package pins, mixer
input impedance, LNA output impedance, etc. These
parasitics at high frequencies cannot be ignored, and
can have a dramatic effect on the tank filter center frequency. Lab experimentation should be done to optimize the center frequency of the tank. The parasitic
capacitance is generally 5pF to 7pF.
Automatic Gain Control (AGC)
When the AGC is enabled, it monitors the RSSI output.
When the RSSI output reaches 1.28V, which corresponds to an RF input level of approximately -55dBm,
the AGC switches on the LNA gain-reduction attenuator. The attenuator reduces the LNA gain by 36dB,
thereby reducing the RSSI output by about 540mV to
740mV. The LNA resumes high-gain mode when the
RSSI output level drops back below 680mV (approximately -59dBm at the RF input) for a programmable
interval called the AGC dwell time (see Table 1). The
AGC has a hysteresis of approximately 4dB. With the
AGC function, the RSSI dynamic range is increased.
AGC is not necessary for most FSK applications.
AGC Dwell Time Settings
The AGC dwell timer holds the AGC in a low-gain state
for a set amount of time after the power level drops
below the AGC switching threshold. After that set
amount of time, if the power level is still below the AGC
threshold, the LNA goes into high-gain state.
1
2π L TOTAL × C TOTAL
______________________________________________________________________________________
11
MAX7031
Pin Description (continued)
MAX7031
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
Table 1. AGC Dwell Time Settings for
MAX7031
AGC1
AGC0
0
0
AGC disabled, high gain selected
DESCRIPTION
0
1
K = 11, short dwell time
1
0
K = 14, medium dwell time
1
1
K = 20, long dwell time
The MAX7031 uses the two AGC control pins (AGC0
and AGC1) to enable or disable the AGC and set three
user-controlled dwell timer settings. The AGC dwell
time is dependent on the crystal frequency and the bit
settings of the AGC control pins. To calculate the dwell
time, use the following equation:
Dwell Time =
2K
fXTAL
where K is an integer in decimal, determined by the
control pin settings shown in Table 1.
For example, a receiver operating at 315MHz has a
crystal oscillator frequency of 12.679MHz. For K = 11
(AGC setting = 0, 1), the dwell timer is 162µs; for K =
14 (AGC setting = 1, 0), the dwell timer is 1.3ms; for K
= 20 (AGC setting = 1, 1), the dwell time is 83ms.
Mixer
A unique feature of the MAX7031 is the integrated
image rejection of the mixer. This eliminates the need
for a costly front-end SAW filter for many applications.
The advantage of not using a SAW filter is increased
sensitivity, simplified antenna matching, less board
space, and lower cost.
The mixer cell is a pair of double-balanced mixers that
perform an IQ downconversion of the RF input to the
10.7MHz intermediate frequency (IF) with low-side
injection (i.e., fLO = fRF - fIF). The image-rejection circuit
then combines these signals to achieve a typical 46dB
of image rejection over the full temperature range. Lowside injection is required as high-side injection is not
possible due to the on-chip image rejection. The IF output is driven by a source follower, biased to create a
driving impedance of 330Ω to interface with an off-chip
330Ω ceramic IF filter. The voltage conversion gain driving a 330Ω load is approximately 20dB. Note that the
MIXIN+ and MIXIN- inputs are functionally identical.
Integer-N, Phase-Locked Loop (PLL)
The MAX7031 utilizes a fixed integer-N PLL to generate
the receive LO. All PLL components, including the loop
filter, voltage-controlled oscillator, charge pump, asynchronous 24x divider, and phase-frequency detector
are internal. The loop bandwidth is approximately
500kHz. The relationship between RF, IF, and reference
frequencies is given by:
fREF = (fRF - fIF)/24
Intermediate Frequency (IF)
The IF section presents a differential 330Ω load to provide matching for the off-chip ceramic filter. The internal
six AC-coupled limiting amplifiers produce an overall
gain of approximately 65dB, with a bandpass filter-type
response centered near the 10.7MHz IF frequency with
a 3dB bandwidth of approximately 10MHz. The RSSI
circuit demodulates the IF to baseband by producing a
DC output proportional to the log of the IF signal level
with a slope of approximately 15mV/dB.
FSK Demodulator
The FSK demodulator uses an integrated 10.7MHz PLL
that tracks the input RF modulation and converts the
frequency deviation into a voltage difference. The PLL
is illustrated in Figure 1. The input to the PLL comes
from the output of the IF limiting amplifiers. The PLL
control voltage responds to changes in the frequency
of the input signal with a nominal gain of 2.0mV/kHz.
For example, an FSK peak-to-peak deviation of 50kHz
FSK
DEMOD
MAX7031
TO FSK BASEBAND FILTER
AND DATA SLICER
PHASE
DETECTOR
IF
LIMITING
AMPS
CHARGE
PUMP
LOOP
FILTER
100kΩ
100kΩ
10.7MHz VCO
2.0mV/kHz
DS+
OP+
DF
CF2
Figure 1. FSK Demodulator PLL Block Diagram
12
CF1
Figure 2. Sallen-Key Lowpass Data Filter
______________________________________________________________________________________
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
MAX7031
MAX7031
MAX7031
DATA
SLICER
DATA
DS-
PEAK
DET
PEAK
DET
DATA
SLICER
DS+
R
PDMAX
R
DATA
PDMIN
R
C
C
C
Figure 3. Generating Data Slicer Threshold Using a Lowpass
Filter
Figure 4. Generating Data Slicer Threshold Using the Peak
Detectors
generates a 100mVP-P signal on the control line. This
control voltage is then filtered and sliced by the baseband circuitry.
The FSK demodulator PLL requires calibration to overcome variations in process, voltage, and temperature.
This is done by cycling the ENABLE pin when the
AUTOCAL pin is a logic 1. If the AUTOCAL pin is a
logic 0, calibration cannot occur.
and a rolloff rate of 40dB/decade for the two-pole filter.
The Bessel filter has a linear phase response, which
works well for filtering digital data. To calculate the
value of the capacitors, use the following equations,
along with the coefficients in Table 2:
Data Filter
The data filter for the demodulated data is implemented
as a 2nd-order, lowpass Sallen-Key filter. The pole
locations are set by the combination of two on-chip
resistors and two external capacitors. Adjusting the
value of the external capacitors changes the corner frequency to optimize for different data rates. Set the corner frequency in kHz to approximately 2 times the
fastest expected Manchester data rate in kbps from the
transmitter (1.0 times the fastest expected NRZ data
rate). Keeping the corner frequency near the data rate
rejects any noise at higher frequencies, resulting in an
increase in receiver sensitivity.
The configuration shown in Figure 2 can create a
Butterworth or Bessel response. The Butterworth filter
offers a very-flat-amplitude response in the passband
b
a(100kΩ)(π)(fc )
a
CF2 =
4(100kΩ)(π)(fc )
CF1 =
where fC is the desired 3dB corner frequency.
For example, choose a Butterworth filter response with
a corner frequency of 5kHz:
1.000
≈ 450pF
(1.414)(100kΩ)(3.14)(5kHz)
1.414
CF2 =
≈ 225pF
(4)(100kΩ)(3.14)(5kHz)
CF1 =
Choosing standard capacitor values changes CF1 to
470pF and CF2 to 220pF. In the Typical Application
Circuit , C F1 and C F2 are named C16 and C17,
respectively.
Table 2. Coefficients to Calculate C F1
and CF2
FILTER TYPE
a
b
Butterworth
(Q = 0.707)
1.414
1.000
Bessel
(Q = 0.577)
1.3617
0.618
______________________________________________________________________________________
13
MAX7031
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
Data Slicer
The data slicer takes the analog output of the data filter
and converts it to a digital signal. This is achieved by
using a comparator and comparing the analog input to
a threshold voltage. The threshold voltage is set by the
voltage on the DS- pin, which is connected to the negative input of the data-slicer comparator.
Numerous configurations can be used to generate the
data-slicer threshold. For example, the circuit in Figure
3 shows a simple method using only one resistor and
one capacitor. This configuration averages the analog
output of the filter and sets the threshold to approximately 50% of that amplitude. With this configuration,
the threshold automatically adjusts as the analog signal
varies, minimizing the possibility for errors in the digital
data. The values of R and C affect how fast the threshold tracks the analog amplitude. Be sure to keep the
corner frequency of the RC circuit much lower (about
10 times) than the lowest expected data rate.
With this configuration, a long string of NRZ zeros or
ones can cause the threshold to drift. This configuration
works best if a coding scheme, such as Manchester
coding, which has an equal number of zeros and ones,
is used.
Figure 4 shows a configuration that uses the positive and
negative peak detectors to generate the threshold. This
configuration sets the threshold to the midpoint between
a high output and a low output of the data filter.
Peak Detectors
The maximum peak detector (PDMAX) and minimum
peak detector (PDMIN), with resistors and capacitors
shown in Figure 4, create DC output voltages equal to
the high- and low-peak values of the filtered demodulated signal. The resistors provide a path for the capacitors to discharge, allowing the peak detectors to
dynamically follow peak changes of the data filter output voltages.
The maximum and minimum peak detectors can be
used together to form a data slicer threshold voltage at
a value midway between the maximum and minimum
voltage levels of the data stream (see the Data Slicer
section and Figure 4). Set the RC time constant of the
peak-detector combining network to at least 5 times the
data period.
If there is an event that causes a significant change in
the magnitude of the baseband signal, such as an AGC
gain switch or a power-up transient, the peak detectors
may “catch” a false level. If a false peak is detected,
the slicing level is incorrect. The MAX7031 peak detectors correct these problems by temporarily tracking the
incoming baseband filter voltage when an AGC state
14
switch occurs, or by forcing the peak detectors to track
the baseband filter output voltage until all internal circuits are stable following an enable pin low-to-high
transition. The peak detectors exhibit a fast attack/slow
decay response. This feature allows for an extremely
fast startup or AGC recovery.
Transmitter
Power Amplifier (PA)
The PA of the MAX7031 is a high-efficiency, opendrain, switch-mode amplifier. The PA with proper output- matching network can drive a wide range of
antenna impedances, which includes a small-loop PCB
trace and a 50Ω antenna. The output-matching network
for a 50Ω antenna is shown in the Typical Application
Circuit. The output-matching network suppresses the
carrier harmonics and transforms the antenna impedance to an optimal impedance at PAOUT (pin 5). The
optimal impedance at PAOUT is 250Ω.
When the output-matching network is properly tuned,
the PA transmits power with a high overall efficiency of
up to 32%. The efficiency of the PA itself is more than
46%. The output power is set by an external resistor at
PAOUT, and is also dependent on the external antenna
and antenna-matching network at the PA output.
Envelope Shaping
The MAX7031 features an internal envelope-shaping
resistor, which connects between the open-drain output
of the PA and the power supply. The envelope-shaping
resistor slows the turn-on/turn-off of the PA. Envelope
shaping is not necessary for FSK. For most applications, the PA pullup inductor should be connected to
PAVDD instead of ROUT.
Fractional-N Phase-Locked Loop (PLL)
The MAX7031 utilizes a fully integrated, fractional-N
PLL for its transmit frequency synthesizer. All PLL components, including the loop filter, are integrated internally. The loop bandwidth is approximately 200kHz.
Power-Supply Connections
The MAX7031 can be powered from a 2.1V to 3.6V supply or a 4.5V to 5.5V supply. If a 4.5V to 5.5V supply is
used, then the on-chip linear regulator reduces the 5V
supply to the 3V needed to operate the chip.
To operate the MAX7031 from a 3V supply, connect
PAVDD, AVDD, DVDD, and HVIN to the 3V supply.
When using a 5V supply, connect the supply to HVIN
only and connect AVDD, PAVDD, and DVDD together.
In both cases, bypass PAVDD, DVDD, and HVIN to
GND with a 0.01µF and 220pF capacitor and bypass
AVDD to GND with a 0.1µF and 220pF capacitor.
______________________________________________________________________________________
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
where:
fP is the amount the crystal frequency is pulled in ppm.
Cm is the motional capacitance of the crystal.
CCASE is the case capacitance.
CSPEC is the specified load capacitance.
CLOAD is the actual load capacitance.
When the crystal is loaded as specified, i.e., CLOAD =
CSPEC, the frequency pulling equals zero.
Chip Information
PROCESS: CMOS
Pin Configuration
N.C.
25
DVDD
HVIN
ENABLE
T/R
RSSI
DF
OP+
DS+
DS-
TOP VIEW
24
23
22
21
20
19
18
17
16
PDMAX
26
15
PDMIN
27
14
IFIN+
AUTOCAL
28
13
IFIN-
AGC1
29
12
MIXOUT
AGC0
30
11
MIXIN-
XTAL1
31
10
MIXIN+
XTAL2
32
9
LNAOUT
4
5
6
7
8
AVDD
LNAIN
LNASRC
3
PAOUT
2
TX/RX2
1
PAVDD
+
MAX7031
ROUT
Crystal Oscillator (XTAL)
The XTAL oscillator in the MAX7031 is designed to present a capacitance of approximately 3pF between the
XTAL1 and XTAL2 pins. In most cases, this corresponds to a 4.5pF load capacitance applied to the
external crystal when typical PCB parasitics are added.
It is very important to use a crystal with a load
capacitance that is equal to the capacitance of the
MAX7031 crystal oscillator plus PCB parasitics. If a
crystal designed to oscillate with a different load
capacitance is used, the crystal is pulled away from its
stated operating frequency, introducing an error in the
reference frequency. Crystals designed to operate with
higher differential load capacitance always pull the reference frequency higher.
⎞
Cm ⎛
1
1
−
x 106
⎜
2 ⎝ CCASE + CLOAD
CCASE + CSPEC ⎟⎠
TX/RX1
The switch state is controlled by the T/R pin (pin 22).
Drive T/R high to put the device in transmit mode; drive
T/R low to put the device in receive mode.
fP =
DATA
Transmit/Receive Antenna Switch
The MAX7031 features an internal SPST RF switch that,
when combined with a few external components, allows
the transmit and receive pins to share a common antenna (see the Typical Application Circuit) . In receive
mode, the switch is open and the power amplifier is
shut down, presenting a high impedance to minimize
the loading of the LNA. In transmit mode, the switch
closes to complete a resonant tank circuit at the PA output and forms an RF short at the input to the LNA. In
this mode, the external passive components couple the
output of the PA to the antenna to protect the LNA input
from strong transmitted signals.
In actuality, the oscillator pulls every crystal. The crystal’s natural frequency is really below its specified frequency, but when loaded with the specified load
capacitance, the crystal is pulled and oscillates at its
specified frequency. This pulling is already accounted
for in the specification of the load capacitance.
Additional pulling can be calculated if the electrical
parameters of the crystal are known. The frequency
pulling is given by:
THIN QFN
______________________________________________________________________________________
15
MAX7031
Bypass T/R, ENABLE, DATA, AGC0-1, and AUTOCAL
with 10pF capacitors to GND. Place all bypass capacitors as close to the respective pins as possible.
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
MAX7031
Typical Application Circuit
AGC0
AGC1
AUTOCAL
VDD
Y1
VDD
C22
2
27
26
25
N.C.
28
DVDD
29
HVIN
PAVDD
30
AUTOCAL
1
31
AGC1
32
AGC0
VDD
XTAL1
C23
C24
C19
C18
C20
C21
XTAL2
3.0V
24
DATA
ROUT
23
ENABLE
R3*
C1
4
L1
5
VDD
6
C5
OP+
19
C17
C6
L4
LNAIN
LNASRC
9
11
10
C10
12
C12
C9
13
C13
15
14
PDMAX
8
PDMIN
DS+
7
IFIN+
L6
IFIN-
L3
EXPOSED
PAD
AVDD
MIXOUT
C7
C8
20
DF
PAOUT
MIXIN-
C4
C3
21
RSSI
MAX7031
TX/RX2
MIXIN+
L2
TRANSMIT/
RECEIVE
TX/RX1
LNAOUT
C2
ENABLE
22
T/R
3
DATA
DS-
16
C16
18
17
R1
C15
VDD
L5
IN
C11
GND
Y2
R2
OUT
C14
*OPTIONAL POWER-ADJUST RESISTOR
Selector Guide
PART
CARRIER
FSK DEVIATION
FREQUENCY (MHz) FREQUENCY (kHz)
MAX7031LATJ+†
308
±51.413
MAX7031MATJ15+
315
±15.477
MAX7031MATJ50+
315
±49.528
MAX7031HATJ17+
433.92
±17.221
MAX7031HATJ51+
433.92
±51.663
+Denotes a lead(Pb)-free/RoHS-compliant package.
†Contact factory for availability.
16
______________________________________________________________________________________
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
MAX7031
Table 3. Component Values for Typical Application Circuit
COMPONENT
VALUE FOR
433.92MHz RF
VALUE FOR
315MHz RF
DESCRIPTION
C1
220pF
220pF
10%
C2
680pF
680pF
10%
C3
6.8pF
12pF
5%
C4
6.8pF
10pF
5%
C5
10pF
22pF
5%
C6
220pF
220pF
10%
C7
0.1µF
0.1µF
10%
C8
100pF
100pF
5%
C9
1.8pF
2.7pF
±0.1pF
C10
100pF
100pF
5%
C11
220pF
220pF
10%
C12
100pF
100pF
5%
C13
1500pF
1500pF
10%
C14
0.047µF
0.047µF
10%
C15
0.047µF
0.047µF
10%
C16
470pF
470pF
10%
C17
220pF
220pF
10%
C18
220pF
220pF
10%
C19
0.01µF
0.01µF
10%
C20
100pF
100pF
5%
C21
100pF
100pF
5%
C22
220pF
220pF
10%
C23
0.01µF
0.01µF
10%
C24
0.01µF
0.01µF
10%
L1
22nH
27nH
Coilcraft 0603CS
L2
22nH
30nH
Coilcraft 0603CS
L3
22nH
30nH
Coilcraft 0603CS
L4
10nH
12nH
Coilcraft 0603CS
L5
16nH
30nH
Murata LQW18A
L6
68nH
100nH
Coilcraft 0603CS
R1
100kΩ
100kΩ
5%
R2
100kΩ
100kΩ
5%
R3
0Ω
0Ω
—
Y1
17.63416MHz
12.67917MHz
Crystal, 4.5pF load
capacitance
Y2
10.7MHz ceramic filter
10.7MHz ceramic filter
Murata SFECV10.7 series
Note: Component values vary depending on PCB layout.
______________________________________________________________________________________
17
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
MAX7031
Functional Diagram
LNAOUT MIXIN+ MIXIN9
10
MIXOUT
IFIN+
IFIN-
12
14
13
11
IF LIMITING
AMPS
0°
LNAIN
7
LNA
FSK
DEMODULATOR
Σ
LNASRC
8
90°
I
Q
RSSI
20 DF
100kΩ
19 OP+
RX
FREQUENCY
DIVIDER
XTAL1
21 RSSI
DATA FILTER
18 DS+
31
CRYSTAL
OSCILLATOR
XTAL2
100kΩ
RX VCO
PHASE
DETECTOR
32
TX
FREQUENCY
DIVIDER
15 PDMIN
CHARGE
PUMP
16 PDMAX
TX VCO
HVIN 27
3.0V
REGULATOR
∆Σ
MODULATOR
LOOP FILTER
17 DSRX
DATA
AVDD
6
EXPOSED
PAD
MAX7031
30 AGC0
PA
29 AGC1
DIGITAL LOGIC
28 AUTOCAL
24 DATA
18
2
1
5
3
4
22
26
23
ROUT
PAVDD
PAOUT
TX/RX1
TX/RX2
T/R
DVDD
ENABLE
______________________________________________________________________________________
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
32 TQFN-EP
T3255+3
21-0140
90-0001
______________________________________________________________________________________
19
MAX7031
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
MAX7031
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
Revision History
PAGES
CHANGED
REVISION
NUMBER
REVISION
DATE
0
5/05
Initial release
—
9/08
Added + to each part to denote lead-free/RoHS-compliant package and explicitly
calling out the odd frequency as contact factory for availability
16
1
DESCRIPTION
2
6/09
Made correction in Power Amplifer (PA) section
3
11/10
Updated AUTOCAL pin function description and FSK Demodulator section
14
11, 12
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.