LANSDALE MC13145FTA Uhf wideband receiver subsystem Datasheet

ML13145
UHF Wideband Receiver Subsystem
(LNA, Mixer, VCO, Prescaler, IF
Subsystem, Coiless Detector)
LOW POWER INTEGRATED RECEIVER FOR ISM BAND APPLICATIONS
SEMICONDUCTOR TECHNICAL DATA
Legacy Device: Motorola MC13145
The ML13145 is a dual conversion integrated RF receiver intended for ISM
band applications. It features a Low Noise Amplifier (LNA), two 50 Ω linear
Mixers with linearity control, Voltage Controlled Oscillator (VCO), second
LO amplifier, divide by 64/65 dual modulus Prescalar, split IF Amplifier and
Limiter, RSSI output, Coilless FM/FSK Demodulator and power down control. Together with the transmit chip (ML13146) and the baseband chip
(MC33410 or MC33411A/B), a complete 900 MHz cordless phone system
can be implemented. This device may be used in applications up to 1.8 GHz,
and operating temperature TA = –20° to +70°C.
48
1
LQFP 48 = -9P
PLASTIC PACKAGE
CASE 932
CROSS REFERENCE/ORDERING INFORMATION
• Low (<1.8 dB @ 900 MHz) Noise Figure LNA with 14 dB Gain
PACKAGE
MOTOROLA
LANSDALE
• Externally Programmable Mixer linearity: IIP3 = 10(nom.) to 17 dBm
LQFP
48
MC13145FTA
ML13145-9P
(Mixer1); IIP3 = 10 (nom.) to 17 dBm (Mixer2)
• 50 Ω Mixer Input Impedance and Open Collector Output (Mixer 1 and
Note: Lansdale lead free (Pb) product, as it
Mixer 2); 50 Ω Second LO (LO2) Input Impedance
becomes available, will be identified by a part
• Low Power 64/65 Dual Modulus Prescalar (ML12054A type)
number prefix change from ML to MLE.
• Split IF for Improved Filtering and Extended RSSI Range
• Internal 330 Ω Terminations for 10.7 MHz Filters
• Linear Coilless FM/FSK Demodulator with Externally Programmable Bandwidth,
Center Frequency and Audio level
•2.7 to 6.5 V Operation, Low Current Drain (<27 mA, Typ @ 3.6 V) with Power Down
Mode (<10 µA, Typ)
•2.4 GHz RF, 1.0 GHz IF1 and 50 MHz IF2 Bandwidth
V CC
V CC
MC
P R S C O ut
VEE
R SSI
D et O ut
D et G ain
A F T In
A F T O ut
Fadj
VEE
PIN CONNECTIONS AND FUNCTIONAL BLOCK DIAGRAM
12
11
10
9
8
7
6
5
4
3
2
1
V EE 13
48 V EE
Demod
47 BWadj
LNA In 14
V EE 15
V EE 16
Page 1 of 17
45 Lim Dec1
44 Lim In
43 V CC
Mxr1In 19
42 V CC
Lin Adj1 20
41 IF Out
C ontrol
V EE 18
40 IF Dec2
IF
29
30
31
32 33
34
35
36
IF 2–
28
IF 2+
27
V EE
26
V EE
25
LO 2
37 V EE
VCC
oscB 24
Mxr2In
38 IF In
LinA dj2
oscE 23
IF 1–
39 IF Dec1
IF 1+
oscC 22
V EE
ESD Sensitive —
Handle with Care
Lim
LNA Out 17
Enable 21
LO
/64, 65
VCC
RF
46 Lim Dec2
LNA
IF1
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IF2
This device contains
626 active transistors.
Issue 0
LANSDALE Semiconductor, Inc.
ML13145
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Power Supply Voltage
VCC(max)
7.0
Vdc
Junction Temperature
TJ(max)
150
°C
Storage Temperature Range
Tstg
– 65 to 150
°C
Maximum Input Signal
Pin
5.0
dBm
NOTES: 1. Meets Human Body Model (HBM) ≤250 V and Machine Model (MM) ≤25 V.
RECOMMENDED OPERATING CONDITIONS
Rating
Power Supply Voltage (TA = 25°C)
Symbol
Min
Typ
Max
Unit
VCC
VEE
2.7
–
6.5
Vdc
0
0
0
Input Frequency (LNA In, Mxr1 In)
fin
100
–
1800
MHz
Ambient Temperature Range
TA
– 20
–
70
°C
Input Signal Level (with minor performance degradation)
Pin
–
–10
–
dBm
RECEIVER DC ELECTRICAL CHARACTERISTICS (TA = 25°C; VCC = 3.6 Vdc; No Input Signal,
unless otherwise noted)
Characteristics
Symbol
Min
Typ
Max
Unit
Total Supply Current (Enable = VCC)
Itotal
24
27
34
mA
Power Down Current (Enable = VEE)
Itotal
–
10
50
A
RECEIVER AC ELECTRICAL CHARACTERISTICS (TA = 25°C; VCC = 3.6 Vdc; RF In = 1.0 GHz; 1st LO Freq = 1070.7 MHz; 2nd
LO Freq = 60 MHz; fmod = 1.0 kHz; fdev = ± 40 kHz; IF filter bandwidth = 280 kHz, unless otherwise noted. See Figure 1 Test Circuit)
Input
Pin
Measure
Pin
Symbol
MIn
Typ
Max
Unit
SINAD @ –110 dBm LNA Input
LNA In
Det Out
SINAD
12
20
–
dB
12 dB SINAD Sensitivity (Apps Circuit with
C–message filter at DetOut)
LNA In
Det Out
SINAD12dB
–
–115
–
dBm
30 dB SINAD Sensitivity (No IF filter distortion within
±40 kHz)
LNA In
Det Out
SINAD30dB
–
–100
–
dBm
SINAD Variation with IF Offset of ±40 kHz (No IF filter
distortion within ±40 kHz)
LNA In
Det Out
–
–
5.0
–
dB
Noise Figure: LNA, 1st Mixer & 2nd Mixer
LNA In
IF Out
NF
–
3.5
5.0
dB
Power Gain: LNA, 1st Mixer & 2nd Mixer
LNA In
IF Out
G
15
19
25
dB
RSSI Dynamic Range
IF In
RSSI
–
–
80
–
dB
RSSI Current
–10 dBm @ IF Input
–20 dBm @ IF Input
–30 dBm @ IF Input
–40 dBm @ IF Input
–50 dBm @ IF Input
–60 dBm @ IF Input
–70 dBm @ IF Input
–80 dBm @ IF Input
–90 dBm @ IF Input
IF In
RSSI
–
35
–
–
–
15
–
–
–
–
40
35
30
25
20
15
10
5.0
1.0
55
–
–
–
37
–
–
–
7.0
Characteristics
µA
Input 1.0 dB Compression Point(Measured at IF
output)
Pin1dB
–
–18
–
dBm
Input 3rd Order Intercept Point (Measured at IF
output)
IIP3
–
–8.0
–
dBm
Vout
0.8
1.0
1.2
Vpp
Demodulator Output Swing (50 k || 56 pF Load)
Page 2 of 17
IF In
Det Out
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LANSDALE Semiconductor, Inc.
ML13145
RECEIVER AC ELECTRICAL CHARACTERISTICS (TA = 25°C; VCC = 3.6 Vdc; RF In = 1.0 GHz; 1st LO Freq = 1070.7 MHz; 2nd
LO Freq = 60 MHz; fmod = 1.0 kHz; fdev = ± 40 kHz; IF filter bandwidth = 280 kHz, unless otherwise noted. See Figure 1 Test Circuit)
Input
Measure
Pin
Pin
Characteristics
Symbol
MIn
Typ
Max
Unit
Demodulator Bandwidth (±1.0 dB bandwidth)
Det Out
BW
–
100
–
Prescalar Output Level (10 k //8.0 pF load)
Prescaler 64 Frequency = 16.72968 MHz
Prescaler 65 Frequency = 16.4723 MHz
PRSCout
Vout
MC Current Input (High)
MC
MC Current Input (Low)
0.4
0.4
0.51
0.51
0.6
0.6
Iih
70
100
130
µA
MC
Iil
–130
–100
–70
µA
Input high voltage
Enable
Vih
VCC
– 0.4
–
VCC
V
Input low voltage
Enable
Vil
0
–
0.4
V
Input Current
Enable
Iin
–50
–
50
µA
PRSCout
TPLL
–
10
–
nS
SNR @ –30 dBm Signal Input (<40 kHz
deviation;with C–Message Filter)
–
50
–
dB
Total Harmonic Distortion (<40 kHz deviation;with
C–Message Filter)
–
1.0
–
%
Spurious Response SINAD (RF In: –50 dBm)
–
12
–
dB
PLL Setup Time [Note 1]
Page 3 of 17
MC
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kHz
Vpp
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LANSDALE Semiconductor, Inc.
ML13145
Figure 1. Test Circuit
MC
PRSC Out
10 k
7.2 p
10 n
1.0 n
RSSI
2.0 k
51 k
2.0 k
56 p
10 k
3
2
48
46
64/65
LNA
Lim
18
ML13145
21
1.0 n
4.7 p
3.3 nH
4.7 p
43
V CC
42
41
40
IF
22
1.0 n
100 n
39
1.0 n
38
23
24
47 p
V CC
C ontrol
20
1.0 n
1.0 n
44
19
EN
100 n
10M7
1.0 p
1.0 n
45
17
1.0 M
100 k
47
V CC
25
37
V CC
26
27
28
29
30
31
32
33
34
35
*C F 2
BWadj
*C F 1
6.8 n
1
F adj
4
16
20
36
10 n
1.0 M
1.0 n
10 p
1.0 k
50
16 p
V CC
1.0 µ
100 n
T1**
12 p
100 n
10
1.0 µ
1.0 n
RF LO2
10 n
1.0 n
IF In
10
1.0 µ
*CF1 & CF2 = 280 kHz, 6.0 dB BW, 10.7 MHz Ceramic Filter
**T1 = Toko Part # 600ENAS–A998EK
Page 4 of 17
5
2.7 k
10M7
15
RF LO
6
A F T O ut
7
AFT
13
1.5 p
14
1.0 n
8
D et G ain
9
D et O ut
6.8 p
10
100 n 68 k
V CC V CC
6.8 n
100 p
11
R SSI
LNA In
12
P R S C O ut
1.0 n
MC
51 k
Det Out
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100 n
T2
TC4
IF Out
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LANSDALE Semiconductor, Inc.
ML13145
Low Noise Amplifier (LNA)
The LNA is a cascoded common emitter amplifier configuration. Under very large RF input signals, the DC base current
of the common emitter and cascode transistors can become
very significant. To maintain linear operation of the LNA, adequate dc current source is needed to establish the 2Vbe reference at the base of the RF cascoded transistor and to provide
the base voltage on the common emitter transistor. A sensing
circuit, together with a current mirror guarantees that there is
always sufficient DC base current available for the cascode
transistor under all power levels.
1st and 2nd Mixer
Each mixer is a double–balanced class AB four quadrant
multiplier which may be externally biased for high mixer
dynamic range. Mixer input third order intercept point of up
to17 dBm is achieved with only 7.0 mA of additional supply
current. The 1st mixer has a single–ended input at 50 Ω and
operates at 1.0 GHz with –3.0 dB of power gain at approximately 100 mVrms LO drive level. The mixers have open collector differential outputs to provide excellent mixer dynamic
range and linearity.
1st Local Oscillator
The 1st LO has an on–chip transistor which operates with
coaxial transmssion line and LC resonant elements up to 1.8
GHz. A VCO output is available for multi–frequency operation
under PLL synthesizer control.
RSSI
The received signal strength indicator (RSSI) output is a current proportional to the log of the received signal amplitude.
The RSSI current output (Pin 7) is derived by summing the
currents from the IF and limiting amplifier stages. An increase
in RSSI dynamic range, particularly at higher input signal levels is achieved. The RSSI circuit is designed to provide typical-
Page 5 of 17
IF Amplifier
The first IF amplifier section is composed of three differential stages with the second and third stages contributing to the
RSSI. This section has internal DC feedback and external input
decoupling for improved symmetry and stability. The total gain
of the IF amplifier block is approximately 40 dB up to 40MHz.
The fixed internal input impedance is 330 Ω. When using
ceramic filters requiring source and load impedances of 330Ω,
no external matching is necessary. Overall RSSI linearity is
dependent on having total midband attenuation of 10 dB (4.0
dB insertion loss plus 6.0 dB impedance matching loss) for the
filter. The output of the IF amplifier is buffered and the impedance is 330 Ω.
Limiter
The limiter section is similar to the IF amplifier section
except that five stages are used with the middle three contributing to the RSSI. The fixed internal input impedance is
330 Ω. The total gain of the limiting amplifier section is
approximately 84 dB. This IF limiting amplifier section internally drives the coilless quadrature detector section.
Coilless Quadrature Detector
The coilless detector is a unique design which eliminates the
conventional tunable quadrature coil in FM receiver systems.
The frequency detector implements a phase locked loop with a
fully integrated on chip relaxation oscillator which is current
controlled and externally adjusted, a bandwidth adjust, and an
automatic frequency tuning circuit. The loop filter is external
to the chip allowing the user to set the loop dynamics. Two
outputs are used: one to deliver the audio signal (detector output) and the other to filter and tune the detector (AFT).
Figure 2. 2nd Mixer NF & Gain
versus LO Power
25
20
15
–4.0
–6.0
NF
10
–8.0
Gain
5.0
0
–14
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–2.0
G A IN
Current Regulation/Enable
The ML13145 is designed for battery powered portable
applications. Supply current is typically 27 mA at 3.6 Vdc.
Temperature compensating, voltage independent current regulators are controlled by the Enable Pin where ”high” powers
up and ”low” powers down the entire circuit.
ly 80 dB of dynamic range with temperature compensation.
Linearity of the RSSI is optimized by using external ceramic
bandpass filters which have an insertion loss of 4.0 dB and
330 Ω source and load impedance.
N O IS E F IG U R E ( dB)
General
The ML13145 is a low power dual conversion wideband FM
receiver incorporating a split IF. This device is designated for
use as the receiver in analog and digital FM systems such as
900 Mhz ISM Band Cordless phones and wideband data links
with data rates up to 150kbps. It contains a 1st and 2nd mixer,
1st and 2nd local oscillator, Received Signal Strength Indicator
(RSSI), IF amplifier, limiting IF, a unique coilless quadrature
detector, and a device enable function.
–9.0
–4.0
–1.0
V CC = 3.6 Vdc
TA = 25°C
P RF = –25 dBm
Lim Adj Current = 0
–10
6.0
–12
11
LO POWER (dBm)
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LANSDALE Semiconductor, Inc.
ML13145
PIN FUNCTION DESCRIPTION
Pin
Symbol/Type
Description
Description
47
BWadj
2
Fadj
Frequency Adjust
The free running frequency of the detector
oscillator is defined by the combination of an
on–chip capacitor and an external resistor, Radj
from frequency adjust pin to ground.
1, 48
VEE
VEE, Negative Supply
These pins are VEE supply for the coilless detector
circuit.
3
AFT Out
AFT Out
The AFT is low pass filtered with a corner frequency
below the audio bandwidth allowing the error to be
added to the center frequency adjust signal at Fadj,
Pin 2. The low frequency high pass corner is set by
the external capacitor, Ct from AFT out (Pin 3) to
AFT in (Pin 4) and external resistor, Rt from AFT
out to Fadj (Pin 2).
4
AFT In
5
Det Gain
Detector Gain
The AFT buffer is used to set the buffer transfer
function.
6
Det Out
Detector Output
Set gain and output level of detector with resistor to
Det Out Pin.
See Figure 3.
COILLESS DETECTOR
Bandwidth Adjust
The deviation bandwidth of the detector response is
determined by the combination of an on–chip
capacitor and an external resistor to ground.
AFT In
The AFT in is used to set the buffer transfer
function.
Figure 3. Coilless Detector Internal Circuit
i
Current Amplifier
i
Phase
Detector
ICO
V CC
V CC
IF
4
A*i
A*i
5
AFT In
V ref2
Fadj
V ref1
BWadj
2Ib
RI
Ct
2
Rt
3
AFT Out
47
Rb
6
Det Out
Rf
2I
V EE
48, 1
Page 6 of 17
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LANSDALE Semiconductor, Inc.
Pin
Symbol/Type
8
VEE
ML13145
Description
Description
VEE, Negative Supply Voltage
11
V CC
9
Prescaler Output
The prescaler output provides typically 500 mVpp
drive to the fin pin of a PLL synthesizer. Conjugately
matching the interface will increase the drive
delivered to the PLL input.
PRSCout
9
PRSC Out
1.0 mA
8
10
MC
V CC
V EE
Dual Modulus Control Current Input
This requires a current input of typically 200 µApp.
10
MC
11, 12
VCC
14
LNA In
VCC, Positive Supply
VCC pin is taken to the incoming positive battery or
regulated dc voltage through a low impedance trace
on the PCB. It decoupled to VEE ground at the pin
of the IC.
17
LNA In
The input is the base of the common emitter
transistor. Minimum external matching is required to
optimize the input return loss and gain.
LNA out
15, 16
V EE
13, 15,
& 16
VEE
133
V ref2
V EE
14
V ref1
LNA in
2.0 mA
11,12
VEE, Negative Supply
VEE pin is taken to an ample dc ground plane
through a low impedance path. The path should be
kept as short as possible. A minimum two sided
PCB is recommended so that ground returns can
be easily made through via holes.
V CC
17
LNAout
19
Mxr1In
LNA Out
The output is from the collector of the cascode
transistor amplifier. The output may be conjugately
matched with a shunt L (needed to dc bias the open
collector), and series L and C network.
1st Mixer Input
The mixer input impedance is broadband 50 Ω for
applications up to 2.4 GHz. It easily interfaces with
a RF ceramic filter.
V CC
20
LinAdj1
20
Lin Adj1
19
Mxr1 In
450 µA
Page 7 of 17
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1st Mixer Linearity Control
The mixer linearity control circuit accepts
approximately 0 to 300 µA control current to set the
dynamic range of the mixer. An Input Third Order
Intercept Point, IIP3 of 17 dBm may be achieved at
300 µA of control current.
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LANSDALE Semiconductor, Inc.
ML13145
Pin
Symbol/Type
21
Enable
Description
Description
Enable
Enable the receiver by pulling the pin up to VCC.
21
10 k
Enable
26
VEE, Negative Supply
VEE supply for the mixer IF output.
VEE
27
27
IF1+
IF1+
1st Mixer Outputs
The Mixer is a differential open collector output
configuration which is designed to use over a wide
frequency range. The differential output of the mixer
has back to back diodes across them to limit the
output voltage swing and to prevent pulling of the
VCO. Differential to single–ended circuit
configuration and matching options are shown in
the Test Circuit. Additional mixer gain can be
achieved by matching the outputs for the desired
passband Q.
26
V EE
28
IF1–
22
Collector
288
IF1–
On–board VCO Transistor
The transistor has the emitter, base, collector, VCC,
and VEE pins available. Internal biasing which is
compensated for stability over temperature is
provided. It is recommended that the base pin is
pulled up to VCC through an RFC chosen for the
particular oscillator center frequency .
25
23
Emitter
V CC
24
24
Base
25
VCC
Base
18, 26
VCC, Positive Supply Voltage
A VCC pin is provided for the VCO. The operating
supply voltage range is from 2.7 Vdc to 6.5 Vdc.
V EE
23
Emitter
18, 26
VEE
2.0 mA
500 µA
VEE, Negative Supply Voltage
22
Collector
29
Lin Adj2
31, V CC
29
Lin Adj2
30
Mxr2 In
2nd Mixer Input
The mixer input impedance is broadband 50 Ω.
30
Mxr2 In
31
Page 8 of 17
VCC
2nd Mixer Linearity Control
The mixer linearity control circuit accepts
approximately 0 to 400 µA control current to set the
dynamic range of the mixer. An Input Third Order
Intercept Point, IIP3 of 17 dBm may be achieved at
400 µA of control current. IIP3 default with no
external bias is 10 dBm.
450 µA
µ
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VCC, Positive Supply
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LANSDALE Semiconductor, Inc.
Pin
Symbol/Type
32, 34
VEE
ML13145
Description
Description
VEE, Negative Supply Voltage
V CC
LO Out+
LO Out–
33
(to Mxr2)
2nd Local Oscillator
The 2nd LO input impedance is broadband 50 Ω; it
is driven from an external 50 Ω source. Typical level
is –15 to –10 dBm.
LO2
33
LO2
390 µA
32
V EE
35
IF2+
2nd Mixer Outputs
The Mixer is a differential open collector
configuration.
35
IF2+
34
V EE
36
IF2–
36
IF2–
See Figure 4.
VEE, Negative Supply Voltage
37
VEE
38
IF In
IF Amplifier Input
IF amplifier input source impedance is 330 Ω.. The
three stage amplifier has 40 dB of gain with 3.0 dB
bandwidth of 40 MHz.
39, 40
IF Dec1,
IF Dec2
IF Decoupling
These pins are decoupled to VCC to provide stable
operation of the limiting IF amplifier.
41
IF Out
42
VCC
VCC, Positive Supply Voltage
7
RSSI
RSSI
The RSSI circuitry in the 2nd & 3rd amplifier stages
outputs a current when the output of the previous
stage enters limiting. The net result is a RSSI
current which represents the logarithm of the IF
input voltage. An external resistor to ground is used
to provide a voltage output.
Page 9 of 17
IF Amplifier Output
IF amplifier output load impedance is 330 Ω.
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LANSDALE Semiconductor, Inc.
ML13145
Figure 4. IF Amplifier Functional Diagram
RSSI
39
IF Dec1
Σ
38
IF In
40
IF Dec2
41
IF Out
Pin
Symbol/Type
Description
43
VCC
44
Lim In
Limiting Amplifier Input
Limiting amplifier input source impedance is 330 Ω.
This amplifier has 84 dB of gain with 3.0 dB
bandwidth of 40 MHz; this enables the IF and
limiting ampliers chain to hard limit on noise.
45, 46
Lim Dec1,
Lim Dec2
If Decoupling
These pins are decoupled to VCC to provide stable
operation of the 2nd IF limiting amplifier.
7
RSSI
RSSI
The RSSI circuitry in the 2nd, 3rd, & 4th amplifier
stages outputs a current when the output of the
previous stage enters limiting. The net result is a
RSSI current which represents the logarithm of the
IF input voltage. An external resistor to ground is
used to provide a voltage output.
See Figure 5.
Description
VCC, Positive Supply Voltage
Figure 5. Limiter Amplifier Functional Diagram
7
RSSI
45
Lim Dec1
Σ
44
Lim+
Lim In
46
Demod
Lim–
Lim Dec2
Page 10 of 17
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LANSDALE Semiconductor, Inc.
Figure 6. 2nd Mixer Gain
versus LO Drive
–6.0
V CC = 3.6 V
TA = 25°C
P RF = –25 dBm
Lin Adj Current = 400µA
5.0
4.0
–6.8
–7.2
3.0
2.0
–7.6
–18
18
–16
–14
–12
0
–20
–10
–12
Figure 9. 2nd Mixer Gain
versus Lin Adj Current
–6.0
V CC = 3.6 V
TA = 25°C
P LO = –15 dBm
Adj Channel = 75 kHz
10
8.0
G A IN ( dB)
dBm
–14
Figure 8. 2nd Mixer IP3/P1dB
versus Lin Adj Current
IP3
P 1dB
4.0
–16
LO DRIVE (dBm)
–6.2
6.0
–18
LO DRIVE (dBm)
16
12
V CC = 3.6 V
TA = 25°C
Lin Adj Current = 400µA
1.0
–8.0
–20
14
Figure 7. 2nd Mixer P1dB
versus LO Drive
6.0
P1dB ( dB)
G A IN ( dB)
–6.4
ML13145
–6.4
–10
V CC = 3.6 V
TA = 25°C
P LO = –15 dBm
P RF = –25 dBm
–6.6
–6.8
2.0
0
0
100
200
300
400
500
–7.0
0
600
100
LIN ADJ CURRENT ( µA)
200
300
400
500
600
LIN ADJ CURRENT ( µA)
Figure 10. Test Circuit for Figures 6 thru 9.
Lin Adj
Current
RF in
LO2 in
5.1 k
29 Lin Adj2
V CC
10 n
30 Mxr2 In
33 LO2
IF2+
35
IF2–
1.0 k
36
T1
IF out
16:1
T1 = Toko 600ENAS–A998EK
Page 11 of 17
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LANSDALE Semiconductor, Inc.
ML13145
Figure 11. Fadj Current
versus IF Frequency
500
7.0
450
6.0
F adj R E S IS TO R ( K Ω )
400
C U R R ENT ( µ A )
Figure 12. Fadj Resistor
versus IF Frequency
350
300
250
200
5.0
4.0
3.0
2.0
150
100
5.0
10
15
1.0
5.0
20
10
IF FREQUENCY (MHz)
10.85
IF F R E Q U E N C Y ( MH z)
C U R R ENT ( µ A )
700
600
500
400
300
10.80
10.75
10.70
10.65
10.60
200
2.0
3.0
4.0
5.0
6.0
10.55
1.0
BWadj CURRENT ( µA)
Page 12 of 17
Figure 14. IF Frequency
versus BWadj Current
10.90
800
100
1.0
20
IF FREQUENCY (MHz)
Figure 13. BWadj Resistor
versus BWadj Current
900
15
2.0
3.0
4.0
5.0
6.0
BWadj CURRENT ( µA)
www.lansdale.com
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LANSDALE Semiconductor, Inc.
ML13145
Table 1. LNA S–Parameters: 3.6 Vdc
Freq
(MHz)
S11
Mag
S11
Ang
S21
Mag
S21
Ang
S12
Mag
S12
Ang
S22
mag
S22
Ang
25
0.84
–3.0
10.8
176
0.00005
–27
1.0
–1.2
50
0.84
–71
10.7
171
0.0004
76
1.0
–3.7
100
0.83
–15
10.3
162
0.0006
61
0.99
–4.9
150
0.81
–22
10.
154
0.0011
91
0.99
–7.3
200
0.78
–28
9.6
147
0.001
60
0.99
–9.7
300
0.73
–41
9.0
132
0.002
42
0.99
–15
400
0.66
–50
7.8
116
0.00070
22
0.95
–19
450
0.64
–54
7.4
111
0.0014
39
0.96
–21
500
0.62
–59
7.0
106
0.0009
69
0.96
–23
750
0.51
–77
5.5
80
0.0013
–51
0.94
–33
800
0.49
–80
5.2
75
0.002
–80
0.93
–36
850
0.47
–81
4.9
71
0.004
–120
0.92
–37
900
0.46
–82
4.6
67
0.0057
–130
0.92
–38
950
0.44
––82
4.3
62
0.008
–142
0.91
–40
1000
0.45
–81
3.9
58
0.014
–162
0.95
–41
1250
0.55
–94
3.5
47
0.029
140
0.099
–50
1500
0.48
–120
3.1
24
0.02
63
0.94
–65
1750
0.43
–126
2.5
6.9
0.0066
79
0.93
–74
2000
0.43
–135
2.1
–9.9
0.0099
129
0.92
–85
2250
0.45
–145
1.8
–27
0.017
133
0.91
–96
2500
0.47
–155
1.5
–43
0.021
132
0.89
–106
2750
0.51
–167
1.2
–60
0.03
130
0.88
–118
3000
0.55
–180
1.0
–78
0.039
120
0.85
–129
Page 13 of 17
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Page 14 of 17
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TP 2
L6 R F C
LO 2
FRx
R X MC
Rx PD
D et O ut
R SSI
Rx EN
C 40 10
C 50 1.0
C 15 0.01
C 44 100 p
R x MC
Rx EN
C 41 100 p
C 42 100 p
C 43 100 p
VC C
VC C
L7 2.7 n
C 39 1.0 n
C 38 1.0 n
C 37 1.0 n
C 36 1.0 n
IF 10
R 3 33 k
D 1 MMBV 809
R 12 U /D
R 6 51 k
C 35 0.01
R 11 68 k
R 10 2.7 k
R 9 68 k
C 34 1.0 n
R 8 U /D
C 33 1.0 n
R 7 U /D
VC C
C 46 2.0 p
C 47 2.0 p
R 13
51
C 16 0.01
C 48 100 p
C 13 100 p
C 12 1.0 n
C 3 100 p
C 2 1.5 p
L1 6.8 n
10 MC
21 E nable
4 A F T In
3 A F T O ut
2 F adj
47 BWadj
29 Lin A dj2
20 Lin A dj1
33 LO 2
30 Mxr2 In
24 oscB
23 oscE
22 oscC
19 Mxr1 In
14 LN A In
L8
U /D
C 32 0.01
C 54 1.0 n
R 14 51 k
FRx
R SSI
P R S C O ut 9
R SSI 7
C 20 30 p
L5 2.7
L4 2.7
C 52 U /D
T1
R 2 10
D et O ut
C 31 100 p
R 5 27 k
C 29 1.0 n
C 30 0.1
C 28 1.0 n
C 27 1.0 n
C 25 0.1
C 26 1.0 n
C 19 36 p
L9
U /D
C 9 16 p
C 7 100 p
C 8 0.01
D et O ut 6
D et G ain 5
Lim In 44
Lim D ec2 46
Lim D ec1 45
IF In 38
IF O ut 41
IF D ec2 40
IF D ec1 39
IF 2– 36
IF 2+ 35
IF 1– 28
IF 1+ 27
LN A O ut 17
C 45
3.3 p
VC C
CF3
H 5X 2
1
2
3
4
5
6
7
8
9
10
JP 1
C 49 22
Mxr2 In
Rx PD
C 14
2.0 – 4.0 p
480/481
C 51 100 p
CF1
C 1 100 p
L2
5.6 n
C 5 100 p
R1
C 6 1.0 n
U /D
CF2
G nd
VC C
TP 1
oscB
Mxr1 In
LN A I n
U1
ML13145
Figure 15. ML 13145 Evaluation PCB Schematic
VC C
IF In
C 24 0.1
C 23 1.0 n
TP 4
IF O ut
IF 1 O ut
IF 10
VC C
C 18 0.01
C 17 100 p
IF 1 O ut
TP 5
C 53 0.01
C 22 0.1
C 21 1.0 n
JP 2 Jumper
T P 3 IF 2 I/O
C 10 10 p
C 11 12 p
VC C
LN A O ut
ML13145
LANSDALE Semiconductor, Inc.
Figure 15.
Issue 0
LANSDALE Semiconductor, Inc.
ML13145
Legacy Applications Information
Figure 16. Evaluation PCB Component Side
Figure 17. Evaluation PCB Solder Side
2.25″
2.25″
2.5″
CF1
CF2,CF3
C1, C3, C5, C7, C13, C17, C31,
C41, C42, C43, C44, C48, C51
C2
C6, C12, C21, C23, C26, C27,
C28, C29, C33, C34, C36, C37,
C38, C39, C54
C8, C15, C16, C18, C32, C53
C9
C10
C11
C14
C19
C20
C22, C24, C25, C30, C35
R2, C40
Page 15 of 17
2.5″
480/481
10.7M
100 p
1.5 p
1.0 n
0.01
16 p
10 p
12 p
2.0–4.0 p
36 p
39 p
0.1
10
C45
C46, C47
C49
C50
R1, R7, R8, L8, L9, R12, C52
L1
L2
L4, L5
L6
L7
R3
R5
R6,R14
R11,R9
R10
R13
T1
U1
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3.3 p
2.0 p
22
1.0
U/D
6.8 n
5.6 n
2.7
RFC
2.7 n
33 k
27 k
51 k
68 k
2.7 k
51
A099
ML13145
Issue 0
LANSDALE Semiconductor, Inc.
ML13145
Legacy Applications Information
Page 16 of 17
www.lansdale.com
Issue 0
LANSDALE Semiconductor, Inc.
ML13145
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s
technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
Page 17 of 17
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Issue 0