LINER LTC3701 2-phase, low input voltage, dual step-down dc/dc controller Datasheet

LTC3701
2-Phase, Low Input Voltage,
Dual Step-Down DC/DC Controller
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FEATURES
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DESCRIPTIO
The LTC®3701 is a 2-phase dual constant frequency current mode step-down DC/DC controller providing excellent
load and line regulation. Power loss and noise due to ESR
of the input capacitor are minimized by operating the two
controller output stages out-of-phase.
Out-of-Phase Controllers Reduce Required
Input Capacitance
True PLL for Frequency Locking or Frequency
Adjustment
Operating Frequency Range: 300kHz to 750kHz
Wide VIN Range: 2.5V to 10V
Constant Frequency Current Mode Architecture
Low Dropout: 100% Duty Cycle
Power Good Output Voltage Monitor
Internal Soft-Start Circuitry
Selectable Burst Mode®/Pulse Skipping Operation
at Light Loads
Output Overvoltage Protection
Low Quiescent Current: 460µA
0.8V ±2% Voltage Reference
Small 16-Lead Narrow SSOP Package
The LTC3701 provides a 0.8V ±2% voltage reference and
consumes only 460µA of quiescent current. To further
maximize the life of a battery source, the external
P-channel MOSFET is turned on continuously in dropout
(100% duty cycle).
Switching frequency is internally set at 550kHz, allowing
the use of small inductors and capacitors. For noise sensitive applications, the LTC3701 can be externally synchronized using its phase-locked loop. The frequency can
also be externally set from 300kHz to 750kHz by applying
a voltage to the PLLLPF pin. Burst Mode operation is inhibited during synchronization or when the EXTCLK/MODE
pin is pulled low to reduce noise and RF interference.
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APPLICATIO S
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One or Two Lithium-Ion Powered Applications
Notebook and Handheld Computers
Personal Digital Assistants
Portable Instruments
Distributed DC Power Systems
The LTC3701 contains independent internal soft-start
circuitry for each controller. Other features include a
power good output voltage monitor and output overvoltage and short-circuit protection.
The LTC3701 is available in a small footprint 16-lead narrow SSOP package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation.
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TYPICAL APPLICATIO
VIN
2.5V TO 9.8V
Efficiency vs Load Current
100
169k
80.6k
100k
10k
220pF
SENSE1 –
VFB1
SENSE1 +
16
15
VIN
14
ITH/RUN1
PGATE1
13
4
LTC3701
SGND
PGND
12
6
ITH/RUN2
PGATE2
11
5
PGOOD
VFB2
10
7
PLLLPF EXTCLK/MODE
9
8
SENSE2 +
SENSE2 –
0.03Ω
M1
2
10k
220pF
L1
4.7µH
D1
+
47µF
D2
M2
0.03Ω
D1, D2: IR10BQ015 L1, L2: LQN6C-4R7 M1, M2: FDC638P
VOUT1
2.5V
2A
10µF
47µF
L2
4.7µH
3701 F01a
Figure 1. High Efficiency 2-Phase 550kHz Dual Step-Down Converter
VOUT2
1.8V
2A
VIN = 4.2V
VIN = 3.3V
90
EFFICIENCY (%)
78.7k
3
+
1
80
VIN = 6V
VIN = 8.4V
70
60
50
VOUT = 2.5V
40
1
100
1000
10
LOAD CURRENT (mA)
10000
3701 F01b
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LTC3701
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ABSOLUTE
RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
Input Supply Voltage (VIN)........................ – 0.3V to 10V
SENSE1 –, SENSE2 –, PGATE1, PGATE2,
PLLLPF, SENSE1+, SENSE2 +,
EXTCLK/MODE Voltages .............. – 0.3V to (VIN + 0.3V)
VFB1, VFB2, ITH/RUN1,
ITH/RUN2 Voltages .................................. – 0.3V to 2.4V
PGOOD Voltage ........................................ – 0.3V to 10V
PGATE1, PGATE2 Peak Output Current (<10µs) ....... 1A
Operating Ambient Temperature Range
(Note 2) ...................................................–40°C to 85°C
Storage Ambient Temperature Range ... – 65°C to 150°C
Junction Temperature (Note 3) ............................ 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
TOP VIEW
SENSE1–
1
16 SENSE1+
ITH/RUN1
2
15 VIN
VFB1
3
14 PGATE1
SGND
4
13 PGND
VFB2
5
12 PGATE2
ITH/RUN2
6
11 PGOOD
PLLLPF
7
10 EXTCLK/MODE
SENSE2 –
8
9
LTC3701EGN
GN PART
MARKING
SENSE2 +
3701
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 140°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN = 4.2V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
460
305
9
18
780
470
28
30
µA
µA
µA
µA
1.55
1.70
2.00
2.12
2.50
2.55
V
V
Main Control Loops
Input DC Supply Current
Normal Operation
Sleep Mode
Shutdown
UVLO
(Note 4)
2.5V < VIN < 9.8V
2.5V < VIN < 9.8V
2.5V < VIN < 9.8V, ITH/RUN1 = ITH/RUN2 = 0V
VIN < UVLO Threshold
Undervoltage Lockout Threshold
VIN Falling
VIN Rising
●
Shutdown Threshold at ITH/RUN1, 2
0.2
0.35
0.5
V
0.25
0.5
0.85
µA
0.784
0.774
0.8
0.8
0.816
0.826
V
V
2.5V < VIN < 9.8V (Note 5)
0.05
0.20
mV/V
Output Voltage Load Regulation
ITH/RUN = 0.9V (Note 5)
ITH/RUN = 1.6V
0.2
– 0.2
0.8
– 0.8
%
%
VFB1, 2 Input Current
(Note 5)
10
50
nA
Output Overvoltage Protect Threshold
Measured at VFB
0.88
0.930
V
Start-Up Current Source on ITH/RUN1, 2
VITH/RUN1, 2 = 0V
Regulated Feedback Voltage
0°C to 70°C (Note 5), ITH/RUN = 1.3V
–40°C to 85°C (Note 5)
Output Voltage Line Regulation
●
●
0.835
Output Overvoltage Protect Hysteresis
20
mV
Gate Drive 1, 2 Rise Time
CL = 3000pF
40
ns
Gate Drive 1, 2 Fall Time
CL = 3000pF
40
ns
Maximum Current Sense Voltage (SENSE + – SENSE–)
(Note 6)
Soft-Start
Current Sense Voltage Step
Time to Maximum Sense Voltage
95
120
30
2048
145
mV
mV
Cycles
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LTC3701
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN = 4.2V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VPLLLPF = 1.2V or Floating
VPLLLPF = 0V
VPLLLPF ≥ 2.4V
500
230
690
550
280
775
600
320
890
kHz
kHz
kHz
Oscillator and Phase-Locked Loop
Oscillator Frequency
Phase Detector Output Current
Sinking
Sourcing
µA
µA
fEXTCLK/MODE < fOSC
fEXTCLK/MODE > fOSC
–5
5
PGOOD Voltage Low
IPGOOD = 500µA
70
150
mV
PGOOD Trip Level
VFB with Respect to Set Output Voltage
VFB Ramping Positive
VFB Ramping Negative
–8
8
–2.5
15
%
%
PGOOD Output
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC3701E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula:
TJ = TA + (PD • θJA°C/W)
–15
2.5
Note 4: Dynamic supply current is higher due to gate charge being
delivered at the switching frequency.
Note 5: The LTC3701 is tested in a feedback loop that servos ITH/RUN to a
specified voltage and measures the resultant VFB voltage.
Note 6: Peak current sense voltage is reduced dependent on duty cycle to
a percentage of value as given in Figure 2.
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TYPICAL PERFOR A CE CHARACTERISTICS
Shutdown Threshold
vs Temperature
0.810
VIN = 4.2V
ITH/RUN VOLTAGE (V)
REFERENCE VOLTAGE (V)
0.805
0.800
0.795
0.790
0.785
0.780
0.775
20 40 60
–60 –40 –20 0
TEMPERATURE (°C)
80
100
3701 G01
0.50
0.48 VIN = 4.2V
0.46
0.44
0.42
0.40
0.38
0.36
0.34
0.32
0.30
0.28
0.26
0.24
0.22
0.20
20
40 60
–60 –40 –20 0
TEMPERATURE (°C)
Oscillator Frequency
vs Temperature
1000
900
800
FREQUENCY (kHz)
Reference Voltage vs Temperature
VIN = 4.2V
PLLLPF = 2.4V
700
600
PLLLPF = FLOAT
500
400
300
PLLLPF = 0V
200
100
80 100
3701 G02
0
–60 –40 –20 0 20 40 60
TEMPERATURE (°C)
80
100
3701 G03
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LTC3701
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TYPICAL PERFOR A CE CHARACTERISTICS
Undervoltage Lockout Trip
Voltage (Falling) vs Temperature
Undervoltage Lockout Trip
Voltage (Rising) vs Temperature
Maximum Current Sense
Threshold vs Temperature
MAXIMUM CURRENT SENSE THRESHOLD (mV)
2.20
2.15
2.18
2.16
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
2.10
2.05
2.00
1.95
2.14
2.12
2.10
2.08
2.06
2.04
1.90
2.02
1.85
–60 –40 –20 0
20 40 60
TEMPERATURE (°C)
80
100
2.00
–60 –40 –20 0 20 40 60
TEMPERATURE (°C)
80
3701 G04
115
110
105
100
20
40 60
–60 –40 –20 0
TEMPERATURE (°C)
3701 G06
100
FIGURE 1 CIRCUIT
EXTCLK/MODE = GND
90 VOUT = 2.5V
400
EFFICIENCY (%)
PULSE SKIPPING MODE OPERATION
(EXTCLK/MODE = 0V)
500
BURST MODE OPERATION
(EXTCLK/MODE = VIN)
300
FIGURE 1 CIRCUIT
200
LOAD CURRENT = 0A
100
70
VIN = 6V
60
40
3
4
VIN = 4.2V
50
SHUTDOWN
(ITH/RUN1,2 = 0V)
2
9
5
7
8
6
INPUT VOLTAGE (V)
10
11
1
100
100O
10
LOAD CURRENT (mA)
1OOOO
3701 G08
PGOOD RON vs Input Voltage
500
VIN = 3.3V
VIN = 8.4V
80
3701 G07
2-Phase Operation
IPGOOD = 500µA
450
SW1
5V/DIV
400
PGOOD RDS(ON) (Ω)
80 100
Efficiency vs Load Current (Pulse
Skipping Mode)
600
INPUT CURRENT (µA)
120
3701 G05
Input and Shutdown Currents vs
Input Voltage
0
100
125
350
SW2
5V/DIV
300
INPUT
CURRENT
1A/DIV
250
200
150
FIGURE 1 CIRCUIT
100
500ns/DIV
50
0
0
1
2
3 4 5 6 7
INPUT VOLTAGE (V)
8
9
10
3701 G09
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LTC3701
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PI FU CTIO S
SENSE1–, SENSE2– (Pins 1, 8): The (–) Inputs to the
Differential Current Comparators.
ITH/RUN1, ITH/RUN2 (Pins 2, 6): These pins each serve
two functions. Each pin serves as the error amplifier
compensation point as well as the run control input for the
respective controller. Forcing one pin below 0.35V causes
the functions associated with that controller to be shut
down. Forcing both ITH/RUN pins below 0.35V causes the
device to be shut down. Nominal operating voltage range
on these pins is from 0.7V to 1.9V.
VFB1, VFB2 (Pins 3, 5): Each receives the remotely sensed
feedback voltage for each controller from an external
resistive divider across the output.
SGND (Pin 4): Signal Ground.
PLLLPF (Pin 7): Serves as the lowpass filter point for the
PLL and as the voltage control input to the internal
oscillator. Normally, a series RC is connected between this
pin and ground when synchronizing to an external clock.
Nominal voltage range is from 0V to 2.4V. Frequency can
be set by forcing this pin with a voltage. Tying this pin to
GND selects 300kHz. Tying to VIN or a voltage ≥ 2.4V
selects 750kHz. Floating this pin selects 550kHz operation.
SENSE2+ (PVIN2), SENSE1+ (PVIN1) (Pins 9, 16): The (+)
Inputs to the Differential Current Comparators. These pins
also power the gate drivers.
EXTCLK/MODE (Pin 10): External Clock Input. Applying a
clock to this pin causes the internal oscillator to phaselock to the external clock (nominal lock frequency range
between 300kHz and 750kHz). This also disables Burst
Mode operation but allows pulse-skipping at low load
currents.
Forcing this pin high enables Burst Mode operation.
Forcing this pin low enables pulse-skipping mode. In
these cases, the frequency of the internal oscillator is set
by the voltage on the PLLLPF pin. If the PLLLPF voltage is
not set externally, the frequency internally defaults to
550kHz.
PGOOD (Pin 11): Power Good Output Voltage Monitor
Open-Drain Logic Output. This pin is pulled to ground
when the voltage on either feedback pin (VFB1, VFB2) is not
within ±8% of its nominal set point. PGOOD is pulled low
when channel 1 or both channels are shut down. When
channel 2 is shut down and channel 1 enabled, the
PGOOD output indicates the state of VFB1 only.
PGATE2, PGATE1 (Pins 12, 14): Gate Drivers for the
External P-Channel MOSFETs. These pins swing from 0 to
SENSE+ (PVIN).
PGND (Pin 13): Ground Pin for Gate Drivers.
VIN (Pin 15): Chip Signal Power Supply Input. This pin
powers the entire chip except for the gate drivers.
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LTC3701
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RSENSE1
L1
M1
VOUT
VIN
CIN
SENSE1 +
15 VIN
COUT
D1
16
1
SENSE1 –
SLOPE1
–
CLK1
S
ICMP
VOLTAGE
REFERENCE
VREF
0.8V
Q
R
+
OV1
UV
EXTCLK/MODE
PLLLPF
SCP
–
BURSTDIS
PHASE
DETECTOR
0.3V
+
–
0.5µA
VFB1
R1
+
–
SLOPE
COMP
SLOPE1
VIN
VREF
0.8V
ITH/RUN1
SLOPE2
0.35V
SHDN1
PGOOD1
PGOOD
CLK1
100Ω
4
SGND
2
RC
+
VIN
11
3
EAMP
CLK1
VOLTAGE
CONTROLLED CLK2
OSCILLATOR
CC
0.880V
+
SC1
10k
RC
13
R2
CLOCK DETECT
7
–
SLEEP1
0.3V
BURSTDIS
14
OVP
–
SHDN1
SHDN2
10
PGND
+
UVSD
0.15V
BURST DEFEAT
PGATE1
+
VIN
UNDERVOLTAGE
LOCKOUT
PVIN1
SWITCHING
LOGIC AND
BLANKING
CIRCUIT
SOFT-START
ITH
CLAMP
CC
–
SHDN1
PGOOD2
SHDN2
PGOOD1
OV1
+
0.74V
–
DUPLICATE FOR SECOND CHANNEL
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LTC3701
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OPERATIO
(Refer to Functional Diagram)
Main Control Loop
The LTC3701 uses a constant frequency, current mode
architecture with the two controller channels operating
180 degrees out of phase. During normal operation, each
external P-channel power MOSFET is turned on when the
clock for that channel sets the RS latch, and turned off
when the current comparator (ICMP) resets the latch. The
peak inductor current at which ICMP resets the RS latch is
controlled by the voltage on the ITH/RUN pin, which is the
output of each error amplifier, EAMP. The VFB pin receives
the voltage feedback signal, which is compared to the
internal reference voltage by the EAMP. When the load
current increases, it causes a slight decrease in VFB
relative to the 0.8V reference, which in turn, causes the ITH/
RUN voltage to increase until the average inductor current
matches the new load current.
Each main control loop is shut down by pulling the
respective ITH/RUN pin low. When both ITH/RUN1 and ITH/
RUN2 are low, all LTC3701 controller functions are shut
down. Releasing ITH/RUN allows an internal 0.5µA current
source to charge up the external compensation network.
When the ITH/RUN pin reaches 0.35V, the main control
loop is enabled with the ITH/RUN voltage then pulled up to
its zero current level of approximately 0.7V. After the loop
is enabled, an internal soft-start begins. During this softstart time of 2048 clock cycles, the ITH/RUN voltage is
clamped such that the maximum peak current sense
voltage (VSENSE + – VSENSE –) is held to approximately 0%,
25%, 50% and 75%, respectively, of its maximum value of
120mV for four equally timed intervals. After soft-start is
completed, full current operation is allowed. As the external compensation network continues to charge, the corresponding output current trip level follows, allowing normal
operation.
Comparator OVP guards against transient output voltage
overshoots greater than 10% by turning off the external
P-channel power MOSFET and keeping it off until the fault
is removed.
Burst Mode Operation
VIN or to a voltage of at least 2V. To disable Burst Mode
operation and enable PWM pulse skipping mode, connect
the EXTCLK/MODE pin to ground. In this mode, the
efficiency is lower at light loads. However, pulse skipping
mode has the advantages of lower output ripple and less
interference to audio circuitry.
When a controller is in Burst Mode operation, the peak
current of the inductor is set as if VITH/RUN = 1V, even
though the voltage at the ITH/RUN pin is at a lower value.
If the inductor’s average current is greater than the load
requirement, the voltage at the ITH/RUN pin will drop.
When the ITH/RUN voltage goes below 0.85V, the sleep
signal goes high, turning off the external MOSFET. The
sleep signal goes low when the ITH/RUN voltage goes
above 0.925V and that controller channel resumes normal
operation. The next oscillator cycle will turn the external
MOSFET on and the switching cycle repeats.
Frequency Synchronization
A phase-locked loop (PLL) is available on the LTC3701 to
allow the internal oscillator to be synchronized to an
external clock source connected to the EXTCLK/MODE
pin. The output of the phase detector at the PLLLPF pin
operates over a 0V to 2.4V range corresponding to approximately 300kHz to 750kHz. When locked, the PLL
aligns the turn-on of the external MOSFET of controller
channel 1 to the rising edge of the synchronizing signal.
The turn-on of the external MOSFET of controller channel
2 is 180 degrees out of phase with the rising edge of the
external clock source.
When the LTC3701 is clocked by an external source, Burst
Mode operation is disabled and the LTC3701 operates in
PWM pulse skipping mode. In this mode, when the output
load is very low, the current comparator ICMP may remain
tripped for several cycles and force the external MOSFET
to stay off for the same number of cycles. Increasing the
output load slightly allows constant frequency PWM operation to resume. This mode exhibits low output ripple as
well as low audio noise and reduced RF interference while
providing reasonable low current efficiency.
The LTC3701 can be enabled to enter Burst Mode operation at low load currents by tying the EXTCLK/MODE pin to
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LTC3701
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OPERATIO
(Refer to Functional Diagram)
Dropout Operation
Slope Compensation and Peak Inductor Current
When the input supply voltage decreases towards the
output voltage, the rate of change of the inductor current
during the ON cycle decreases. This reduction means that
the external P-channel MOSFET will remain on for more
than one oscillator cycle if the inductor current has not
ramped up to the threshold set by EAMP on the ITH/RUN
pin. Further reduction in input supply voltage will eventually cause the P-channel MOSFET to be turned on 100%,
i.e., DC. The output voltage will then be determined by the
input voltage minus the voltage drop across the MOSFET,
the sense resistor and the inductor.
The inductor’s peak current is determined by:
IPK =
VITH/RUN – 0.7 V
10 • RSENSE
when the LTC3701 is operating below 20% duty cycle.
However, once the duty cycle exceeds 20%, slope
compensation begins and effectively reduces the peak
inductor current. The amount of reduction is given by the
curve in Figure 2.
110
100
Undervoltage Lockout
Short-Circuit Protection
When an output is shorted to ground (VFB < 0.3V), the
switching frequency of that channel is reduced to 1/5 of
the normal operating frequency. The other controller
channel is unaffected and maintains normal operation.
This lower frequency allows the inductor current to safely
discharge, thereby preventing current runaway. The switching frequency will return to its normal value when the
feedback voltage rises above 0.3V. During the first 64
cycles (nonzero-current cycles) of soft-start, however, the
controller operates at its full frequency.
Output Overvoltage Protection
As a further protection, the overvoltage comparator in the
LTC3701 will turn the external MOSFET off when the
feedback voltage has risen 10% above the reference
voltage of 0.8V. This comparator has a typical hysteresis
of 20mV.
80
SF = I/IMAX (%)
To prevent operation of the P-channel MOSFET below safe
input voltage levels, an undervoltage lockout is incorporated into the LTC3701. When the input supply voltage
drops below 2V, the P-channel MOSFET and all circuitry
are turned off except the undervoltage block, which draws
only several microamperes.
90
70
60
50
40
30
20
10
0
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
3701 F02
Figure 2. Maximum Peak Current vs Duty Cycle
Power Good (PGOOD) Pin
A window comparator monitors both output voltages and
the open-drain PGOOD output is pulled low when the
divided down output voltages are not within ±8% of the
reference voltage of 0.8V. PGOOD is pulled low when
channel 1 or both channels are shut down. When channel␣ 2 is shut down and channel 1 enabled, the PGOOD
output indicates the state of channel 1 only.
2-Phase Operation
The LTC3701 dual switching controller offers the considerable benefits of using 2-phase operation. Circuit benefits include lower input filtering requirements, reduced
electromagnetic interference (EMI) and increased efficiency associated with 2-phase operation.
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LTC3701
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OPERATIO
(Refer to Functional Diagram)
Why the need for 2-phase operation? Until recently, constant frequency dual switching regulators operated both
channels in phase (i.e., single phase operation). This
means that both topside MOSFETs are turned on at the
same time, causing current pulses of up to twice the
amplitude of those from a single regulator to be drawn
from the input capacitor. These large amplitude pulses
increase the total RMS current flowing into the input
capacitor, requiring the use of more expensive input
capacitors, and increasing both EMI and losses in the
input capacitor and input power supply.
With 2-phase operation, the two channels of the LTC3701
are operated 180 degrees out of phase. This effectively
interleaves the current pulses coming from the switches,
greatly reducing the overlap time where they add
together. The result is a significant reduction in the total
RMS input current, which in turn allows for use of less
expensive input capacitors, reduces shielding requirements
for EMI and improves real world operating efficiency.
Figure 3 shows example waveforms for a single switching
regulator channel versus a 2-phase LTC3701 system with
Single Phase
Dual Controller
2-Phase
Dual Controller
both channels switching. A single phase dual regulator
system with both sides switching would exhibit twice the
single side numbers. In this example, 2-phase operation
reduced the RMS input current from 1.79ARMS to
0.91ARMS. While this is an impressive reduction in itself,
remember that power losses are proportional to IRMS2,
meaning that actual power wasted is reduced by a factor
of 3.86. The reduced input ripple current also means that
less power is lost in the input power path, which could
include batteries, switches, trace/connector resistances,
and protection circuitry. Improvements in both conducted
and radiated EMI also directly accrue as a result of the
reduced RMS input current and voltage.
Of course, the improvement afforded by 2-phase operation is a function of the dual switching regulator’s relative
duty cycles, which in turn are dependent upon the input
voltage VIN. Figure 4 shows how the RMS input current
varies for 1-phase and 2-phase operation for 2.5V and
1.8V regulators over a wide input voltage range.
It can be readily seen that the advantages of 2-phase
operation are not limited to a narrow operating range, but
in fact extend over a wide region. A good rule of thumb for
most applications is that 2-phase operation will reduce the
input capacitor requirement to that for just one channel
operating at maximum current and 50% duty cycle.
SW1 (V)
2.0
SW2 (V)
INPUT CAPACITOR RMS CURRENT
1.8
IL1
IL2
SINGLE PHASE
DUAL CONTROLER
1.6
1.4
2-PHASE
DUAL CONTROLER
1.2
1.0
0.8
0.6
0.4
VOUT1 = 2.5V/2A
VOUT2 = 1.8V/2A
0.2
0
2
IIN
3
4
8
6
5
7
INPUT VOLTAGE (V)
9
10
3701 F04
3701 F03
Figure 3. Example Waveforms for a Single Switching
Regulator Channel vs 2-Phase LTC3701 System with
Both Channels Switching
Figure 4. RMS Input Current Comparison
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The basic LTC3701 application circuit is shown in Figure␣ 1. External component selection is driven by the load
requirement and begins with the selection of L and RSENSE.
Next, the power MOSFET M1 and the output diode D1 are
selected. Finally CIN (C1) and COUT (C2) are chosen.
RSENSE Selection for Output Current
RSENSE is chosen based on the required output current.
Since the current comparator monitors the voltage developed across RSENSE, the threshold of the comparator
determines the inductor’s peak current. The output current that the LTC3701 can provide is given by:
IOUT
0.095 IRIPPLE
=
–
RSENSE
2
where IRIPPLE is the inductor peak-to-peak ripple current
(see Inductor Value Calculation).
A reasonable starting point for setting ripple current is
IRIPPLE = (0.4)(IOUT). Rearranging the above equation
yields:
RSENSE =
1
for Duty Cycle < 20%
12.7 • IOUT
However, for operation above 20% duty cycle, slope
compensation has to be taken into consideration to select
the appropriate value of RSENSE to provide the required
amount of current. Using Figure 2, the value of RSENSE is:
RSENSE =
SF
(12.7)(IOUT )(100)
smaller inductor for the same amount of inductor ripple
current. However, this is at the expense of efficiency due
to an increase in MOSFET gate charge and switching
losses.
The inductance value also has a direct effect on ripple
current. The ripple current, IRIPPLE, decreases with higher
inductance or frequency. The inductor’s peak-to-peak
ripple current is:
IRIPPLE =
VIN – VOUT  VOUT + VD 


f • L  VIN + VD 
where f is the operating frequency and VD is the forward
voltage drop of the external Schottky diode. Accepting
larger values of IRIPPLE allows the use of low inductances,
but results in higher output voltage ripple and greater core
losses. A reasonable starting point for setting ripple current is IRIPPLE = 0.4(IOUT(MAX)). The maximum IRIPPLE
occurs at the maximum input voltage.
With Burst Mode operation selected on the LTC3701, the
ripple current is normally set such that the inductor
current is continuous during the burst periods. Therefore,
the peak-to-peak ripple current must not exceed:
IRIPPLE ≤ (0.03)/RSENSE
This implies a minimum inductance of:
LMIN =
VIN – VOUT  VOUT + VD 


 0.03   VIN + VD 
f

 RSENSE 
(Use VIN = VIN(MAX) )
For noise sensitive applications, a 1nF capacitor placed
between the SENSE+ and SENSE– pins very close to the
chip is suggested.
A smaller value than LMIN could be used in the circuit,
however, the inductor current will not be continuous
during burst periods.
Inductor Value Calculation
Inductor Core Selection
The inductor selection will depend on the operating frequency of the LTC3701. The internal nominal frequency is
550kHz, but can be externally synchronized or set from
approximately 300kHz to 750kHz.
Once the value of L is known, the type of inductor must be
selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy
or Kool Mµ® cores. Actual core loss is independent of core
The operating frequency and inductor selection are interrelated in that higher frequencies permit the use of a
Kool Mµ is a registered trademark of Magnetics, Inc.
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size for a fixed inductor value, but is very dependent on the
inductance selected. As inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore copper losses will increase. Ferrite designs have very low core losses and are
preferred at high switching frequencies, so design goals
can concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but is more expensive than
ferrite. A reasonable compromise from the same manufacturer is Kool Mµ. Toroids are very space efficient,
especially when several layers of wire can be used, while
inductors wound on bobbins are generally easier to surface mount. However, new designs for surface mount that
do not increase the height significantly are available from
Coiltronics, Coilcraft, Dale and Sumida.
Power MOSFET Selection
An external P-channel MOSFET must be selected for use
with each channel of the LTC3701. The main selection
criteria for the power MOSFET are the threshold voltage
VGS(TH), “on” resistance RDS(ON), reverse transfer capacitance CRSS and the total gate charge.
Since the LTC3701 is designed for operation down to low
input voltages, a sublogic level threshold MOSFET (RDS(ON)
guaranteed at VGS = 2.5V) is required for applications that
work close to this voltage. When these MOSFETs are used,
make sure that the input supply to the LTC3701 is less than
the absolute maximum MOSFET VGS rating, typically 8V.
The required minimum RDS(ON) of the MOSFET is governed by its allowable power dissipation. For applications
that may operate the LTC3701 in dropout, i.e., 100% duty
cycle, the required RDS(ON) is given by:
RDS(ON)DC=100% =
PP
(IOUT(MAX) ) (1+ δp)
2
where PP is the allowable power dissipation and δp is the
temperature dependency of RDS(ON) . (1 + δp) is generally
given for a MOSFET in the form of a normalized RDS(ON) vs
temperature curve, but δp = 0.005/°C can be used as an
approximation for low voltage MOSFETs.
In applications where the maximum duty cycle is less than
100% and the LTC3701 is in continuous mode, the RDS(ON)
is governed by:
RDS(ON) ≅
PP
(DC)IOUT2 (1+ δp)
where DC is the maximum operating duty cycle for that
channel of the LTC3701.
Output Diode Selection
The catch diode carries load current during the switch offtime. The average diode current is therefore dependent on
the P-channel MOSFET duty cycle. At high input voltages,
the diode conducts most of the time. As VIN approaches
VOUT, the diode conducts for only a small fraction of the
time. The most stressful condition for the diode is when
the output is short-circuited. Under this condition, the
diode must safely handle IPEAK at close to 100% duty
cycle. Therefore, it is important to adequately specify the
diode peak current and average power dissipation so as
not to exceed the diode’s ratings.
Under normal load conditions, the average current conducted by the diode is:
V –V 
ID =  IN OUT  IOUT
 VIN + VD 
The allowable forward voltage drop in the diode is calculated from the maximum short-circuit current as:
VF ≈
PD
IPEAK
where PD is the allowable power dissipation and will be
determined by efficiency and/or thermal requirements.
A Schottky diode is a good choice for low forward drop and
fast switching time. Remember to keep lead length short
and observe proper grounding (see Board Layout Checklist) to avoid ringing and increased dissipation.
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CIN and COUT Selection
The selection of CIN is simplified by the 2-phase architecture and its impact on the worst-case RMS current drawn
through the input network (battery/fuse/capacitor). It can
be shown that the worst-case capacitor RMS current
occurs when only one controller is operating. The controller with the highest (VOUT)(IOUT) product needs to be used
in the formula below to determine the maximum RMS
capacitor current requirement. Increasing the output current drawn from the other controller will actually decrease
the input RMS ripple current from its maximum value. The
out-of-phase technique typically reduces the input
capacitor’s RMS ripple current by a factor of 30% to 70%
when compared to a single phase power supply solution.
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle (VOUT + VD)/
(VIN + VD). To prevent large voltage transients, a low ESR
capacitor sized for the maximum RMS current of one
channel must be used. The maximum RMS capacitor
current is given by:
CIN Required IRMS ≈
1/ 2
IMAX
VOUT + VD )( VIN – VOUT )
(
VIN + VD
[
]
This formula has a maximum at VIN = 2VOUT + VD, where
IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations
do not offer much relief. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000
hours of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may be
paralleled to meet size or height requirements in the
design. Due to the high operating frequency of the LTC3701,
ceramic capacitors can also be used for CIN. Always
consult the manufacturer if there is any question.
The benefit of the LTC3701 2-phase operation can be calculated by using the equation above for the higher power
controller and then calculating the loss that would have
resulted if both controller channels switched on at the
same time. The total RMS power lost is lower when both
controllers are operating due to the reduced overlap of
current pulses required through the input capacitor’s ESR.
This is why the input capacitor’s requirement calculated
above for the worst-case controller is adequate for the
dual controller design. Also, the input protection fuse resistance, battery resistance, and PC board trace resistance
losses are also reduced due to the reduced peak currents
in a 2-phase system. The overall benefit of a multiphase
design will only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. The sources of the P-channel MOSFETs
should be placed within 1cm of each other and share a
common CIN(s). Separating the sources and CIN may produce undesirable voltage and current resonances at VIN.
A small (0.1µF to 1µF) bypass capacitor between the chip
VIN pin and ground, placed close to the LTC3701, is also
suggested. A 10Ω resistor placed between CIN (C1) and
the VIN pin provides further isolation between the two
channels.
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement is
satisfied, the capacitance is adequate for filtering. The
output ripple (∆VOUT) is approximated by:

1 
∆VOUT ≈ IRIPPLE ESR +

8fC OUT 

where f is the operating frequency, COUT is the output
capacitance and IRIPPLE is the ripple current in the inductor. The output ripple is highest at maximum input voltage
since IRIPPLE increases with input voltage.
Low Supply Operation
Although the LTC3701 can function down to approximately
2V, the maximum allowable output current is reduced when
VIN decreases below 3V. Figure 5 shows the amount of
change as the supply is reduced down to 2V. Also shown
is the effect of VIN on VREF as VIN goes below 2.3V.
Setting Output Voltage
The LTC3701 output voltages are each set by an external
feedback resistive divider carefully placed across the
output capacitor (see Figure 6). The resultant feedback
signal is compared with an internal 0.8V reference by the
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error amplifier. The regulated output voltage is determined by:
 R2 
VOUT = 0.8 V •  1 + 
 R1
For most applications, an 80k resistor is suggested for R1.
To prevent stray pickup, a 100pF capacitor is suggested
across R1 close to the LTC3701.
NORMALIZED VOLTAGE OR CURRENT (%)
105
100
95
VREF
MAXIMUM
OUTPUT CURRENT
90
85
80
75
2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
INPUT VOLTAGE (V)
3701 F05
Figure 5. Line Regulation of VREF and Maximum Output Current
VOUT
R2
1/2 LTC3701
VFB
100pF
R1
3701 F06
Figure 6. Setting Output Voltage
The output of the phase detector is a pair of complementary current sources that charge or discharge the external
filter network connected to the PLLLPF pin. The relationship between the voltage on the PLLLPF pin and operating
frequency is shown in Figure 7 and specified in the
electrical characteristics table. Note that the LTC3701 can
only be synchronized to an external clock whose frequency is within the frequency range of the LTC3701’s
internal oscillator, which is specified in the electrical
characteristics table. A simplified block diagram of the
PLL is shown in Figure 8.
If the external frequency (VEXTCLK/MODE) is greater than
the internal oscillator frequency fOSC, current is sourced
continuously, pulling up the PLLLPF pin. When the external frequency is less than fOSC, current is sunk continuously, pulling down the PLLLPF pin. If the external and
internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time
corresponding to the phase difference. The voltage on the
PLLLPF pin is adjusted until the phase and frequency of
the external oscillators are identical. At the stable operating point, the phase comparator output is high impedance
and the filter capacitor CLP holds the voltage.
The loop filter components CLP and RLP smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components RLP and CLP determine how fast the loop
acquires lock. Typically, RLP = 10k and CLP is 2200pF to
0.01µF. When not synchronized to an external clock, the
800
Phase-Locked Loop and Frequency Synchronization
700
650
FREQUENCY (kHz)
The LTC3701 has a phase-locked loop comprised of an
internal voltage-controlled oscillator and phase detector.
This allows the turn-on of the external P-channel MOSFET
of controller 1 to be locked to the rising edge of an external
frequency source. The turn-on of controller 2’s external
P-channel MOSFET is thus 180 degrees out of phase to the
external clock. The nominal frequency range of the voltage-controlled oscillator is 280kHz to 775kHz. The phase
detector is an edge sensitive digital type that provides zero
degrees phase shift between the external and internal
oscillators. This type of phase detector does not exhibit
false lock to harmonics of the external oscillator.
750
600
550
500
450
400
350
300
250
0
0.4
0.8
1.2
1.6
2.0
PLLLPF PIN VOLTAGE (V)
2.4
3701 F07
Figure 7. Relationship Between Oscillator Frequency
and Voltage at PLLLPF Pin
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internal oscillator frequency may be set by applying a DC
voltage to the PLLLPF pin. 550kHz operation can be
selected by floating the PLLLPF pin. The PLLLPF pin may
be connected to voltages as high as VIN.
2.4V
RLP
CLP
EXTCLK/
MODE
EXTERNAL
OSCILLATOR
PLLLPF
DIGITAL
PHASE/
FREQUENCY
DETECTOR
10k
OSCILLATOR
3701 F08
Figure 8. Phase-Locked Loop Block Diagram
typically much larger than the DC supply current. In
continuous mode, IGATECHG = f • QP.
3) I2R losses are calculated from the DC resistances of the
MOSFET, inductor and sense resistor. In continuous
mode, the average output current flows through L but
is “chopped” between the P-channel MOSFET in series
with RSENSE and the output diode. The MOSFET RDS(ON)
plus RSENSE multiplied by duty cycle can be summed
with the resistance of L to obtain I2R losses.
4) The output diode is a major source of power loss at high
currents and is worse at high input voltages. The diode
loss is calculated by multiplying the forward voltage
times the load current times the diode duty cycle.
5) Transition losses apply to the external MOSFET and
increase with higher operating frequencies and input
voltages. Transition losses can be estimated from:
Transition Loss = 2 (VIN)2IO(MAX)CRSS(f)
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting efficiency and which change would produce the
most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + …)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, five main sources usually account for most of the
losses in LTC3701 circuits: 1) LTC3701 DC bias current,
2) MOSFET gate charge current, 3) I2R losses, 4) voltage
drop of the output diode and 5) transition losses.
1) The VIN (pin) current is the DC supply current, given in
the electrical characteristics, that excludes MOSFET
driver currents. VIN current results in a small loss that
increases with VIN.
2) MOSFET gate charge current results from switching the
gate capacitance of the power MOSFET. Each time a
MOSFET gate is switched from low to high to low again,
a packet of charge dQ moves from PVIN to ground. The
resulting dQ/dt is a current out of PVIN, which is
Other losses, including CIN and COUT ESR dissipative
losses and inductor core losses, generally account for less
than 2% total additional loss.
Foldback Current Limiting
As described in the Output Diode Selection, the worstcase diode dissipation occurs with a short-circuited output when the diode conducts the current limit value almost
continuously. To prevent excessive heating in the diode,
foldback current limiting can be added to reduce the
current in proportion to the severity of the fault.
Foldback current limiting is implemented by adding diodes DFB1 and DFB2 between the output and the ITH/RUN
pin as shown in Figure 9. In a hard short (VOUT = 0V), the
current will be reduced to approximately 50% of the
maximum output current.
VOUT
1/2 LTC3701
R2
+
DFB1
ITH/RUN VFB
R1
DFB2
3701 F09
Figure 9. Foldback Current Limiting
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Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to (∆ILOAD)(ESR), where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or discharge COUT, which generates a feedback error signal. The
regulator loop then returns VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for overshoot or ringing. OPTI-LOOP compensation allows the
transient response to be optimized over a wide range of
output capacitance and ESR values.
The ITH series RC-CC filter (see Functional Diagram) sets
the dominant pole-zero loop compensation. The ITH external components shown in the Figure 1 circuit will provide
an adequate starting point for most applications. The
values can be modified slightly (from 0.2 to 5 times their
suggested values) to optimize transient response once the
final PC layout is done and the particular output capacitor
type and value have been determined. The output capacitors need to be decided upon because the various types
and values determine the loop feedback factor gain and
phase. An output current pulse of 20% to 100% of full load
current having a rise time of 1µs to 10µs will produce
output voltage and ITH pin waveforms that will give a sense
of the overall loop stability. The gain of the loop will be
increased by increasing RC, and the bandwidth of the loop
will be increased by decreasing CC. The output voltage
settling behavior is related to the stability of the closedloop system and will demonstrate the actual overall supply
performance. For a detailed explanation of optimizing the
compensation components, including a review of control
loop theory, refer to Application Note 76.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(CLOAD).
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest amount of
time that the LTC3701 is capable of turning the top
MOSFET on and then off. It is determined by internal
timing delays and the gate charge required to turn on the
top MOSFET. The minimum on-time for the LTC3701 is
about 250ns. Low duty cycle and high frequency applications may approach this minimum on-time limit and care
should be taken to ensure that:
tON(MIN) <
VOUT
f • VIN
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC3701 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple current and ripple voltage will increase.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3701. These items are illustrated graphically in the
layout diagram of Figure 10. Figure 11 illustrates the
current waveforms present in the various branches of the
2-phase regulators. Check the following in your layout:
1) Are the sense resistors and P-channel MOSFETs for the
two channels located within 1cm of each other with a
common connection at CIN? Do not attempt to split the
input decoupling for the two channels as it can cause a
large resonant loop.
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2) Are the signal and power grounds kept separate? The
LTC3701 signal ground consists of the feedback resistor
divider, the ITH/RUN compensation network, and Pin 4.
The power ground consists of the (–) terminal of CIN, the
(–) terminals of COUT1,2, the anodes of the Schottky
diodes, and Pin 13 of the LTC3701. The power ground
traces should be kept short, direct, and wide. Connect the
anode of the Schottky diodes directly to the input capacitor
ground.
3) Do the VFB pins connect directly to the feedback
resistors? Put the feedback resistors close to the VFB pins.
The traces connecting the top feedback resistors to the
corresponding output capacitor should to be Kelvin traces.
4) Are the SENSE– and SENSE+ leads routed together with
minimum PC trace spacing? The (optional) filter capacitor
between SENSE+ and SENSE– should be as close as
possible to the IC. Ensure accurate current sensing with
Kelvin connections at the sense resistor.
5) Keep the switching nodes (SW1, SW2) and top gate
nodes (PGATE1, PGATE2) away from small-signal nodes,
especially the opposite channel’s voltage and current
sensing feedback pins. All of these nodes have large and
fast moving signals and therefore should be keep on the
“output side” of the LTC3701 and occupy minimum PC
trace area.
From Figure 2, SF = 57%.
RSENSE =
SF
0.57
=
= 0.03Ω
12.7 • IOUT • 100 12.7 • 1.5
In the application, a 0.03Ω resistor is used. The PLLLPF
pin will be left floating, so the LTC3701 will operate at its
default frequency of 550kHz. For continuous operation in
Burst Mode, the required minimum inductor value is:
LMIN =
4.2V – 2.5V  2.5V + 0.3V 

 = 2.00µH
 0.03V   4.2V + 0.3V 
550kHz 

 0.03Ω 
For the selection of the external MOSFET, the RDS(ON)
must be guaranteed at 2.5V since the LTC3701 has to work
down to 2.7V. Let’s assume that the MOSFET dissipation
is to be limited to PP = 250mW and its thermal resistance
is 50°C/W. Hence, the junction temperature at TA = 25°C
will be 37.5°C and δp = 0.005 • (37.5 – 25) = 0.0625. The
required RDS(ON) is then given by:
RDS(ON) ≈
PP
DC • IOUT2 (1 + δp)
= 0.11Ω
The P-channel MOSFET requirement can be met by an
Si3443DV.
As a design example for one channel, assume VIN will be
operating from a maximum of 4.2V down to a minimum of
2.7V. Load current requirement is a maximum of 1.5A , but
most of the time it will be in a standby mode requiring only
2mA. Efficiency at both low and high load currents is
important. Burst Mode operation at light loads is desired.
Output voltage is 2.5V.
The requirement for the Schottky diode is the most stringent when VOUT = 0V, i.e., short circuit. With a 0.03Ω
RSENSE resistor, the short-circuit current through the
Schottky is 0.1/0.03 = 3.3A. An MBRS340T3 Schottky
diode is chosen. With 3.3A flowing through, the diode is
rated with a forward voltage of 0.4V. Therefore, the worstcase power dissipated by the diode is 1.32W. The addition
of DFB1 and DFB2 (Figure 6) will reduce the diode dissipation to approximately 0.66W
 V
+ VD 
Maximum Duty Cycle =  OUT
 = 93%
 VIN(MIN) + VD 
The input capacitor requires an RMS current rating of at
least 0.75A at temperature, and COUT will require an ESR
of 0.1Ω for optimum efficiency.
Design Example
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+
COUT1
2
3
4
5
6
7
8
SENSE1
–
SENSE1
ITH/RUN1
VIN
VFB1
SGND
+
PGATE1
LTC3701
PGND
VFB2
PGATE2
ITH/RUN2
PGOOD
PLLLPF EXTCLK/MODE
SENSE2 –
M1
VOUT1
RSENSE1
16
15
D1
14
13
VIN
+
12
CIN
11
10
9
SENSE2 +
D2
L2
M2
+
1
–
+
L1
RSENSE2
COUT2
–
+
VOUT2
BOLD LINES INDICATE
HIGH CURRENT PATHS
3701 F10
Figure 10. LTC3701 Layout Diagram
RSENSE1
SW1
L1
D1
VOUT1
COUT1
+
RL1
VIN
RIN
CIN
+
RSENSE2
BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH.
SW2
L2
D2
VOUT2
COUT2
+
RL2
3701 F11
Figure 11. Branch Current Waveforms
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2-Phase, Synchronizable Dual Output Step-Down DC/DC Converter
VIN
2.7V to 9.8V
1
R6
78.7k
2
R10 C6 220pF
10k
3
4
5
R5
10k C4 220pF
R8
80k
R9
100k
6
7
8
10k
SENSE1 –
SENSE1 +
ITH/RUN1
VIN
VFB1
SGND
PGATE1
LTC3701
PGND
VFB2
PGATE2
ITH/RUN2
PGOOD
PLLLPF EXTCLK/MODE
SENSE2 –
SENSE2 +
16
M1
R1
0.03Ω
15
14
L1
4.7µH
D1
VOUT1
2.5V
2A
+
C1
47µF
GND
13
C2
10µF
12
100k
11
D2
VIN
L2
4.7µH
10
9
C5
47µF
VOUT2
1.8V
2A
M2
R2
0.03Ω
10nF
+
R7
169k
3701 TA02
C1, C5: SANYO 6TPA47M
C2: TAIYO YUDEN LMK325BJ106K-T
M1, M2: Si3443DV
R1, R2: DALE 0.25W
D1, D2: IR10BQ015
L1, L2: MURATA LQN6C-4R7
2-Phase, 550kHz Single Output Step-Down DC/DC Converter
Optional Output Sequencing Circuit
VIN
2.5V TO 9.8V
R7
169k
VIN
1
R6
78.7k
0.01µF
2
3
15k
3
LT1004-1
1.2V
VOUT1
+
LT1797
4
–
4
5
1
1N4148
5
FB2
R5
10k
2
C4
220pF
6
7
8
3701 TA05
SENSE1 –
SENSE1 +
ITH/RUN1
VIN
VFB1
SGND
PGATE1
LTC3701
PGND
VFB2
PGATE2
ITH/RUN2
PGOOD
PLLLPF EXTCLK/MODE
SENSE2 –
16
M1
R1
0.03Ω
15
14
L1
4.7µH
D1
+
13
VOUT
2.5V
4A
C1
47µF
C2
10µF
12
D2
11
10
L2
4.7µH
R2
0.03Ω
9
SENSE2 +
M2
C1: SANYO 6TPA47M
C2: TAIYO YUDEN LMK325BJ106K-T
D1, D2: IR10BQ015
3701 TA03
L1, L2: MURATA LQN6C-4R7
M1, M2: Si3443DV
R1, R2: DALE 0.25W
Single Cell Li-Ion to 3.3V (Zeta Converter) and 1.8V (Buck Converter)
VIN
2.7V to 4.2V
R7
249k
R8
80.6k
R9
100k
1
R10 C6 470pF
47k
R5
10k C4 220pF
10k
3
SENSE1 –
VFB1
2
SENSE1 +
VIN
16
15
14
ITH/RUN1
PGATE1
13
4
LTC3701
SGND
PGND
12
6
ITH/RUN2
PGATE2
11
5
PGOOD
VFB2
10
7
PLLLPF EXTCLK/MODE
9
8
SENSE2 +
SENSE2 –
10nF
L1B
M1
•
•
R1
0.025Ω
L1A
D1
VOUT1
3.3V
1A
+
C1
C2
22µF
GND
100k
D2
VIN
R2
0.03Ω
L2
4.7µH
+
R6
78.7k
C3 10µF
C5
47µF
VOUT2
1.8V
2A
M2
3701 TA06
C1, C5: SANYO 6TPA47M
C2: TAIYO YUDEN JMK325BJ226MM
C3: TAIYO YUDEN JMK316BJ106ML
D1, D2: IR10BQ015
L1A, L1B: COILTRONICS CTX5-2
L2: MURATA LQN6C-4R7
M1, M2: Si3443DV
R1, R2: DALE 0.25W
3701fa
18
LTC3701
U
TYPICAL APPLICATIO S
2-Phase, Synchronizable Dual Output Step-Down DC/DC Converter with 4A Output Currents
1nF
R6
78.7k
1
2
R10 C6 220pF
10k
3
4
5
R8
80k
R5
10k C4 220pF
R9
100k
6
7
8
10k
SENSE1 –
SENSE1 +
ITH/RUN1
VIN
PGATE1
VFB1
SGND
LTC3701
PGND
VFB2
PGATE2
ITH/RUN2
PGOOD
PLLLPF EXTCLK/MODE
SENSE2 –
SENSE2 +
16
15
R1
0.012Ω
VIN
2.7V to 9.8V
M1
L1
1.5µH
10Ω
14
13
D1
1µF
+
C1
47µF
GND
VOUT1
2.5V
4A
C2
10µF
12
11
100k
D2
VIN
L2
1.5µH
10
9
R2
0.015Ω
10nF
+
R7
169k
C5
47µF
VOUT2
1.8V
4A
M2
1nF
3701 TA02
D1, D2: IR30BQ015
L1, L2: COILCRAFT DO3316P-152
C1, C5: SANYO 6TPA47M
C2: TAIYO YUDEN LMK325BJ106K-T
M1, M2: Si9803DY
R1, R2: DALE 0.25W
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
16 15 14 13 12 11 10 9
.254 MIN
.009
(0.229)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ± .0015
.150 – .157**
(3.810 – 3.988)
.0250 TYP
RECOMMENDED SOLDER PAD LAYOUT
1
.015 ± .004
× 45°
(0.38 ± 0.10)
.007 – .0098
(0.178 – 0.249)
2 3
4
5 6
7
.053 – .068
(1.351 – 1.727)
8
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
.0250
(0.635)
BSC
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN16 (SSOP) 0502
3701fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC3701
U
TYPICAL APPLICATIO
Dual Input Voltage Single Output, 2-Phase, 550kHz, Step-Down DC/DC Converter
R7
169k
1
SENSE1 –
2
R6
78.7k
R8
10k
C5
220pF
SENSE1 +
ITH/RUN1
3
VIN
VFB1
4
SGND
5
6
7
PGATE1
LTC3701
PGND
VFB2
PGATE2
ITH/RUN2
PGOOD
PLLLPF EXTCLK/MODE
8
SENSE2 –
SENSE2 +
16
15
14
VIN1
2.5V TO 9.8V
VIN1 ≥ VIN2
M1
R1
0.03Ω
L1
4.7µH
D1
+
13
VOUT
2.5V
2A
C1
47µF
C2
10µF
12
D2
11
10
9
L2
4.7µH
R2
0.03Ω
C3
10µF
M2
3701 TA04
C1: SANYO 6TPA47M
C2, C3: TAIYO YUDEN LMK325BJ106K-T
D1, D2: IR10BQ015
VIN2
2.5V TO 9.8V
L1, L2: MURATA LQN6C-4R7
M1, M2: Si3443DV
R1, R2: DALE 0.25W
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1622
Synchronizable Low Input Voltage Current Mode
Step-Down DC/DC Controller
VIN 2V to 10V, Burst Mode Operation, 8-Lead MSOP
LTC1628/
LTC1628-PG
Dual High Efficiency, 2-Phase Synchronous
Step Down Controllers
Constant Frequency, Standby, 5V and 3.3V LDOs, VIN to 36V,
28-Lead SSOP
LTC1629/
LTC1629-PG
20A TO 200A PolyPhaseTM High Efficiency Controllers
Expandable Up to 12 Phases, No Heat Sinks, VIN to 36V,
28-Lead SSOP
LTC1702A
No RSENSETM 2-Phase Dual Synchronous Controller
550kHz, No Sense Resistor, GN24, VIN to 7V
LTC1708-PG
Dual High Efficiency, 2-Phase Synchronous
Step-Down Switching Regulators
1.3V≤ VOUT ≤ 3.5V, Current Mode, 3.5V ≤ VIN ≤ 36V
LTC1735
High Efficiency Synchronous Step-Down Controller
Burst Mode Operation, 16-Pin Narrow SSOP, Fault Protection,
3.5V ≤ VIN ≤ 36V
LTC1767
1.2A IOUT, 1.25MHz, High Efficiency Step-Down DC/DC Converter 90% Efficiency, VIN: 3V to 25V, VOUT = 1.2V, IQ = 1mA,
ISD = 6µA, MS8E Package
LTC1772
Constant Frequency Current Mode Step-Down
DC/DC Controller
2.5V ≤ VIN ≤ 9.8V, IOUT Up to 4A, SOT-23 Package, 550kHz
LTC1773
Synchronous Step-Down Controller
2.65V ≤ VIN ≤ 8.5V, IOUT Up to 4A, 10-Lead MSOP
LTC1778
No RSENSE Synchronous Step-Down Controller
Current Mode Operation Without Sense Resistor,
Fast Transient Response, 4V ≤ VIN ≤ 36V
LTC1872
Constant Frequency Current Mode Step-Up Controller
2.5V ≤ VIN ≤ 9.8V, SOT-23 Package, 550kHz
LTC1929
Constant Frequency Current Mode 2-Phase
Synchronous Controller
Up to 42A, No Heat Sink, 3.5V ≤ VIN ≤ 36V
LTC3411
1.25A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 2.5V to 5.5V, VOUT = 0.8V, IQ = 60µA,
ISD = <1µA, MS Package
LTC3412
2.5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 2.5V to 5.5V, VOUT = 0.8V, IQ = 60µA,
ISD = <1µA, TSSOP-16E Package
LTC3700
Constant Frequency Step-Down Controller with LDO Regulator
2.65≤ VIN␣ ≤␣ 9.8V, 550kHz, 10-Lead SSOP
LTC3728/LTC3728L
Dual, 550kHz, 2-Phase Synchronous Step-Down
Switching Regulator
Constant Frequency, VIN to 36V, 5V and 3.3V LDOs,
5mm × 5mm QFN or 28-Lead SSOP
PolyPhase and No RSENSE are trademarks of Linear Technology Corporation.
3701fa
20
Linear Technology Corporation
LT/TP 0403 1K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2002