OKI ML87V2105TB Video signal noise reduction ic with a built-in 5.6 mbit frame memory Datasheet

OKI Semiconductor
ML87V2105
PEDL87V2105DIGEST-02
Issue Date: Dec. 20, 2003
Preliminary
Video Signal Noise Reduction IC with a Built-in 5.6 Mbit Frame Memory
This document contains minimum specifications. For full specifications, please contact your nearest Oki office or
representative.
GENERAL DESCRIPTION
The ML87V2105 comprises a 5.6 Mbit frame memory, a noise reduction filter, and a memory controller to reduce
frame-recursive 3D noise in video signals.
The motion adaptive noise reduction is performed between frames, between fields, or between lines, to reduce the
afterimage particular to 3D noise reduction as far as possible, while achieving effective noise reduction.
The ML87V2105 also features an automatic noise reduction mode that automatically detects the noise level in the
input video data to set the optimum noise reduction.
Because it is possible to select the same format for output as for input, the ML87V2105 can be introduced into an
existing system, making it easy to achieve noise reduction.
FEATURES
• Built-in memory:
Frame memory (4:1:1 data equivalent) × 1 unit
• Maximum input and output operating frequencies (16 bits/8 bits, ITU-R BT.656):
14.75/29.5 MHz
• Power supply voltage:
3.3 V ± 0.3 V
• Input pin:
LVTTL (3.3 V)
• Output pin:
LVCMOS (3.3 V)
• Input data format:
YCbCr (8 bits (Y) + 8 bits (CbCr) (4:2:2) + Sync.):
16-bit mode
YCbCr (8 bits (YCbCr) (4:2:2) + Sync.):
8-bit mode
ITU-R BT.656 (8 bits (YCbCr)):
ITU-R BT.656 mode
• Output data format:
YCbCr (8 bits (Y) + 8 bits (CbCr) (4:2:2) + Sync.):
16-bit mode
YCbCr (8 bits (YCbCr) (4:2:2) + Sync.):
8-bit mode (Selectable in 8-bit input mode)
ITU-R BT.656 (8 bits (YCbCr)):
ITU-R BT.656 mode (Selectable in input ITU-R
BT.656)
• Serial bus:
I2C-bus interface: (Standard mode: 100 kbps/Fast mode: 400 kbps)
• Internal memory controller:
Compatible with 625/50 Hz 2:1, 525/60 Hz 2:1
Compatible horizontal effective pixels: 640 (525 line mode only), 720, 768
• Frame-recursive noise reduction:
Frame-recursive noise detection and subtraction
Auto mode noise reduction
• Package:
100 pin TQFP (TQFP100-P-1414-0.50-K)(ML87V2105TB)
1/14
PEDL87V2105DIGEST-02
OKI Semiconductor
ML87V2105
BLOCK DIAGRAM
YI0-7
CI0-7
x16
Frame Memory
5.6Mbits
Input/Output
Process
Block
+
3D NR
x16
YO0-7
CO0-7
OVS
ICLK
Memory
Controller
IVS
IHS
OHS
HREF
CLKO
SCL
SDA
SLA1
SLA2
MODE0-2
I2C-bus
I/F
Register
Control
Signal
TEST1-7
RESET
2/14
PEDL87V2105DIGEST-02
OKI Semiconductor
ML87V2105
VSS
YO7
YO6
YO5
YO4
VDD
YO3
YO2
YO1
YO0
VSS
N.C.
VDD
CO7
CO6
CO5
CO4
VSS
CO3
CO2
CO1
CO0
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
TEST7
73
71
TEST6
74
72
RESET
75
PIN CONFIGURATION (TOP VIEW)
VDD 76
50
VDD
N.C. 77
49
N.C.
VSS 78
48
VSS
N.C. 79
47
HREF
N.C. 80
46
OVS
N.C. 81
45
OHS
N.C. 82
44
N.C.
N.C. 83
43
N.C.
N.C. 84
42
N.C.
N.C. 85
41
N.C.
N.C. 86
40
VDD
39
N.C.
38
N.C.
37
VSS
TEST3 90
36
VDD
TEST2 91
35
CLKO
TEST1 92
34
MODE2
N.C. 93
33
N.C.
N.C. 94
32
MODE1
N.C. 95
31
MODE0
TESTM 96
30
IHS
SELF 97
29
IVS
VSS 98
28
VSS
N.C. 99
27
N.C.
VDD 100
26
VDD
TEST5 87
ML87V2105TB
VDD 88
CI0 25
CI1 24
CI2 23
CI3 22
CI4 21
CI5 20
CI6 19
CI7 18
VSS 17
ICLK 16
VDD 15
YI0 14
YI1 13
YI2 12
YI3 11
YI5 9
YI6 8
YI7 7
SLA2 6
SLA1 5
SCL 4
SDA 3
VSS 2
N.C. 1
YI4 10
(TQFP100-P-1414-0.50-K)
TEST4 89
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PEDL87V2105DIGEST-02
OKI Semiconductor
ML87V2105
PIN DESCRIPTIONS
No.
1
2
Symbol
N.C.
VSS
I/O
—
—
3
SDA
I/O
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SCL
SLA1
SLA2
YI7
YI6
YI5
YI4
YI3
YI2
YI1
YI0
VDD
ICLK
VSS
CI7
CI6
CI5
CI4
CI3
CI2
CI1
CI0
VDD
N.C.
VSS
I
I
I
I
I
I
I
I
I
I
I
—
I
—
I
I
I
I
I
I
I
I
—
—
—
29
IVS
I
30
IHS
I
31
MODE0
I
32
33
34
35
36
37
38
39
MODE1
N.C.
MODE2
CLKO
VDD
VSS
N.C.
N.C.
Pad Remarks
Pin Description
Unused pin
Ground
Schmitt(IN)/
OpenDrain(OUT)
Schmitt
Internal pull-down 50k
Internal pull-down 50k
Internal pull-down 50k
Internal pull-down 50k
Internal pull-down 50k
Internal pull-down 50k
Internal pull-down 50k
Internal pull-down 50k
Internal pull-down 50k
Internal pull-down 50k
I2C-bus data pin
I2C-bus clock pin
Slave address setting pin
Slave address setting pin
Luminance signal input pin bit 7 (MSB)
Luminance signal input pin bit 6
Luminance signal input pin bit 5
Luminance signal input pin bit 4
Luminance signal input pin bit 3
Luminance signal input pin bit 2
Luminance signal input pin bit 1
Luminance signal input pin bit 0 (LSB)
Power supply 3.3 V
Input system clock pin
Ground
Color difference signal input pin bit 7 (MSB)
Color difference signal input pin bit 6
Color difference signal input pin bit 5
Color difference signal input pin bit 4
Color difference signal input pin bit 3
Color difference signal input pin bit 2
Color difference signal input pin bit 1
Color difference signal input pin bit 0 (LSB)
Power supply 3.3 V
Unused pin
Ground
Schmitt
Input system vertical sync signal input pin
Internal pull-down 50k
Schmitt
Input system horizontal sync signal input pin
Internal pull-down 50k
Internal pull-down 50k Mode setting pin – bit 0
I Internal pull-down 50k
—
I Internal pull-down 50k
O/(I)
—
—
—
—
Mode setting pin – bit 1
Unused pin
Mode setting pin – bit 2
Clock output (I2C-bus control possible)
Power supply 3.3 V
Ground
Unused pin
Unused pin
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PEDL87V2105DIGEST-02
OKI Semiconductor
ML87V2105
No.
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
Symbol
VDD
N.C.
N.C.
N.C.
N.C.
OHS
OVS
HREF
VSS
N.C.
VDD
CO0
CO1
CO2
CO3
VSS
CO4
CO5
CO6
CO7
VDD
N.C.
VSS
YO0
YO1
YO2
YO3
VDD
YO4
YO5
YO6
YO7
VSS
TEST7
TEST6
I/O
—
—
—
—
—
O
O
O
—
—
—
O/(I)
O/(I)
O/(I)
O/(I)
—
O/(I)
O/(I)
O/(I)
O/(I)
—
—
—
O
O
O
O
—
O
O
O
O
—
I
I
Pad Remarks
75
RESET
I
Schmitt
Pin Description
Power supply 3.3 V
Unused pin
Unused pin
Unused pin
Unused pin
Horizontal sync signal output pin
Vertical sync signal output pin
Data output horizontal reference signal output pin
Ground
Unused pin
Power supply 3.3 V
Color difference signal output pin – bit 0 (LSB)
Color difference signal output pin – bit 1
Color difference signal output pin – bit 2
Color difference signal output pin – bit 3
Ground
Color difference signal output pin – bit 4
Color difference signal output pin – bit 5
Color difference signal output pin – bit 6
Color difference signal output pin – bit 7(MSB)
Power supply 3.3 V
Unused pin
Ground
Luminance signal output pin – bit 0 (LSB)
Luminance signal output pin – bit 1
Luminance signal output pin – bit 2
Luminance signal output pin – bit 3
Power supply 3.3 V
Luminance signal output pin – bit 4
Luminance signal output pin – bit 5
Luminance signal output pin – bit 6
Luminance signal output pin – bit 7 (MSB)
Ground
Test input pin – bit 7 (1: test mode)
Test input pin – bit 6 (1: test mode)
System reset/input pin
0: System reset
1: Operation
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PEDL87V2105DIGEST-02
OKI Semiconductor
ML87V2105
No.
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
Symbol
VDD
N.C.
VSS
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
TEST5
VDD
TEST4
TEST3
TEST2
TEST1
N.C.
N.C.
N.C.
TESTM
I/O
—
—
—
—
—
—
—
—
—
—
—
I
—
I
I
I
I
—
—
—
I
97
SELF
I
98
VSS
—
Pad Remarks
Pin Description
Power supply 3.3 V
Unused pin
Ground
Unused pin
Unused pin
Unused pin
Unused pin
Unused pin
Unused pin
Unused pin
Unused pin
Internal pull-down 50k Test input pin – bit 5 (1: test mode)
Power supply 3.3 V
Internal pull-down 50k Test input pin – bit 4 (1: test mode)
Internal pull-down 50k Test input pin – bit 3 (1: test mode)
Internal pull-down 50k Test input pin – bit 2 (1: test mode)
Internal pull-down 50k Test input pin – bit 1 (1: test mode)
Unused pin
Unused pin
Unused pin
Internal pull-down 50k Memory test input pin (1: test mode)
Internal pull-down 50k
Self refresh setting pin (0: Self refresh stopped, 1: Self refresh
operated)
Ground
Notes: Keep the test mode pins fixed to 0 or leave them open.
CL0 to CL7 and CLK0 are configured as inputs only in the test mode.
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PEDL87V2105DIGEST-02
OKI Semiconductor
ML87V2105
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Power supply voltage
Symbol
Condition
Rating
Unit
VDD
Ta = 25°C
–0.3 to + 4.6
V
Input pin voltage
VI
Ta = 25°C
–0.3 to + 7.0
V
Output pin short-circuit current
IOS
Ta = 25°C
50
mA
Power dissipation
PD
Ta = 25°C
1
W
Operating temperature
Topr
—
0 to 70
°C
Storage temperature
Tstg
—
–50 to + 150
°C
Recommended Operating Conditions
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power supply voltage
VDD
3.0
3.3
3.6
V
Power supply voltage
VSS
0
0
0
V
Operating temperature
Ta
0
—
70
°C
Pin Capacitance
(VCC = 3.3 V ± 0.3 V, f = 1 MHz, Ta = 25°C)
Parameter
Symbol
Min.
Max.
Unit
Ci
—
5
pF
Input/output capacitance
(CO0 to CO7, CLK0)
Cio1
—
10
pF
Input/output capacitance (SDA)
Cio2
—
10
pF
Co
—
10
pF
Input capacitance
Output capacitance
(YO0 to YO7, OVS, OHS, HREF)
7/14
PEDL87V2105DIGEST-02
OKI Semiconductor
ML87V2105
DC Characteristics
(Ta = 0 to 70°C)
Parameter
H level input voltage
L level input voltage
Schmitt trigger threshold voltage
(SDA, SCL, IVS, IHS, RESET)
Schmitt trigger threshold voltage
(SDA, SCL, IVS, IHS, RESET)
Hysteresis voltage width
H level input current (pull-down)
Input leakage current
H level output voltage (other than SDA)
L level output voltage (other than SDA)
L level output voltage (N-Ch.OD)
(SDA)
Symbol
VIH
VIL
Condition
—
—
Min.
2.0
–0.3
Max.
VDD+0.3
0.8
Unit
V
V
Vt+
—
—
2.0
V
Vt–
—
0.8
—
V
Vh
IIH
IIL
VOH
VOL
—
50 kΩ Pull Down
TTL
IOH = –4 mA
IOL = 4 mA
0.1
20
–10
2.4
0
—
200
10
VDD
0.4
V
µA
µA
V
V
VOOL
IOL = 4 mA
0
0.4
V
–10
10
µA
—
80
mA
—
5
mA
Condition
16-bit input mode
8-bit input mode
ITU-R BT.656 mode
—
—
—
CL = 30 pF
CL = 30 pF (IICLK output)
CL = 30 pF (ICLK output)
Min.
66
Max.
—
Unit
ns
33
—
ns
40
5
3
5
2
2
60
—
—
25
25
25
ns
ns
ns
ns
ns
CL = 30 pF
5
20
ns
Output leakage current
IOL
Supply current (during operation)
IDD1
Supply current (during standby)
IDD2
0 ≤ Vout ≤ VDD
Output disabled
ICLK: 29.5 MHz
Output disabled
Input pin = VIL
AC Characteristics
(Ta = 0 to 70°C)
Parameter
ICLK clock cycle time
Symbol
tICLK
ICLK clock cycle time
tICLK
ICLK clock duty ratio
ICLK input set-up time
ICLK input hold time
ICLK output delay time
dtICLK
tIISU
tIIH
tIOD
CLKO delay time
tCKD
Data through time
tDIDO
%
*1: ( ) indicates the input internal system clock cycle.
Note 1: Measurement conditions
Output comparison level: VOH = 1.5 V, VOL = 1.5 V
Input voltage level: VIH = 3.0 V, VIL = 0.0 V
Note 2: .When writing input data to the memory, compensation is applied from the second input system
vertical synchronization signal when VDD reaches 3.0 V after the power is turned on, and when
RESET = 1. (Due to memory initialization, the first data for the first field is not compensated.)
Note 3: .When reading output data from the memory, compensation is applied from the second output
system vertical synchronization signal when VDD reaches 3.0 V after the power is turned on, and
when RESET = 1. (Due to memory initialization, the first data for the first field is not compensated.)
8/14
PEDL87V2105DIGEST-02
OKI Semiconductor
ML87V2105
INPUT/OUTPUT TIMING
1. ICLK input/output timing
tICLK
ICLK
DATA &
CONTROL
INPUT(ICLK)
DATA &
CONTROL
OUTPUT(ICLK)
50%
tIIH
tIISU
50%
tIOD
50%
tCKD
CLKO
(CKINV=0)
50%
tCKD
CLKO
(CKINV=1)
50%
2. Data through mode input/output timing
DATA &
CONTROL
INPUT
50%
tDIDO
DATA &
CONTROL
OUTPUT
50%
9/14
PEDL87V2105DIGEST-02
OKI Semiconductor
ML87V2105
CIRCUIT APPLICATION EXAMPLES
Application Example 1
Mode setting: Open
Slave address: 1011100
Input format: 16-bit YCbCr (Register setting: DISEL = 0, R656 = 0)
3.3V
System
Reset
SELF
97
YO7
YO6
YO5
YO4
YO3
YO2
YO1
YO0
CO7
CO6
CO5
CO4
CO3
CO2
CO1
CO0
HREF
OVS
OHS
CLKO
SCAN
CONVERTER
(ML87V230X)
or
MPEG
ENCODER
DATA
OUT
CLK
RESET
75
16
71
70
69
68
66
65
64
63
59
58
57
56
54
53
52
51
47
46
45
35
RESET
ICLK
29
30
NR-FIFO
ML87V2105
2,17,28,37,48,
55,62,72,78,98
IVS
IHS
7
8
9
10
11
12
13
14
18
19
20
21
22
23
24
25
GND
VIDEO
IN
DIGITAL
VIDEO
DECODER
(ML86V766X)
YI7
YI6
YI5
YI4
YI3
YI2
YI1
YI0
CI7
CI6
CI5
CI4
CI3
CI2
CI1
CI0
15,26,36,40,50,
60,67,76,88,100
3
4
SDA
SCL
VDD
I2C-bus
MATER
CONTROLLER
10/14
PEDL87V2105DIGEST-02
OKI Semiconductor
ML87V2105
Application Example 2
Mode setting: Open
Slave address: 1011100
Input format: ITU-R BT656 (Register setting: DISEL = 0, R656 = 1)
3.3V
System
Reset
16
SELF
97
YO7
YO6
YO5
YO4
YO3
YO2
YO1
YO0
CO7(OPEN)
CO6(OPEN)
CO5(OPEN)
CO4(OPEN)
CO3(OPEN)
CO2(OPEN)
CO1(OPEN)
CO0(OPEN)
HREF(OPEN)
OVS(OPEN)
OHS(OPEN)
CLKO(OPEN)
SCAN
CONVERTER
(ML87V230X)
or
MPEG
ENCODER
CLK
DATA
OUT
RESET
ICLK(27MHz)
75
IVS(OPEN) 29
IHS(OPEN) 30
NR-FIFO
ML87V2105
71
70
69
68
66
65
64
63
59
58
57
56
54
53
52
51
47
46
45
35
RESET
CI7(OPEN)
CI6(OPEN)
CI5(OPEN)
CI4(OPEN)
CI3(OPEN)
CI2(OPEN)
CI1(OPEN)
CI0(OPEN)
2,17,28,37,48,
55,62,72,78,98
VIDEO
IN
DIGITAL
VIDEO
DECODER
(ML86V7666)
7
8
9
10
11
12
13
14
18
19
20
21
22
23
24
25
GND
YI7
YI6
YI5
YI4
YI3
YI2
YI1
YI0
15,26,36,40,50,
60,67,76,88,100
3
4
SDA
SCL
VDD
I2C-bus
MATER
CONTROLLER
11/14
PEDL87V2105DIGEST-02
OKI Semiconductor
ML87V2105
PACKAGE DIMENSIONS
(Unit: mm)
TQFP100-P-1414-0.50-K
Mirror finish
5
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5µm)
0.55 TYP.
4/Oct. 28, 1996
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
12/14
PEDL87V2105DIGEST-02
OKI Semiconductor
ML87V2105
REVISION HISTORY
Page
Document
No.
Date
Previous
Edition
Current
Edition
PEDL87V2105DIGEST-01
Oct.20,2003
–
14
Preliminary edition 1
PEDL87V2105DIGEST-02
Dec.20,2003
14
14
Internal pull down, application schematic
Description
13/14
PEDL87V2105DIGEST-02
OKI Semiconductor
ML87V2105
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an explanation
for the standard action and performance of the product. When planning to use the product, please ensure that the
external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting
from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical
or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or
operation outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by
us in connection with the use of the product and/or the information and drawings contained herein. No
responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics,
etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application
that requires special or enhanced quality and reliability characteristics nor in any system or application where the
failure of such system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products and
will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2003 Oki Electric Industry Co., Ltd.
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