INNOVASIC N8344AH Sdlc communications controller Datasheet

IA8044/IA8344
SDLC Communications Controller
Data Sheet
March 30, 2010
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SDLC Communications Controller
Data Sheet
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Data Sheet
March 30, 2010
2010 by Innovasic Semiconductor, Inc.
Published by Innovasic Semiconductor, Inc.
3737 Princeton Drive NE, Suite 130, Albuquerque, NM 87107
Intel is a registered trademark of Intel Corporation.
MILES™ is a trademark of Innovasic Semiconductor, Inc.
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TABLE OF CONTENTS
List of Figures ..................................................................................................................................6
List of Tables ...................................................................................................................................7
1.
Introduction.............................................................................................................................9
1.1 Features .........................................................................................................................9
1.2 Variants .......................................................................................................................10
2.
Packaging, Pin Descriptions, and Physical Dimensions .......................................................10
2.1 PDIP Package ..............................................................................................................11
2.2 PDIP Physical Dimensions..........................................................................................13
2.3 PLCC Package .............................................................................................................14
2.4 PLCC Physical Dimensions ........................................................................................16
3.
Maximum Ratings and DC Characteristics ..........................................................................17
4.
Functional Description..........................................................................................................17
4.1 Functional Block Diagram ..........................................................................................17
4.2 Input/Output Characteristics .......................................................................................19
4.3 Memory Organization .................................................................................................20
4.3.1 Program Memory ............................................................................................20
4.3.2 External Data Memory ...................................................................................20
4.3.3 Internal Data Memory.....................................................................................20
4.3.4 Bit Addressable Memory ................................................................................22
4.4 Special Function Registers ..........................................................................................23
4.5 Ports .............................................................................................................................24
4.6 Port Registers ..............................................................................................................24
4.6.1 Port 0 (P0) .......................................................................................................24
4.6.2 Port 1 (P1) .......................................................................................................25
4.6.3 Port 2 (P2) .......................................................................................................25
4.6.4 Port 3 (P3) .......................................................................................................25
4.7 Timers/Counters ..........................................................................................................26
4.7.1 Timers 0 and 1 ................................................................................................26
4.7.2 Mode 0 ............................................................................................................26
4.7.3 Mode 1 ............................................................................................................27
4.7.4 Mode 2 ............................................................................................................27
4.7.5 Mode 3 ............................................................................................................27
4.7.6 Timer Mode (TMOD) .....................................................................................27
4.7.7 Timer Control (TCON) ...................................................................................28
4.7.8 Timer 0 High Byte (TH0) ...............................................................................29
4.7.9 Timer 0 Low Byte (TL0) ................................................................................29
4.7.10 Timer 1 High Byte (TH1) ...............................................................................29
4.7.11 Timer 1 Low Byte (TL1) ................................................................................29
4.7.12 Timer/Counter Configuration .........................................................................30
4.8 General CPU Registers ................................................................................................32
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5.
Data Sheet
March 30, 2010
4.8.1 Accumulator (ACC)........................................................................................32
4.8.2 B Register (B) .................................................................................................32
4.8.3 Program Status Word (PSW) ..........................................................................32
4.8.4 Stack Pointer (SP) ...........................................................................................33
4.8.5 Data Pointer (DPTR) ......................................................................................33
4.9 Interrupts .....................................................................................................................34
4.9.1 External Interrupts ..........................................................................................34
4.9.2 Timer 0 and Timer 1 Interrupts ......................................................................34
4.9.3 Serial Interface Unit Interrupt .........................................................................34
4.9.4 Interrupt Priority Level Structure ...................................................................34
4.9.5 Interrupt Handling ..........................................................................................35
4.9.6 Interrupt Priority Register (IP)........................................................................35
4.9.7 Interrupt Enable Register (IE) ........................................................................36
4.10 SIU—Serial Interface Unit ..........................................................................................36
4.10.1 SIU Special Function Registers ......................................................................37
4.10.2 Serial Mode Register (SMD) ..........................................................................37
4.10.3 Status/Command Register (STS) ....................................................................38
4.10.4 Send/Receive Count Register (NSNR) ...........................................................39
4.10.5 Station Address Register (STAD) ..................................................................40
4.10.6 Transmit Buffer Start Address Register (TBS) ..............................................40
4.10.7 Transmit Buffer Length Register (TBL) .........................................................40
4.10.8 Transmit Control Byte Register (TCB) ..........................................................40
4.10.9 Receive Buffer Start Address Register (RBS) ................................................41
4.10.10 Receive Buffer Length Register (RBL) ..........................................................41
4.10.11 Receive Field Length Register (RFL) .............................................................41
4.10.12 Receive Control Byte Register (RCB) ............................................................41
4.10.13 DMA Count Register (DMA CNT) ................................................................42
4.10.14 DMA Count Register (FIFO)..........................................................................42
4.10.15 SIU State Counter (SIUST) ............................................................................42
4.11 Data Clocking Options ................................................................................................43
4.12 Operational Modes ......................................................................................................43
4.13 Frame Format Options ................................................................................................44
4.14 HDLC Restrictions ......................................................................................................46
4.15 SIU Details ..................................................................................................................46
4.15.1 BIP ..................................................................................................................46
4.15.2 BYP.................................................................................................................48
4.16 Diagnostics ..................................................................................................................48
AC Specifications .................................................................................................................50
5.1 Memory Access Waveforms .......................................................................................51
5.2 Serial I/O Waveforms ..................................................................................................55
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6.
7.
8.
9.
10.
11.
Data Sheet
March 30, 2010
Reset .....................................................................................................................................56
Instruction Set .......................................................................................................................57
Innovasic/Intel Part Number Cross-Reference Tables .........................................................61
Errata.....................................................................................................................................62
9.1 Summary .....................................................................................................................62
9.2 Detail ...........................................................................................................................62
Revision History ...................................................................................................................64
For Additional Information...................................................................................................65
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LIST OF FIGURES
Figure 1. IA8044 and IA8344 40-Lead PDIP Package Diagram..................................................11
Figure 2. PDIP Physical Package Dimensions .............................................................................13
Figure 3. IA8044 and IA8344 44-Pin PLCC Package Diagram ...................................................14
Figure 4. PLCC Physical Package Dimensions ............................................................................16
Figure 5. Functional Block Diagram ............................................................................................18
Figure 6. Internal Data Memory Addresses 00h to FFh ...............................................................21
Figure 7. Timer 0 Mode 0 .............................................................................................................30
Figure 8. Timer 0 Mode 1 .............................................................................................................30
Figure 9. Timer 0 Mode 2 .............................................................................................................31
Figure 10. Timer 0 Mode 3 ...........................................................................................................31
Figure 11. Bit and Byte Processors ...............................................................................................47
Figure 12. Diagnostic Signal Routing ...........................................................................................49
Figure 13. Program Memory Read Cycle .....................................................................................52
Figure 14. Data Memory Read Cycle ...........................................................................................53
Figure 15. Data Memory Write Cycle ..........................................................................................54
Figure 16. Synchronous Data Transmission .................................................................................55
Figure 17. Synchronous Data Reception ......................................................................................55
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LIST OF TABLES
Table 1. IA8044 and IA8344 40-Lead PDIP Pin Listing..............................................................12
Table 2. IA8044 and IA8344 44-Pin PLCC Pin Listing ...............................................................15
Table 3. IA8044 and IA8344 Absolute Maximum Ratings ..........................................................17
Table 4. IA8044 and IA8344 DC Characteristics .........................................................................17
Table 5. Input/Output Characteristics of IC Signals .....................................................................19
Table 6. Reset Vectors ..................................................................................................................20
Table 7. SFR Bit Addressable Locations ......................................................................................22
Table 8. Internal RAM Bit Addressable Locations ......................................................................22
Table 9. Special Function Registers..............................................................................................23
Table 10. Additional Functions of Port P3 ...................................................................................24
Table 11. Port 0 Register ..............................................................................................................25
Table 12. Port 1 Register ..............................................................................................................25
Table 13. Port 2 Register ..............................................................................................................25
Table 14. Port 3 Register ..............................................................................................................26
Table 15. Timer Mode Register ....................................................................................................27
Table 16. Timer Mode Select Bits ................................................................................................28
Table 17. Timer Control Register .................................................................................................28
Table 18. Timer 0 High Byte Register ..........................................................................................29
Table 19. Timer 0 Low Byte Register ..........................................................................................29
Table 20. Timer 1 High Byte Register ..........................................................................................29
Table 21. Timer 1 Low Byte Register ..........................................................................................29
Table 22. Accumulator Register ...................................................................................................32
Table 23. B Register .....................................................................................................................32
Table 24. Program Status Word Register .....................................................................................32
Table 25. RS1/RS0 Bank Selections by State ...............................................................................33
Table 26. Stack Pointer .................................................................................................................33
Table 27. Data Pointer (High) Register ........................................................................................33
Table 28. Data Pointer (Low) Register .........................................................................................33
Table 29. Interrupt Priority Register .............................................................................................35
Table 30. Interrupt Enable Register ..............................................................................................36
Table 31. Serial Mode Register ....................................................................................................37
Table 32. Serial Mode Select Clock Mode Bits ............................................................................38
Table 33. Status/Command Register.............................................................................................38
Table 34. Send/Receive Count Register .......................................................................................39
Table 35. Station Address Register ...............................................................................................40
Table 36. Transmit Buffer Start Address Register........................................................................40
Table 37. Transmit Buffer Length Register ..................................................................................40
Table 38. Transmit Control Byte Register ....................................................................................41
Table 39. Receive Buffer Start Address Register .........................................................................41
Table 40. Receive Buffer Length Register ...................................................................................41
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Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Data Sheet
March 30, 2010
Receive Field Length Register ......................................................................................41
Receive Control Byte Register .....................................................................................42
DMA Count Register (DMA CNT) ..............................................................................42
DMA Count Register (FIFO) ........................................................................................42
SIU State Counter .........................................................................................................42
Basic SDLC Frame .......................................................................................................44
Frame Format Options ..................................................................................................45
External Program Memory Characteristics...................................................................50
External Data Memory Characteristics .........................................................................50
Serial Interface Characteristics .....................................................................................51
External Clock Drive Characteristics ...........................................................................51
Reset Values Register ...................................................................................................56
Arithmetic Operations...................................................................................................57
Logic Operations...........................................................................................................58
Data Transfer ................................................................................................................59
Boolean Manipulation...................................................................................................60
Program Branches .........................................................................................................60
Innovasic/Intel Part Number Cross-Reference for the PDIP ........................................61
Innovasic/Intel Part Number Cross-Reference for the PLCC .......................................61
Summary of Errata ........................................................................................................62
Revision History ...........................................................................................................64
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1.
Data Sheet
March 30, 2010
Introduction
The Innovasic Semiconductor IA8044 and IA8344 are ―plug-and-play‖ drop-in replacements and
are form, fit, and function compatible parts to the Intel 8044 and 8344 (see Chapter 4,
Innovasic/Intel Part Number Cross-Reference Tables). These devices are produced using
Innovasic’s Managed IC Lifetime Extension System (MILES™). This cloning technology, which
produces replacement ICs beyond simple emulations, ensures complete compatibility with the
original device, including any ―undocumented features.‖ Additionally, the MILES™ process
captures the clone design in such a way that production of the clone can continue even as silicon
technology advances. The IA8044 and IA8344 replace the obsolete Intel 8044 and 8344, allowing
users to retain existing board designs, software compilers/assemblers, and emulation tools—thus
avoiding expensive redesign efforts.
The IA8044 and IA8344 are Fast Single-Chip 8-Bit Microcontrollers with an integrated
SDLC/HDLC serial interface controller. They are fully functional 8-Bit Embedded Controllers
that execute all ASM51 instructions and have the same instruction set as the Intel 80C51. The
IA8044 and IA8344 can access the instructions from two types of program memory, serve
software and hardware interrupts, and provide interface for serial communications and a timer
system. The IA8044 and IA8344 are fully compatible with the Intel 8X44 series.
This data sheet documents all necessary engineering information about the IA8044 and IA8344
including functional and I/O descriptions, electrical characteristics, and applicable timing.
1.1
Features
Form, fit, and function compatible with the Intel 8044 and 8344
Packaging options available in both leaded and RoHS versions:
– 40-Pin Plastic Dual In-Line Package (PDIP) (see IA8044 40-Lead PDIP Package
Diagram)
– 44-Pin Plastic Leaded Chip Carrier (PLCC) (see IA8344 44-Pin PLCC Package
Diagram)
8-bit control unit (see Functional Block Diagram)
8-bit arithmetic-logic unit with 16-bit multiplication and division
12-MHz clock
Four 8-bit input/output ports
Two 16-bit timer/counters
Serial interface unit with SDLC/HDLC compatibility
2.4-Mbps maximum serial data rate
Two-level priority interrupt system
5 interrupt sources
Internal clock prescaler and phase generator
192 bytes of read/write data memory space
64-Kbyte external program memory space
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64-Kbyte external data memory space
4-Kbyte internal ROM (IA8044 only)
1.2
Variants
IA8044
– 4-Kbyte internal ROM with R0117 version 2.3 firmware
– 192-byte internal RAM
– 64-Kbyte external program and data space
IA8344
– 192-byte internal RAM
– 64-Kbyte external program and data space
2.
Packaging, Pin Descriptions, and Physical Dimensions
The Innovasic Semiconductor IA8044 and IA8344 serial controllers are available in the following
packages:
40-Pin Plastic Dual In-Line Package (PDIP), equivalent to original PDIP package
(see Physical Package Dimensions)
44-Lead Plastic Leaded Chip Carrier (PLCC), equivalent to original PLCC package
(see Physical Package Dimensions)
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2.1
Data Sheet
March 30, 2010
PDIP Package
The pinout for the IA8044 and IA8344 40 PDIP package is as shown in Figure 1. Although
Figure 1 shows ―IA8X44,‖ each device has a complete part number marked on its face (see
Chapter 8, Innovasic/Intel Part Number Cross-Reference Tables). The corresponding pinout is
provided in Table 1.
P1.0
(1)
( 40)
VCC
P1.1
(2)
( 39)
P0. 0 ( AD0)
P1.2
(3)
( 38)
P0.1 ( AD 1)
P1.3
(4)
( 37)
P0. 2 ( AD 2)
P1.4
(5)
( 36)
P0.3 ( AD 3)
P1.5
(6)
( 35)
P0. 4 ( AD 4)
®
( RTS ) P1.6
(7)
( 34)
P0.5 ( AD 5)
( CTS ) P1.7
(8)
( 33)
P0.6 ( AD 6)
RST
(9)
( 32)
P 0.7 ( AD 7)
( 31)
EA
IA8X44
PDIP
( RXD ) P 3.0
(10)
( TXD ) P 3.1
(11)
( 30)
ALE
( INT0 ) P 3.2
(12)
( 29)
PSEN
( INT1 ) P 3.3
(13)
( 28)
P 2.7 ( A15)
( T0 ) P3.4
(14)
( 27)
P 2.6 ( A14)
( SCLK/T1 ) P3.5
(15)
( 26)
P 2.5 ( A13 )
( WR ) P 3.6
(16)
( 25)
P 2.4 ( A12)
( RD ) P 3.7
(17)
( 24)
P 2.3 ( A11)
XTAL2
(18)
( 23)
P 2.2 ( A10 )
XTAL1
(19)
( 22)
P 2.1 ( A9)
VSS
( 20)
( 21)
P 2. 0 ( A8)
Figure 1. IA8044 and IA8344 40-Lead PDIP Package Diagram
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Table 1. IA8044 and IA8344 40-Lead PDIP Pin Listing
Pin
1
2
3
4
5
6
7
8
9
10
Name
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6 (RTS)
P1.7 (CTS)
RST
P3.0 (RXD)
Pin
11
12
13
14
15
16
17
18
19
20
®
Name
P3.1 (TXD)
P3.2 (INT0)
P3.3 (INT1)
P3.4 (T0)
P3.5 (SCLK/T1)
P3.6 (WR)
P3.7 (RD)
XTAL2
XTAL1
VSS
Pin
21
22
23
24
25
26
27
28
29
30
Name
P2.0 (A8)
P2.1 (A9)
P2.2 (A10)
P2.3 (A11)
P2.4 (A12)
P2.5 (A13)
P2.6 (A14)
P2.7 (A15)
PSEN
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Pin
31
32
33
34
35
36
37
38
39
40
Name
EA
P0.7 (AD7)
P0.6 (AD6)
P0.5 (AD5)
P0.4 (AD4)
P0.3 (AD3)
P0.2 (AD2)
P0.1 (AD1)
P0.0 (AD0)
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2.2
Data Sheet
March 30, 2010
PDIP Physical Dimensions
The physical dimensions for the 40 PDIP are as shown in Figure 2.
E1
E
Lead 1
Identifier
Lead Count 1
Direction
C
eB
Top
Side View (Width)
Legend:
A
D
A1
Symbol
A
A1
B
B1
C
D
e
E
E1
eB
L
Typical
(in Inches)
0.155
0.010
0.018
0.050
0.010
2.055
0.100
0.600
0.545
0.650
0.130
L
B
B1
e
Side View (Length)
Figure 2. PDIP Physical Package Dimensions
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2.3
Data Sheet
March 30, 2010
PLCC Package
P1.4
P1.3
P1.2
P1.1
P1.0
N.C.
VCC
P0.0
P0.1
P0.2
P0.3
(6)
(5)
(4)
(3)
(2)
(1)
(44)
(43)
(42)
(41)
(40)
The pinout for the IA8044 and IA8344 44 PLCC package is as shown in Figure 3. Although
Figure 3 shows ―IA8X44,‖ each device has a complete part number marked on its face (see
Chapter 8, Innovasic/Intel Part Number Cross-Reference Tables). The corresponding pinout is
provided in Table 2.
P1.5
(7)
(39)
P0.4
P1.6
(8)
(38)
P0.5
P1.7
(9)
(37)
P0.6
(36)
P0.7
RST/ VPD
(10)
®
P3.0
(11)
(35)
EA
N.C.
(12)
(34)
N.C.
P3.1
(13)
(33)
ALE
P3.2
(14)
(32)
PSEN
P3.3
(15)
(31)
P2.7
P3.4
(16)
(30)
P2.6
P3.5
(17)
(29)
P2.5
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
P3.6
P3.7
XTAL2
XTAL1
VSS
N.C.
P2.0
P2.1
P2.2
P2.3
P2.4
IA8X44
PLCC
Figure 3. IA8044 and IA8344 44-Pin PLCC Package Diagram
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Table 2. IA8044 and IA8344 44-Pin PLCC Pin Listing
Pin
1
2
3
4
5
6
7
8
9
10
11
Name
N.C.
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST/VPD
P3.0
Pin
12
13
14
15
16
17
18
19
20
21
22
®
Name
N.C.
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
XTAL2
XTAL1
VSS
Pin
23
24
25
26
27
28
29
30
31
32
33
Name
N.C.
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
PSEN
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Pin
34
35
36
37
38
39
40
41
42
43
44
Name
N.C.
EA
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
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2.4
Data Sheet
March 30, 2010
PLCC Physical Dimensions
0.045*45°
The physical dimensions for the 44 PLCC are as shown in Figure 4.
D
Pin 1
Identifier & Zone
E1
E
E3
D1
D3
Top View
Bottom View
0.026–0.032
Legend:
A1
A
Seating Plane
0.004
e
0.02 Min.
R 0.035
0.013–0.021
D2 /E2
Symbol
A
A1
D1
D2
D3
E1
E2
E3
e
D
E
Typical
(in Inches)
0.180
0.110
0.653
0.610
0.500
0.653
0.610
0.500
0.050
0.690
0.690
Side View
Figure 4. PLCC Physical Package Dimensions
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3.
Data Sheet
March 30, 2010
Maximum Ratings and DC Characteristics
The IA8044/IA8344 absolute maximum ratings and DC characteristics are provided in Tables 3
and 4, respectively.
Table 3. IA8044 and IA8344 Absolute Maximum Ratings
Parameter
Ambient temperature under bias
Storage temperature
Power supply (VDD)
Voltage on any pin to VSS
Power dissipation
Rating
−40°C to +85°C
−40°C to +150°C
−0.3 to +6VDC
−0.3 to (VDD +0.3)a
2W
aThis
device does not contain EPROM or its related programming circuitry. Therefore, this limit must be
adhered to especially for input pin EA, which is used as the programming voltage pin in the Intel device.
Exceeding the listed maximum voltage will cause damage to the device.
Table 4. IA8044 and IA8344 DC Characteristics
Symbol
VIL
VIH
VOL
VOH
RPU
RPD
IIL
IIL1
IIH
IIH1
IOZ
ICC
CIO
Parameter
Input Low Voltage
Input High Voltage
Output Low Voltage (IOL= 4mA)
Output High Voltage (IOH= 4mA)
Pull-Up Resistance (Ports 1, 2, 3)
Pull-Down Resistance (RST)
Input Low Current (Ports 1, 2, 3)
Input Low Current (PO, EA)
Input High Current (RST)
Input High Current (PO, EA)
Tri-state Leakage Current (Port 0)
Power Supply Current (@ 12 MHz)
Pin Capacitance
4.
Functional Description
4.1
Functional Block Diagram
Min
–
2.0
–
3.5
–
–
−200
−1
−1
−1
−10
–
–
Typ
–
–
–
–
50
50
–
–
–
–
–
–
4
Max
0.8
–
0.4
–
–
–
1
1
200
1
10
50
–
Unit
V
V
V
V
KW
KW
µA
µA
µA
µA
µA
mA
pF
A functional block diagram of the IA8044 and IA8344 is shown in Figure 5. Descriptions of the
functional modules are provided in the following subsections.
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Data Sheet
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I/O for Memory, SIU, DMA, Interrupts, and Timers
Port 0
ADDR/DATA/IO
Port 2
Addr/Data/IO
Port 1
SPCL FUNC/IO
Port 3
SPCL FUNC/IO
Memory
Control
XTAL
Clock Gen.
& Timing
192x8 Dual Port
RAM
C8051
CPU
Control
Reset
Address/Data
SIU
Interrupts
Timers
Figure 5. Functional Block Diagram
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4.2
Data Sheet
March 30, 2010
Input/Output Characteristics
Table 5 describes the I/O characteristics for each signal on the IC. The signal names correspond
to those on the pinout diagrams provided. The table provides the I/O description of the IA8044
and the IA8344.
Table 5. Input/Output Characteristics of IC Signals
Name
RST
Type
I
ALE
O
PSEN
O
EA
I
P0.7–P0.0
I/O
P1.7–P1.0
I/O
P2.7–P2.0
I/O
P3.7–P3.0
I/O
XTAL1
I
XTAL2
O
VSS
VCC
P
P
®
Description
Reset—This pin will cause the chip to reset when held high for two machine
cycles while the oscillator is running.
Address Latch Enable—Used to latch the address on the falling edge for
external memory accesses.
Program Store Enable—When low, acts as an output enable for external
program memory.
External Access—When held low, EA will cause the IA8044/IA8344 to fetch
instructions from external memory.
Port 0—8-bit I/O port and low order multiplexed address/data byte for external
accesses.
Port 1—8-bit I/O port. Two bits have alternate functions, P1.6 (RTS) and P1.7
(CTS).
Port 2—8-bit I/O port. It also functions as the high order address byte during
external accesses.
Port 3—8-bit I/O port. Port 3 bits also have alternate functions as described
below.
P3.0 (RXD)—Receives data input for SIU or direction control for P3.1
dependent upon data link configuration.
P3.1 (TXD)—Transmits data output for SIU or data input/output dependent
upon data link configuration. Also enables diagnostic mode when cleared.
P3.2 (INT0)—Interrupt 0 input or gate control input for Counter 0.
P3.3 (INT1)—Interrupt 1 input or gate control input for Counter 1.
P3.4 (T0)—Input to Counter 0.
P3.5 (SCLK/T1)—SCLK input to SIU or input to Counter 1.
P3.6 (WR)—External memory write signal.
P3.7 (RD)—External memory read signal.
Crystal Input 1—Connects to VSS when external clock is used on XTAL2.
May be connected to a crystal (with XTAL2) or may be driven directly with a
clock source (XTAL2 not connected).
Crystal Input 2—May be connected to a crystal (with XTAL1) or may be driven
directly with an inverted clock source (XTAL1 tied to ground).
Ground.
+5V power.
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4.3
Data Sheet
March 30, 2010
Memory Organization
4.3.1
Program Memory
Program Memory includes interrupt and Reset vectors. The interrupt vectors are spaced at 8-byte
intervals, starting from 0003H for External Interrupt 0.
Table 6. Reset Vectors
Location
0003H
000BH
0013H
001BH
0023H
Service
External Interrupt 0
Timer 0 overflow
External Interrupt 1
Timer 1 overflow
SIU Interrupt
These locations may be used for program code, if the corresponding interrupts are not used
(disabled). The program memory space is 64K, from 0000H to FFFFH. The lowest 4K of
program code (0000H to 0FFFH) can be fetched from external or internal program memory. This
selection is made by strapping pin ―EA‖ (External Address) to GND or VCC. If during reset
―EA‖ is held low, all the program code is fetched from external memory. If during reset ―EA‖ is
held high, the lowest 4K of program code (0000H to 0FFFH) is fetched from internal memory
(ROM). Program memory addresses above 4K (0FFFH) will cause the program code to be
fetched from external memory regardless of the setting of ―EA.‖
4.3.2
External Data Memory
The IA8044/IA8344 Microcontroller core incorporates the Harvard architecture, with separate
code and data spaces. The code from external memory is fetched by ―psen‖ strobe, while data
is read from RAM by Bit [7] of P3 (read strobe) and written to RAM by Bit [6] of P3 (write
strobe). The External Data Memory space is active only by addressing through use of the MOVX
instruction and the 16-bit Data Pointer Register (DPTR). A smaller subset of external data
memory (8-bit addressing) may be accessed by using the MOVX instruction with register indexed
addressing.
4.3.3
Internal Data Memory
As presented in Figure 6, the Internal Data Memory address is always one byte wide. The
memory space is 192 bytes large (00H to BFH), and can be accessed by either direct or indirect
addressing. The special function registers (SFRs) occupy the upper 128 bytes. This SFR area is
available only by direct addressing. Internal memory that overlaps the SFR address space is only
accessible by indirect addressing.
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FFh
Special Function
Registers
(SFRs)
BFh
Addressable
Bits in SFRs
(128 Bits)
RAM
Indirect
Addressing
80h
Direct Addressing
80h
7Fh
30h
2Fh
20h
1Fh
Bit Addressable
Memory
Register Bank 3
18h
17h
Register Bank 2
10h
0Fh
Register Bank 1
08h
07h
Register Bank 0
00h
Internal Data RAM
Figure 6. Internal Data Memory Addresses 00h to FFh
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4.3.4
Data Sheet
March 30, 2010
Bit Addressable Memory
Both the internal RAM and the SFRs have locations that are bit addressable in addition to the byte
addressable locations (see Tables 7 and 8).
Table 7. SFR Bit Addressable Locations
Byte Address
F0h
E0h
D8h
D0h
C8h
B8h
B0h
A8h
A0h
90h
88h
80h
Bit [7]
F7h
E7h
DFh
D7h
CFh
–
B7h
AFh
A7h
97h
8Fh
87h
Bit [6]
F6h
E6h
DEh
D6h
CEh
–
B6h
–
A6h
96h
8Eh
86h
Bit [5]
F5h
E5h
DDh
D5h
CDh
–
B5h
–
A5h
95h
8Dh
85h
Bit [4]
F4h
E4h
DCh
D4h
CCh
BCh
B4h
ACh
A4h
94h
8Ch
84h
Bit [3]
F3h
E3h
DBh
D3h
CBh
BBh
B3h
ABh
A3h
93h
8Bh
83h
Bit [2]
F2h
E2h
DAh
D2h
CAh
BAh
B2h
AAh
A2h
92h
8Ah
82h
Bit [1]
F1h
E1h
D9h
D1h
C9h
B9h
B1h
A9h
A1h
91h
89h
81h
Bit [0]
F0h
E0h
D8h
D0h
C8h
B8h
B0h
A8h
A0h
90h
88h
80h
Bit [3]
Bit [2]
Bit [1]
Bit [0]
7Bh
73h
6Bh
63h
5Bh
53h
4Bh
43h
3Bh
33h
2Bh
23h
1Bh
13h
0Bh
03h
7Ah
72h
6Ah
62h
5Ah
52h
4Ah
42h
3Ah
32h
2Ah
22h
1Ah
12h
0Ah
02h
79h
71h
69h
61h
59h
51h
49h
41h
39h
31h
29h
21h
19h
11h
09h
01h
78h
70h
68h
60h
58h
50h
48h
40h
38h
30h
28h
20h
18h
10h
08h
00h
Register
B
ACC
NSNR
PSW
STS
IP
P3
IE
P2
P1
TCON
P0
Table 8. Internal RAM Bit Addressable Locations
Byte Address
30h-BFh
2Fh
2Eh
2Dh
2Ch
2Bh
2Ah
29h
28h
27h
26h
25h
24h
23h
22h
21h
20h
18h-1Fh
10h-17h
08h-0Fh
00h-07h
Bit [7] Bit [6] Bit [5] Bit [4]
Upper Internal RAM Locations
7Fh
7Eh
7Dh
7Ch
77h
76h
75h
74h
6Fh
6Eh
6Dh
6Ch
67h
66h
65h
64h
5Fh
5Eh
5Dh
5Ch
57h
56h
55h
54h
4Fh
4Eh
4Dh
4Ch
47h
46h
45h
44h
3Fh
3Eh
3Dh
3Ch
37h
36h
35h
34h
2Fh
2Eh
2Dh
2Ch
27h
26h
25h
24h
1Fh
1Eh
1Dh
1Ch
17h
16h
15h
14h
0Fh
0Eh
0Dh
0Ch
07h
06h
05h
04h
Register Bank 3
Register Bank 2
Register Bank 1
Register Bank 0
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4.4
Data Sheet
March 30, 2010
Special Function Registers
Table 9 presents the SFRs of the IA8044 and IA8344.
Table 9. Special Function Registers
Symbol
ACC
B
PSW
SP
DPH
DPL
P0
P1
P2
P3
IP
IE
TMOD
TCON
TH0
TL0
TH1
TL1
SMD
STS
NSNR
STAD
TBS
TBL
TCB
RBS
RBL
RFL
RCB
DMA CNT
FIFO
SIUST
Register Description
Accumulator
B register
Program Status Word
Stack Pointer
Data Pointer High Byte
Data Pointer Low Byte
Port 0
Port 1
Port 2
Port 3
Interrupt Priority
Interrupt Enable
Timer/Counter Mode
Timer/Counter Control
Timer/Counter 0 high byte
Timer/Counter 0 low byte
Timer/Counter 1 high byte
Timer/Counter 1 low byte
Serial Mode
SIU Status and Command
SIU Send/Receive Count
SIU Station Address
Transmit Buffer Start Address
Transmit Buffer Length
Transmit Control Byte
Receive Buffer Start Address
Receive Buffer Length
Receive Field Length
Receive Control Byte
DMA Count
FIFO contents (3 bytes)
SIU State Counter
®
Byte Address (Hex)
E0h
F0h
D0h
81h
82h
83h
80h
90h
A0h
B0h
B8h
A8h
89h
88h
8Ch
8Ah
8Dh
8Bh
C9h
C8h
D8h
CEh
DCh
DBh
DAh
CCh
CBh
CDh
CAh
CFh
DF,DE,DDh
D9h
Bit Addresses (Hex)
(MSB–LSB)
E7h–E0h
F7h–F0h
D7h–D0h
–
–
–
87h–80h
97h–90h
A7h–A0h
B7h–B0h
BCh–B8h
AFh,ACh–A8h
–
8Fh–88h
–
–
–
–
–
CFh–C8h
DFh–D8h
–
–
–
–
–
–
–
–
–
–
–
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4.5
Data Sheet
March 30, 2010
Ports
Ports P0, P1, P2, and P3 are SFRs. The contents of the SFR can be observed on corresponding
pins on the chip. Writing a ―1‖ to any of the ports causes the corresponding pin to be at high level
(VCC), and writing a ―0‖ causes the corresponding pin to be held at low level (GND).
All four ports on the chip are bi-directional. Each of them consists of a Latch (SFR P0 to P3), an
output driver, and an input buffer, so the CPU can output or read data through any of these ports if
they are not used for alternate purposes.
Ports P0, P1, P2, and P3 can perform some alternate functions. Ports P0 and P2 are used to access
external memory. In this case, port ―p0‖ outputs the multiplexed lower eight bits of address with
―ALE‖ strobe high and then reads/writes eight bits of data. Port P2 outputs the higher eight bits of
address. Keeping ―ea‖ pin low (tied to GND) activates this alternate function for Ports P0 and P2.
Port P3 and P1 can perform some alternate functions. The pins of Port P3 are multifunctional.
They can perform the additional functions described in Table 10.
Table 10. Additional Functions of Port P3
Pin
P3.0
Symbol
RxD, I/O
P3.1
TxD, DATA
P3.2
P3.3
P3.4
INT0
INT1
T0
P3.5
T1, SCLK
P3.6
WR
P3.7
RD
P1.6
P1.7
RTS
CTS
4.6
4.6.1
Function
In point-to-point or multipoint configurations (SMD.3 = 0) this pin is I/O and signals
the direction of data flow on DATA (P3.1). In loop mode (SMD.3 = 1) and
diagnostic mode this pin is RxD, Receive Data input.
In point-to-point or multipoint configurations (SMD.3 = 0) this pin is DATA and is
the transmit/receive data pin. In loop mode (SMD.3 = 1) this pin is the transmit
data, TxD pin. Writing a ―0‖ to this port buffer bit enables the diagnostic mode.
External Interrupt 0 input. Also gate control input for Counter 0.
External Interrupt 1 input. Also gate control input for Counter 1.
Timer/Counter 0 external input. Setting the appropriate bits in the Special
Function Registers TCON and TMOD activates this function.
Timer/Counter 1 external input. Setting the appropriate bits in the SFRs TCON
and TMOD activates this function. Can also function as the external clock source
for the SIU.
External Data Memory write strobe, active LOW. This function is activated by a
CPU write access to External Data Memory (i.e., MOVX @DPTR, A).
External Data Memory read strobe, active LOW. This function is activated by a
CPU read access from External Data Memory (i.e., MOVX A, @DPTR).
Request To Send output, active low.
Clear To Send input, active low.
Port Registers
Port 0 (P0)
Table 11 presents the values for Port 0 (P0), a general purpose, 8-bit, I/O port and multiplexed low
order address and data bus with open-drain output buffers.
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Table 11. Port 0 Register
7
P0.7
4.6.2
6
P0.6
5
P0.5
4
P0.4
3
P0.3
2
P0.2
1
P0.1
0
P0.0
Port 1 (P1)
Table 12 presents the values for Port 1 (P1), a general purpose, eight-bit, I/O port with pullups and
auxiliary functions.
Table 12. Port 1 Register
7
CTS/P1.7
6
RTS/P1.6
5
P1.5
4
P1.4
3
P1.3
2
P1.2
1
P1.1
0
P1.0
Bit [7]—P1.7/Clear To Send input
Bit [6]—P1.6/Request To Send output
Bit [5]—P1.5
Bit [4]—P1.4
Bit [3]—P1.3
Bit [2]—P1.2
Bit [1]—P1.1
Bit [0]—P1.0
4.6.3
Port 2 (P2)
Table 13 presents the values for Port 2, a general purpose, 8-bit, I/O port with pullups and high
order address bus.
Table 13. Port 2 Register
7
P2.7
4.6.4
6
P2.6
5
P2.5
4
P2.4
3
P2.3
2
P2.2
1
P2.1
0
P2.0
Port 3 (P3)
Table 14 presents the values for Port 2, a general purpose, 8-bit I/O port with pullups and auxiliary
functions. Bits on this port also function as the SIU data transmit/receive I/O, external interrupt
inputs, timer inputs and the read and write strobes for external memory accesses.
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Table 14. Port 3 Register
7
RD
6
WR
5
T1
4
T0
3
INT1
2
INT0
1
TxD
0
RxD
Bit [7]—RD → (P3.7) External Data Memory read strobe, active LOW
Bit [6]—WR → (P3.6) External Data Memory write strobe, active LOW
Bit [5]—T1 → (P3.5) Timer/Counter 1 external input
Bit [4]—T0 → (P3.4) Timer/Counter 0 external input
Bit [3]—INT1 → (P3.3) External Interrupt 1
Bit [2]—INT0 → (P3.2) External Interrupt 0
Bit [1]—TxD → (P3.1) Serial output pin
Bit [0]—RxD → (P3.0) Serial input pin
4.7
4.7.1
Timers/Counters
Timers 0 and 1
The IA8X44 has two 16-bit timer/counter registers, Timer 0 and Timer 1. Both can be configured
for counter or timer operations. In timer mode, the register is incremented every machine cycle,
which means that it counts up after every 12 oscillator periods. In counter mode, the register is
incremented when the falling edge is observed at the corresponding input pin T0 or T1. Because it
takes two machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/24 of the
oscillator frequency. There are no restrictions on the duty cycle, however to ensure proper
recognition of 0 or 1 state, an input should be stable for at least one machine cycle (12 clock
periods).
Four operating modes can be selected for Timer 0 and Timer 1. Two SFRs (TMOD and TCON)
are used to select the appropriate mode.
4.7.2
Mode 0
In Mode 0 the timers operate as an 8-bit timer (TH0/1) with a divide by 32-bit prescalar (TL0/1).
Mode 0 uses all eight bits of TH0/1 and the lower five bits of TL0/1. The upper three bits of
TL0/1 are unknowns. Setting TR0/1 does not reset the registers TH0/1 and TL0/1. As the timer
rolls over from all 1s to all 0s it will set the interrupt flag TF0/1.
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4.7.3
Data Sheet
March 30, 2010
Mode 1
Mode 1 is the same as Mode 0 except that all eight bits of TL0/1 are used instead of just the lower
five bits.
4.7.4
Mode 2
Mode 2 configures TL0/1 as an 8-bit counter with automatic reload from the contents of TH0/1.
Overflow of TL0/1 causes the interrupt TF0/1 to be set and the reload to occur. The contents of
TH0/1 are not affected by the reload.
4.7.5
Mode 3
Mode 3 creates two separate 8-bit counters from TL0 and TH0. TL0 uses the Timer 0 mode bits
from TMOD, TMOD.0 through TMOD.3. TH0 is a timer only (not a counter) and uses Timer 1’s
control bits, TR1 and TF1, for operation. Timer 1 can still be used if an interrupt is not required
by switching it in and out of its own Mode 3. With TMOD.4 and TMOD.5 both high, Timer 1
will stop and hold its count.
4.7.6
Timer Mode (TMOD)
Table 15 presents the values for the Timer Mode register, which contains bits that select the mode
that the timers are to be operated in. The lower nibble controls Timer 0 and the upper nibble
controls Timer 1. Table 16 presents the timer mode select bits.
Table 15. Timer Mode Register
7
GATE
6
C/T
5
M1
4
M0
3
GATE
2
C/T
1
M1
0
M0
Bit [7]—GATE → (TMOD.7) If set, enables external gate control for Counter/Timer 1 (pin
INT1 for Counter 1). When INT1 is high, and TR1 bit is set (see TCON register), the
counter is incremented every falling edge on T1 input pin.
Bit [6]—C/T → (TMOD.6) C/T selects Timer 1 or Counter 1 operation. When set to 1, the
counter operation is performed. When cleared to 0, the register will function as a timer.
Bit [5]—M1 → (TMOD.5) Timer 1 mode selector bit.
Bit [4]—M0 → (TMOD.4) Timer 1 mode selector bit.
Bit [3]—GATE → (TMOD.3) If set, enables external gate control for Counter/Timer 0 (pin
INT0 for Counter 0). When INT0 is high, and TR0 bit is set (see TCON register), the
counter is incremented every falling edge on T0 input pin.
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Bit [2]—C/T → (TMOD.2) C/T selects Timer 0 or Counter 0 operation. When set to 1, the
counter operation is performed. When cleared to 0, the register will function as a timer.
Bit [1]—M1 → (TMOD.1) Timer 0 mode selector bit.
Bit [0]—M0 → (TMOD.0) Timer 0 mode selector bit.
Table 16. Timer Mode Select Bits
M1
0
0
1
1
M0
0
1
0
1
0
1
2
3
1
1
3
4.7.7
Operating Mode
13-bit timer
16-bit timer/counter
8-bit auto-reload timer/counter
Timer 0–TL0 is a standard 8-bit timer/counter controlled by Timer 0 control bits. TH0 is an
8-bit timer function only, controlled by Timer 1 control bits.
Timer/Counter 1 stopped and holds its count. Can be used to start/stop Timer 1 when
Timer 0 is in Mode 3.
Timer Control (TCON)
Table 17 presents the timer control register, which provides control bits that start and stop the
counters. It also contains bits to select the type of external interrupt desired, edge or level.
Additionally, TCON contains status bits showing when a timer overflows and when an interrupt
edge has been detected.
Table 17. Timer Control Register
7
TF1
6
TR1
5
TF0
4
TR0
3
IE1
2
IT1
1
IE0
0
IT0
Bit [7]—TF1 → (TCON.7) Timer 1 overflow flag set by hardware when Timer 1
overflows. This flag should be cleared by software. In Mode 3 this bit is controlled by
TH0.
Bit [6]—TR1 → (TCON.6) Timer 1 run control bit. If cleared, Timer 1 stops. In Mode 3
this bit controls TH0.
Bit [5]—TF0 → (TCON.5) Timer 0 overflow flag set by hardware when Timer 0
overflows. This flag should be cleared by software.
Bit [4]—TR0 → (TCON.4) Timer 0 run control bit. If cleared, Timer 0 stops.
Bit [3]—IE1→ (TCON.3) Interrupt 1 edge flag. Set by hardware, when falling edge on
external pin INT1 is detected cleared when interrupt is processed.
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Bit [2]—IT1→ (TCON.2) Interrupt 1 type control bit. Selects falling edge or low level on
input pin to cause interrupt.
Bit [1]—IE0→ (TCON.1) Interrupt 0 edge flag. Set by hardware, when falling edge on
external pin INT1 is observed. Cleared when interrupt is processed.
Bit [0]—IT0→ (TCON.0) Interrupt 0 type control bit. Selects falling edge or low level on
input pin to cause interrupt.
4.7.8
Timer 0 High Byte (TH0)
Table 18 presents the high-order byte of Timer/Counter 0.
Table 18. Timer 0 High Byte Register
7
TH0.7
4.7.9
6
TH0.6
5
TH0.5
4
TH0.4
3
TH0.3
2
TH0.2
1
TH0.1
0
TH0.0
Timer 0 Low Byte (TL0)
Table 19 presents the low-order byte of Timer/Counter 0.
Table 19. Timer 0 Low Byte Register
7
TL0.7
6
TL0.6
5
TL0.5
4
TL0.4
3
TL0.3
2
TL0.2
1
TL0.1
0
TL0.0
4.7.10 Timer 1 High Byte (TH1)
Table 20 presents the high-order byte of Timer/Counter 1.
Table 20. Timer 1 High Byte Register
7
TH1.7
6
TH1.6
5
TH1.5
4
TH1.4
3
TH1.3
2
TH1.2
1
TH1.1
0
TH1.0
4.7.11 Timer 1 Low Byte (TL1)
Table 21 presents the low order byte of Timer/Counter 1.
Table 21. Timer 1 Low Byte Register
7
TL1.7
6
TL1.6
5
TL1.5
®
4
TL1.4
3
TL1.3
2
TL1.2
1
TL1.1
0
TL1.0
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4.7.12 Timer/Counter Configuration
Figures 7, 8, 9, and 10 present the configurations of Timer 0 Mode 0, Timer 0 Mode 1, Timer 0
Mode 2, and Timer 0 Mode 3, respectively.
OSC
12
C/ T
0
TLO
( 5 Bits )
C/ T
P3.4/T0
=1
TF0
Interrupt
TH0
( 8 Bits )
TF0
Interrupt
1
&
TR0
TH0
( 8 Bits )
Control
Gate
1
P3.2/ INT0
Figure 7. Timer 0 Mode 0
OSC
12
C/ T
0
TLO
( 8 Bits )
C/ T
P3.4/T0
=1
TR0
1
&
Control
Gate
1
P3.2/ INT0
Figure 8. Timer 0 Mode 1
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OSC
Data Sheet
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12
C/ T
0
TLO
( 8 Bits )
C/ T
P3.4/T0
=1
Interrupt
TF0
Interrupt
1
&
TR0
TF0
Control
Reload
Gate
1
TH0
( 8 Bits )
P3.2/ INT0
Figure 9. Timer 0 Mode 2
OSC
1/ 12 fOSC
12
C/ T
0
TLO
( 8 Bits )
C/ T
P3.4/T0
=1
TR0
1
&
Control
Gate
1
P3.2/ INT0
TH0
( 8 Bits )
1/ 12 fOSC
TF1
Interrupt
Control
TR1
Figure 10. Timer 0 Mode 3
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4.8
Data Sheet
March 30, 2010
General CPU Registers
4.8.1
Accumulator (ACC)
Table 22 presents the Accumulator Register. Most instructions use the accumulator to hold the
operand. The mnemonics for accumulator-specific instructions refer to accumulator as A, not
ACC.
Table 22. Accumulator Register
7
ACC.7
4.8.2
6
ACC.6
5
ACC.5
4
ACC.4
3
ACC.3
2
ACC.2
1
ACC.1
0
ACC.0
B Register (B)
Table 23 presents the B register, which is used during multiply and divide instructions. It can also
be used as a scratch-pad register to hold temporary data.
Table 23. B Register
7
B.7
4.8.3
6
B.6
5
B.5
4
B.4
3
B.3
2
B.2
1
B.1
0
B.0
Program Status Word (PSW)
Table 24 presents program status word, which contains CPU status flags, register select bits, and
user flags.
Table 24. Program Status Word Register
7
CY
6
AC
5
F0
4
RS1
3
RS0
2
OV
1
–
0
P
Bit [7]—CY → (PSW.7) Carry flag for carry out of or into Bit [7]
Bit [6]—AC → (PSW.7) Auxiliary carry flag for carry out of or into Bit [3]
Bit [5]—F0 → (PSW.7) General purpose Flag 0 available for user
Bit [4]—RS1 → (PSW.7) Register bank select control Bit [1], used to select working
register bank
Bit [3]—RS0 → (PSW.7) Register bank select control Bit [0], used to select working
register bank
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Bit [2]—OV → (PSW.7) Overflow flag
Bit [1]—(PSW.7) User defined flag
Bit [0]—P → (PSW.7) Parity flag, affected by hardware to indicate odd/even number of
―one‖ bits in the Accumulator (i.e., even parity)
The state of Bits RS1 and RS0 selects the working registers bank as presented in Table 25.
Table 25. RS1/RS0 Bank Selections by State
RS1/RS0
00
01
10
11
4.8.4
Bank selected location
Bank 0 (00H–07H)
Bank 1 (08H–0FH)
Bank 2 (10H–17H)
Bank 3 (18H–1FH)
Stack Pointer (SP)
Table 26 presents the stack pointer, which is a 1-byte register initialized to 07H after reset. This
register is incremented before PUSH and CALL instructions, causing the stack to begin at location
08H. The stack pointer points to a location in internal RAM.
Table 26. Stack Pointer
7
SP.7
4.8.5
6
SP.6
5
SP.5
4
SP.4
3
SP.3
2
SP.2
1
SP.1
0
SP.0
Data Pointer (DPTR)
The data pointer (DPTR) is two bytes wide. Table 27 presents the highest, which is DPH.
Table 28 presents the lower part, DPL. It can be loaded as a 2-byte register (MOV
DPTR,#data16) or as two registers (MOV DPL,#data8 each). It is generally used to access
external code (MOVC A,@A+DPTR each) or data space (MOV A,@DPTR).
Table 27. Data Pointer (High) Register
7
DPH.7
6
DPH.6
5
DPH.5
4
DPH.4
3
DPH.3
2
DPH.2
1
DPH.1
0
DPH.0
Table 28. Data Pointer (Low) Register
7
DPL.7
6
DPL.6
5
DPL.5
®
4
DPL.4
3
DPL.3
2
DPL.2
1
DPL.1
0
DPL.0
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4.9
Data Sheet
March 30, 2010
Interrupts
The IA8044/IA8344 provides five interrupt sources. There are two external interrupts accessible
through pins INT0 and INT1, edge or level sensitive (falling edge or low level). There are also
internal interrupts associated with Timer 0 and Timer 1 and an internal interrupt from the SIU.
4.9.1
External Interrupts
The choice between external interrupt level or transition activity is made by setting IT1 and IT0
bits in the SFR TCON. When the interrupt event happens, a corresponding Interrupt Control Bit is
set (IT0 or IT1). This control bit triggers an interrupt if the appropriate interrupt bit is enabled.
When the interrupt service routine is vectored, the corresponding control bit (IT0 or IT1) is
cleared, provided that the edge triggered mode was selected. If level mode is active, the external
requesting source controls flags IT0 or IT1 by the logic level on pins INT0 or INT1 (0 or 1).
4.9.2
Timer 0 and Timer 1 Interrupts
Timer 0 and 1 interrupts are generated by TF0 and TF1 flags, which are set by the rollover of
Timers 0 and 1, respectively. When an interrupt is generated, the flag that caused this interrupt is
cleared by the hardware if the CPU accessed the corresponding interrupt service vector. This can
be done only if this interrupt is enabled in the IE register.
4.9.3
Serial Interface Unit Interrupt
The SIU generates an interrupt when a frame is received or transmitted. No interrupts are
generated for a received frame with errors.
4.9.4
Interrupt Priority Level Structure
There are two priority levels in the IA8044/IA8344—any interrupt can be individually
programmed to a high or low priority level. Modifying the appropriate bits in the SFR IP can
accomplish this. A low-priority interrupt service routine will be interrupted by a high-priority
interrupt. However, the high-priority interrupt cannot be interrupted.
If two interrupts of the same priority level occur, an internal polling sequence determines which
will be processed first. This polling sequence is a second priority structure defined as follows:
IE0 1—highest
TF0 2
IE1 3
TF1 4
SIU—lowest
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4.9.5
Data Sheet
March 30, 2010
Interrupt Handling
The interrupt flags are sampled during each machine cycle. The samples are polled during the
next machine cycle. If an interrupt flag is captured, the interrupt system will generate an LCALL
instruction to the appropriate service routine, provided that this is not disabled by the following
conditions:
An interrupt of the same or higher priority is processed.
The current machine cycle is not the last cycle of the instruction (the instruction cannot be
interrupted).
The instruction in progress is RETI or any write to IE or IP registers.
Note: If an interrupt is disabled and the interrupt flag is cleared before the
blocking condition is removed, no interrupt will be generated because the
polling cycle will not sample any active interrupt condition. In other words,
the interrupt condition is not remembered; every polling cycle is new.
4.9.6
Interrupt Priority Register (IP)
This register sets the interrupt priority to high or low for each interrupt. When the bit is set, it
selects high priority. Within each level the interrupts are prioritized as follows:
External Interrupt 0
Timer/Counter 0
External Interrupt 1
Timer/Counter 1
SIU
An interrupt process routine cannot be interrupted by an interrupt of lesser or equal priority (see
Table 29).
Table 29. Interrupt Priority Register
7
–
6
–
5
–
4
PS
3
PT1
2
PX1
1
PT0
0
PX0
Bit [7]—(IP.7)
Bit [6]—(IP.6)
Bit [5]—(IP.5)
Bit [4]—PS → (IP.4) SIU interrupt priority bit
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Bit [3]—PT1 → (IP.3) Timer 1 interrupt priority bit
Bit [2]—PX1 → (IP.2) External Interrupt 1 interrupt priority bit
Bit [1]—PT0 → (IP.1) Timer 0 interrupt priority bit
Bit [0]—PX0 → (IP.0) External Interrupt 0 interrupt priority bit
4.9.7
Interrupt Enable Register (IE)
Table 30 presents the interrupt enable register, which contains the global interrupt enable bit and
individual interrupt enable bits. Setting a bit enables the corresponding interrupt.
Table 30. Interrupt Enable Register
7
EA
6
–
5
–
4
ES
3
ET1
2
EX1
1
ET0
0
EX0
Bit [7]—EA → (PCON.7) Enable all interrupts bit
Bit [6]—(PCON.6)
Bit [5]—(PCON.5)
Bit [4]—ES → (PCON.4) SIU interrupt enable bit
Bit [3]—ET1 → (PCON.3) Timer 1 interrupt enable bit
Bit [2]—EX1→ (PCON.2) External Interrupt 1 interrupt enable bit
Bit [1]—ET0→ (PCON.1) Timer 0 interrupt enable bit
Bit [0]—EX0→ (PCON.7) External Interrupt 0 interrupt enable bit
4.10
SIU—Serial Interface Unit
The SIU is a serial interface customized to support SDLC/HDLC protocol. As such, it supports
Zero Bit insertion/deletion, flags automatic access recognition and a 16-bit CRC. The SIU has
two modes of operation AUTO and FLEXIBLE. The AUTO mode uses a subset of the SDLC
protocol implemented in hardware. This frees the CPU from having to respond to every frame but
limits the frame types. In the FLEXIBLE mode every frame is under CPU control and therefore
more options are available. The SIU is controlled by and communicates to the CPU by using
several SFRs. Data transmitted by or received by the SIU is stored in the 192-byte internal RAM
in blocks referred to as the transmit and receive buffers. The SIU can support operation in one of
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three serial data link configurations, 1) half-duplex, point-to-point, 2) half-duplex, multipoint,
or 3) loop mode.
4.10.1 SIU Special Function Registers
The CPU controls the SIU and receives status from the SIU via 11 SFRs. The Serial Interface
Unit Control Registers are detailed in the sections that follow.
4.10.2 Serial Mode Register (SMD)
Table 31 presents the serial mode register, which sets the operational mode of the SIU. The CPU
can read and write SMD. The SIU can read SMD. To prevent conflicts between CPU and SIU,
accesses to SMD the CPU should write SMD only when RTS and RBE bits in the STS register are
both zero. SMD is normally only accessed during initialization. This register is byte addressable.
Table 32 presents the serial mode select clock mode bits.
Table 31. Serial Mode Register
7
SCM2
6
SCM1
5
SCM0
4
NRZI
3
LOOP
2
PFS
1
NB
0
NFCS
Bit [7]—SCM2 → (SMD.7) Select clock mode—Bit [2].
Bit [6]—SCM1 → (SMD.6) Select clock mode—Bit [1].
Bit [5]—SCM0 → (SMD.5) Select clock mode—Bit [0].
Bit [4]—NRZI → (SMD.4) When set selects NRZI encoding otherwise NRZ.
Bit [3]—LOOP → (SMD.3) When set, selects loop configuration, else point-to-point
mode.
Bit [2]—PFS → (SMD.2) Pre-frame sync mode. When set, causes two bytes to be
transmitted before the first flag of the frame for DPLL synchronization. If NRZI is set,
00H is transmitted, otherwise 55H. This ensures that 16 transitions are sent before the
opening flag.
Bit [1]—NB → (SMD.1) Non-buffered mode. No control field contained in SDLC frame.
Bit [0]—NFCS → (SMD.0) When set, selects No FCS field contained in the SDLC frame.
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Table 32. Serial Mode Select Clock Mode Bits
SCM
210
000
001
010
011
100
101
110
111
Clock Mode
Externally clocked
Undefined
Self clocked, timer overflow
Undefined
Self clocked, external 16X
Self clocked, external 32X
Self clocked, internal fixed
Self clocked, internal fixed
Data Rate
(bits/sec)a
0–2.4Mb
244–62.5K
0–375K
0–187.5K
375K
187.5K
aBased
b0–1
on a12-MHz crystal frequency.
Mbps in loop configuration.
4.10.3 Status/Command Register (STS)
Table 33 presents the Status/Command Register, which provides SIU control from and status to
the CPU. The SIU can read the STS and can write certain bits in the STS. The CPU can read and
write the STS. Accessing the STS by the CPU via two cycle instructions—JBC bit,rel and
MOV bit,C—should not be used. STS is bit addressable.
Table 33. Status/Command Register
7
TBF
6
RBE
5
RTS
4
SI
3
BOV
2
OPB
1
AM
0
RBP
Bit [7]—TBF → (STS.7) Transmit buffer full. TBF is set by the CPU to indicate that the
transmit buffer is ready and TBF is cleared by the SIU.
Bit [6]—RBE → (STS.6) Receive buffer empty. RBE is set by the CPU when it is ready
to receive a frame or has just read the buffer. RBE is cleared by the SIU when a frame has
been received. Can be thought of as a Receive Enable.
Bit [5]—RTS → (STS.5) Request to send. This bit is set when the SIU is ready to transmit
or is transmitting. May be written by the SIU in AUTO mode. RTS is only applied to the
external pin in non-loop mode. Can be thought of as a Transmit Enable.
Note: RTS signal at the pin (P1.6) is the inverted version of this bit.
Bit [4]—SI → (STS.4) SIU interrupt. This bit is set by the SIU and should be cleared by
the CPU before returning from the interrupt routine.
Bit [3]—BOV → (STS.3) Receive buffer overrun. The SIU can set or clear BOV.
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Bit [2]—OPB → (STS.2) Optional poll bit. When set, the SIU will AUTO respond to an
optional poll (UP with P=0). The SIU can set or clear the OPB.
Bit [1]—AM → (STS.1) Auto mode. Dual purpose bit depending upon the setting of bit
NB (SMD.1). If NB is cleared, AM selects the AUTO mode when set, Flexible mode
when clear. If NB is set, AM selects the addressed mode when set and the non-addressed
mode when clear. The SIU can clear AM.
Bit [0]—RBP → (STS.0) Receive buffer protect. When set, prevents writing of data into
the receive buffer. Causes RNR response instead of RR in AUTO mode.
4.10.4 Send/Receive Count Register (NSNR)
Table 34 presents the Send/Receive Count Register, which contains both the transmit and receive
sequence numbers in addition to the tally error indications. The CPU can read and write the STS.
Accessing the STS by the CPU via two cycle instructions—JBC bit,rel and MOV bit,C—should
not be used. The SIU can read and write the NSNR. The NS and NR counters are not used in
non-AUTO mode. NSNR is bit addressable.
Table 34. Send/Receive Count Register
7
NS2
6
NS1
5
NS0
4
SES
3
NR2
2
NR1
1
NR0
0
SER
Bit [7]—NS2 → (NSNR.7) Send sequence counter, Bit [2].
Bit [6]—NS1 → (NSNR.6) Send sequence counter, Bit [1].
Bit [5]—NS0 → (NSNR.5) Send sequence counter, Bit [0].
Bit [4]—SES → (NSNR.4) Sequence error send. NR (P) ≠ NS (S) and
NR (P) ≠ NS (S) + 1.
Bit [3]—NR2 → (NSNR.3) Receive sequence counter, Bit [2].
Bit [2]—NR1 → (NSNR.2) Receive sequence counter, Bit [1].
Bit [1]—NR0 → (NSNR.1) Receive sequence counter, Bit [0].
Bit [0]—SER → (NSNR.0) Sequence error receive. NS (P) ≠ NR (S).
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4.10.5 Station Address Register (STAD)
Table 35 presents the Station Address Register, which contains the station address (node address)
of the chip. The CPU can read or write STAD but should access STAD only when RTS = 0 and
RBE = 0. Normally STAD is accessed only during initialization. STAD is byte addressable.
Table 35. Station Address Register
7
STAD.7
6
STAD.6
5
STAD.5
4
STAD.4
3
STAD.3
2
STAD.2
1
STAD.1
0
STAD.0
4.10.6 Transmit Buffer Start Address Register (TBS)
Table 36 presents the Transmit Buffer Start Address Register, which contains the address in
internal RAM where the frame to be transmitted (starting with the I-field) is stored. The CPU
should access TBS only when the SIU is not transmitting a frame, TBF = 0. TBS is byte
addressable.
Table 36. Transmit Buffer Start Address Register
7
TBS.7
6
TBS.6
5
TBS.5
4
TBS.4
3
TBS.3
2
TBS.2
1
TBS.1
0
TBS.0
4.10.7 Transmit Buffer Length Register (TBL)
Table 37 presents the Transmit Buffer Length Register, which contains the length, in number of
bytes, of the I-field to be transmitted. TBL = 0 is valid (no I-field). The CPU should access TBL
only when the SIU is not transmitting a frame, TBF = 0. The transmit buffer will not wrap around
after address 191 (BFH). A buffer end is automatically generated when address 191 is reached.
TBL is byte addressable.
Table 37. Transmit Buffer Length Register
7
TBL.7
6
TBL.6
5
TBL.5
4
TBL.4
3
TBL.3
2
TBL.2
1
TBL.1
0
TBL.0
4.10.8 Transmit Control Byte Register (TCB)
Table 38 presents the Transmit Control Byte Register, which contains the byte to be placed in the
control field of the transmitted frame during non-AUTO-mode transmission. The CPU should
access TCB only when the SIU is not transmitting a frame, TBF = 0. TCB is byte addressable.
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Table 38. Transmit Control Byte Register
7
TCB.7
6
TCB.6
5
TCB.5
4
TCB.4
3
TCB.3
2
TCB.2
1
TCB.1
0
TCB.0
4.10.9 Receive Buffer Start Address Register (RBS)
Table 39 presents the Receive Buffer Start Address Register, which contains the address in
internal RAM where the frame (starting with the I-field) being received is to be stored. The CPU
should write RBS only when the SIU is not receiving a frame, RBE = 0. RBS is byte addressable.
Table 39. Receive Buffer Start Address Register
7
RBS.7
6
RBS.6
5
RBS.5
4
RBS.4
3
RBS.3
2
RBS.2
1
RBS.1
0
RBS.0
4.10.10 Receive Buffer Length Register (RBL)
Table 40 presents the Receive Buffer Length Register, which contains the length, in number of
bytes, of the I-field storage area in internal RAM. RBL = 0 is valid (no I-field). The CPU should
write RBL only when the SIU is not receiving a frame, RBE = 0. The receive buffer will not wrap
around after address 191 (BFH). A buffer end is automatically generated when address 191 is
reached. RBL is byte addressable.
Table 40. Receive Buffer Length Register
7
RBL.7
6
RBL.6
5
RBL.5
4
RBL.4
3
RBL.3
2
RBL.2
1
RBL.1
0
RBL.0
4.10.11 Receive Field Length Register (RFL)
Table 41 presents the Receive Field Length Register, which contains the length, in number of
bytes, of the I-field of the frame received and stored in internal RAM. RFL = 0 is valid (no
I-field). The CPU should access RFL only when the SIU is not receiving a frame, RBE = 0. RFL
is loaded by the SIU. RFL is byte addressable.
Table 41. Receive Field Length Register
7
RFL.7
6
RFL.6
5
RFL.5
4
RFL.4
3
RFL.3
2
RFL.2
1
RFL.1
0
RFL.0
4.10.12 Receive Control Byte Register (RCB)
Table 42 presents the Receive Control Byte Register, which contains the control field of the frame
received and stored in internal RAM. RCB is only readable by the CPU and the CPU should
access RCB only when the SIU is not receiving a frame, RBE = 0. RCB is loaded by the SIU.
RCB is byte addressable.
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Table 42. Receive Control Byte Register
7
RCB.7
6
RCB.6
5
RCB.5
4
RCB.4
3
RCB.3
2
RCB.2
1
RCB.1
0
RCB.0
4.10.13 DMA Count Register (DMA CNT)
Table 43 presents the DMA Count Register (DMA CNT), which contains the number of bytes
remaining for the information field currently being used. This register is an ICE support register.
DMA CNT is byte addressable.
Table 43. DMA Count Register (DMA CNT)
7
DMA
CNT.7
6
DMA
CNT.6
5
DMA
CNT.5
4
DMA
CNT.4
3
DMA
CNT.3
2
DMA
CNT.2
1
DMA
CNT.1
0
DMA
CNT.0
4.10.14 DMA Count Register (FIFO)
Table 44 presents the DMA Count Register (FIFO), which is actually three registers that make a
three-byte FIFO. These are used as temporary storage between the eight-bit shift register and the
receive buffer when an information field is received. This register is an ICE support register.
FIFO is byte addressable.
Table 44. DMA Count Register (FIFO)
7
FIFO#a.7
a1,
6
FIFO#a.6
5
FIFO#a.5
4
FIFO#a.4
3
FIFO#a.3
2
FIFO#a.2
1
FIFO#a.1
0
FIFO#a.0
2, or 3 for FIFO1, FIFO2, or FIFO3, respectively.
4.10.15 SIU State Counter (SIUST)
Table 45 presents the SIU State Counter Register, which indicates what state the SIU state
machine is currently in. This in turn indicates what task the SIU is performing or which field is
expected next by the SIU. This register should not be written to. This register is an ICE support
register. SIUST is byte addressable.
Table 45. SIU State Counter
7
SIUST .7
6
SIUST .6
5
SIUST .5
®
4
SIUST .4
3
SIUST .3
2
SIUST .2
1
SIUST .1
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4.11
Data Sheet
March 30, 2010
Data Clocking Options
The SIU may be clocked in one of two ways, with an external clock or in a self-clocked mode. In
the external clocked mode, a serial clock must be provided on SCLK. This clock must be
synchronized to the serial data. Incoming data is sampled at the rising edge of SCLK. Outgoing
data is shifted out at the falling edge of SCLK.
In the self-clocked mode, the SIU uses a reference clock and the serial data to reproduce the serial
data clock. The reference clock can be an external source applied to SCLK, the IA8044/IA8344’s
internal clock or the Timer 1 overflow. The reference clock must be 16 or 32 the data rate. A
DPLL uses the reference clock and the serial data to adjust the sample time to the center of the
serial bit. It does this by adjusting from a serial data transition in increments of 1/16 of a bit time.
The maximum data rate in the externally clocked mode is 2.4 Mbps in a point-to-point
configuration and 1.0 Mbps in a loop configuration. With a 12-MHz CPU clock, the maximum
data rate in the self-clocked mode with an external clock is 375 Kbps. The maximum data rate in
the self-clocked mode with an internal clock will depend on the frequency of the
IA8044/IA8344’s input clock. An IA8044/IA8344 using a 12-MHz input clock can operate at a
maximum data rate of 375 Kbps.
The Serial mode register Bits [5], [6], and [7] select the clocking option for the SIU (see SMD
register description).
4.12
Operational Modes
The SIU operates in one of two modes, AUTO or FLEXIBLE. The mode selected determines
how much intervention is required by the CPU when receiving and transmitting frames. In both
modes, short frames, aborted frames, and frames with CRC errors will be ignored.
AUTO mode allows the SIU to recognize and respond to specific SDLC frames without the
CPU’s intervention. This provides for a faster turnaround time but restricts the operation of the
SIU. When in AUTO mode, the SIU can only act as a normal response secondary station and
responses will adhere to IBM’s SDLC definitions.
When receiving in the AUTO mode, the SIU receives the frame and examines the control byte. It
will then take the appropriate action for that frame. If the frame is an information frame, the SIU
will load the receive buffer, interrupt the CPU and make the required response to the primary
station. The SIU in AUTO mode can also respond to the following commands from the primary
station:
RR (Receive ready)
RNR (Receive Not Ready)
REJ (Reject)
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UP (Unnumbered Poll) also called NSP, (Non-Sequenced Poll), or ORP (Optional
Response Poll)
In AUTO mode when the transmit buffer is full, the SIU can transmit an information frame when
polled for information. After transmission the SIU waits for acknowledgement from the receiving
station. If the response is positive, the SIU interrupts the CPU. If the response is negative, the
SIU retransmits the frame. The SIU can send the following responses to the primary station:
RR (Receive Ready)
RNR (Receive Not Ready)
The FLEXIBLE mode requires the CPU to control the SIU for both transmitting and receiving.
This slows response time but allows full SDLC and limited HDLC compatibility as well as
variations. In FLEXIBLE mode, the SIU can act as a primary station. The SIU will interrupt the
CPU after completion of a transmission without waiting for a positive acknowledgement from the
receiving station (see Table 46).
Table 46. Basic SDLC Frame
FLAG
ADDRESS
CONTROL
INFORMATION
FCS
FLAG
IA8044/IA8344 frame parameters:
Flag—8 bits
Address—8 bits
Control—8 bits
Information—n bytes (where n
FCS—16 bits
Flag—8 bits
4.13
192)
Frame Format Options
The various frame formats available with the IA8044/IA8344 are the standard SDLC format, the
no-control field format, the no-control field and no-address field formats, and the no-FCS field
format.
The standard SDLC format consists of an opening flag, an 8-bit address field, an 8-bit control
field, an n-byte information field, a 16-bit frame check sequence field, and a closing flag. The
FCS is generated by the CCIT-CRC polynomial (X16 + X12 + X5 + 1). The FCS is calculated on
the address, control, and information fields. The address and control fields may not be extended.
The address is contained in STAD and the control filed is contained in either RCB or TCB. This
format is supported by both AUTO and FLEXIBLE modes.
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The no-control field format is only supported by the FLEXIBLE mode. In this format, TCB and
RCB are not used and the information field starts immediately after the address field. A control
field may still be used in the frame but the SIU will treat it as a byte of the information field.
The no-control field and no-address field formats are supported only by the FLEXIBLE mode. In
this format STAD, TCB, and RCB are not used and the information field starts immediately after
the opening flag. This option can only be used with the no-control field option. A control field
and address field may still be used in the frame but the SIU will treat each as a byte of the
information field.
The no FCS field format prevents an FCS from being generated during transmission or being
checked during reception. This option may be used in conjunction with the other frame format
options. This option will work with both FLEXIBLE and AUTO modes. In AUTO mode, it
could cause protocol violations. An FCS field may still be used in the frame but the SIU will treat
it as a byte of the information field.
All the possible Frame Format combinations are presented in Table 47, along with the bit settings
that select a given format.
Table 47. Frame Format Options
Frame Option
Standard
SDLC
FLEXIBLE
Mode
Standard
SDLC
AUTO Mode
No-Control
Field
FLEXIBLE
Mode
No-Control
Field
No-Address
Field
FLEXIBLE
Mode
No-FCS Field
FLEXIBLE
Mode
No-FCS Field
AUTO Mode
NFCS
0
NB
0
AM
0
Ad
Frame Format
Co
Inf
Fl
FCS
Fl
0
0
1
Fl
Ad
Co
Inf
FCS
Fl
0
1
1
Fl
Ad
Inf
FCS
0
1
0
Fl
Inf
FCS
1
0
0
Fl
Ad
Co
Inf
Fl
1
0
1
Fl
Ad
Co
Inf
Fl
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Frame Option
No-Control
Field
No-FCS Field
FLEXIBLE
Mode
No-Control
Field
No-Address
Field
No-FCS Field
FLEXIBLE
Mode
Data Sheet
March 30, 2010
NFCS
1
NB
1
AM
1
Fl
Ad
Inf
1
1
0
Fl
Inf
Fl
Frame Format
Fl
Ad = Address field
Co = Control field
FCS = Frame check sequence
Fl = Flag
Inf = Information field
4.14
HDLC Restrictions
The IA8044/IA8344 supports a subset of the HDLC protocol. The differences include the
restriction by the IA8044/IA8344 of the serial data to be in 8-bit increments. In contrast, HDLC
allows for any number of bits in the information field. HDLC provides an unlimited address field
and an extended frame number sequencing. HDLC does not support loop configuration.
4.15
SIU Details
The SIU is composed of two functional blocks with each having several sub blocks. The two
blocks are called the bit processor (BIP) and the byte processor (BYP) (see Figure 11).
4.15.1 BIP
The BIP consists of the DPLL, NRZI encoder/decoder, serial/parallel shifter, zero
insertion/deletion, shutoff logic, and FCS generation/checking. The NRZI logic compares the
current bit to the previous bit to determine if the bit should be inverted. The serial shifter converts
the outgoing byte data to bit data and incoming bit data to byte data. The zero insert/delete
circuitry inserts and deletes zeros and also detects flags (01111110), go-aheads (GA) (01111111),
and aborts (1111111). The pattern 1111110 is detected as an early go-ahead that can be turned
into a flag in loop configurations. The shutoff detector is a three-bit counter that is used to detect
a sequence of eight zeros, which is the shutoff command in loop-mode transmissions. It is cleared
whenever a ―1‖ is detected. The FCS logic performs the generation and checking of the FCS
value according to the polynomial described above. The FCS register is set to all 1s prior to each
calculation. If a CRC error is generated on a receive frame, the SIU will not interrupt the CPU
and the error will be cleared upon receiving an opening flag.
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Bit Processor
Int clk
T1 ovrflw
div by 2
SCLK
RXD
DPLL
Byte Processor
TXD
Bit timing
generator
zero insert/
delete
start detect
NRZI encode/
decode
serial/parallel
shifter
FCS
generator/
checker
Control State
Machine
Decision
Logic
Serial Information Bus
Internal Ram
SIU SFRs
Information Bus
Figure 11. Bit and Byte Processors
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4.15.2 BYP
The BYP contains registers and controllers used to perform the manipulations required for SDLC
communications. The BYP registers may be accessed by the CPU (see Table 7, SFR Bit
Addressable Locations). The BYP contains the SIU state machine that controls transmission and
reception of frames.
4.16
Diagnostics
A diagnostic mode is included with the IA8044/IA8344 to allow testing of the SIU. Diagnostics
use port pins P3.0 and P3.1. Writing a ―0‖ to P3.1 enables the diagnostic mode. When P3.1 is
cleared, writing data to P3.0 has the effect of writing a serial data stream to the SIU. P3.0 is the
serial data and any write to Port 3 will clock SCLK. The transmit data may be monitored on P3.1
with any write to Port 3, again clocking SCLK. In the test mode P3.0 and P3.1 pins are placed in
the high impedance state (see Figure 12).
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P3.5 Out Latch
SCLK
Pin
Q
D
T1 OVRF
SYS CLK
SIU
Serial
Data
CLK
P3.0 Out Latch
RXD
Pin
Q
D
SIU RX Data In
Loop
Pin 3.1 Out Latch
TXD
Pin
Q
D
Write Port 3
SIU TX Data Out
Figure 12. Diagnostic Signal Routing
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5.
Data Sheet
March 30, 2010
AC Specifications
AC characteristics, external data memory characteristics, serial interface characteristics, and
external clock drive characteristics are provided in Tables 48 through 51, respectively.
TA
= −40 C to +85 C, VDD = 5V
10%, VSS = 0V, Load Capacitance = 87pF
Table 48. External Program Memory Characteristics
Symbol
TLHLL
TAVLL
TLLAX
TLLIV
TLLPL
TPLPH
TPLIV
TPXIX
TPXIZ
TPXAV
TAVIV
TAZPL
TCY
12 MHz Osc
Min
Max
171
–
75
–
74
–
–
298
83
–
254
–
–
215
0
–
–
76
91
–
–
373
-9
–
996
–
Parameter
ALE Pulse Width
Address Valid to ALE Low
Address Hold After ALE Low
ALE Low to Valid Instr. In.
ALE Low to PSENn Low
PSENn Pulse Width
PSENn Low to Valid Instr. In
Input Instr. Hold After PSENn
Input Instr. Float After PSENn
PSENn to Address Valid
Address to Valid Instr. In
Address Float to PSENn
Machine cycle
Variable Clock
1/TCLCL = 3.5 MHz to 12 MHz
Min
Max
2TCLCL+4
–
TCLCL-8
–
TCLCL-9
–
–
4TCLCL-35
TCLCL
–
3TCLCL+4
–
–
3TCLCL-35
0
–
–
TCLCL-7
TCLCL+8
–
–
5TCLCL-43
-9
–
12TCLCL
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 49. External Data Memory Characteristics
Symbol
TRLRH
TWLWH
TLLAX
TRLDV
TRHDX
TRHDZ
TLLDV
TAVDV
TLLWL
TAVWL
TQVWX
TQVWH
TWHQX
Parameter
RDn Pulse Width
WRn Pulse Width
Address Hold After ALE
RDn Low to Valid Data In
Data Hold After RDn
Data Float After RDn
ALE Low to Valid Data In
Address to Valid Data In
ALE Low to RDn or WRn Low
Address to RDn or WRn Low
Data Valid to WRn Transition
Data Setup Before WRn High
Data Held After WRn
®
12 MHz Osc
Min
Max
487
–
487
–
74
–
–
383
0
–
–
165
–
633
–
708
250
250
325
–
76
–
563
–
86
–
Variable Clock
1/TCLCL = 3.5 MHz to 12 MHz
Min
Max
6TCLCL-13
–
6TCLCL-13
–
TCLCL-9
–
–
5TCLCL-35
0
–
–
2TCLCL-2
–
8TCLCL-34
–
9TCLCL-42
3TCLCL
3TCLCL
4TCLCL-8
–
TCLCL-7
–
7TCLCL-20
–
TCLCL+3
–
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ns
ns
ns
ns
ns
ns
ns
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TRLAZ
TWHLH
Data Sheet
March 30, 2010
–
83
RDn Low to Address Float
RDn or WRn High to ALE High
9
83
–
TCLCL
9
TCLCL
ns
ns
Table 50. Serial Interface Characteristics
Symbol
TDCY
TDCL
TDCH
tTD
tDSS
tDHS
Parameter
Data Clock
Data Clock Low
Data Clock High
Transmit Data Delay
Data Setup Time
Data Hold Time
Min
420
184
184
–
26
58
Max
–
–
–
125
–
–
Unit
ns
ns
ns
ns
ns
ns
Table 51. External Clock Drive Characteristics
Symbol
TCLCL
5.1
Parameter
Oscillator Period
Min
52
Max
–
Unit
ns
Memory Access Waveforms
The IA8044/IA8344 program memory read cycle, data memory read cycle, and data memory
write cycle are presented in Figures 13 through 15, respectively.
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TCY
TLHLL
TLLIV
TLLPL
ALE
TPLPH
PSENn
TPXAV
TAVLL
PORT_0 INSTR. IN
TPLIV
A7-A0
TPXIZ
INSTR. IN
TAZPL
A7-A0
INSTR. IN
TPXIX
TLLAX
TAVIV
PORT_2 ADDRESS OR SFR-P2
ADDRESS A15-A8
ADDRESS A15-A8
Figure 13. Program Memory Read Cycle
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TLLDV
TWHLH
ALE
PSENn
TLLWL
TRLRH
RDn
TAVDV
TAVWL
TLLAX
PORT_0
A7-A0
TRHDX
TRLDV
TRHDZ
DATA IN
TRLAZ
PORT_2
ADDRESS A15-A8 OR SFR-P2
Figure 14. Data Memory Read Cycle
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TWHLH
ALE
PSENn
TLLWL
TWLWH
WRn
TQVWH
TLLAX
TAVWL
TQVWX
PORT_0
A7-A0
PORT_2
TWHQX
DATA OUT
ADDRESS A15-A8 or SFR-P2
Figure 15. Data Memory Write Cycle
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5.2
Data Sheet
March 30, 2010
Serial I/O Waveforms
The IA8044/IA8344 synchronous data transmission and synchronous data reception are
presented in Figures 16 and 17, respectively.
TDCY
TDCL
TDCH
SCLK
TTD
DATA
Figure 16. Synchronous Data Transmission
TDCY
TDCL
TDCH
SCLK
TDSS
TDHS
DATA
Figure 17. Synchronous Data Reception
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6.
Data Sheet
March 30, 2010
Reset
A reset is accomplished by holding the RST pin high for at least two machine cycles (24
oscillator periods) while the oscillator is running. The CPU responds by generating an internal
reset, which is executed during the second cycle in which RST is high.
The internal reset sequence affects all SFRs as shown in Table 52. The internal reset sequence
does not affect the contents of internal RAM.
Table 52. Reset Values Register
Register
PC
ACC
B
PSW
SP
DPTR
P0–P3
IP
IE
TMOD
TCON
TH0
TL0
TH1
TL1
SMD
STS
NSNR
STAD
TBS
TBL
TCB
RBS
RBL
RFL
RCB
DMA CNT
FIFO1
FIFO2
FIFO3
SIUST
Reset value
0000H
00000000B
00000000B
00000000B
00000111B
0000H
11111111B
XXX00000B
0XX00000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
00000000B
00000000B
00000000B
00000001B
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7.
Data Sheet
March 30, 2010
Instruction Set
The IA8044 and IA8344 architecture and instruction set are identical to the Intel 8051’s.
Tables 53 through 57 present the instruction set of the IA8044/IA8344 microcontroller core.
Table 53. Arithmetic Operations
Mnemonic
ADD A,Rn
ADD A, direct
ADD A,@Ri
ADD A,#data
ADDC A,Rn
ADDC A,direct
ADDC A,@Ri
ADDC A,#data
SUBB A,Rn
SUBB A,direct
SUBB A,@Ri
SUBB A,#data
INC A
INC Rn
INC direct
INC @ Ri
DEC A
DEC Rn
DEC direct
DEC @Ri
INC DPTR
MUL A,B
DIV A,B
DA A
Description
Add register to accumulator
Add direct byte to accumulator
Add indirect RAM to accumulator
Add immediate data to accumulator
Add register to accumulator with carry flag
Add direct byte to A with carry flag
Add indirect RAM to A with carry flag
Add immediate data to A with carry flag
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A with borrow
Subtract immediate data from A with borrow
Increment accumulator
Increment register
Increment direct byte
Increment indirect RAM
Decrement accumulator
Decrement register
Decrement direct byte
Decrement indirect RAM
Increment data pointer
Multiply A and B
Divide A by B
Decimal adjust accumulator
®
Byte
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
Cycle
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
4
4
1
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Table 54. Logic Operations
Mnemonic
ANL A,Rn
ANL A,direct
ANL A,@Ri
ANL A,#data
ANL direct,A
ANL direct,#data
ORL A,Rn
ORL A,direct
ORL A,@Ri
ORL A,#data
ORL direct,A
ORL direct,#data
XRL A,Rn
XRL A,direct
XRL A,@Ri
XRL A,#data
XRL direct,A
XRL direct,#data
CLR A
CPL A
RL A
RLC A
RR A
RRC A
SWAP A
Description
AND register to accumulator
AND direct byte to accumulator
AND indirect RAM to accumulator
AND immediate data to accumulator
AND accumulator to direct byte
AND immediate data to direct byte
OR register to accumulator
OR direct byte to accumulator
OR indirect RAM to accumulator
OR immediate data to accumulator
OR accumulator to direct byte
OR immediate data to direct byte
Exclusive OR register to accumulator
Exclusive OR direct byte to accumulator
Exclusive OR indirect RAM to accumulator
Exclusive OR immediate data to accumulator
Exclusive OR accumulator to direct byte
Exclusive OR immediate data to direct byte
Clear accumulator
Complement accumulator
Rotate accumulator left
Rotate accumulator left through carry
Rotate accumulator right
Rotate accumulator right through carry
Swap nibbles within the accumulator
®
Byte
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
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Cycle
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
1
1
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Table 55. Data Transfer
Mnemonic
MOV A,Rn
MOV A,direct
MOV A,@Ri
MOV A,#data
MOV Rn,A
MOV Rn,direct
MOV Rn,#data
MOV direct,A
MOV direct,Rn
MOV direct,direct
MOV direct,@Ri
MOV direct,#data
MOV @Ri,A
MOV @Ri,direct
MOV @ Ri, #data
MOV DPTR, #data16
MOVC A,@A + DPTR
MOVC A,@A + PC
MOVX A,@Ri
MOVX A,@DPTR
MOVX @Ri,A
MOVX @DPTR,A
PUSH direct
POP direct
XCH A,Rn
XCH A,direct
XCH A,@Ri
XCHD X,@ Ri
®
Description
Move register to accumulator
Move direct byte to accumulator
Move indirect RAM to accumulator
Move immediate data to accumulator
Move accumulator to register
Move direct byte to register
Move immediate data to register
Move accumulator to direct byte
Move register to direct byte
Move direct byte to direct byte
Move indirect RAM to direct byte
Move immediate data to direct byte
Move accumulator to indirect RAM
Move direct byte to indirect RAM
Move immediate data to indirect RAM
Load data pointer with a 16-bit constant
Move code byte relative to DPTR to accumulator
Move code byte relative to PC to accumulator
Move external RAM (8-bit address) to A
Move external RAM (16-bit address) to A
Move A to external RAM (8-bit address)
Move A to external RAM (16-bit address)
Push direct byte onto stack
Pop direct byte from stack
Exchange register with accumulator
Exchange direct byte with accumulator
Exchange indirect RAM with accumulator
Exchange low-order nibble indirect RAM with A
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2
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Cycle
1
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1
2
2
2
2
1
2
1
2
2
2
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1
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IA8044/IA8344
SDLC Communications Controller
Data Sheet
March 30, 2010
Table 56. Boolean Manipulation
Mnemonic
CLR C
CLR bit
SETB C
SETB bit
CPL C
CPL bit
ANL C,bit
ANL C,bit
ORL C,bit
ORL C,bit
MOV C,bit
MOV bit,C
Description
Clear carry flag
Clear direct bit
Set carry flag
Set direct bit
Complement carry flag
Complement direct bit
AND direct bit to carry flag
AND complement of direct bit to carry
OR direct bit to carry flag
OR complement of direct bit to carry
Move direct bit to carry flag
Move carry flag to direct bit
Byte
1
2
1
2
1
2
2
2
2
2
2
2
Cycle
1
1
1
1
1
1
2
2
2
2
1
2
Table 57. Program Branches
Mnemonic
ACALL addr11
LCALL addr16
RET Return
RETI Return
AJMP addr11
LJMP addr16
SJMP rel
JMP @A + DPTR
JZ rel
JNZ rel
JC rel
JNC rel
JB bit,rel
JNB bit,rel
JBC bit,rel
CJNE A,direct,rel
CJNE A,#data,rel
CJNE Rn,#data rel
CJNE @Ri,#data,rel
DJNZ Rn,rel
DJNZ direct,rel
NOP
Description
Absolute subroutine call
Long subroutine call
From subroutine
From interrupt
Absolute jump
Long jump
Short jump (relative address)
Jump indirect relative to the DPTR
Jump if accumulator is zero
Jump if accumulator is not zero
Jump if carry flag is set
Jump if carry flag is not set
Jump if direct bit is set
Jump if direct bit is not set
Jump if direct bit is set and clear bit
Compare direct byte to A and jump if not equal
Compare immediate to A and jump if not equal
Compare immediate to register and jump if not equal
Compare immediate to indirect and jump if not equal
Decrement register and jump if not zero
Decrement direct byte and jump if not zero
No operation
®
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1
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IA8044/IA8344
SDLC Communications Controller
8.
Data Sheet
March 30, 2010
Innovasic/Intel Part Number Cross-Reference Tables
Tables 58 and 59 cross-reference each Innovasic part number with the corresponding Intel part
number for the PDIP and PLCC, respectively.
Table 58. Innovasic/Intel Part Number Cross-Reference for the PDIP
Innovasic Part Number
IA8X44PDW40IR3
lead-free (RoHS)
IA8X44PDW40I3
lead frame (SnPb)
Intel Part Number
P8344
P8344AH
TP8344AH
P8044
P8044AH
P8044AH-R0117
TP8044AH
TP8044AH-R0117
Package Type
40-Pin Plastic Dual In-Line
Package (PDIP) (600 mils)
Temperature Grades
Industrial
Table 59. Innovasic/Intel Part Number Cross-Reference for the PLCC
Innovasic Part Number
IA8X44-PLC44I-R-P03
lead-free (RoHS)
IA8X44PLC44I3
lead frame (SnPb)
®
Intel Part Number
N8344
N8344AH
TN8344AH
N8044
N8044AH
N8044AH-R0117
TN8044AH
TN8044AH-R0117
8044AHN
8044AN
Package Type
44-Pin Plastic Leaded Chip
Carrier (PLCC)
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Temperature Grades
Industrial
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IA8044/IA8344
SDLC Communications Controller
9.
Errata
9.1
Summary
Data Sheet
March 30, 2010
Table 60 presents a summary of errata in the IA8044/IA8344 controller.
Table 60. Summary of Errata
Errata
No.
9.2
Ver. 3
Problem
1
Cannot read internal ROM with EPROM verification method.
Exists
2
The device has a different pullup value than the Intel version.
Exists
3
The device responds to an idle flag one bit time too early.
Exists
4
Under certain conditions the SIU will overwrite the RCB register when starting a
transmission.
Exists
Detail
Errata No. 1
Problem: Cannot read internal ROM with EPROM verification method.
Description: The IA8044/IA8344 does not contain internal EPROM and therefore does not
support the EPROM read feature.
Workaround: Must use alternate method to read internal ROM.
Errata No. 2
Problem: The device has a different pullup value than the Intel version.
Description: The Intel version can source more current than the IA8044/IA8344.
Workaround: Adjust external circuits if necessary.
®
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SDLC Communications Controller
Data Sheet
March 30, 2010
Errata No. 3
Problem: The device responds to an idle flag one bit time too early.
Description: This causes problems in a loop-mode network. It only occurs in loop mode when
using an external SIU clock source and idle flags.
Workaround: None.
Errata No. 4
Problem: Under certain conditions the SIU will overwrite the RCB register when starting a
transmission.
Description: The conditions are:
The SIU is externally clocked.
The SIU is in flexible mode.
The CPU has not already read the RCB from a previous reception before the
transmission takes place.
Workaround: Read the RCB before initiating a transmit.
®
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SDLC Communications Controller
10.
Data Sheet
March 30, 2010
Revision History
Table 61 presents the sequence of revisions to document IA211010112.
Table 61. Revision History
Date
January 20, 2006
August 28, 2007
Revision
01
02
January 2, 2009
03
March 30, 2010
04
®
Description
First edition released.
Updated RoHS info, header, footer, cover
page. Errata added.
Reformatted and reorganized to meet
publication standards. Technical data
updated. ―Summary of Errata‖ table added.
Updated Innovasic part numbers on Cross
Reference Table to reflect current part
marking scheme. (Part is still Version 3
release.)
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IA8044/IA8344
SDLC Communications Controller
11.
Data Sheet
March 30, 2010
For Additional Information
The Innovasic Semiconductor IA8044 and IA8344 are ―plug-and-play‖ drop-in replacements and
are form, fit, and function compatible parts to the Intel 8044 and 8344. The IA8044 and
IA8344 replace the obsolete Intel 8044 and 8344, allowing users to retain existing board designs,
software compilers/assemblers, and emulation tools—thus avoiding expensive redesign efforts.
The Innovasic Support Team is continually planning and creating tools for your use. Visit
http://www.Innovasic.com for up-to-date documentation and software. Our goal is to provide
timely, complete, accurate, useful, and easy-to-understand information. Please feel free to
contact our experts at Innovasic at any time with suggestions, comments, or questions.
Innovasic Support Team
3737 Princeton NE
Suite 130
Albuquerque, NM 87107
(505) 883-5263
Fax: (505) 883-5477
Toll Free: (888) 824-4184
E-mail: [email protected]
Website: http://www.Innovasic.com
®
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