TI1 HD3SS3212IRKSR Two-channel differential 2:1/1:2 usb3.1 mux/demux Datasheet

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HD3SS3212, HD3SS3212I
SLASE74E – MAY 2015 – REVISED MAY 2016
HD3SS3212x Two-Channel Differential 2:1/1:2 USB3.1 Mux/Demux
1 Features
3 Description
•
The HD3SS3212 is a high-speed bidirectional
passive switch in mux or demux configurations suited
for USB Type-C™ application supporting USB 3.1
Gen 1 and Gen 2 data rates. Based on control pin
SEL, the device provides switching on differential
channels between Port B or Port C to Port A.
1
•
•
•
•
•
•
•
•
•
Provides MUX/DEMUX Solution for USB TypeC™ Ecosystem for USB 3.1 Gen 1 and Gen 2
Data Rates
Compatible With MIPI DSI/CSI, FPDLinkIII, LVDS,
and PCIE Gen II, III
Operates up to 10 Gbps
Wide –3-dB Differential BW of over 8 GHz
Excellent Dynamic Characteristics (at 5 GHz)
– Crosstalk = –32 dB
– Off Isolation = –19 dB
– Insertion Loss = –1.6 dB
– Return Loss = –12 dB
Bidirectional "Mux/De-Mux" Differential Switch
Supports Common Mode Voltage 0 to 2 V
Single Supply Voltage VCC of 3.3 V
Commercial Temperature Range of 0°C to 70°C
(HD3SS3212RKS)
Industrial Temperature Range of –40°C to 85°C
(HD3SS3212IRKS)
Excellent dynamic characteristics of the device allow
high-speed switching with minimum attenuation to the
signal eye diagram with very little added jitter. It
consumes <2 mW of power when operational and
has a shutdown mode exercisable by OEn pin
resulting <20 µW.
Device Information(1)
PART NUMBER
HD3SS3212
2 Applications
•
•
•
•
•
•
The HD3SS3212 is a generic analog differential
passive switch that can work for any high-speed
interface applications requiring a common mode
voltage range of 0 to 2 V and differential signaling
with differential amplitude up to 1800 mVpp. It
employs adaptive tracking that ensures the channel
remains unchanged for the entire common mode
voltage range.
USB Type-C™ Ecosystem
Desktop and Notebook PCs
Server/Storage Area Networks
PCI Express Backplanes
Shared I/O Ports
FPDLinkII and FPDLinkIII Switching
PACKAGE
BODY SIZE (NOM)
2.50 mm × 4.50 mm ×
0.5-mm pitch
VQFN (20)
HD3SS3212I
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SPACE
Simplified Schematic
A0+
A0±
C1+
C1±
Copyright © 2016, Texas Instruments Incorporated
19
A0p
3
18
B0n
A0n
4
17
B1p
GND
5
16
B1n
VCC
6
15
C0p
A1p
7
14
C0n
A1n
8
13
C1p
SEL
9
12
C1n
11
A1+
A1±
B0p
OEn
GND
B1+
B1±
20
10
SEL
1
2
RSVD2
C0+
C0±
GND
B0+
B0±
RSVD1
Pinout
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
HD3SS3212, HD3SS3212I
SLASE74E – MAY 2015 – REVISED MAY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
High-Speed Performance Parameters ......................
Switching Characteristics ..........................................
Parameter Measurement Information .................. 6
Detailed Description .............................................. 8
9.1 Overview ................................................................... 8
9.2 Functional Block Diagram ......................................... 8
9.3 Feature Description................................................... 8
9.4 Device Functional Modes.......................................... 9
10 Application and Implementation........................ 10
10.1 Application Information.......................................... 10
10.2 Typical Applications .............................................. 13
10.3 Systems Examples................................................ 14
11 Power Supply Recommendations ..................... 17
12 Layout................................................................... 17
12.1 Layout Guidelines ................................................. 17
12.2 Layout Example .................................................... 17
13 Device and Documentation Support ................. 18
13.1
13.2
13.3
13.4
13.5
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
14 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2016) to Revision E
Page
•
Changed Features From: Single Supply Voltage VCC of 3.3 V ±10% To: Single Supply Voltage VCC of 3.3 V .................... 1
•
Changed text "HD3SS3212 requires 3.3-V ±10%" To: "HD3SS3212 requires 3.3-V" in the Design Requirements
section .................................................................................................................................................................................. 13
•
Changed Figure 11, moved 0.1 µF capacitors From: pins 7 and 8 To: pins 3 and 4........................................................... 14
Changes from Revision C (January 2016) to Revision D
•
Page
Changed the VCC MIN value From: 3 V To: 2.7 V in Recommended Operating Conditions ................................................. 4
Changes from Revision B (January 2016) to Revision C
Page
•
Changed the PINOUT image - pin 1 From: NC To: RSVD1 and pin 10 From: NC To: RSVD2 ........................................... 1
•
Changed pin 1 From: NC To: RSVD1 , changed pin 10 From: NC To: RSVD2, and updated the Description in the
Pin Functions table ................................................................................................................................................................. 4
Changes from Revision A (August 2015) to Revision B
•
Page
Changed the Vih MIN value From: 2 V To: 1.7 V in Recommended Operating Conditions .................................................. 4
Changes from Original (May 2015) to Revision A
Page
•
. Removed "or GND" from NC pin description ...................................................................................................................... 4
•
Updated Figure 16 ............................................................................................................................................................... 17
2
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SLASE74E – MAY 2015 – REVISED MAY 2016
5 Device Comparison Table
PACKAGE (1) (2)
OPERATING TEMPERATURE (°C)
(1)
(2)
ORDERABLE PART NUMBER
0 to 70
RKS
20 pins
HD3SS3212RKSR
–40 to 85
RKS
20 pins
HD3SS3212IRKSR
For the most current package and ordering information, see Mechanical, Packaging, and Orderable Information.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
6 Pin Configuration and Functions
RSVD1
GND
RKS Package
20-Pin VQFN
Top View
1
20
B0p
18
B0n
A0n
4
17
B1p
GND
5
16
B1n
VCC
6
15
C0p
A1p
7
14
C0n
A1n
8
13
C1p
SEL
9
12
C1n
11
3
GND
A0p
10
19
RSVD2
OEn
2
Pin Functions
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
VCC
6
P
3.3-V power
OEn
2
I
Active-low chip enable
L: Normal operation
H: Shutdown
A0p
3
I/O
Port A, channel 0, high-speed positive signal
A0n
4
I/O
Port A, channel 0, high-speed negative signal
GND
5, 11, 20
G
Ground
A1p
7
I/O
Port A, channel 1, high-speed positive signal
A1n
8
I/O
Port A, channel 1, high-speed negative signal
SEL
9
I
C1n
12
I/O
Port C, channel 1, high-speed negative signal (connector side)
C1p
13
I/O
Port C, channel 1, high-speed positive signal (connector side)
C0n
14
I/O
Port C, channel 0, high-speed negative signal (connector side)
C0p
15
I/O
Port C, channel 0, high-speed positive signal (connector side)
B1n
16
I/O
Port B, channel 1, high-speed negative signal (connector side)
B1p
17
I/O
Port B, channel 1, high-speed positive signal (connector side)
B0n
18
I/O
Port B, channel 0, high-speed negative signal (connector side)
(1)
Port select pin. Internally tied to GND via 100-kΩ resistor.
L: Port A to Port B
H: Port A to Port C
The high-speed data ports incorporate 20-kΩ pulldown resistors that are switched in when a port is not selected and switched out when
the port is selected.
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Pin Functions (continued)
PIN
NAME
NO.
TYPE (1)
B0p
19
I/O
RSVD1
1
O
RSVD2
10
O
DESCRIPTION
Port B, channel 0, high-speed positive signal (connector side)
Can be left not connected or can be fed to VCC
7 Specifications
7.1 Absolute Maximum Ratings
see
(1)
VCC
Supply voltage
Voltage
Tstg
(1)
MIN
MAX
UNIT
–0.5
4
V
Differential I/O
–0.5
2.5
Control pins
–0.5
VCC+ 0.5
–65
150
Storage temperature
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage
2.7
3.6
V
Vih
Input high voltage (SEL, OEn pins)
1.7
VCC
V
Vil
Input low voltage (SEL, OEn pins)
–0.1
0.8
V
Vdiff
High-speed signal pins differential voltage
0
1.8
Vpp
Vcm
High speed signal pins common mode voltage
0
2
HD3SS3212RKS
0
70
HD3SS3212IRKS
–40
85
TA
Operating free-air/ambient temperature
V
°C
7.4 Thermal Information
HD3SS3212
THERMAL METRIC
(1)
RKS (VQFN)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
46.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
41.8
°C/W
RθJB
Junction-to-board thermal resistance
4.4
°C/W
ψJT
Junction-to-top characterization parameter
17.6
°C/W
ψJB
Junction-to-board characterization parameter
1.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
17.6
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.6
0.8
UNIT
mA
5
20
µA
ICC
Device active current
VCC = 3.3 V, OEn = 0
ISTDN
Device shutdown current
VCC = 3.3 V, OEn = VCC
CON
Output ON capacitance
0.6
pF
COFF
Output OFF capacitance
0.8
pF
RON
Output ON resistance
VCC = 3.3 V; VCM = 0 to 2 V; IO = –8
mA
ΔRON
On-resistance match between pairs of the
same channel
RFLAT_ON
On-resistance flatness RON(MAX) –
RON(MAIN)
IIH,CTRL
Input high current, control pins (SEL, OEn)
IIL,CTRL
Input low current, control pins (SEL, OEn)
IIH,HS
Input high current, high-speed pins
[Ax/Bx/Cx][p/n]
VIN = 2 V for selected port, A and B
with SEL = 0, and A and C with SEL
= VCC
IIH,HS
Input high current, high-speed pins
[Ax/Bx/Cx][p/n]
VIN = 2 V for non-selected port, C
with SEL = 0, and B with SEL =
VCC (1)
IIL,HS
Input low current, high-speed pins
[Ax/Bx/Cx][p/n]
(1)
8
Ω
VCC = 3.3 V; –0.35 V ≤ VIN ≤ 2.35 V;
IO = –8 mA
0.5
Ω
VCC = 3.3 V; –0.35 V ≤ VIN ≤ 2.35 V
1
Ω
1
µA
1
µA
1
µA
140
µA
1
µA
5
100
There is a 20-kΩ pull-down in non-selected port.
7.6 High-Speed Performance Parameters
PARAMETER
TEST CONDITION
MIN
ƒ = 0.3 MHz
ƒ = 0.625 MHz
IL
BW
RL
OIRR
XTALK
Differential insertion loss
Differential OFF isolation
Differential crosstalk
ƒ = 4 GHz
–1.4
ƒ = 5 GHz
–1.6
8
ƒ = 0.3 MHz
–25
ƒ = 2.5 GHz
–13
ƒ = 4 GHz
–13
ƒ = 5 GHz
– 12
ƒ = 0.3 MHz
–75
ƒ = 2.5 GHz
–23
ƒ = 4 GHz
–19
ƒ = 5 GHz
–19
ƒ = 0.3 MHz
–90
ƒ = 2.5 GHz
–35
ƒ = 4 GHz
–32.5
ƒ = 5 GHz
–32
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UNIT
-0.55
–0.8
Copyright © 2015–2016, Texas Instruments Incorporated
MAX
–0.5
ƒ = 2.5 GHz
–3-dB bandwidth
Differential return loss
TYP
dB
GHz
dB
dB
dB
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7.7 Switching Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
tPD
Switch propagation delay (see Figure 3)
80
ps
tSW_ON
Switching time SEL-to-Switch ON (see Figure 2)
0.5
µs
tSW_OFF
Switching time SEL-to-Switch OFF (see Figure 2)
0.5
µs
tSK_INTRA
Intra-pair output skew (see Figure 3)
6
ps
tSK_INTER
Inter-pair output skew (see Figure 3)
20
ps
8 Parameter Measurement Information
VCC
RSC = 50 Ÿ
Bxp/Cxp
Axp
RL = 50 Ÿ
RSC = 50 Ÿ
Axn
RL = 50 Ÿ
Bxn/Cxn
SEL
Figure 1. Test Setup
50%
50%
SEL
90%
10%
VOUT
tSW_ON
tSW_OFF
Figure 2. Switch On and Off Timing Diagram
6
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Parameter Measurement Information (continued)
2.6-V Max
50%
VIN
50%
0V
2.6-V Max
50%
VOUT
0V
50%
tPD
VOUTp
50%
VOUTn
TSK_INTRA
B0/C0
VOUT
B1/C1
VOUT
50%
50%
50%
50%
tSK_INTER
Figure 3. Timing Diagrams and Test Setup
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9 Detailed Description
9.1 Overview
The HD3SS3212 is a generic analog differential passive switch that can work for any high-speed interface
applications requiring a common mode voltage range of 0 to 2 V and differential signaling with differential
amplitude up to 1800 mVpp. It employs adaptive tracking that ensures the channel remains unchanged for the
entire common mode voltage range.
Excellent dynamic characteristics of the device allow high-speed switching with minimum attenuation to the
signal eye diagram with very little added jitter. It consumes <2 mW of power when operational and has a
shutdown mode exercisable by OEn pin resulting <20 µW.
9.2 Functional Block Diagram
B0+
B0±
A0+
A0±
C0+
C0±
SEL
B1+
B1±
A1+
A1±
C1+
C1±
Copyright © 2016, Texas Instruments Incorporated
9.3 Feature Description
9.3.1 Output Enable and Power Savings
The HD3SS3212 has two power modes, active/normal operating mode and standby/shutdown mode. During
standby mode, the device consumes very-little current to save the maximum power. To enter standby mode, the
OEn control pin is pulled high through a resistor and must remain high. For active/normal operation, the OEn
control pin should be pulled low to GND or dynamically controlled to switch between H or L.
HD3SS3212 consumes <2 mW of power when operational and has a shutdown mode exercisable by the EN pin
resulting <20 µW.
8
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9.4 Device Functional Modes
Table 1. Port Select Control Logic (1)
PORT A CHANNEL
(1)
PORT B OR PORT C CHANNEL CONNECTED TO PORT A CHANNEL
SEL = L
SEL = H
A0p
B0p
C0p
A0n
B0n
C0n
A1p
B1p
C1p
A1n
B1n
C1n
The HD3SS3212 can tolerate polarity inversions for all differential signals on Ports A, B, and C. Take
care to ensure the same polarity is maintained on Port A versus Ports B/C.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The HD3SS3212 is a generic 2-channel high-speed mux/demux type of switch that can be used for routing highspeed signals between two different locations on a circuit board. The HD3SS3212 supports several high-speed
data protocols with a differential amplitude of <1800 mVpp and a common mode voltage of <2.0 V, as with USB
3.0 and DisplayPort 1.2. The device’s one select input (SEL) pin can easily be controlled by an available GPIO
pin within a system or from a microcontroller.
The HD3SS3212 with its adaptive common mode tracking technology can support applications where the
common mode is different between the RX and TX pair. The two USB3.1 Type C connector applications show
both a host and device side. The cable between the two connectors swivels the pairs to properly route the
signals to the correct pin. The other applications are more generic because different connectors can be used.
Many interfaces require AC coupling between the transmitter and receiver. The 0402 capacitors are the preferred
option to provide AC coupling; 0603 size capacitors also work. Avoid the 0805 size capacitors and C-packs.
When placing AC coupling capacitors, symmetric placement is best. A capacitor value of 0.1 µF is best, and the
value should match for the ±signal pair. The designer should place them along the TX pairs on the system board,
which are usually routed on the top layer of the board.
The AC coupling capacitors have several placement options. Because the switch requires a bias voltage, the
designer must place the capacitors on one side of the switch. If they are placed on both sides of the switch, a
biasing voltage should be provided. Figure 4 shows a few placement options. The coupling capacitors are placed
between the switch and endpoint. In this situation, the switch is biased by the system/host controller.
0.1 µF
Connector
Port B
Port C
Device/
Endpoint
TX
0.1 µF
Port B
Port C
0.1 µF
RX
Connector
RX
HD3SS3212
TX
System/Host
controller
RX
Device/
Endpoint
0.1 µF
TX
Figure 4. AC Coupling Capacitors between Switch TX and Endpoint TX
In Figure 5, the coupling capacitors are placed on the host transmit pair and endpoint transmit pair. In this
situation, the switch on top is biased by the endpoint and the lower switch is biased by the host controller.
10
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Application Information (continued)
RX
Port C
Connector
System/Host
controller
HD3SS3212
TX
Port B
RX
Device/
Endpoint
TX
0.1 µF
Port B
Port C
RX
Connector
0.1 µF
Device/
Endpoint
TX
0.1 µF
Figure 5. AC Coupling Capacitors on Host TX and Endpoint TX
In the case where the common mode voltage in the system is higher than 2 V, the coupling capacitors are placed
on both sides of the switch (shown in Figure 6). A biasing voltage of <2 V is required in this case.
V BIAS
V BIAS
RX
Port C
Device/
Endpoint
TX
Port B
Port C
Connector
System/Host
controller
HD3SS3212
TX
Connector
Port B
RX
RX
Device/
Endpoint
TX
VBIAS can be GND
Capacitor and resistor values depend upon application
Figure 6. AC Coupling Capacitors on Both Sides of Switch
The HD3SS3212 can be used with the USB Type C connector to support the connector’s flip ability. Figure 7
provides the generic location for the AC coupling capacitors for this application.
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Application Information (continued)
Down Facing Port
RX±
RX1±
RX+
TX1+
RX±
0.1 µF
RX1±
TX2+
TX2±
RX2+
0.1 µF
TX1±
0.1 µF
RX2+
RX2±
HD3SS3212
RX
HD3SS3212
RX+
TX1±
RX1+
TX±
System/Host
Controller
RX1+
Type C Connector
TX
TX1+
Type C Connector
TX+
Up Facing Port
RX
Hub
TX+
TX±
TX
TX2+
RX2±
TX2±
0.1 µF
Figure 7. AC Coupling Capacitors for USB Type C
12
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10.2 Typical Applications
10.2.1 Down Facing Port for USB3.1 Type C
HD3SS3212
B0+
SSTXp
SSTXn
0.1 µF
3
0.1 µF
4
7
SSRXp
8
SSRXn
USB Host
2
Optional
9
Controller
10 NŸ
1
10
B0±
A0+
C0+
A0C0±
A1+
B1+
A1B1±
OEn
C1+
SEL
NC
NC
VCC
VCC
0.01 µF
0.1 µF 10 µF
C1±
GND
GND
GND
19
A2
SSTXp1
GND
SSTXn1
GND
B2
SSTXp2
GND
B3
SSTXn2
GND
B11
SSRXp1
18
A3
15
14
17
16
B10
13
A11
12
5
A10
A5
11
20
A1
B12
A12
B1
SSRXn1
SSRXp2
SSRXn2
CC1
B5
CC2
USB C
6
VCC
CC
Controller
Copyright © 2016, Texas Instruments Incorporated
Figure 8. Down Facing Port for USB3.1 Type C Connector
10.2.1.1 Design Requirements
The HD3SS3212 can be designed into many different applications. All the applications have certain requirements
for the system to work properly. The HD3SS3212 requires 3.3-V ±10% VCC rail. The OEn pin must be low for
device to work otherwise it disables the outputs. This pin can be driven by a processor. The expectation is that
one side of the device has AC coupling capacitors. Table 2 provides information on expected values to perform
properly.
Table 2. Design Parameters
DESIGN PARAMETER
VCC
VALUE
3.3 V
AXp/n, BXp/n, CXp/n CM input voltage
Control/OEn pin max voltage for low
Control/OEn pin min voltage for high
AC coupling capacitor
RBIAS (Figure 8) when needed
0 to 2 V
0.8 V
2.0 V
100 nF
1 kΩ
10.2.1.2 Detailed Design Procedure
The HD3SS3212 is a high-speed passive switch device that can behave as a mux or demux. Because this is a
passive switch, signal integrity is important because the device provides no signal conditioning capability. The
device can support 2 to 3 inches of board trace and a connector on either end.
To
•
•
•
•
•
design in the HD3SS3212, the designer needs to understand the following.
Determine the loss profile between circuits that are to be muxed or demuxed.
Provide clean impedance and electrical length matched board traces.
Depending upon the application, determine the best place to put the 100-nF coupling capacitor.
Provide a control signal for the SEL and OEn pins.
The thermal pad must be connected to ground.
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•
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See the application schematics on recommended decouple capacitors from VCC pins to ground
10.2.1.3 Application Curves
Figure 9. 10 Gbps Source Eye Diagram
Figure 10. 10 Gbps Output Eye Diagram
10.3 Systems Examples
10.3.1 Up Facing Port for USB3.1 Type C
HD3SS3212
A1
B12
SSTXp1
GND
SSTXn1
GND
SSTXp2
A12
GND
B1
A2
19 B0+
A3
18
B2
15
B3
14
SSTXn2
GND
SSRXP1
SSRXn1
SSRXp2
B11
B10
C0+
A0±
C0±
A1+
B1+
16 B1±
OEn
13
A10
12 C1±
5
GND
11
GND
20
GND
A5
B5
A1±
C1+
SEL
3
0.1 µF
4
0.1 µF
SSTXp
SSTXn
7
SSRXp
8
SRTXn
USB Device
2
Optional
9
Controller
NC 1
10 k:
NC 10
VCC
VCC
CC2
USB C
A0+
A11
SSRXn2
CC1
17
B0±
6
10 µF
0.1 µF
0.01 µF
VCC
CC
Controller
Copyright © 2016, Texas Instruments Incorporated
Figure 11. Up Facing Port for USB3.1 USB Type-C Connector
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Systems Examples (continued)
10.3.2 PCIE/SATA/USB
HD3SS3212
B0+
TXp
0.1 µF
3
0.1 µF
4
TXn
B0±
A0+
B1+
A0±
B1±
7
RXp
C0±
OEn
9
C1+
SEL
C1±
Controller
GND
VCC
VCC
VCC
10 NŸ
VCC
17
16
C0+ 15
A1±
2
PCIE/USB/
SATA
Optional
18
TXp1
TXn1
RXp1
RXn1
A1+
8
RXn
19
GND
GND
14
13
12
Con
TXp2
TXn2
RXp2
RXn2
5
Con
11
20
1 6 10
0.01 µF
0.1 µF 0.1 µF 10 µF
VCC
Copyright © 2016, Texas Instruments Incorporated
Figure 12. PCIE Motherboard
10.3.3 PCIE/eSATA
HD3SS3212
B0+
3
TXp
4
TXn
7
RXp
8
RXn
MINI CARD
mSATA Con
2
9
Optional
1
10
Controller
10 NŸ
B0±
A0+
B1+
A0±
A1+
A1±
OEn
SEL
0.01 µF
0.1 µF 10 µF
C0+
C0±
C1+
C1±
NC
NC
GND
VCC
VCC
B1±
GND
GND
19
18
15 0.1 µF
14 0.1 µF
17
16
13 0.1 µF
12 0.1 µF
5
11
PCIE Controller
RXp1
RXn1
TXp1
TXn1
RXp2
RXn2
TXp2
TXn2
eSATA Controller
20
6
VCC
Copyright © 2016, Texas Instruments Incorporated
Figure 13. PCIE and eSATA Combo
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Systems Examples (continued)
10.3.4 USB/eSATA
HD3SS3212
B0+
B0±
3
TXp
A0+
B1+
4
TXn
A0±
7
RXp
8
RXn
USB/eSATA
Con
C1±
NC
NC
GND
GND
RXp1
18
RXn1
15 0.1 µF
TXp1
14 0.1 µF
TXn1
17
RXp2
16
RXn2
13 0.1 µF
TXp2
12 0.1 µF
TXn2
5
GND
VCC
VCC
eSATA Controller
11
20
6
0.1 µF 10 µF
0.01 µF
C1+
SEL
1
10
10 NŸ
C0±
OEn
9
Controller
C0+
A1±
2
Optional
B1±
A1+
USB Controller
19
VCC
Copyright © 2016, Texas Instruments Incorporated
Figure 14. eSATA and USB 3.0 Combo Connector
10.3.5 MIPI Camera Serial Interface
HD3SS3212
B0+
3
D0p
4
D0n
7
CLKp
8
CLKn
CSI RX
Chipset
Optional
2
9
Controller
1
10
10 NŸ
B0±
A0+
B1+
A0±
B1±
0.1 µF 10 µF
D0p
18
D0n
15
CLKp
14
CLKn
A1+
A1±
OEn
SEL
C0+
C0±
C1+
C1±
NC
NC
GND
VCC
VCC
0.01 µF
CSI Camera
19
GND
GND
17
D0p
16
D0n
13
CLKp
12
CLKn
5
CSI Camera
11
20
6
VCC
Copyright © 2016, Texas Instruments Incorporated
Figure 15. CSI Camera Array
16
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11 Power Supply Recommendations
The HD3SS3212 does not require a power supply sequence. However, TI recommends that OEn is asserted low
after device supply VCC is stable and in specification. TI also recommends to place ample decoupling capacitors
at the device VCC near the pin.
12 Layout
12.1 Layout Guidelines
On a high-K board, TI always recommends to solder the PowerPAD™ onto the thermal land. A thermal land is
the area of solder-tinned-copper underneath the PowerPAD package. On a high-K board, the HD3SS3212 can
operate over the full temperature range by soldering the PowerPAD onto the thermal land without vias.
On a low-K board, for the device to operate across the temperature range, the designer must use a 1-oz Cu
trace connecting the GND pins to the thermal land. A general PCB design guide for PowerPAD packages is
provided in PowerPAD Thermally-Enhanced Package, SLMA002.
12.2 Layout Example
Figure 16. HD3SS3212 Basic Layout Example for Application Shown
in Down Facing Port for USB3.1 Type C
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13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
HD3SS3212
Click here
Click here
Click here
Click here
Click here
HD3SS3212I
Click here
Click here
Click here
Click here
Click here
13.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
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www.ti.com
SLASE74E – MAY 2015 – REVISED MAY 2016
PACKAGE OUTLINE
RKS0020A
VQFN - 1 mm max height
SCALE 3.300
PLASTIC QUAD FLATPACK - NO LEAD
2.6
2.4
A
B
PIN 1 INDEX AREA
4.6
4.4
C
1 MAX
SEATING PLANE
0.05
0.00
0.08
1±0.1
2X 0.5
14X 0.5
(0.2) TYP
11
10
9
12
2X
3.5
EXPOSED
THERMAL PAD
3±0.1
2
PIN 1 ID
(OPTIONAL)
19
1
20X
20
20X
0.5
0.3
0.3
0.2
0.1
0.05
C A
B
4222490/A 10/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RKS0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1)
SYMM
1
20
20X (0.6)
2
19
20X (0.25)
(1.25)
SYMM
(3)
(4.3)
16X (0.5)
(R0.05) TYP
12
9
( 0.2) VIA
TYP
10
11
(2.3)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222490/A 10/2015
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
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SLASE74E – MAY 2015 – REVISED MAY 2016
EXAMPLE STENCIL DESIGN
RKS0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (0.95)
1
20
20X (0.6)
2
19
20X (0.25)
2X (1.31)
16X (0.5)
SYMM
(4.3)
(0.76)
METAL
TYP
9
12
(R0.05) TYP
11
10
SYMM
(2.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
83% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4222490/A 10/2015
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
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13-Jul-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
HD3SS3212IRKSR
ACTIVE
VQFN
RKS
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
HD3212I
HD3SS3212IRKST
ACTIVE
VQFN
RKS
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
HD3212I
HD3SS3212RKSR
ACTIVE
VQFN
RKS
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
0 to 70
HDS3212
HD3SS3212RKST
ACTIVE
VQFN
RKS
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
0 to 70
HDS3212
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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13-Jul-2016
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jul-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
HD3SS3212IRKSR
VQFN
RKS
20
HD3SS3212IRKST
VQFN
RKS
HD3SS3212RKSR
VQFN
RKS
HD3SS3212RKST
VQFN
RKS
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
177.8
12.4
2.73
4.85
1.03
4.0
12.0
Q1
20
250
177.8
12.4
2.73
4.85
1.03
4.0
12.0
Q1
20
3000
177.8
12.4
2.73
4.85
1.03
4.0
12.0
Q1
20
250
177.8
12.4
2.73
4.85
1.03
4.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jul-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
HD3SS3212IRKSR
VQFN
RKS
20
3000
223.0
270.0
35.0
HD3SS3212IRKST
VQFN
RKS
20
250
223.0
270.0
35.0
HD3SS3212RKSR
VQFN
RKS
20
3000
223.0
270.0
35.0
HD3SS3212RKST
VQFN
RKS
20
250
223.0
270.0
35.0
Pack Materials-Page 2
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