a FEATURES DC PERFORMANCE 25 mV max Offset Voltage (AD705T) 0.6 mV/8C max Drift (AD705K/T) 100 pA max Input Bias Current (AD705K) 600 pA max IB Over MIL Temperature Range (AD705T) 114 dB min CMRR (AD705K/T) 114 dB min PSRR (AD705T) 200 V/mV min Open Loop Gain 0.5 mV p-p typ Noise, 0.1 Hz to 10 Hz 600 mA max Supply Current AC PERFORMANCE 0.15 V/µs Slew Rate 800 kHz Unity Gain Crossover Frequency 10,000 pF Capacitive Load Drive Capability Low Cost Available in 8-Pin Plastic Mini-DlP, Hermetic Cerdip and Surface Mount (SOIC) Packages MIL-STD-883B Processing Available Dual Version Available: AD706 Quad Version: AD704 APPLICATIONS Low Frequency Active Filters Precision Instrumentation Precision Integrators PRODUCT DESCRIPTION The AD705 is a low power bipolar op amp that has the low input bias current of a BiFET amplifier but which offers a significantly lower IB drift over temperature. The AD705 offers many of the advantages of BiFET and bipolar op amps without their inherent disadvantages. It utilizes superbeta bipolar input transistors to achieve the picoampere input bias current levels of FET input amplifiers (at room temperature), while its IB typically only increases 5 times vs. BiFET amplifiers which exhibit a 1000X increase over temperature. This means that, at room temperature, while a typical BiFET may have less IB than the AD705, the BiFET’s input current will increase to a level of several nA at +125°C. Superbeta bipolar technology also permits the AD705 to achieve the microvolt offset voltage and low noise characteristics of a precision bipolar input amplifier. The AD705 is a high quality replacement for the industrystandard OP07 amplifier while drawing only one sixth of its power supply current. Since it has only 1/20th the input bias current of an OP07, the AD705 can be used with much higher source impedances, while providing the same level of dc precision. In addition, since the input bias currents are at picoAmp Picoampere Input Current Bipolar Op Amp AD705 CONNECTION DIAGRAM Plastic Mini-DIP (N) Cerdip (Q) and Plastic SOIC (R) Packages OFFSET NULL 1 TOP VIEW 8 OFFSET NULL –IN 2 7 V+ +IN 3 6 OUTPUT V– 4 5 OVER COMP AD705 levels, the commonly used “balancing” resistor (connected between the noninverting input of a bipolar op amp and ground) is not required. The AD705 is an excellent choice for use in low frequency active filters in 12- and 14-bit data acquisition systems, in precision instrumentation and as a high quality integrator. The AD705 is internally compensated for unity gain and is available in five performance grades. The AD705J and AD705K are rated over the commercial temperature range of 0°C to +70°C. The AD705A and AD705B are rated over the industrial temperature range of –40°C to +85°C. The AD705T is rated over the military temperature range of –55°C to +125°C and is available processed to MIL-STD-883B, Rev. C. The AD705 is offered in three varieties of 8-pin package: plastic DIP, hermetic cerdip and surface mount (SOIC). “J” grade chips are also available. PRODUCT HIGHLIGHTS 1. The AD705 is a low drift op amp that offers BiFET level input bias currents, yet has the low IB drift of a bipolar amplifier. It upgrades the performance of circuits using op amps such as the LT1012. 2. The combination of Analog Devices’ advanced superbeta processing technology and factory trimming provides both low drift and high dc precision. 3. The AD705 can be used in applications where a chopper amplifier would normally be required but without the chopper’s inherent noise and other problems. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD705–SPECIFICATIONS (@ T = +258C, V A Parameter INPUT OFFSET VOLTAGE Initial Offset Offset vs. Temp, Average TC vs. Supply (PSRR) TMIN to TMAX Long Term Stability Conditions Min TMIN to TMAX VS = ± 2 V to ± 18 V VS = ± 2.5 V to ± 18 V 110 108 CM = 0 V, and VS = 615 V dc, unless otherwise noted) AD705J/A Typ Max 30 45 0.2 129 126 0.3 90 150 1.2 60 80 0.3 80 100 150 200 40 40 0.3 80 80 150 200 Min 110 108 AD705K/B Typ Max 10 25 0.2 129 126 0.3 35 60 0.6 30 50 0.3 50 70 100 150 30 30 0.3 50 50 100 150 Min 114 108 AD705T Typ Max Units 10 25 0.2 129 126 0.3 25 60 0.6 µV µV µV/°C dB dB µV/month 30 50 0.6 90 120 100 150 pA pA pA/°C pA pA INPUT BIAS CURRENT 1 VCM = 0 V VCM = ± 13.5 V vs. Temp, Average TC TMIN to TMAX TMIN to TMAX INPUT OFFSET CURRENT VCM = 0 V VCM = ± 13.5 V VCM = 0 V VCM = ± 13.5 V vs. Temp, Average TC TMIN to TMAX TMIN to TMAX VCM = 0 V VCM = ± 13.5 V FREQUENCY RESPONSE Unity Gain Crossover Frequency Slew Rate, Unity Gain Slew Rate G = –1 TMIN to TMAX 0.4 0.1 0.05 INPUT IMPEDANCE Differential Common Mode INPUT VOLTAGE NOISE 0.8 0.15 0.15 VCM = ± 13.5 V TMIN to TMAX 40i2 300i2 0.8 0.15 0.15 MHz V/µs V/µs 40i2 300i2 MΩipF GΩipF ± 14 V 110 108 132 128 114 108 132 128 114 108 132 128 dB dB OPEN-LOOP GAIN VO = ± 12 V RLOAD = 10 kΩ TMIN to TMAX VO = ± 10 V RLOAD = 2 kΩ TMIN to TMAX TEMPERATURE RANGE FOR RATED PERFORMANCE Commercial (0°C to +70°C) Industrial (–40°C to +85°C) Military (–55°C to +125°C) 0.4 0.1 0.05 ± 13.5 50 0.5 17 15 22 1.0 0.5 17 15 22 50 1.0 22 µV p-p nV/√Hz nV/√Hz 50 fA/√Hz 300 200 2000 1500 400 300 2000 1500 400 300 2000 1500 V/mV V/mV 200 150 1000 1000 300 200 1000 1000 300 200 1000 1000 V/mV V/mV ± 13 613 ± 14 ± 14 ± 15 ± 13 613 ± 14 ± 14 ± 15 ± 13 613 ± 14 ± 14 ± 15 V V mA 10,000 200 pF Ω Gain = +1 Open Loop 10,000 200 62.0 TMIN to TMAX 0.8 0.15 0.15 250 450 pA pA pA/°C pA pA ± 14 f = 10 Hz POWER SUPPLY Rated Performance Operating Range Quiescent Current 150 350 100 150 ± 13.5 INPUT CURRENT NOISE RLOAD = 10 kΩ TMIN to TMAX Short Circuit 30 30 0.4 80 80 600 750 ± 14 0.5 17 15 Current Capacitive Load Drive Capability Output Resistance 0.4 0.1 0.05 150 350 ± 13.5 0.1 Hz to 10 Hz f = 10 Hz f = 1 kHz OUTPUT CHARACTERISTICS Voltage Swing 250 450 40i2 300i2 INPUT VOLTAGE RANGE Common-Mode Voltage COMMON-MODE REJECTION RATIO 250 450 ± 15 10,000 200 618 600 800 380 400 AD705J AD705A 62.0 ± 15 380 400 618 600 800 62.0 ± 15 380 400 618 600 800 V V µA µA AD705K AD705B AD705T –2– REV. B AD705 Parameter Conditions Min PACKAGE OPTIONS 8-Pin Cerdip (Q-8) 8-Pin Plastic Mini-DIP (N-8) 8-Pin SOIC (R-8) Chips AD705J/A Typ Max Min AD705AQ AD705JN AD705JR AD705JCHIPS TRANSISTOR COUNT # of Transistors AD705K/B Typ Max AD705BQ AD705KN 45 45 Min AD705T Typ Max Units AD705TQ 45 NOTES 1 Bias current specifications are guaranteed maximum at either input. All min and max specifications are guaranteed Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS 1 METALIZATION PHOTOGRAPH Dimensions shown in inches and (mm). 0.074 (1.88) NULL 8 +VS 7 VOUT 6 7 8 6 5 OVER COMP 5 0.0677 (1.72) 1 NULL 1 4 2 –IN 2 3 3 +IN 4 –VS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . 650 mW Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS Differential Input Voltage3 . . . . . . . . . . . . . . . . . . . . . ± 0.7 V Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite Storage Temperature Range (N, R) . . . . . . . –65°C to +125°C Storage Temperature Range (Q) . . . . . . . . . –65°C to +150°C Operating Temperature Range AD705J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C AD705A/B . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C AD705T . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C NOTES 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 8-Pin Plastic Package: θJA = 165°C/Watt 8-Pin Cerdip Package: θJA = 110°C/Watt 8-Pin Small Outline Package: θJA = 155°C/Watt 3 The input pins of these amplifiers are protected by back-to-back diodes. If the differential voltage exceeds ± 0.7 V, external series protection resistors should be added to limit the input current to less than 25 mA. ORDERING GUIDE Model AD705AQ AD705BQ AD705JCHIPS AD705JN AD705JR AD705JR-REEL AD705JR-REEL7 AD705KN AD705TQ AD705TQ/883B Temperature Range –40°C to +85°C –40°C to +85°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C –55°C to +125°C –55°C to +125°C Package Description 8-Pin Ceramic DIP 8-Pin Ceramic DIP Bare Die 8-Pin Plastic DIP 8-Pin Plastic SOIC 8-Pin Plastic SOIC 8-Pin Plastic SOIC 8-Pin Plastic DIP 8-Pin Ceramic DIP 8-Pin Ceramic DIP CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD705 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. B –3– Package Option Q-8 Q-8 N-8 R-8 R-8 R-8 N-8 Q-8 Q-8 WARNING! ESD SENSITIVE DEVICE AD705–Typical Characteristics (@ +258C, V = 615 V, unless otherwise noted) S 100 40 NUMBER OF UNITS NUMBER OF UNITS 120 80 20 40 0 – 80 0 –60 – 40 – 20 0 + 20 +40 +60 +80 INPUT OFFSET VOLTAGE – Microvolts Figure 1. Typical Distribution of Input Offset Voltage 0 –120 –60 0 +60 +120 INPUT OFFSET CURRENT – Picoamperes Figure 3. Typical Distribution of Input Offset Current 100 35 –0.5 –1.5 +1.5 +1.0 OFFSET VOLTAGE DRIFT – µV/°C 30 OUTPUT VOLTAGE – Volts p-p –1.0 25 20 15 10 5 +0.5 –VS 0 5 10 15 SUPPLY VOLTAGE – ±Volts 0 1k 20 Figure 4. Input Common-Mode Voltage Range vs. Supply Voltage 30 20 10 0 CHANGE IN OFFSET VOLTAGE – µV 40 –0.2 0 +0.2 +0.4 OFFSET VOLTAGE DRIFT – µV/°C Figure 7. Typical Distribution of Offset Voltage Drift 1.0 1k 10k 100k 1M 10M SOURCE RESISTANCE – Ω 100M Figure 6. Offset Voltage Drift vs. Source Resistance 60 40 3 2 1 20 POSITIVE IB 0 –20 –40 0 –0.4 10 1M 4 SAMPLE SIZE: 85 –55°C TO +125°C SOURCE RESISTANCE MAY BE EITHER BALANCED OR UNBALANCED 0.1 10k 100k FREQUENCY – Hz Figure 5. Large Signal Frequency Response 50 80 –120 0 +60 +120 –60 INPUT BIAS CURRENT – Picoamperes Figure 2. Typical Distribution of Input Bias Current +VS 120 40 INPUT BIAS CURRENT – pA NUMBER OF UNITS 160 160 60 INPUT COMMON MODE VOLTAGE LIMIT – Volts (REFERRED TO SUPPLY VOLTAGES) SAMPLE SIZE: 510 SAMPLE SIZE: 1040 80 NUMBER OF UNITS 200 200 SAMPLE SIZE: 610 0 1 2 3 4 WARM-UP TIME IN MINUTES 5 Figure 8. Change in Input Offset Voltage vs. Warm-Up Time –4– –60 –15 NEGATIVE IB –10 –5 0 +5 +10 COMMON MODE VOLTAGE – Volts +15 Figure 9. Input Bias Current vs. Common-Mode Voltage REV. B AD705 1000 CURRENT NOISE – fA/√Hz VOLTAGE NOISE – nV/√Hz 1000 100 10 100 0.5µV 100Ω 10kΩ 20MΩ 10 VOUT = in(2 • 109Ω) 1 1 10 100 FREQUENCY – Hz 1 1000 Figure 10. Input Noise Voltage Spectral Density CMRR – dB +125°C 180 140 160 120 140 100 120 80 60 –PSRR 80 + PSRR 40 60 20 40 0 5 10 15 SUPPLY VOLTAGE – ±Volts 0.1 20 Figure 13. Quiescent Supply Current vs. Supply Voltage 10 100 1k 10k FREQUENCY – Hz 100k OPEN LOOP VOLTAGE GAIN –55°C +25°C +125°C 140 0 120 30 100 60 PHASE 90 80 120 60 100k 2 4 6 10 20 40 60 LOAD RESISTANCE – kΩ 100 GAIN 40 150 20 180 Figure 16. Open Loop Gain vs. Load Resistance over Temperature REV. B – 20 0.01 0.1 1 10 100 1k 10k FREQUENCY – Hz 100k 1M Figure 15. Power Supply Rejection vs. Frequency 0 1 20 0.1 1M Figure 14. Common-Mode Rejection vs. Frequency 10M 1M 1 +VS OUTPUT VOLTAGE LIMIT – Volts (REFERRED TO SUPPLY VOLTAGES) 300 0 10 100 +25°C 350 PHASE SHIFT – Degrees QUIESCENT CURRENT – µA 450 5 TIME – Seconds Figure 12. 0.1 Hz to 10 Hz Noise Voltage 160 +55°C OPEN LOOP VOLTAGE GAIN 0 1000 Figure 11. Input Noise Current Spectral Density 500 400 10 100 FREQUENCY – Hz PSRR – dB 1 –0.5 –1.0 –1.5 +1.5 +1.0 +0.5 –VS 1 10 100 1k 10k 100k 1M 10M FREQUENCY – Hz Figure 17. Open Loop Gain and Phase Shift vs. Frequency –5– 0 5 10 15 SUPPLY VOLTAGE – ±Volts Figure 18. Output Voltage Limit vs. Supply Voltage 20 AD705 1M 0.1 100k SLEW RATE 0.01 10k ADDING AN EXTERNAL CAPACITOR BETWEEN PIN 5 AND GROUND INCREASES THE AMPLIFIER'S COMPENSATION 0.001 1 10 100 1000 1k 10,000 CLOSED LOOP OUTPUT IMPEDANCE – Ω SLEW RATE – V/µs GAIN BANDWIDTH RF 1000 GAIN BANDWIDTH PRODUCT – Hz 1 +VS 100 0.1µF AV = –1000 10 7 2 AD705 1 VIN AV = +1 3 VOUT 6 RL 2kΩ 4 CL 0.1 –VS 0.1µF 0.01 IOUT = +1mA SQUARE WAVE INPUT 0.001 1 10 100 1k 10k 100k FREQUENCY – Hz VALUE OF OVERCOMPENSATION CAPACITOR – pF Figure 20. Magnitude of Closed Loop Output Impedance vs. Frequency Figure 19. Slew Rate & Gain Bandwidth Product vs. Value of Overcompensation Capacitor Figure 21a. Unity Gain Follower (For Large Signal Applications, Resistor RF Limits the Current Through the Input Protection Diodes) 5µs 20µs 5µs 100 100 100 90 90 90 10 10 10 0% 0% 0% 20mV 2V Figure 21b. Unity Gain Follower Large Signal Pulse Response RF = 10 kΩ, CL = 50 pF 20mV Figure 21c. Unity Gain Follower Small Signal Pulse Response RF = 0 Ω, CL = 100 pF Figure 21d. Unity Gain Follower Small Signal Pulse Response RF = 0 Ω, CL = 1000 pF 10kΩ 0.1µF 10kΩ VIN 2 5µs 100 100 90 90 10 10 0% 0% 7 AD705 3 50µs 2V +VS 4 –VS VOUT 6 RL 2.5kΩ CL 0.1µF 20mV SQUARE WAVE INPUT Figure 22a. Unity Gain Inverter Figure 22b. Unity Gain Inverter Large Signal Pulse Response CL = 50 pF –6– Figure 22c. Unity Gain Inverter Small Signal Pulse Response CL = 100 pF REV. B AD705 A High Performance Differential Amplifier Circuit 5µs Figure 25 shows a high input impedance, differential amplifier circuit that features a high common-mode voltage, and which operates at low power. Table I details its performance with changes in gain. To optimize the common-mode rejection of this circuit at low frequencies and dc, apply a 1 volt, 1 Hz sine wave to both inputs. Measuring the output with an oscilloscope, adjust trimming potentiometer R6 for minimum output. For the best CMR at higher frequencies, capacitor C2 should be replaced with a 1.5 pF to 20 pF trimmer capacitor. 100 90 10 0% 20mV Figure 22d. Unity Gain Inverter Small Signal Pulse Response C, = 1000 pF Both the IC socket and any standoffs at the op amp’s input terminals should be made of Teflon* to maintain low input current drift over temperature. *Teflon is a registered trademark of E.I. DuPont, Co. 10pF* C1 5pF 10kΩ R3 200kΩ R2 10MΩ +VS R5* 0.1µF +VS SQUARE WAVE INPUT 7 2 AD705 5kΩ VIN R1 100MΩ VOUT 6 VIN– 5 3 4 *RESPONSE IS 0.1µF –VS 0.1µF AD705 3 NEARLY IDENTICAL FOR CAPACITANCE VALUES OF 0 TO 100pF R4* 7 2 4 SOURCE 0.1µF –VS R1' 100MΩ 4.1nF VIN+ Figure 23a. Follower Connected in Feed-Forward Mode GND R2' 10MΩ C2 5pF VOUT 6 DC CMR ADJUST R6 500kΩ CIRCUIT GAIN, G = – R2+R3 (1+ R5 ) R4 R1 VOUT = G (VIN– – VIN+) COMMON MODE INPUT RANGE = 10 (VS – 1.5V) FOR VS = ±15V, VCM RANGE = ±135V RESISTORS R1 AND R1', R2 AND R2' ARE VICTOREEN MOX-200 1/4 WATT, 1% METAL OXIDE. *SEE TABLE I 5V WARNING: POTENTIAL DANGER FROM HIGH SOURCE VOLTAGE. THIS DIFFERENTIAL AMPLIFIER DOES NOT PROVIDE GALVANIC ISOLATION. INPUT SOURCE MUST BE REFERRED TO THE SAME GROUND CONNECTION AS THIS AMPLIFIER. 5µs 100 90 INPUT Figure 25. A High Performance Differentials Amplifier Circuit 10 0% Table I. Typical Performance of Differential Amplifier Circuit Operating at Various Gains OUTPUT 5V Circuit R4 Gain (V) Figure 23b. Follower Feed-Forward Pulse Response VOS ADJUST +VS 20kΩ 1 0.1µF 8 2 1 10 100 7 AD705 6 5 3 0.1µF 4 OVERCOMPENSATION CAPACITOR –VS Figure 24. Offset Null and Overcompensation Connections REV. B –7– R5 (V) Trimmed DC CMR (dB) 1.13 kΩ 10 kΩ ≥85 100 Ω 9.76 kΩ ≥85 10.2 Ω 10 kΩ ≥85 RTI Average Circuit Drift TC Bandwidth (mV/8C) –3 dB 30 30 30 4.4 kHz 2.8 kHz 930 Hz AD705 Table II. Recommended Component Values for the 1 Hz Low-Pass Filter Table II gives recommended component values for the 1 Hz filter of Figure 26. An unusual characteristic of the AD705 is that both the input bias current and the input offset current and their drift remain low over most of the op amps rated temperature range. Therefore, for most applications, there is no need to use the normal balancing resistor tied between the noninverting terminal of the op amp and ground. Eliminating the standard balancing resistor reduces board space and lowers circuit noise. However, this resistor is needed at temperatures above 110°C, because input bias current starts to change rapidly, as shown by Figure 27. Desired Low Pass Response Bessel Response Butterworth Response 0.1 dB Chebychev 0.2 dB Chebychev 0.5 dB Chebychev 1.0 dB Chebychev Pole Frequency (Hz) Pole Q 1.27 1.00 0.93 0.90 0.85 0.80 0.58 0.707 0.77 0.80 0.86 0.96 C1 Value C2 Value (mF) (mF) 0.14 0.23 0.26 0.28 0.32 0.38 0.11 0.11 0.11 0.11 0.11 0.10 C1357a–2–10/94 A 1 Hz, 2-Pole, Active Filter Specified values are for a –3 dB point of 1.0 Hz. For other frequencies, simply scale capacitors C1 and C2 directly; i.e., for 3 Hz Bessel response, C1 = 0.046 µF, C2 = 0.037 µF. C1 R2 1MΩ OFFSET VOLTAGE OF FILTER CIRCUIT (RTI) – µV +VS R1 1MΩ 0.1µF 7 3 INPUT C2 AD705 2 VOUT 6 4 0.1µF –VS OPTIONAL BALANCE RESISTOR NETWORK R3 2MΩ WITHOUT THE NETWORK, PINS 2 AND 6 OF THE AD705 ARE TIED TOGETHER. C3 0.01µF CAPACITORS C1, C2 AND C3 ARE SOUTHERN ELECTRONICS MPCC, POLYCARBONATE, ±5%, 50 VOLT. 90 60 WITHOUT OPTIONAL BALANCE RESISTOR, R3 30 0 WITH OPTIONAL BALANCE RESISTOR, R3 –30 –60 –90 –60 –40 –20 0 +20 +40 +60 +80 +100 +120 +140 TEMPERATURE – °C Figure 26. A 1 Hz, 2-Pole Active Filter Figure 27. VOS vs. Temperature of 1 Hz Filter OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Cerdip (Q) Package 0.055 (1.4) MAX 8 8 5 5 8 0.25R (0.64) 0.25 (6.35) PIN 1 1 1 4 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) MAX 0.150 (3.81) MIN 0.200 (5.08) 0.125 (3.18) 0.154 ± 0.004 (3.91 ± 0.10) PIN 1 4 0.236 ± 0.012 (6.00 ± 0.20) 4 1 0.100 0.070 (1.78) (2.54) 0.030 (0.76) BSC SEATING PLANE 0.193 ± 0.008 (4.90 ± 0.10) 0.035 ± 0.01 (0.89 ± 0.25) 0.165 ± 0.01 (4.19 ± 0.25) 0.18 ± 0.03 (4.57 ± 0.76) 0.125 (3.18) MIN 0.018 ± 0.003 (0.46 ± 0.08) 0.310 (7.87) 0.220 (5.59) 0.100 (2.54) TYP 0.033 (0.84) NOM 0.30 (7.62) REF 0.32 (8.13) 0.29 (7.37) 0-15 ° 5 0.31 (7.87) 0.39 (9.91) MAX 0.405 (10.29) MAX 0.023 (0.58) 0.014 (0.36) 8-Pin SOIC (R) Package 0.098 ± 0.006 (2.49 ± 0.23) 0.008 ± 0.004 (0.203 ± 0.075) 0.0500 (1.27) BSC 0.017 ± 0.003 (0.42 ± 0.07) SEATING PLANE 0.011 ± 0.002 (0.269 ± 0.03) 0.033 ± 0.017 (0.83 ± 0.43) 0.011 ± 0.003 (0.28 ± 0.08) 0.015 (0.38) 0.008 (0.20) 0-15 ° –8– REV. B PRINTED IN U.S.A. 0.005 (0.13) MIN Plastic Mini-DIP (N) Package