February 2005 AS7C33128NTD32B AS7C33128NTD36B ® 3.3V 128K×32/36 Pipelined SRAM with NTDTM Features • Clock enable for operation hold • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ • Self-timed write cycles • Interleaved or linear burst modes • Snooze mode for reduced power standby • Organization: 131,072 words × 32 or 36 bits • NTD™ architecture for efficient bus operation • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous operation • Asynchronous output enable control • Available in 100-pin TQFP package • Byte write enables Logic block diagram 17 A[16:0] D 17 Q Address register 17 Burst logic CLK 17 D Q Write delay addr. registers CE0 CE1 CE2 17 CLK R/W BWc BWd ADV / LD LBO ZZ DQ [a:d] Write Data Registers Control logic BWa BWb 128K x 32/36 SRAM Array CLK 32/36 D CLK 32/36 Data Q Input Register 32/36 32/36 CLK 32/36 CLK CLK CEN OE Output Register 32/36 OE DQ [a:d] Selection Guide -200 -166 -133 Units 5 6 7.5 ns Maximum clock frequency 200 166 133 MHz Maximum clock access time 3.0 3.5 4 ns Maximum operating current 375 350 325 mA Maximum standby current 135 120 110 mA Maximum CMOS standby current (DC) 30 30 30 mA Minimum cycle time 2/8/05; v.1.5 Alliance Semiconductor P. 1 of 18 Copyright © Alliance Semiconductor. All rights reserved. AS7C33128NTD32B AS7C33128NTD36B ® 4 Mb Synchronous SRAM products list1,2 Org 256KX18 128KX32 128KX36 256KX18 128KX32 128KX36 256KX18 128KX32 128KX36 256KX18 Part Number AS7C33256PFS18B AS7C33128PFS32B AS7C33128PFS36B AS7C33256PFD18B AS7C33128PFD32B AS7C33128PFD36B AS7C33256FT18B AS7C33128FT32B AS7C33128FT36B AS7C33256NTD18B Mode PL-SCD PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD FT FT FT NTD-PL Speed 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 200/166/133 MHz 128KX32 128KX36 256KX18 128KX32 128KX36 AS7C33128NTD32B AS7C33128NTD36B AS7C33256NTF18B AS7C33128NTF32B AS7C33128NTF36B NTD-PL NTD-PL NTD-FT NTD-FT NTD-FT 200/166/133 MHz 200/166/133 MHz 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 1 Core Power Supply: VDD = 3.3V + 0.165V 2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O VDDQ = 2.5V + 0.125V for 2.5V I/O PL-SCD PL-DCD FT NTD1-PL NTD-FT : : : : : Pipelined Burst Synchronous SRAM - Single Cycle Deselect Pipelined Burst Synchronous SRAM - Double Cycle Deselect Flow-through Burst Synchronous SRAM Pipelined Burst Synchronous SRAM with NTDTM Flow-through Burst Synchronous SRAM with NTDTM 1. NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners. 2/8/05; v.1.5 Alliance Semiconductor P. 2 of 18 AS7C33128NTD32B AS7C33128NTD36B ® 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 TQFP 14x20mm 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPb/NC DQb7 DQb6 VDDQ VSSQ DQb5 DQb4 DQb3 DQb2 VSSQ VDDQ DQb1 DQb0 VSS NC VDD ZZ DQa7 DQa6 VDDQ VSSQ DQa5 DQa4 DQa3 DQa2 VSSQ VDDQ DQa1 DQa0 DQPa/NC LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQPc/NC DQc0 DQc1 VDDQ VSSQ DQc2 DQc3 DQc4 DQc5 VSSQ VDDQ DQc6 DQc7 NC VDD NC VSS DQd0 DQd1 VDDQ VSSQ DQd2 DQd3 DQd4 DQd5 VSSQ VDDQ DQd6 DQd7 DQPd/NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE0 CE1 BWd BWc BWb BWa CE2 VDD VSS CLK R/W CEN OE ADV/LD NC NC A A Pin arrangement for TQFP (top view) Note: Pins 1,30,51,80 are NC for x32 2/8/05; v.1.5 Alliance Semiconductor P. 3 of 18 AS7C33128NTD32B AS7C33128NTD36B ® Functional description The AS7C33128NTD36B family is a high performance CMOS 4 Mbit synchronous Static Random Access Memory (SRAM) organized as 131,072 words × 32 or 36 bits and incorporates a LATE LATE Write. This variation of the 4Mb sychronous SRAM uses the No Turnaround Delay (NTD™) architecture, featuring an enhanced write operation that improves bandwidth over pipeline burst devices. In a normal pipeline burst device, the write data, command, and address are all applied to the device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead' cycles for valid data to become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or read-modify-write operations. NTD™ devices use the memory bus more efficiently by introducing a write 'latency' which matches the two (one) cycle pipeline (flowthrough) read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With NTD™, write and read operations can be used in any order without producing dead bus cycles. Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 32/36 bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device two clock cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for normal operations. Outputs go to a high impedance state when the device is deselected by any of the three chip enable inputs (refer to synchronous truth table on page 6.) In pipeline mode, a two cycle deselect latency allows pending read or write operations to be completed. Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations, including burst, can be stalled using the CEN=1, the clock enable input. The AS7C33128NTD36B and AS7C33128NTD32B operate with a 3.3V ± 5% power supply for the device core (VDD). DQ circuits use a separate power supply (VDDQ) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin 14×20 mm TQFP package. TQFP Capacitance Symbol Test conditions Min Max Unit Input capacitance Parameter CIN* Vin = 0V - 5 pF I/O capacitance CI/O* Vin = Vout = 0V - 7 pF Symbol Typical Units 1–layer θJA 40 °C/W 4–layer θJA 22 °C/W θJC 8 °C/W *Guranteed not tested TQFP thermal resistance Description Thermal resistance (junction to ambient)1 Thermal resistance (junction to top of case)1 Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 1 This parameter is sampled 2/8/05; v.1.5 Alliance Semiconductor P. 4 of 18 AS7C33128NTD32B AS7C33128NTD36B ® Signal descriptions Signal I/O Properties Description CLK I CLOCK Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock. CEN I SYNC Clock enable. When de-asserted high, the clock input signal is masked. A, A0, A1 I SYNC Address. Sampled when all chip enables are active and ADV/LD is asserted. DQ[a,b,c,d] I/O SYNC Data. Driven as output when the chip is enabled and OE is active. CE0, CE1, CE2 I SYNC Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted. Are ignored when ADV/LD is high. ADV/LD I SYNC Advance or Load. When sampled high, the internal burst address counter will increment in the order defined by the LBO input value. When low, a new address is loaded. R/W I SYNC A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE operation. Is ignored when ADV/LD is high. BW[a,b,c,d] I SYNC Byte write enables. Used to control write on individual bytes. Sampled along with WRITE command and BURST WRITE. OE I ASYNC Asynchronous output enable. I/O pins are not driven when OE is inactive. LBO I STATIC Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When driven Low, device follows linear Burst order. This signal is internally pulled High. ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused. NC - - No connect Snooze Mode SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of SNOOZE MODE is dictated by the length of time the ZZ is in a High state. The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE. When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE. Burst order Interleaved burst order (LBO = 1) Linear burst order (LBO = 0) A1 A0 A1 A0 A1 A0 A1 A0 Starting address 0 0 0 1 1 0 1 1 First increment 0 1 0 0 1 1 Second increment 1 0 1 1 Third increment 1 1 1 0 2/8/05; v.1.5 A1 A0 A1 A0 A1 A0 A1 A0 Starting Address 0 0 0 1 1 0 1 1 1 0 First increment 0 1 1 0 1 1 0 0 0 0 0 1 Second increment 1 0 1 1 0 0 0 1 0 1 00 Third increment 1 1 0 0 0 1 1 0 Alliance Semiconductor P. 5 of 18 AS7C33128NTD32B AS7C33128NTD36B ® Synchronous truth table[5,6,7,8,9,11] CE0 CE1 CE2 ADV/LD R/W BWn OE CEN Address source CLK Operation DQ H X X L X X X L NA L to H DESELECT Cycle High-Z X X H L X X X L NA L to H DESELECT Cycle High-Z X L X L X X X L NA L to H DESELECT Cycle High-Z X X X H X X X L NA L to H CONTINUE DESELECT Cycle High-Z L H L L H X L L READ Cycle (Begin Burst) Q X X X H X X L L READ Cycle (Continue Burst) Q L H L L H X H L X X X H X X H L L H L L L L X L X X X H X L X L L H L L L H X L X X X H X H X L X X X X X X X H External L to H Next L to H External L to H NOP/DUMMY READ (Begin Burst) High-Z Next L to H External L to H Next L to H DUMMY READ (Continue Burst) L to H 1,10 2 High-Z 1,2,10 D 3 WRITE CYCLE (Continue Burst) D 1,3,10 High-Z 2,3 WRITE ABORT (Continue Burst) High-Z 1,2,3, 10 INHIBIT CLOCK - 4 Current L to H Key: X = Don’t Care, H = HIGH, L = LOW. BWn = H means all byte write signals (BWa, BWb, BWc, and BWd) are HIGH. BWn = L means one or more byte write signals are LOW. Notes: 1 CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chose in the initial BEGIN BURST cycle. A CONINUE DESELECT cycle can only be entered if a DESELECT CYCLE is executed first. 2 DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a WRITE command is given, but no operation is performed. 3 OE may be wired LOW to minimize the number of control signal to the SRAM. The device will automatically turn off the output drivers during a WRITE cycle. OE may be used when the bus turn-on and turn-off times do not meet an application’s requirements. 4 If an INHIBIT CLOCK command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the INHIBIT CLOCK cycle. 5 BWa enables WRITEs to byte “a” (DQa pins); BWb enables WRITEs to byte “b” (DQb pins); BWc enables WRITEs to byte “c” (DQc pins); BWd enables WRITEs to byte “d” (DQd pins). 6 All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 7 Wait states are inserted by setting CEN HIGH. 8 This device contains circuitry that will ensure that the outputs will be in High-Z during power-up. 9 The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST CYCLE. 10 The address counter is incremented for all CONTINUE BURST cycles. 11 ZZ pin is always Low. 2/8/05; v.1.5 1 WRITE CYCLE (Begin Burst) External L to H NOP/WRITE ABORT (Begin Burst) Next Notes Alliance Semiconductor P. 6 of 18 AS7C33128NTD32B AS7C33128NTD36B ® State Diagram for NTD SRAM Read Burst Read Burst Read Read Dsel ad Re W rit Burst ite Wr Burst Write Dsel Write Dsel l Dse e Write Read Write Dsel Dse l Re ad Burst Burst Write Burst Absolute maximum ratings Parameter Symbol Min Max Unit VDD, VDDQ –0.5 +4.6 V Input voltage relative to GND (input pins) VIN –0.5 VDD + 0.5 V Input voltage relative to GND (I/O pins) VIN –0.5 VDDQ + 0.5 V Power dissipation Pd – 1.8 W Short circuit output current IOUT – 20 mA Storage temperature Tstg –65 +150 oC Temperature under bias Tbias –65 +135 oC Power supply voltage relative to GND Stresses greater than those listed under “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability. Recommended operating conditions at 3.3V I/O Parameter Symbol Min Nominal Max Unit Supply voltage for inputs VDD 3.135 3.3 3.465 V Supply voltage for I/O VDDQ 3.135 3.3 3.465 V Vss 0 0 0 V Symbol Min Nominal Max Unit Supply voltage for inputs VDD 3.135 3.3 3.465 V Supply voltage for I/O VDDQ 2.375 2.5 2.625 V Vss 0 0 0 V Ground supply Recommended operating conditions at 2.5V I/O Parameter Ground supply 2/8/05; v.1.5 Alliance Semiconductor P. 7 of 18 AS7C33128NTD32B AS7C33128NTD36B ® DC electrical characteristics for 3.3V I/O operation Parameter Sym Conditions Min Max Unit current† |ILI| VDD = Max, 0V < VIN < VDD -2 2 µA Output leakage current |ILO| OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ -2 2 µA Input high (logic 1) voltage VIH Address and control pins 2* VDD+0.3 I/O pins 2* VDDQ+0.3 Input low (logic 0) voltage VIL Address and control pins -0.3** 0.8 I/O pins -0.5** 0.8 Output high voltage VOH IOH = –4 mA, VDDQ = 3.135V 2.4 – V Output low voltage VOL IOL = 8 mA, VDDQ = 3.465V – 0.4 V Input leakage V V DC electrical characteristics for 2.5V I/O operation Parameter Sym Conditions Min Max Unit Input leakage current† |ILI| VDD = Max, 0V < VIN < VDD -2 2 µA Output leakage current |ILO| OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ -2 2 µA Input high (logic 1) voltage VIH Address and control pins 1.7* VDD+0.3 V I/O pins 1.7* VDDQ+0.3 V Input low (logic 0) voltage VIL Address and control pins -0.3** 0.7 V I/O pins -0.3** 0.7 V Output high voltage VOH IOH = –4 mA, VDDQ = 2.375V 1.7 – V Output low voltage VOL IOL = 8 mA, VDDQ = 2.625V – 0.7 V † LBO and ZZ pins have an internal pull-up or pull-down, and input leakage = ±10 µA. * VIH max < VDD +1.5V for pulse width less than 0.2 X tCYC ** VIL min = -1.5 for pulse width less than 0.2 X tCYC IDD operating conditions and maximum limits Parameter Sym Operating power supply current1 ICC ISB Standby power supply current Test conditions CE0 < VIL, CE1 > VIH, CE2 < VIL, f = fMax, IOUT = 0 mA, ZZ < VIL All VIN ≤ 0.2V or > VDD – 0.2V, Deselected, f = fMax, ZZ < VIL -200 -166 -133 Unit 375 350 325 mA 135 120 110 ISB1 Deselected, f = 0, ZZ < 0.2V, all VIN ≤ 0.2V or ≥ VDD – 0.2V 30 30 30 ISB2 Deselected, f = fMax, ZZ ≥ VDD – 0.2V, all VIN ≤ VIL or ≥ VIH 30 30 30 mA 1 ICC given with no output loading. ICC increases with faster cycle times and greater output loading. 2/8/05; v.1.5 Alliance Semiconductor P. 8 of 18 AS7C33128NTD32B AS7C33128NTD36B ® Timing characteristics over operating range -200 Parameter -166 -133 Notes1 Sym Min Max Min Max Min Max Unit Clock frequency fMAX – 200 - 166 - 133 MHz Cycle time tCYC 5 – 6 - 7.5 - ns Clock access time tCD – 3.0 - 3.5 - 4.0 ns Output enable Low to data valid tOE – 3.0 - 3.5 - 4.0 ns Clock High to output Low Z tLZC 0 – 0 - 0 - ns 2,3,4 Data output invalid from clock High tOH 1.5 – 1.5 - 1.5 - ns 4 Output enable Low to output Low Z tLZOE 0 – 0 - 0 - ns 2,3,4 Output enable High to output High Z tHZOE – 3.0 - 3.5 - 4.0 ns 2,3,4 Clock High to output High Z tHZC – 3.0 - 3.5 - 4.0 ns 2,3,4 Clock High to output High Z tHZCN – 1.5 - 1.5 - 2.0 ns 5 tCH 2.0 – 2.4 - 2.5 - ns 6 Clock Low pulse width tCL 2.3 – 2.4 - 2.5 - ns 6 Address setup to clock High tAS 1.4 – 1.5 - 1.5 - ns 7 Data setup to clock High tDS 1.4 – 1.5 - 1.5 - ns 7 Write setup to clock High tWS 1.4 – 1.5 - 1.5 - ns 7 Clock High pulse width Chip select setup to clock High tCSS 1.4 – 1.5 - 1.5 - ns 7 Clock enable setup to clock High tCENS 1.4 – 1.5 - 1.5 - ns 7 ADV/LD setup to clock High tADVS 1.4 – 1.5 - 1.5 - ns 7 Address hold from clock High tAH 0.4 – 0.5 - 0.5 - ns 7 Data hold from clock High tDH 0.4 – 0.5 - 0.5 - ns 7 Write hold from clock High tWH 0.4 – 0.5 - 0.5 - ns 7 ADV/LD hold from clock High tADVH 0.4 – 0.5 - 0.5 - ns 7 Clock enable hold from clock High tCENH 0.4 – 0.5 - 0.5 - ns 7 tCSH 0.4 – 0.5 - 0.5 - ns 7 Chip select hold from clock High 1 See “Notes” on page 15. Snooze Mode Electrical Characteristics Description Current during Snooze Mode ZZ active to input ignored ZZ inactive to input sampled ZZ active to SNOOZE current ZZ inactive to exit SNOOZE current 2/8/05; v.1.5 Conditions Symbol ZZ > VIH ISB2 tPDS tPUS tZZI tRZZI Alliance Semiconductor Min Max Units 30 mA cycle cycle cycle cycle 2 2 2 0 P. 9 of 18 AS7C33128NTD32B AS7C33128NTD36B ® Key to switching waveforms Rising input don’t care Falling input Undefined Timing waveform of read cycle tCH tCL tCYC CLK tCES tCEH CEN tAS Address tAH A1 A2 A3 tWS tWH R/W tWS tWH BWn tCSH CE0,CE2 CE1 tADVS tADVH ADV/LD OE tOE tLZOE Dout tHZOE Q(A1) tHLZC Q(A2Y‘10) Q(A2) Q(A2Y‘11) Q(A2Y‘01) Read Q(A1) 2/8/05; v.1.5 DSEL Read Q(A2) Continue Read Q(A2Y‘01) Continue Read Q(A2Y‘10) Continue Read Q(A2Y‘11) Alliance Semiconductor Q(A3) Inhibit Clock Read Q(A3) Continue Read Q(A3Y‘01) P. 10 of 18 AS7C33128NTD32B AS7C33128NTD36B ® Timing waveform of write cycle tCH tCL tCYC CLK tCES tCEH CEN tAS Address tAH A1 A2 A3 R/W BWn tCSH CE0,CE2 CE1 tADVS tADVH ADV/LD OE tDS D(A1) Din Q(n-2) D(A2Y‘01) D(A2Y‘10) D(A2Y‘11) Q(n-1) Write D(A1) 2/8/05; v.1.5 D(A3) D(A2) tHZOE Dout tDH DSEL Write D(A2) Continue Write D(A2Y‘01) Continue Write D(A2Y‘10) Continue Write D(A2Y‘11) Alliance Semiconductor Inhibit Clock Write D(A3) Continue Write D(A3Y‘01) P. 11 of 18 AS7C33128NTD32B AS7C33128NTD36B ® Timing waveform of read/write cycle tCH tCL tCYC CLK tCENS tCENH CEN CE1 tCSS tCSH CE0, CE2 tADVS tADVH ADV/LD tWS tWH tWS tWH tAS tAH R/W BWn ADDRESS A1 A3 A2 A4 A6 A5 A7 tCD tDS tDH D/Q D(A1) tLZC D(A2) D(A2Ý01) tOH tOE Q(A3) Q(A4) tHZC Q(A4Ý01) D(A5) Q(A6) tHZOE tLZOE OE Command Write D(A1) Write D(A2) Burst Write D(A2Ý01) Read Q(A3) Read Q(A4) Burst Read Q(A4Ý01) Write D(A5) Read Q(A6) Write D(A7) DSEL Note: Ý = XOR when LBO = high/no connect. Ý = ADD when LBO = low. BW[a:d] is don’t care. 2/8/05; v.1.5 Alliance Semiconductor P. 12 of 18 AS7C33128NTD32B AS7C33128NTD36B ® NOP, stall and deselect cycles CLK CEN CE1 CE0, CE2 ADV/LD R/W BWn Address A2 A1 Q(A1) D/Q Command Read Q(A1) Burst Q(A1Ý01) STALL Q(A1Ý01) Burst Q(A1Ý10) A3 D(A2) Q(A1Ý10) DSEL Burst DSEL Write D(A2) Burst NOP D(A2Ý01) Burst D(A2Ý10) Write NOP D(A3) Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. OE is low. 2/8/05; v.1.5 Alliance Semiconductor P. 13 of 18 AS7C33128NTD32B AS7C33128NTD36B ® Timing waveform of snooze mode CLK tPUS ZZ setup cycle ZZ recovery cycle ZZ tZZI Isupply ISB2 tRZZI All inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation Cycle Dout 2/8/05; v.1.5 High-Z Alliance Semiconductor P. 14 of 18 AS7C33128NTD32B AS7C33128NTD36B ® AC test conditions • Output Load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC see Figure C. • Input pulse level: VSS to 3V. See Figure A. • Input rise and fall time (Measured at 0.3V and 2.7V): 2 ns. See Figure A. • Input and output timing reference levels: 1.5V. +3.0V 90% 10% VSS 90% 10% Figure A: Input waveform Dout Z0=50Ω 50Ω Thevenin equivalent: +3.3V for 3.3V I/O; /+2.5V for 2.5V I/O DOUT VL=1.5V 353Ω / 1538Ω 30 pF* Figure B: Output load (A) 319Ω / 1667Ω 5 pF* GND *including scope and jig capacitance Figure C: Output load (B) Notes 1 2 3 4 5 6 For test conditions, see AC Test Conditions, Figures A, B, C. This parameter measured with output load condition in Figure C 7 This parameter is sampled and not 100% tested. tHZOE is less than tLZOE; and tHZC is less than tLZC at any given temperature and voltage. tHZCN is a ‘no load’ parameter to indicate exactly when SRAM outputs have stopped driving. 2/8/05; v.1.5 tCH measured as HIGH above VIH, and tCL measured as LOW below VIL This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled. Alliance Semiconductor P. 15 of 18 AS7C33128NTD32B AS7C33128NTD36B ® Package Dimensions 100-pin quad flat pack (TQFP) Hd D TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e 15.90 16.10 He 21.90 22.10 L 0.45 0.75 α e 0.65 nominal Hd L1 b He E 1.00 nominal 0° 7° Dimensions in millimeters α c L1 L 2/8/05; v.1.5 Alliance Semiconductor A1 A2 P. 16 of 18 AS7C33128NTD32B AS7C33128NTD36B ® Ordering information Package Width -200 -166 -133 TQFP ×32 AS7C33128NTD32B-200TQC AS7C33128NTD32B-166TQC AS7C33128NTD32B-133TQC TQFP ×36 AS7C33128NTD36B-200TQC AS7C33128NTD36B-166TQC AS7C33128NTD36B-133TQC TQFP ×32 AS7C33128NTD32B-200TQI AS7C33128NTD32B-166TQI AS7C33128NTD32B-133TQI TQFP ×36 AS7C33128NTD36B-200TQI AS7C33128NTD36B-166TQI AS7C33128NTD36B-133TQI Note: Add suffix ‘N’ to the above part number for lead free parts (Ex. AS7C33128NTD32B-166TQCN) Part numbering guide AS7C 33 128 NTD 32/36 B –XXX TQ C/I X 1 2 3 4 5 6 7 8 9 10 1.Alliance Semiconductor SRAM prefix 2.Operating voltage: 33=3.3V 3.Organization: 128=128K 4.NTDTM=No Turn-around Delay, Pipelined mode. 5.Organization: 32=x32; 36=x36 6.Production version: B = Product revision 7.Clock speed (MHz) 8.Package type: TQ=TQFP 9.Operating temperature: C=Commercial ( 0° C to 70° C); I=Industrial (-40° C to 85° C) 10. N = Lead free part 2/8/05; v.1.5 Alliance Semiconductor P. 17 of 18 AS7C33128NTD32B AS7C33128NTD36B ® ® Alliance Semiconductor Corporation Copyright © Alliance Semiconductor 2575, Augustine Drive, All Rights Reserved Santa Clara, CA 95054 Part Number: AS7C33128NTD32B / Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 AS7C33128NTD36B Document Version: v.1.5 www.alsc.com © Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. 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Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.