NCV8186 Fast Transient Response Low Voltage 1 A LDO The NCV8186x series are CMOS LDO regulators featuring 1 A output current. The input voltage is as low as 1.8 V and the output voltage can be set from 1.2 V. www.onsemi.com Features • • • • • • • • • • • • Operating Input Voltage Range: 1.8 V to 5.5 V Output Voltage Range: 1.2 to 3.9 V Quiescent Current typ. 90 mA Low Dropout: 100 mV typ. at 1 A, VOUT = 3.0 V High Output Voltage Accuracy ±1% Stable with Small 1 mF Ceramic Capacitors Over−current Protection Built−in Soft Start Circuit to Suppress Inrush Current Thermal Shutdown Protection: 165°C With (NCV8186A) and Without (NCV8186B) Output Discharge Function Available in Small DFN8 2 x 2 mm Package These are Pb−free Devices Typical Applications • Battery Powered Equipment • Portable Communication Equipment • Cameras, Image Sensors and Camcorders VIN CIN 1 mF ON EN GND OUT 1 8 IN OUT 2 7 IN N/C 3 6 EN FB 4 5 GND MARKING DIAGRAM 1 XXMG G OUT NCV8186 PIN CONNECTIONS (Top View) VOUT IN 1 DFN8 MX SUFFIX CASE 506AA COUT 1 mF FB XX = Specific Device Code M = Date Code G = Pb−Free Package OFF Figure 1. Typical Application Schematic (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the ordering information section on page 9 of this data sheet. © Semiconductor Components Industries, LLC, 2016 June, 2016 − Rev. 0 1 Publication Order Number: NCV8186/D NCV8186 IN OUT VOLTAGE REFERENCE AND SOFT−START IN OUT VOLTAGE REFERENCE AND SOFT−START FB FB EN EN 0.7 V 0.7 V GND THERMAL SHUTDOWN GND THERMAL SHUTDOWN NCV8186A (with output discharge) NCV8186B (without output discharge) Figure 2. Internal Block Diagram Table 1. PIN FUNCTION DESCRIPTION Pin No. DFN8 Pin Name Description 1 OUT LDO output pin 3 N/C Not internally connected. This pin can be tied to the ground plane to improve thermal dissipation. 4 FB Feedback input pin 5 GND Ground pin 6 EN Chip enable input pin (active “H”) 7 IN Power supply input pin EPAD It’s recommended to connect the EPAD to GND, but leaving it open is also acceptable 2 8 EPAD Table 2. ABSOLUTE MAXIMUM RATINGS Rating Input Voltage (Note 1) Output Voltage Chip Enable Input Symbol Value Unit IN −0.3 to 6.0 V OUT −0.3 to VIN + 0.3 V EN −0.3 to 6.0 V IOUT Internally Limited mA TJ(MAX) 125 °C TSTG −55 to 150 °C ESD Capability, Human Body Model (Note 2) ESDHBM 2000 V ESD Capability, Machine Model (Note 2) ESDMM 200 V Output Current Maximum Junction Temperature Storage Temperature Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114) ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115) Latchup Current Maximum Rating tested per JEDEC standard: JESD78 Table 3. THERMAL CHARACTERISTICS Rating Thermal Resistance, Junction−to−Air, DFN8 2 mm x 2 mm www.onsemi.com 2 Symbol Value Unit RqJA 93 °C/W NCV8186 Table 4. ELECTRICAL CHARACTERISTICS VIN = VOUT_NOM + 0.5 V or VIN = 1.8 V whichever is greater; IOUT = 1 mA; CIN = COUT = 1.0 mF (effective capacitance) (Note 3); VEN = 1.2 V; TJ = 25°C; unless otherwise noted. The specifications in bold are guaranteed at −40°C ≤ TJ ≤ 125°C. Parameter Test Conditions Symbol Operating Input Voltage Output Voltage VOUT_NOM + 0.5 V ≤ VIN ≤ 5.5 V, IOUT = 0 to 1 A, −40°C ≤ TJ ≤ 85°C Min Typ Max Unit VIN 1.8 5.5 V VOUT −1.0 1.0 % −2.0 1.0 VOUT_NOM + 0.5 V ≤ VIN ≤ 5.5 V, IOUT = 0 to 1 A, −40°C ≤ TJ ≤ 125°C Load Regulation IOUT = 1 mA to 1000 mA LoadReg 0.7 5.0 mV Line Regulation VIN = VOUT_NOM + 0.5 V to 5.0 V LineReg 0.002 0.1 %/V Dropout Voltage IOUT = 1 A VDO 180 295 mV IQ 90 140 mA 0.1 1.5 mA VOUT_NOM = 1.75 V When VOUT falls to VOUT_NOM – 100 mV Quiescent Current IOUT = 0 mA Standby Current VEN = 0 V ISTBY Output Current Limit VOUT = 90% of VOUT_NOM IOCL 1100 1400 mA Output Short Circuit Current VOUT = 0 V IOSC 1100 1400 mA Enable Input Current Enable Threshold Voltage IEN 0.15 0.6 mA V EN Input Voltage “H” VENH 1.0 EN Input Voltage “L” VENL Power Supply Rejection Ratio VIN = VOUT_NOM + 1.0 V, Ripple 0.2 Vp−p, IOUT = 30 mA, f = 1 kHz PSRR 75 dB Output Noise f = 10 Hz to 100 kHz VN 48 mVRMS Output Discharge Resistance (NCV8186A option only) VIN = 5.5 V, VEN = 0 V, VOUT = 1.75 V RAD 34 W Thermal Shutdown Temperature Temperature rising from TJ = +25°C TSD 165 °C Thermal Shutdown Hysteresis Temperature falling from TSD TSDH 20 °C 0.4 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Effective capacitance, including the effect of DC bias, tolerance and temperature. See the Application Information section for more information. www.onsemi.com 3 NCV8186 TYPICAL CHARACTERISTICS VIN = VOUT−NOM + 0.5 V or VIN = 1.8 V whatever is greater, VEN = 1.2 V, IOUT = 1 mA, CIN = COUT = 1.0 mF, TJ = 25°C. 0.10 1.765 LINE REGULATION (%/V) OUTPUT VOLTAGE (V) 1.755 1.745 1.735 1.725 1.715 −40 VIN = VOUT−NOM + 0.5 V to 5.0 V VIN ≥ 1.8 V 0.08 −20 0 20 40 60 80 100 0.06 0.04 0.02 0 −0.02 −0.04 −0.06 −0.08 −0.10 −40 120 −20 0 20 40 60 80 120 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 3. Output Voltage vs. Temperature Figure 4. Line Regulation vs. Temperature 5 275 2 1 0 −1 −2 IOUT = 1 mA to 1000 mA −3 −4 −5 −40 −20 0 20 40 60 TJ = 25°C 200 175 150 125 TJ = −40°C 100 75 50 80 100 120 0 200 400 600 800 1000 TEMPERATURE (°C) OUTPUT CURRENT (mA) Figure 5. Load Regulation vs. Temperature Figure 6. Dropout Voltage vs. Output Current 450 IOUT = 1000 mA 250 200 175 150 IOUT = 500 mA 125 100 75 IOUT = 200 mA 50 IOUT = 10 mA TJ = 125°C TJ = 25°C 400 225 25 0 −40 TJ = 125°C 250 225 25 0 275 DROPOUT VOLTAGE (mV) DROPOUT VOLTAGE (mV) 3 GROUND CURRENT (mA) LOAD REGULATION (mV) 4 350 TJ = −40°C 300 250 200 150 100 50 0 −20 0 20 40 60 80 100 120 0 200 400 600 800 1000 TEMPERATURE (°C) OUTPUT CURRENT (mA) Figure 7. Dropout Voltage vs. Temperature Figure 8. Ground Current vs. Output Current www.onsemi.com 4 NCV8186 TYPICAL CHARACTERISTICS VIN = VOUT−NOM + 0.5 V or VIN = 1.8 V whatever is greater, VEN = 1.2 V, IOUT = 1 mA, CIN = COUT = 1.0 mF, TJ = 25°C. 120 QUIESCENT CURRENT (mA) QUIESCENT CURRENT (mA) 120 110 100 90 80 70 IOUT = 0 mA 60 −40 −20 100 TJ = −40°C 90 80 70 IOUT = 0 mA 60 20 40 60 80 100 120 2.0 2.5 3.5 3.0 4.0 4.5 5.0 5.5 TEMPERATURE (°C) INPUT VOLTAGE (V) Figure 9. Quiescent Current vs. Temperature Figure 10. Quiescent Current vs. Input Voltage 2.0 VEN = 0 V SHORT CIRCUIT CURRENT (A) 0.9 STANDBY CURRENT (mA) 110 50 0 1.0 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 −40 −20 0 20 40 60 80 100 120 1.8 1.7 1.6 1.5 1.4 1.3 1.2 VOUT−FORCED = 0 V −20 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 11. Standby Current vs. Temperature Figure 12. Short Circuit Current vs. Temperature ENABLE THRESHOLD VOLTAGE (V) 1.9 1.8 1.7 1.6 1.5 1.4 1.3 VOUT−FORCED = 90% of VOUT−NOM 1.2 1.1 −40 1.9 1.1 −40 2.0 OUTPUT CURRENT LIMIT (A) TJ = 125°C TJ = 25°C −20 0 20 40 60 80 100 120 1.0 0.9 OFF −> ON 0.8 ON −> OFF 0.7 0.6 0.5 0.4 −40 −20 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 13. Output Current Limit vs. Temperature Figure 14. Enable Threshold Voltage vs. Temperature www.onsemi.com 5 120 120 NCV8186 TYPICAL CHARACTERISTICS VIN = VOUT−NOM + 0.5 V or VIN = 1.8 V whatever is greater, VEN = 1.2 V, IOUT = 1 mA, CIN = COUT = 1.0 mF, TJ = 25°C. 90 80 0.5 70 0.4 PSRR (dB) 0.3 0.2 50 40 COUT = 1 mF X7R 0805 IOUT = 30 mA 30 20 0.1 VOUT−NOM = 1.75 V, VIN = 2.75 V 10 0 −40 0 −20 0 20 40 60 80 100 120 10 100 1K 10K 100K 1M TEMPERATURE (°C) FREQUENCY (Hz) Figure 15. Enable Input Current vs. Temperature Figure 16. Power Supply Rejection Ratio 6 5 50 mA/div COUT = 1 mF X7R 0805 Integral Noise: 10 Hz − 100 kHz: 48 uVrms 10 Hz − 1 MHz: 62 uVrms 4 10M IIN VIN 3 VOUT−NOM = 1.75 V, VIN = 2.75 V 2 1 V/div VOUT 1 0 10 100 1K 10K 100K 1M 1 ms/div FREQUENCY (Hz) Figure 18. Turn−ON/OFF − VIN Driven (slow) 1 V/div 100 mA/div Figure 17. Output Voltage Noise Spectral Density IIN Device without output discharge VEN VOUT VIN VOUT 50 mA/div 1 V/div OUTPUT VOLTAGE NOISE (nV/√Hz) 60 500 mV/div ENABLE INPUT CURRENT (mA) 0.6 IIN 50 ms/div 200 ms/div Figure 19. Turn−ON − VIN Driven (fast) Figure 20. Turn−ON/OFF − EN Driven www.onsemi.com 6 NCV8186 TYPICAL CHARACTERISTICS 1 V/div tR = tF = 1 ms 1000 mA tR = tF = 1 ms IOUT 1 mA 50 mV/div VIN 2.3 V VIN 500 mA/div 3.3 V VOUT 1.75 V VOUT 1.75 V 10 ms/div 10 ms/div Figure 21. Line Transient Response Figure 22. Load Transient Response 1.8 PD(MAX), 2 oz Cu 280 260 240 1.6 PD(MAX), 1 oz Cu 1.4 220 1.2 200 180 160 1.0 140 0.6 0.8 120 qJA, 1 oz Cu 100 80 60 qJA, 2 oz Cu 0 100 200 300 400 500 PCB COPPER AREA (mm2) Figure 23. qJA and PD(MAX) vs. Copper Area www.onsemi.com 7 600 0.4 0.2 0 PD(MAX), MAXIMUM POWER DISSIPATION (W) 300 qJA, JUNCTION TO AMBIENT THERMAL RESISTANCE (°C/W) 10 mV/div 500 mV/div VIN = VOUT−NOM + 0.5 V or VIN = 1.8 V whatever is greater, VEN = 1.2 V, IOUT = 1 mA, CIN = COUT = 1.0 mF, TJ = 25°C. NCV8186 APPLICATIONS INFORMATION General Enable Operation The NCV8186 is a high performance 1 A low dropout linear regulator (LDO) delivering excellent noise and dynamic performance. Thanks to its adaptive ground current behavior the device consumes only 90 mA typ. of quiescent current (no−load condition). The regulator features low noise of 48 mVRMS, PSRR of 75 dB at 1 kHz and very good line/load transient performance. Such excellent dynamic parameters, small dropout voltage and small package size make the device an ideal choice for powering the precision noise sensitive circuitry in portable applications. A logic EN input provides ON/OFF control of the output voltage. When the EN is low the device consumes as low as 100 nA typ. from the IN pin. The device is fully protected in case of output overload, output short circuit condition or overheating, assuring a very robust design. The LDO uses the EN pin to enable/disable its operation and to deactivate/activate the output discharge function (A−version only). If the EN pin voltage is < 0.4 V the device is disabled and the pass transistor is turned off so there is no current flow between the IN and OUT pins. On A−version the active discharge transistor is active so the output voltage is pulled to GND through 34 W (typ.) resistor. If the EN pin voltage is > 1.0 V the device is enabled and regulates the output voltage. The active discharge transistor is turned off. The EN pin has internal pull−down current source with value of 150 nA typ. which assures the device is turned off when the EN pin is unconnected. In case when the EN function isn’t required the EN pin should be tied directly to IN pin. Output Current Limit Output current is internally limited to a 1.4 A typ. The LDO will source this current when the output voltage drops down from the nominal output voltage (test condition is 90% of VOUT−NOM). If the output voltage is shorted to ground, the short circuit protection will limit the output current to 1.4 A typ. The current limit and short circuit protection will work properly over the whole temperature and input voltage ranges. There is no limitation for the short circuit duration. Input Capacitor Selection (CIN) Input capacitor connected as close as possible is necessary to ensure device stability. The X7R or X5R capacitor should be used for reliable performance over temperature range. The value of the input capacitor should be 1 mF or greater for the best dynamic performance. This capacitor will provide a low impedance path for unwanted AC signals or noise modulated onto the input voltage. There is no requirement for the ESR of the input capacitor but it is recommended to use ceramic capacitor for its low ESR and ESL. A good input capacitor will limit the influence of input trace inductance and source resistance during load current changes. Thermal Shutdown When the LDO’s die temperature exceeds the thermal shutdown threshold value the device is internally disabled. The IC will remain in this state until the die temperature decreases by value called thermal shutdown hysteresis. Once the IC temperature falls this way the LDO is back enabled. The thermal shutdown feature provides the protection against overheating due to some application failure and it is not intended to be used as a normal working function. Output Capacitor Selection (COUT) The LDO requires an output capacitor connected as close as possible to the output and ground pins. The recommended capacitor value is 1 mF, ceramic X7R or X5R type due to its low capacitance variations over the specified temperature range. The LDO is designed to remain stable with minimum effective capacitance of 0.8 mF. When selecting the capacitor the changes with temperature, DC bias and package size needs to be taken into account. Especially for small package size capacitors such as 0201 the effective capacitance drops rapidly with the applied DC bias voltage (refer the capacitor’s datasheet for details). There is no requirement for the minimum value of equivalent series resistance (ESR) for the COUT but the maximum value of ESR should be less than 0.5 W. Larger capacitance and lower ESR improves the load transient response and high frequency PSRR. Only ceramic capacitors are recommended, the other types like tantalum capacitors not due to their large ESR. Power Dissipation Power dissipation caused by voltage drop across the LDO and by the output current flowing through the device needs to be dissipated out from the chip. The maximum power dissipation is dependent on the PCB layout, number of used Cu layers, Cu layers thickness and the ambient temperature. The maximum power dissipation can be computed by following equation: P D(MAX) + TJ * TA [W] q JA (eq. 1) Where (TJ − TA) is the temperature difference between the junction and ambient temperatures and θJA is the thermal resistance (dependent on the PCB as mentioned above). www.onsemi.com 8 NCV8186 The power dissipated by the LDO for given application conditions can be calculated by the next equation: P D + V IN @ I GND ) ǒV IN * V OUTǓ @ I OUT [W] 100 kHz) can be tuned by the selection of COUT capacitor and proper PCB layout. A simple LC filter could be added to the LDO’s IN pin for further PSRR improvement. (eq. 2) Enable Turn−On Time Where IGND is the LDO’s ground current, dependent on the output load current. Connecting the exposed pad and N/C pin to a large ground planes helps to dissipate the heat from the chip. The relation of θJA and PD(MAX) to PCB copper area and Cu layer thickness could be seen on the Figure 23. The enable turn−on time is defined as the time from EN assertion to the point in which VOUT will reach 98% of its nominal value. This time is dependent on various application conditions such as VOUT−NOM, COUT and TA. PCB Layout Recommendations To obtain good transient performance and good regulation characteristics place CIN and COUT capacitors as close as possible to the device pins and make the PCB traces wide. In order to minimize the solution size, use 0402 or 0201 capacitors size with appropriate effective capacitance. Larger copper area connected to the pins will also improve the device thermal resistance. The actual power dissipation can be calculated from the equation above (Power Dissipation section). Exposed pad and N/C pin should be tied to the ground plane for good power dissipation. Reverse Current The PMOS pass transistor has an inherent body diode which will be forward biased in the case when VOUT > VIN. Due to this fact in cases, where the extended reverse current condition can be anticipated the device may require additional external protection. Power Supply Rejection Ratio The LDO features very high power supply rejection ratio. The PSRR at higher frequencies (in the range above ORDERING INFORMATION TABLE Part Number Voltage Option Marking Option Package Shipping NCV8186BMN175TAG 1.75 V GA Without active discharge DFN8 (Pb−Free) 3000 / Tape & Reel www.onsemi.com 9 NCV8186 PACKAGE DIMENSIONS DFN8 2x2, 0.5P CASE 506AA ISSUE E D PIN ONE REFERENCE 0.10 C 2X ÇÇ ÇÇ ÇÇ 0.10 C 2X A B 0.10 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L L1 DETAIL A E OPTIONAL CONSTRUCTIONS ÉÉÉ ÉÉÉ EXPOSED Cu TOP VIEW A DETAIL B DIM A A1 A3 b D D2 E E2 e K L L1 MOLD CMPD DETAIL B OPTIONAL CONSTRUCTION 0.08 C (A3) NOTE 4 A1 C SIDE VIEW SEATING PLANE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.70 0.90 0.50 BSC 0.30 REF 0.25 0.35 −−− 0.10 RECOMMENDED SOLDERING FOOTPRINT* DETAIL A 8X D2 1 8X 1.30 L PACKAGE OUTLINE 4 E2 K 8 5 8X e/2 e 0.50 0.90 b 2.30 1 0.10 C A B 0.05 C 8X 0.30 NOTE 3 BOTTOM VIEW 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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