ON MC100LVEL90DWG −3.3v / −5v triple ecl input to lvpecl output translator Datasheet

MC100LVEL90
−3.3V / −5VTriple ECL Input
to LVPECL Output Translator
Description
The MC100LVEL90 is a triple ECL to LVPECL translator. The device
receives either −3.3 V or −5 V differential ECL signals, determined by the
VEE supply level, and translates them to +3.3 V differential LVPECL
output signals.
To accomplish the level translation, the LVEL90 requires three power
rails. The VCC supply should be connected to the positive supply, and the
VEE pin should be connected to the negative power supply. The GND
pins, as expected, are connected to the system ground plane. Both VEE
and VCC should be bypassed to ground via 0.01 mF capacitors.
Under open input conditions, the D input will be biased at VEE/2 and
the D input will be pulled to VEE. This condition will force the Q output
to a LOW, ensuring stability.
The VBB pin, an internally generated voltage supply, is available to this
device only. For single-ended input conditions, the unused differential
input is connected to VBB as a switching reference voltage. VBB may also
rebias AC coupled inputs. When used, decouple VBB and VCC via a
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When
not used, VBB should be left open.
Features
•
•
•
•
SO−20 WB
DW SUFFIX
CASE 751D
MARKING DIAGRAM*
20
500 ps Propagation Delays
ESD Protection: >2 kV HBM, >200 V MM
100LVEL90
AWLYYWWG
The 100 Series Contains Temperature Compensation
Operating Range: VCC = 3.0 V to 3.8 V;
VEE = −3.0 V to −5.5 V; GND = 0 V
Internal Input Pulldown Resistors
•
• Q Output will Default LOW with Inputs Open or at VEE
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity;
•
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Pb Pkg
Level 1,
Pb−Free Pkg
Level 3
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 261 devices
•
• Pb−Free Packages are Available*
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 11
1
Publication Order Number:
MC100LVEL90/D
MC100LVEL90
VCC
Q0
Q0
GND Q1
Q1 GND
20
19
18
17
15
LVPECL
16
LVPECL
2
3
D0
D0
13
12
11
ECL
4
5
6
D1
D1
7
8
9
10
ECL VBB
1
VCC
14
ECL
VCC
Q2
LVPECL
ECL VBB
ECL
Q2
D2
D2
VEE
Table 1. PIN DESCRIPTION
PIN
FUNCTION
Dn, Dn
Qn, Qn
ECL VBB
VCC
VEE
GND
ECL Inputs
LVPECL Outputs
ECL Reference Voltage Output
Positive Supply
Negative Supply
Ground
* All VCC pins are tied together on the die.
Warning: All VCC, VEE, and GND pins must be externally
connected to Power Supply to guarantee proper operation.
Figure 1. Logic Diagram and Pinout: 20-Lead SOIC (Top View)
Table 2. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Power Supply
GND = 0 V
8 to 0
V
VEE
NECL Power Supply
GND = 0 V
−8 to 0
V
VI
NECL Mode Input Voltage
GND = 0 V
−6 to 0
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
ECL VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
20 SOIC
20 SOIC
90
60
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
20 SOIC
30 to 35
°C/W
Tsol
Wave Solder
265
°C
VI w VEE
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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2
MC100LVEL90
Table 3. NECL INPUT DC CHARACTERISTICS VCC= 3.3 V; VEE= −3.3 V; GND= 0 V (Note 1)
−40°C
Symbol
Min
Characteristic
25°C
Typ
Max
Min
Max
6.0
8.0
Min
Typ
Max
Unit
8.0
mA
IEE
VEE Power Supply Current
VIH
Input HIGH Voltage (Single−Ended)
−1165
−880
−1165
−880
−1165
−880
mV
VIL
Input LOW Voltage (Single−Ended)
−1810
−1475
−1810
−1475
−1810
−1475
mV
ECL VBB
Output Voltage Reference
−1.38
−1.26
−1.38
−1.26
−1.38
−1.26
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 2)
Vpp < 500 mV
Vpp y 500 mV
VEE+1.3
VEE+1.5
−0.4
−0.4
VEE+1.2
VEE+1.4
−0.4
−0.4
VEE+1.2
VEE+1.4
−0.4
−0.4
V
V
150
mA
IIH
Input HIGH Current
IIL
Input LOW Current
8.0
85°C
Typ
150
D
D
0.5
−600
150
0.5
−600
0.5
−600
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input parameters vary 1:1 with GND. VEE can vary −3.0 V to −5.5 V.
2. VIHCMR min varies 1:1 with VEE. VIHCMR max varies 1:1 with GND.
Table 4. LVPECL OUTPUT DC CHARACTERISTICS VCC= 3.3 V; VEE= −3.3 V; GND= 0 V (Note 3)
−40°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
24
85°C
Typ
Max
20
24
Min
Typ
Max
Unit
26
mA
ICC
VCC Power Supply Current
VOH
Output HIGH Voltage (Note 4)
2215
2295
2420
2275
2345
2420
2275
2345
2420
mV
VOL
Output LOW Voltage (Note 4)
1470
1605
1745
1490
1600
1680
1490
1595
1680
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Output parameters vary 1:1 with VCC. VCC can vary +0.5 V / −0.3 V. VEE can vary −3.0 V to −5.5 V.
4. Outputs are terminated through a 50 W resistor to VCC−2 volts.
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3
MC100LVEL90
Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.8 V; VEE= −3.0 V to −5.5 V; GND = 0 V
−40°C
Symbol
Min
Characteristic
fmax
Maximum Toggle Frequency
tPLH
tPHL
Propagation Delay
D to Q
tSKEW
Skew
Typ
25°C
Max
Min
560
Diff
S.E.
390
340
Output−to−Output (Note 5)
Part−to−Part (Diff) (Note 5)
Duty Cycle (Diff) (Note 6)
25
tJITTER
Random Clock Jitter
VPP
Input Voltage Swing (Differential Configuration)
(Note 7)
tr
tf
Output Rise/Fall Times Q
420
370
100
200
Min
25
Typ
Max
700
620
670
20
TBD
(20% − 80%)
85°C
Max
650
590
640
20
Typ
460
410
100
200
20
25
TBD
Unit
MHz
660
710
ps
100
200
ps
TBD
ps
150
1000
150
1000
150
1000
230
500
230
500
230
500
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Skews are valid across specified voltage range, part−to−part skew is for a given temperature.
6. Duty cycle skew is the difference between a TPLH and TPHL propagation delay through a device.
7. VPP(min) is swing measured single−ended on each input in differential configuration. The device has a DC gain of ≈40.
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 2. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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4
MC100LVEL90
ORDERING INFORMATION
Package
Package†
MC100LVEL90DW
SOIC−20
38 Units / Rail
MC100LVEL90DWG
SOIC−20
(Pb−Free)
38 Units / Rail
MC100LVEL90DWR2
SOIC−20
1000 / Tape & Reel
MC100LVEL90DWR2G
SOIC−20
(Pb−Free)
1000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPS I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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5
MC100LVEL90
PACKAGE DIMENSIONS
SO−20 WB
DW SUFFIX
CASE 751D−05
ISSUE G
A
20
q
X 45 _
E
h
H
M
10X
0.25
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
1
10
20X
B
B
0.25
M
T A
S
B
S
L
A
18X
e
A1
SEATING
PLANE
C
T
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
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