FEDL610409-08 Issue Date:May. 23, 2014 ML610407/ML610408/ML610409 8-bit Microcontroller with a Built-in LCD driver GENERAL DESCRIPTION ML610407/ML610408/ML610409 is a high performance CMOS 8-bit microcontroller into which peripheral circuits, such as the synchronous serial port, UART, melody driver, RC oscillation type A/D converter, and LCD driver, are incorporated around LAPIS Semiconductor-original 8-bit CPU nX-U8/100. ML610407/ML610408/ML610409 operates in both high/low-speed mode and power-saving mode, it is most suitable for battery operated products. For industrial use, ML610407P/ML610408P/ML610409P with the extended operating ambient temperature ranging from -40°C to 85°C are available. FEATURES • CPU - 8-bit RISC CPU (CPU name: nX-U8/100) - Instruction system: 16-bit length instruction - Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on - On-Chip debug function - Minimum instruction execution time 30.5 µs (@ 32.768 kHz system clock) 2 µs (@ 500 kHz system clock) 0.5 µs (@ 2 MHz system clock) • Internal memory - Internal 16KByte maskROM (8K x 16 bits) (including unusable 1KByte TEST area) - Internal 1KByte RAM (1024 x 8 bits) • Interrupt controller - 1 non-maskable interrupt source: Internal source: 1 (Watchdog Timer) - 27 maskable interrupt sources: Internal source: 14 (Synchronous serial port 0, Synchronous serial port 1, Timer 0, Timer 1, Timer 2, Timer 3, UART0, Melody 0, RC Oscillation type A/D converter, PWM0, TBC128Hz, TBC32Hz, TBC16Hz, TBC2Hz) External source: 13 (P00, P01, P02, P03, P04, P50, P51, P52, P53, P54, P55, P56, P57) * *: For P50 to P57, the interrupt sources are ORed into a single interrupt request. • Time base counter - Low-speed time base counter x 1 channel Frequency compensation (Compensation range: Approx. -488ppm to +488ppm. Compensation accuracy: Approx. 0.48ppm) - High-speed time base counter x 1 channel • Watchdog timer - Non-maskable interrupt and reset - Free running - Overflow period: 4 types selectable (125ms, 500ms, 2s, 8s) • Timers - 8 bits x 4 channels [also available is 16-bit configuration (using Timers 0 and 1, or Timers 2 and 3) x 2 channels] - Clock frequency measurement function mode (16-bit configuration using Timers 2 and 3 x 1 channel only) 1/34 FEDL610409-08 ML610407/ML610408/ML610409 • Capture - Time base capture x 2 channels (4096 Hz to 32 Hz) • PWM - Resolution 16 bits x 1 channel • Synchronous serial port - Master/slave selectable x 2 channels - LSB first/MSB first selectable - 8-bit length/16-bit length selectable • UART - TXD/RXD × 1 channel - Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits - Positive logic/negative logic selectable - Built-in baud rate generator • Melody driver - Scale: 29 types (Melody sound frequency: 508 Hz to 32.768 kHz) - Tone length: 63 types - Tempo: 15 types - Buzzer output mode (4 output modes, 8 frequencies, 16 duty levels) • RC oscillation type A/D converter - 16-bit counter - Time division x 2 channels • General-purpose ports - Input-only port: 5 channels (including secondary functions) - Output-only port ML610407: 12 channels (including secondary functions) ML610408: 8 channels (including secondary functions) ML610409: 4 channels (including secondary functions) - Input/output port: 22 channels (including secondary functions) • LCD driver - Number of segments ML610407: Up to 145 dots (select among 29 segments x 5 commons, 30 segments x 4 commons, 31 segments x 3 commons, and 32 segments x 2 commons) ML610408: Up to 165 dots (select among 33 segments x 5 commons, 34 segments x 4 commons, 35 segments x 3 commons, and 36 segments x 2 commons) ML610409: Up to 185 dots (select among 37 segments x 5 commons, 38 segments x 4 commons, 39 segments x 3 commons, and 40 segments x 2 commons) - 1/1 to 1/5 duty - 1/3 bias (built-in bias generation circuit) - Frame frequency selectable (approx. 64 Hz, 73 Hz, 85 Hz, and 102 Hz) - Bias voltage multiplying clock selectable (8 types) - LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable - Programmable display allocation function • Reset - Reset through the RESET_N pin - Power-on reset generation when powered on - Reset when oscillation stop of the low-speed clock is detected (Cancellation by a mask option is possible) - Reset by the watchdog timer (WDT) overflow 2/34 FEDL610409-08 ML610407/ML610408/ML610409 •Clock - Low-speed clock (Operation of this LSI is not guaranteed under a condition with no supply of low-speed crystal oscillation clock) Crystal oscillation (32.768 kHz) - High-speed clock Built-in RC oscillation (500 kHz/2 MHz selectable by software) • Power management - HALT mode: Suspends the instruction execution by CPU (peripheral circuits are in operating states) - STOP mode: Stops the low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are stopped.) - High-speed clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock) - Block control function: Completely stops the operation of any function block circuit that is not used (resets registers and stops clock) • Guaranteed Operation Range − Operating temperature: -20°C to +70°C (P version: -40°C to +85°C) − Operating voltage: VDD = 1.25V to 3.6V 3/34 FEDL610409-08 ML610407/ML610408/ML610409 • Product name – Supported Function - Chip (Die) - LCD bias Operating temperature Product availability -20°C to +70°C Yes -20°C to +70°C Yes Cancellation by a mask option is possible -20°C to +70°C Yes Yes Cancellation by a mask option is possible -40°C to +85°C Yes - Yes Cancellation by a mask option is possible -40°C to +85°C Yes - Yes Cancellation by a mask option is possible -40°C to +85°C Yes 1/2 1/3 ML610407-ｘｘｘWA - Yes ML610408-ｘｘｘWA - Yes ML610409-ｘｘｘWA - Yes ML610407P-ｘｘｘWA - ML610408P-ｘｘｘWA ML610409P-ｘｘｘWA -100-pin plastic TQFP - Low-speed oscillation stop detect reset Cancellation by a mask option is possible Cancellation by a mask option is possible LCD bias 1/2 1/3 ML610407-ｘｘｘTB - Yes ML610408-ｘｘｘTB - Yes Low-speed oscillation stop detect reset Cancellation by a mask option is possible Cancellation by a mask option is possible Operating temperature Product availability -20°C to +70°C - -20°C to +70°C - -20°C to +70°C - - ML610409-ｘｘｘTB - Yes Cancellation by a mask option is possible ML610407P-ｘｘｘTB - Yes Cancellation by a mask option is possible -40°C to +85°C ML610408P-ｘｘｘTB - Yes Cancellation by a mask option is possible -40°C to +85°C ML610409P-ｘｘｘTB - Yes Cancellation by a mask option is possible -40°C to +85°C - xxx: ROM code number (xxx of the blank product is NNN) P: Wide range temperature version (P version) WA: Chip (Die) TB: TQFP 4/34 FEDL610409-08 ML610407/ML610408/ML610409 BLOCK DIAGRAM ML610407/ML610408/ML610409 Block Diagram CPU (nX-U8/100) EPSW1-3 GREG 0-15 PSW Timing Controller On-Chip ICE ALU Instruction Decoder LR DSR/CSR EA PC Instruction Register Data-bus Program Memory (maskROM) 16Kbyte BUS Controller INT 2 RAM 1Kbyte RESET & TEST SSIO x2 Interrupt Controller XT0** XT1** INT 1 OSC LSCLK* OUTCLK* INT 4 WDT TBC INT 1 RC-ADC x2 INT 4 SCK1* SIN1* SOUT1* UART RXD0* TXD0* PWM PWM0* INT 1 INT 1 Capture x2 SCK0* SIN0* SOUT0* INT 1 Power VDDL IN0* CS0* RS0* RT0* RCT0* RCM* IN1* CS1* RS1* RT1* ECSR1-3 SP VDD VSS RESET_N TEST0 ELR1-3 Melody/ Buzzer INT 6 8bit Timer x4 Display Allocation RAM Display register 320bit GPIO LCD Driver LCD BIAS MD0* P00 to P04 P20 to P22, P24 P30 to P35 P40 to P47 P50 to P53 P60 to P67 (ML610407) P60 to P63 (ML610408) COM0 to COM4 (*1)(*2)(*3) SEG0 to SEG31 (ML610407) (*1) SEG0 to SEG35 (ML610408) (*2) SEG0 to SEG39 (ML610409) (*3) VL1, VL2, VL3 C1, C2 * Secondary function or Tertiary function “*1”: Select among 29 segments x 5 commons, 30 segments x 4 commons, 31 segments x 3 commons, and 32 segments x 2 commons with the register “*2”: Select among 33 segments x 5 commons, 34 segments x 4 commons, 35 segments x 3 commons, and 36 segments x 2 commons with the register “*3”: Select among 37 segments x 5 commons, 38 segments x 4 commons, 39 segments x 3 commons, and 40 segments x 2 commons with the register Figure 1 ML610413P Block Diagram 5/34 FEDL610409-08 ML610407/ML610408/ML610409 CHIP PAD LAYOUT 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 P60 P61 P62 P63 P64 P65 P66 P67 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 ML610407 Chip Pad Layout & Dimension 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 XT1 RESET_N TEST0 VL1 VL2 VL3 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P52 P51 P50 P40 P41 P42 P43 P44 P45 P46 P47 VDD VSS VDDL XT0 VSS P20 P21 P22 P24 P00 P01 P02 P03 P04 P30 P31 P34 P32 P33 P35 P57 P56 P55 P54 P53 2.26mm SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 2.17mm SEG6 SEG5 SEG4 SEG3 COM4/SEG2 COM3/SEG1 COM2/SEG0 COM1 COM0 C2 C1 Y X Note: The assignment of the pads P30 to P35 are not in order. Chip size: 2.26 mm × 2.17 mm PAD count: 86 pins Minimum PAD pitch: 80µm PAD aperture: 70µm×70µm Chip thickness: 350µm Voltage of the rear side of chip: VSS level. Figure 2 ML610407 Chip Pin Layout & Dimension 6/34 FEDL610409-08 ML610407/ML610408/ML610409 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 P60 P61 P62 P63 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 ML610408 Chip Pad Layout & Dimension 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 XT1 RESET_N TEST0 VL1 VL2 VL3 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P52 P51 P50 P40 P41 P42 P43 P44 P45 P46 P47 VDD VSS VDDL XT0 VSS P20 P21 P22 P24 P00 P01 P02 P03 P04 P30 P31 P34 P32 P33 P35 P57 P56 P55 P54 P53 2.26mm SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 2.17mm SEG6 SEG5 SEG4 SEG3 COM4/SEG2 COM3/SEG1 COM2/SEG0 COM1 COM0 C2 C1 Y X Note: The assignment of the pads P30 to P35 are not in order. Chip size: 2.26 mm × 2.17 mm PAD count: 86 pins Minimum PAD pitch: 80µm PAD aperture: 70µm×70µm Chip thickness: 350µm Voltage of the rear side of chip: VSS level. Figure 3 ML610408 Chip Pin Layout & Dimension 7/34 FEDL610409-08 ML610407/ML610408/ML610409 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 ML610409 Chip Pad Layout & Dimension 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 XT1 RESET_N TEST0 VL1 VL2 VL3 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P52 P51 P50 P40 P41 P42 P43 P44 P45 P46 P47 VDD VSS VDDL XT0 VSS P20 P21 P22 P24 P00 P01 P02 P03 P04 P30 P31 P34 P32 P33 P35 P57 P56 P55 P54 P53 2.26mm SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 2.17mm SEG6 SEG5 SEG4 SEG3 COM4/SEG2 COM3/SEG1 COM2/SEG0 COM1 COM0 C2 C1 Y X Note: The assignment of the pads P30 to P35 are not in order. Chip size: 2.26 mm × 2.17 mm PAD count: 86 pins Minimum PAD pitch: 80µm PAD aperture: 70µm×70µm Chip thickness: 350µm Voltage of the rear side of chip: VSS level. Figure 4 ML610409 Chip Pin Layout & Dimension 8/34 FEDL610409-08 ML610407/ML610408/ML610409 PAD COORDINATES ML610407/ML610408/ML610409 Pad Coordinates Table 1 ML610407/ML610408/ML610409 Pad Coordinates PAD No. Pad Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 P52 P51 P50 P40 P41 P42 P43 P44 P45 P46 P47 VDD VSS VDDL XT0 XT1 RESET_N TEST0 VL1 VL2 VL3 C1 C2 COM0 COM1 COM2/SEG0 COM3/SEG1 COM4/SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 (*1) ML610407/8/9 X (µm) Y (µm) -853 -773 -693 -613 -533 -453 -373 -293 -213 -133 -53 27 107 187 267 427 507 587 667 747 827 1024 1024 1024 1024 1024 1024 1024 1024 1024 1024 1024 1024 1024 1024 1024 1024 1024 1024 1024 1024 1024 1024 840 760 680 600 -979 -979 -979 -979 -979 -979 -979 -979 -979 -979 -979 -979 -979 -979 -979 -979 -979 -979 -979 -979 -979 -845 -765 -685 -605 -525 -445 -365 -285 -205 -125 -45 35 115 195 275 355 435 515 595 675 755 835 979 979 979 979 PAD No. Pad Name 48 49 50 51 52 53 54 55 56 57 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 (*1) P67 (*2)(*3) SEG32 (*1) P66 (*2)(*3) SEG33 (*1) P65 (*2)(*3) SEG34 (*1) P64 (*2)(*3) SEG35 (*1)(*2) P63 (*3) SEG36 (*1)(*2) P62 (*3) SEG37 (*1)(*2) P61 (*3) SEG38 (*1)(*2) P60 (*3) SEG39 VSS P20 P21 P22 P24 P00 P01 P02 P03 P04 P30 P31 P34 P32 P33 P35 P57 P56 P55 P54 P53 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 Chip Center: X=0,Y=0 ML610407/8/9 X (µm) Y (µm) 520 979 440 979 360 979 280 979 200 979 120 979 40 979 -40 979 -120 979 -200 979 -295 979 -375 979 -455 979 -535 979 -615 979 -695 979 -775 979 -855 979 -1024 -1024 -1024 -1024 -1024 -1024 -1024 -1024 -1024 -1024 -1024 -1024 -1024 -1024 -1024 -1024 -1024 -1024 -1024 -1024 -1024 842 762 682 602 522 422 342 262 182 102 22 -58 -138 -218 -298 -378 -458 -538 -618 -698 -778 Pad for ML610407 . (*2) Pad for ML610408. (*3) Pad for ML610409. 9/34 FEDL610409-08 ML610407/ML610408/ML610409 PIN LIST Primary function PIN No. PAD No. Pin name I/O Function 14,77 13 13,66 12 Vss VDD ⎯ ⎯ 15 14 VDDL ⎯ 22 19 VL1 ⎯ 23 20 VL2 ⎯ 24 21 VL3 ⎯ 27 22 C1 ⎯ 28 23 C2 ⎯ 20 19 17 18 18 17 15 16 TEST0 RESET_N XT0 XT1 I/O I I O 82 71 P00/EXI0/ CAP0 I 83 72 P01/EXI1/ CAP1 I 84 73 P02/EXI2/ RXD0 I 85 74 P03/EXI3 I 86 75 P04/EXI4/ T02P0CK I 78 79 80 81 67 68 69 70 P20/LED0 P21/LED1 P22/LED2 P24/LED4 O O O O Negative power supply pin Positive power supply pin Power supply pin for internal logic (internally generated) Power supply pin for LCD bias (internally generated or connected to positive power supply pin)(*2) Power supply pin for LCD bias (internally generated or connected to positive power supply pin)(*2) Power supply pin for LCD bias (internally generated) Capacitor connection pin for LCD bias generation Capacitor connection pin for LCD bias generation Test pin Reset input pin Low-speed clock oscillation pin Low-speed clock oscillation pin Input port, External interrupt, Capture 0 input Input port, External interrupt, Capture 1 input Input port, External interrupt, UART0 received data Input port, External interrupt Input port, Timer 0/Timer 2/PWM0 external clock input External interrupt Output port Output port Output port Output port 87 76 P30 I/O 88 77 P31 89 78 90 Secondary function or Tertiary function Secondary/ Tertiary ⎯ ⎯ Pin name I/O Function ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Secondary Secondary Secondary Secondary LSCLK OUTCLK MD0 PWM0 O O O O Input/output port Secondary IN0 I I/O Input/output port Secondary CS0 O P34 I/O Input/output port Secondary RCT0 O 79 P32 I/O Input/output port Secondary RS0 O 91 80 P33 I/O Input/output port Secondary RT0 O 92 81 P35 I/O Input/output port Secondary RCM O Low-speed clock output High-speed clock output Melody 0 output PWM0 output RC type ADC0 oscillation input pin RC type ADC0 reference capacitor connection pin RC type ADC0 resistor/capacitor sensor connection pin RC type ADC0 reference resistor connection pin RC type ADC0 measurement resistor sensor connection pin RC type ADC oscillation monitor 10/34 FEDL610409-08 ML610407/ML610408/ML610409 Primary function PIN No. PAD No. Pin name I/O 5 4 P40 I/O Input/output port 6 5 P41 I/O Input/output port 7 6 P42 I/O Input/output port 8 7 P43 I/O Input/output port 9 8 P44/ T02P0CK I/O Input/output port, Timer 0/Timer 2/PWM0 external clock input I/O Input/output port, Timer 1/Timer 3 external clock input 10 11 12 9 10 11 P45/T13CK P46 P47 I/O Function Input/output port Secondary function or Tertiary function Secondary /Tertiary Secondary Tertiary Secondary Pin name I/O Function ⎯ SIN0 ⎯ ⎯ I ⎯ Tertiary SCK0 I/O Secondary Tertiary Secondary Tertiary RXD0 SOUT0 TXD0 PWM0 I O O O Secondary IN1 I Tertiary SIN0 I Secondary CS1 O ⎯ SSIO0 data input ⎯ SSIO0 synchronous clock input/output UART data input SSIO0 data output UART data output PWM0 output RC type ADC1 oscillation input pin SSIO0 data input RC type ADC1 reference capacitor connection pin Tertiary SCK0 I/O Secondary RS1 O Tertiary SOUT0 O I/O Input/output port Secondary RT1 O Secondary Tertiary Secondary MD0 SIN1 ⎯ O I ⎯ Tertiary SCK1 I/O Secondary Tertiary ⎯ SOUT1 ⎯ O ⎯ ⎯ ⎯ Secondary Tertiary Secondary ⎯ SIN1 ⎯ ⎯ I ⎯ Tertiary SCK1 I/O Secondary Tertiary ⎯ SOUT1 ⎯ O ⎯ ⎯ ⎯ 4 3 P50/EXI8 I/O Input/output port, External interrupt 3 2 P51/EXI8 I/O Input/output port, External interrupt 2 1 P52/EXI8 I/O 97 86 P53/EXI8 I/O 96 85 P54/EXI8 I/O 95 84 P55/EXI8 I/O 94 83 P56/EXI8 I/O 93 82 P57/EXI8 I/O Input/output port, External interrupt Input/output port, External interrupt Input/output port, External interrupt Input/output port, External interrupt Input/output port, External interrupt Input/output port, External interrupt SSIO0 synchronous clock input/output RC type ADC1 reference resistor connection pin SSIO0 data output RC type ADC1 measurement resistor sensor connection pin Melody 0 output SSIO1 data input ⎯ SSIO1 synchronous clock input/output ⎯ SSIO1 data output ⎯ ⎯ SSIO1 data input ⎯ SSIO1 synchronous clock input/output ⎯ SSIO1 data output ⎯ 11/34 FEDL610409-08 ML610407/ML610408/ML610409 1 PIN No. PAD No. 29 30 24 25 31 26 32 27 33 28 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 52 53 54 55 56 57 58 59 60 61 62 63 64 65 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 66 58 67 59 68 60 69 61 70 62 71 63 72 64 73 65 Primary function Function Secondary function or Tertiary function Secondary/ Tertiary ⎯ ⎯ Pin name ⎯ ⎯ Pin name I/O COM0 COM1 COM2/ SEG0 COM3/ SEG1 COM4/ SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 P67(*2) SEG32(*3) P66(*2) SEG33(*3) P65(*2) SEG34(*3) P64(*2) SEG35(*3) P63(*4) SEG36(*5) P62(*4) SEG37(*5) P61(*4) SEG38(*5) P60(*4) SEG39(*5) O O LCD common pin LCD common pin I/O Function ⎯ ⎯ ⎯ ⎯ O LCD common/segment pin ⎯ ⎯ ⎯ ⎯ O LCD common/segment pin ⎯ ⎯ ⎯ ⎯ O LCD common/segment pin ⎯ ⎯ ⎯ ⎯ O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin Output port LCD segment pin Output port LCD segment pin Output port LCD segment pin Output port LCD segment pin Output port LCD segment pin Output port LCD segment pin Output port LCD segment pin Output port LCD segment pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ (* ) Internally generated, or connect to either positive power supply pin (VDD) or power supply pin for internal logic (VDDL). For details, see "ML610407/ML610408/ML610409 User’s Manual Chapter 22 LCD Drivers." (*2) Pin for ML610407/ML610408 (*3) Pin for ML610409 (*4) Pin for ML610407 (*5) Pin for ML610408/ML610409 12/34 FEDL610409-08 ML610407/ML610408/ML610409 PIN DESCRIPTION Pin name I/O Description Primary/ Logic Secondary/ Tertiary System RESET_N I Reset input pin. When this pin is set to a “L” level, system reset mode is set and the internal section is initialized. When this pin is set to a “H” level subsequently, program execution starts. A pull-up resistor is internally connected. — Negative — — — — I Crystal connection pin for low-speed clock. XT1 O A 32.768 kHz crystal resonator is connected to this pin. Capacitors CDL and CGL are connected across this pin and VSS. (see appendix C measuring circuit 1) LSCLK O Low-speed clock output. Assigned to the secondary function of the P20 pin. Secondary — OUTCLK O High-speed clock output pin. This pin is used as the secondary function of the P21 pin. Secondary — Primary Positive Primary Positive Primary Positive Primary Positive Primary Positive Primary Positive Primary Positive XT0 General-purpose input port P00 to P04 I General-purpose input port. General-purpose output port P20 to P22, P24 O General-purpose output port. This cannot be used as the general output port when used as the secondary function. General-purpose input/output port P30 to P35 I/O General-purpose input/output port. This cannot be used as the general input/output port when used as the secondary function. P40 to P47 I/O General-purpose input/output port. This cannot be used as the general input/output port when used as the secondary or tertiary function. P50 to P57 I/O General-purpose input/output port. This cannot be used as the general input/output port when used as the secondary function. P60 to P63 O General-purpose output port. Incorporated only into ML610407/8, and not into ML610409. P64 to P67 O General-purpose output port. Incorporated only into ML610407, and not into ML610408/ ML610409. 13/34 FEDL610409-08 ML610407/ML610408/ML610409 Primary/ Pin name I/O Description Secondary/ Logic Tertiary UART TXD0 O UART data output pin. This pin is used as the secondary function of the P43 pin. RXD0 I UART data input pin. This pin is used as the secondary function of the P42 or the primary function of the P02 pin. Secondary Primary/ Secondary Positive Positive Synchronous serial (SSIO) SCK0 I/O Synchronous serial clock input/output pin. This pin is used as the tertiary function of the P41 or P45 pin. Tertiary — SIN0 I Synchronous serial data input pin. This pin is used as the tertiary function of the P40 or P44 pin. Tertiary Positive SOUT0 O Synchronous serial data output pin. This pin is used as the tertiary function of the P42 or P46 pin. Tertiary Positive SCK1 I/O Synchronous serial clock input/output pin. Assigned to the tertiary function of the P51 pin and P54 pin. Tertiary — SIN1 I Synchronous serial data input pin. Assigned to the tertiary function of the P50 pin and P54 pin. Tertiary Positive SOUT1 O Synchronous serial data output pin. Assigned to the tertiary function of the P52 pin and P56 pin. Tertiary Positive O PWM0 output pin. This pin is used as the secondary function of the P24 and tertiary function of the P43 pin. Secondary Positive PWM PWM0 T0P02CK Tertiary O PWM0 external clock input pin. This pin is used as the primary function of the P04 pin and P44 pin. Primary — I External maskable interrupt input pins. Interrupt enable and edge selection can be performed for each bit by software. These pins are used as the primary functions of the P00 to P04 pins. Primary Positive/ External maskable interrupt input pins. Interrupt enable and edge selection can be performed for each bit by software. Assigned to the primary function of the P50 to P57 pins. Primary Capture trigger input pins. The value of the time base counter is captured in the register synchronously with the interrupt edge selected by software. These pins are used as the primary functions of the P00 pin(CAP0) and P01 pin(CAP1). Primary External interrupt EXI0-4 EXI8 I negative Positive/ negative Capture CAP0 I CAP1 I Positive/ negative Primary Positive/ negative Timer T0P02CK I External clock input pin used for both Timer 0 and Timer 2. This pin is used as the primary function of the P04 pin and P44 pin. Primary T13CK I External clock input pin used for both Timer 1 and Timer 3. This pin is used as the primary function of the P45 pin. Primary O Melody/buzzer signal output pin. This pin is used as the secondary function of the P22 and P50 pins. Secondary N-channel open drain output pins to drive LED. This pin is used as the primary function of the P20 to P22 and P24 pins. Primary — — Melody MD0 Positive/ negative LED drive LED0 to LED2, LED4 O Positive /negative 14/34 FEDL610409-08 ML610407/ML610408/ML610409 Primary/ Pin name I/O Description Secondary/ Logic Tertiary UART TXD0 O UART data output pin. This pin is used as the secondary function of Secondary the P43 pin. Positive RXD0 I UART data input pin. This pin is used as the secondary function of the P42 or the primary function of the P02 pin. Positive Primary/ Secondary Synchronous serial (SSIO) SCK0 I/O Synchronous serial clock input/output pin. This pin is used as the tertiary function of the P41 or P45 pin. Tertiary — SIN0 I Synchronous serial data input pin. This pin is used as the tertiary function of the P40 or P44 pin. Tertiary Positive SOUT0 O Synchronous serial data output pin. This pin is used as the tertiary function of the P42 or P46 pin. Tertiary Positive SCK1 I/O Synchronous serial clock input/output pin. Assigned to the tertiary function of the P51 pin and P54 pin. Tertiary — SIN1 I Synchronous serial data input pin. Assigned to the tertiary function of the P50 pin and P54 pin. Tertiary Positive SOUT1 O Synchronous serial data output pin. Assigned to the tertiary function of the P52 pin and P56 pin. Tertiary Positive O PWM0 output pin. This pin is used as the secondary function of the P24 and tertiary function of the P43 pin. Secondary Positive PWM PWM0 T0P02CK Tertiary O PWM0 external clock input pin. This pin is used as the primary function of the P04 pin and P44 pin. Primary — I External maskable interrupt input pins. Interrupt enable and edge selection can be performed for each bit by software. These pins are used as the primary functions of the P00 to P04 pins. Primary Positive/ External maskable interrupt input pins. Interrupt enable and edge selection can be performed for each bit by software. Assigned to the primary function of the P50 to P57 pins. Primary Capture trigger input pins. The value of the time base counter is captured in the register synchronously with the interrupt edge selected by software. These pins are used as the primary functions of the P00 pin(CAP0) and P01 pin(CAP1). Primary External interrupt EXI0-4 EXI8 I negative Positive/ negative Capture CAP0 CAP1 I I Positive/ negative Primary Positive/ negative Timer T0P02CK I External clock input pin used for both Timer 0 and Timer 2. This pin is used as the primary function of the P04 pin and P44 pin. Primary T13CK I External clock input pin used for both Timer 1 and Timer 3. This pin is used as the primary function of the P45 pin. Primary O Melody/buzzer signal output pin. This pin is used as the secondary function of the P22 and P50 pins. Secondary N-channel open drain output pins to drive LED. This pin is used as the primary function of the P20 to P22 and P24 pins. Primary — — Melody MD0 Positive/ negative LED drive LED0 to LED2, LED4 O Positive /negative 15/34 FEDL610409-08 ML610407/ML610408/ML610409 Pin name I/O Description Primary/ Logic Secondary/ Tertiary RC oscillation type A/D converter IN0 I Channel 0 oscillation input pin. This pin is used as the secondary function of the P30 pin. Secondary CS0 O Channel 0 reference capacitor connection pin. This pin is used as the secondary function of the P31 pin. Secondary RS0 O This pin is used as the secondary function of the P32 pin the reference resistor connection pin of Channel 0. Secondary RCT0 O Resistor/capacitor sensor connection pin of Channel 0 for measurement. This pin is used as the secondary function of the P34 pin. which is — — — Secondary — RT0 O Resistor sensor connection pin of Channel 0 for measurement. This Secondary pin is used as the secondary function of the P33 pin. — RCM O RC oscillation monitor pin. This pin is used as the secondary function of the P35 pin. Secondary — IN1 I Oscillation input pin of Channel 1. This pin is used as the secondary function of the P44 pin. Secondary CS1 O Reference capacitor connection pin of Channel 1. This pin is used as the secondary function of the P45 pin. Secondary RS1 O Reference resistor connection pin of Channel 1. This pin is used as the secondary function of the P46 pin. Secondary RT1 O Resistor sensor connection pin for measurement of Channel 1. This Secondary pin is used as the secondary function of the P47 pin. COM0 to COM4 O Common output pins. COM2, COM3, and COM4 can be switched to SEG0, SEG1, and SEG2, respectively, through the register setting. To change the setting, switch between COM4 and SEG2 for one pin and switch between COM3, COM4 and SEG1, SEG2 for two pins. — — SEG0 to SEG23 O Segment output pin. The SEG0, SEG1, and SEG2 pins are for switching the register setting with the COM2, COM3, and COM4. — — SEG24 to SEG27 O Segment output pin. Incorporated into ML610408/ML610409, not into ML610407. — — SEG28 to SEG31 O Segment output pin. Incorporated into ML610409, not into ML610407/ML610408. — — — — LCD drive signal LCD driver power supply VL1 — — — VL2 — supply connection pin. Depending on LCD Bias setting and VDD — — VL3 — the connection method, see Chapter 22, "LCD Drivers". — Power supply pins for LCD bias (internally generated). Capacitor — — — — — — C1 C2 Power supply pin for LCD bias (internally generated) or power voltage level, VDD or VDDL or capacitor is connected. For details of C12 (see Appendix C measuring circuit 1) is connected between C1 — and C2. 16/34 FEDL610409-08 ML610407/ML610408/ML610409 Primary/ Pin name I/O Description Secondary/ Logic Tertiary Test TEST0 I/O Pin for testing. A pull-down resistor is internally connected. — Positive VSS — Negative power supply pin. — — VDD — Positive power supply pin. — — VDDL — Positive power supply pin (internally generated) for internal logic. Capacitors CL0 and CL1 (see Appendix C measuring circuit 1) are connected between this pin and VSS. — — Power supply 17/34 FEDL610409-08 ML610407/ML610408/ML610409 TERMINATION OF UNUSED PINS Table 2 shows methods of terminating the unused pins. Table 2 Pin VL1 VL2 VL3 C1, C2 RESET_N TEST0 P00 to P04 P20 to P22, P24 P30 to P35 P40 to P47 P50 to P57 P60 to P67 COM0 to COM4 SEG0 to SEG39 Termination of Unused Pins Recommended pin handling Open Open Open Open Open VSS VDD or VSS Open Open Open Open Open Open Open Note: It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting. 18/34 FEDL610409-08 ML610407/ML610408/ML610409 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (VSS= 0V) Parameter Symbol Condition Rating Unit Power supply voltage 1 VDD Ta=25°C -0.3 to +4.6 V Power supply voltage 2 VDDL Ta=25°C -0.3 to +3.6 V Power supply voltage 3 VL1 Ta=25°C -0.3 to +2.0 V Power supply voltage 4 VL2 Ta=25°C -0.3 to +4.0 V Power supply voltage 5 VL3 Ta=25°C -0.3 to +6.0 V Input voltage VIN Ta=25°C -0.3 to VDD+0.3 V Output voltage VOUT Ta=25°C -0.3 to VDD+0.3 V output current 1 IOUT1 Port 3 to 6, Ta=25°C -12 to +11 mA Output current 2 IOUT2 Port 2, Ta=25°C -12 to +20 mA Power dissipation PD Ta=25°C 0.9 W Storage temperature TSTG ― -55 to +150 °C Recommended Operating conditions (VSS= 0V) Parameter Symbol Operating temperature TOP Operating voltage VDD Operating frequency (CPU) fOP VDD pin external capacitance VDDL pin external capacitance VL1, 2, or 3 pin external capacitance Pin-to-pin (C1 to C2) external capacitance Condition Range Unit without P version -20 to +70 P version -40 to +85 fOP=30k to 625kHz 1.25 to 3.6 fOP=30k to 2.5MHz VDD=1.25 to 3.6V VDD=1.8 to 3.6V 1.8 to 3.6 30k to 625k 30k to 2.5M CV ― 1.0±30% to 2.2±30%*1 µF CL ― 0.47±30% to 2.2±30%*2 µF Ca,b,c ― 0.1±30% µF C12 ― 0.47±30% µF °C V Hz *1: Please select as CV is larger than CL or same as CL. *2: When the load of VDD is small and the power rise time is too short, it may happen that the power-on reset is not generated. In this case please select CL with larger capacitance Clock Generation Circuit Operating Conditions (VSS = 0V) Parameter Low-speed crystal oscillation frequency Recommended equivalent series resistance value of low-speed crystal oscillation Low-speed crystal oscillation external capacitor Min. Rating Typ. Max. Symbol Condition Unit fXTL ⎯ ⎯ 32.768k ⎯ Hz RL ⎯ ⎯ ⎯ 40k Ω ⎯ 12 ⎯ CDL/CGL CL=6pF of crystal oscillation CL=9pF of crystal oscillation CL=12pF of crystal oscillation ⎯ 18 ⎯ ⎯ 24 ⎯ pF 19/34 FEDL610409-08 ML610407/ML610408/ML610409 DC Characteristics (1/5) (VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Parameter Symbol Condition Ta=25°C VDD=1.25 to 3.6V 500kHz/2MHz RC oscillation frequency *3 fRC Ta=25°C VDD=1.8 to 3.6V Low-speed crystal 2 oscillation start time* 500kHz/2MHz RC oscillation start time Low-speed oscillation stop *1 detect time Reset pulse width Reset noise elimination pulse width Power-on reset generated power rise time *3 Min. Typ. -10% Typ. -25% Typ. -10% Typ. -25% Rating Typ. 500 500 2.0 2.0 Max. Typ. +10% Typ. +25% Typ. +10% Typ. +25% Unit Measur ement circuit kHz kHz MHz MHz TXTL ― ― 0.6 2 s TRC ― ― ― 3 µs TSTOP ― 12 16.4 41 ms PRST ― 200 ― ― PNRST ― ― ― 0.3 TPOR ― ― ― 10 1 µs ms 1 * : When low-speed crystal oscillation stops for a duration more than the low-speed oscillation stop detect time, the system is reset to shift to system reset mode. *2: 32.768kHz crystal resonator DT-26 (Load capacitance 6pF) (made by KDS:DAISHINKU CORP.) is used (CGL=CDL=6pF). *3: Recommended operating temperature (Ta=-20 to 70°C, Ta=-40 to 85°C for P version) VIL1 RESET_N VIL1 PRST Reset pulse width (PRST) 0.9xVDD VDD 0.1xVDD TPOR Power-on reset activation power rise time (TPOR ) 20/34 FEDL610409-08 ML610407/ML610408/ML610409 DC Characteristics (2/5) (VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Parameter VDDL voltage VDDL temperature deviation *1 VDDL voltage dependency *1 Min. Rating Typ. fop=30k to 625kHz 1.1 1.2 1.3 fop=30k to 2.5MHz 1.35 1.5 1.65 ∆VDDL VDD=3.0V ― -1 ― mV/°C ∆VDDL ― ― 5 20 mV/V Symbol VDDL Condition Max. Unit Measur ement circuit V 1 1 * : The maximum VDDL voltage becomes the VDD voltage level when the VDDL voltage determined by the temperature and voltage deviations mathematically exceeds the VDD voltage. 21/34 FEDL610409-08 ML610407/ML610408/ML610409 DC Characteristics (3/5) (VDD=3.0V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Parameter Symbol Supply current 1 IDD1 Supply current 2 IDD2 Supply current 3 IDD3 Supply current 4-1 IDD4-1 Supply current 4-2 IDD4-2 Min. Rating Typ. Max. ― 0.4 0.8 * ― ― 6.5 Ta=25°C ― 0.9 1.8 Condition CPU: In STOP state. Low-speed/High-speed oscillation: stopped. CPU: In HALT state. (LTBC, WDT: Operating)*3*4. High-speed 500kHz/2MHz oscillation: Stopped. LCD/BIAS circuits: Operating *6 CPU: In 32.768kHz operating state.*1*3 High-speed 500kHz/2MHz oscillation: Stopped, LCD/BIAS circuits: Operating *2 CPU: In 500kHz RC operating state. LCD/BIAS circuits: Operating.*2 Ta=25°C CPU: In 2MHz RC operating state. LCD/BIAS circuits: Operating.*2 5 Unit Measur ement circuit µA µA 5 * ― ― 7.5 Ta=25°C ― 4.0 7.5 1 µA *5 ― ― 11.0 Ta=25°C ― 60 80 * ― ― 90 Ta=25°C ― ― 240 ― 300 320 5 *5 µA µA *1: When the CPU operating rate is 100% (no HALT state). *2: All SEGs: off waveform, No LCD panel load, 1/3 bias, 1/3 duty, Frame frequency: Approx. 64 Hz, Bias voltage multiplying clock: 1/128 LSCLK (256Hz) *3 : 32.768KHz crystal resonator DT-26 (Load capacitance 6pF) (made by KDS:DAISHINKU CORP.) is used (CGL=CDL=6pF) *4 : Significant bits of BLKCON0 to BLKCON4 registers are all “1” except DLCD bit on BLKCON4. *5 : Recommended operating temperature (Ta=-20 to 70°C, Ta=-40 to 85°C for P version) *6: LCD stop mode, 1/3 bias, Bias voltage multiplying clock: 1/128 LSCLK (256Hz) 22/34 FEDL610409-08 ML610407/ML610408/ML610409 DC Characteristics (4/5) (VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Parameter Output voltage 1 (P20 to P22, P24 (N-channel open drain output mode is not selected)) (P30 to P35) (P40 to P47) (P50 to P57) (P60 to P63) *1 *2 (P64 to P67) *1 Output voltage 2 (P20 to P22, P24 (N-channel open drain output mode is selected)) Output voltage 3 (COM0 to 4) (SEG0 to 31)*1 (SEG0 to 35) *2 (SEG0 to 39) *3 Output leakage (P20 to P22,P24) (P30 to P35) (P40 to P47) (P50 to P57) (P60 to P63) *1 *2 (P60 to P67) *1 Input current 1 (RESET_N) (TEST1_N) Input current 2 (TEST0) Symbol IOH1=-0.5mA, VDD=1.8 to 3.6V VOH1 IOH1=-0.03mA, VDD=1.25 to 3.6V Rating Min. VDD -0.5 VDD -0.3 Typ. Max. ― ― ― ― IOL1=+0.5mA, VDD=1.8 to 3.6V ― ― 0.5 IOL1=+0.1mA, VDD=1.25 to 3.6V ― ― 0.3 VOL2 IOL2=+5mA, VDD=1.8 to 3.6V ― ― 0.5 VOH3 IOH3=-0.05mA, VL1=1.2V VL3 -0.2 ― ― VOML3 IOML3=+0.05mA, VL1=1.2V ― ― VL2 +0.2 VOML3S IOML3S=-0.05mA, VL1=1.2V VL2 -0.2 ― ― VOLM3 IOLM3=+0.05mA, VL1=1.2V ― ― VL1 +0.2 VOLM3S IOLM3S=-0.05mA, VL1=1.2V VL1 -0.2 ― ― VOL3 IOL3=+0.05mA, VL1=1.2V ― ― 0.2 IOOH VOH=VDD (in high-impedance state) ― ― 1 Unit Measur ement circuit V 2 µA 3 µA 4 VOL1 IOOL VOL=VSS (in high-impedance state) -1 ― ― IIH1 VIH1=VDD ― ― 1 IIL1 VIL1=VSS -600 -300 -2 IIH2 IIL2 2 -1 300 ― 600 ― 2 30 200 0.01 30 200 -200 -30 -2 -200 -30 -0.01 IIH3Z VIH2=VDD VIL2=VSS VIH3=VDD, VDD=1.8 to 3.6V (when pulled-down) VIH3=VDD, VDD=1.25 to 3.6V (when pulled-down) VIL3=VSS, VDD=1.8 to 3.6V (when pulled-up) VIL3=VSS, VDD=1.25 to 3.6V (when pulled-up) VIH3=VDD (in high-impedance state) ― ― 1 IIL3Z VIL3=VSS (in high-impedance state) -1 ― ― IIH3 Input current 3 (P00 to P04) (P30 to P35) (P40 to P47) (P50 to P57) Condition IIL3 *1: Characteristics for ML610407. *2: Characteristics for ML610408. *3: Characteristics for ML610409. 23/34 FEDL610409-08 ML610407/ML610408/ML610409 DC Characteristics (5/5) (VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Parameter Input voltage 1 (RESET_N) (TEST0, TEST1_N) (P00 to P04) (P30 to P35) (P40 to P47) (P50 to P57) Input pin capacitance (P00 to P04) (P30 to P35) (P40 to P47) (P50 to P57) Symbol Condition VIH1 Rating Min. Typ. Max. ― 0.7 ×VDD ― VDD VDD=1.8 to 3.6V 0 ― 0.3 ×VDD VDD=1.25 to 3.6V 0 ― 0.2 ×VDD f=10kHz Vrms=50mV Ta=25°C ― ― 5 VIL1 CIN Unit Measur ement circuit V 5 pF ― 24/34 FEDL610409-08 ML610407/ML610408/ML610409 Measuring Circuits Measuring Circuit 1 CGL XT0 CDL XT1 C2 32.768kHz crystal resonator C12 C1 VDD VDDL VSS VL1 VL2 VL3 A CV CL CV : 1µF CL : 2.2uF Ca,Cb,Cc : 0.1µF C12 : 0.47µF 32.768kHz crystal resonator : DT-26 (Load capacitance 6pF) (Made by KDS:DAISHINKU CORP.) Cc Ca CGL, CDL : 6pF Measuring Circuit 2 (Note 2) VIH Output pin VIL Input pin (Note 1) VDD VDDL VL1 VL2 VL3 V VSS (Note 1) Input logic circuit to determine the specified measuring conditions. (Note 2) Repeats for the specified output pin 25/34 FEDL610409-08 ML610407/ML610408/ML610409 Measuring Circuit 3 (Note 2) VIH Output pin VIL Input pin (Note 1) VDD VDDL VL1 VL2 VL3 A VSS (Note 1) Input logic circuit to determine the specified measuring conditions. (Note 2) Repeats for the specified output pin Measuring Circuit 4 (Note 1) Output pin Input pin A VDD VDDL VL1 VL2 VL3 VSS (Note 1) Repeats for the specified input pin 26/34 FEDL610409-08 ML610407/ML610408/ML610409 Measuring Circuit 5 VIH VDD VDDL VL1 VL2 VL3 Waveform observation Output pin VIL Input pin (Note 1) VSS (Note 1) Input logic circuit to determine the specified measuring conditions. 27/34 FEDL610409-08 ML610407/ML610408/ML610409 AC Characteristics (External Interrupt) (VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Parameter Symbol External interrupt disable period TNUL Condition Rating Min. Typ. Max. 76.8 ― 106.8 Unit Interrupt: Enabled (MIE = 1), CPU: NOP operation µs System clock: 32.768kHz P00–P07 (Rising-edge interrupt) tNUL P00–P07 (Falling-edge interrupt) tNUL P00–P07 (Both-edge interrupt) tNUL 28/34 FEDL610409-08 ML610407/ML610408/ML610409 AC Characteristics (UART) (VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Parameter Symbol Condition Transmit baud rate tTBRT ― Receive baud rate tRBRT ― Rating Min. Typ. Max. ― BRT* 1 1 BRT* -3% ― Unit s 1 1 BRT* BRT* +3% s *1: Baud rate period (including the error of the clock frequency selected) set with the UART baud rate register (UA0BRTL,H) and the UART mode register 0 (UA0MOD0). tTBRT TXD0* tRBRT RXD0* *: Indicates the secondary function of the port. 29/34 FEDL610409-08 ML610407/ML610408/ML610409 AC Characteristics (Synchronous Serial Port) (VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Parameter Symbol SCLK input cycle (slave mode) Rating Condition In the 500kHz oscillation mode* tSCYC In the 2MHz oscillation mode* Typ. Max. 10 ― ― µs 1 ― ― µs ― SCLK* ― s 4 ― ― µs 0.4 ― ― µs 2 3 VDD=1.8 to 3.6V SCLK output cycle (master mode) SCLK input pulse width (slave mode) ― tSCYC In the 500kHz oscillation mode* tSW In the 2MHz oscillation mode* 2 (master mode) 1 tSW ― In the 500kHz oscillation mode* SOUT output delay time (slave mode) tSD SCLK* ×0.4 ×0.5 ×0.6 ― ― 500 ― ― 240 ― ― 500 (master mode) ns 2 Output load 10pF In the 2MHz oscillation mode* s 2 3 In the 500kHz oscillation mode* tSD 1 SCLK* Output load 10pF In the 2MHz oscillation mode* 1 SCLK* Output load 10pF SOUT output delay time 1 3 VDD=1.8 to 3.6V SCLK output pulse width Unit Min. ns 3 ― ― 240 80 ― ― 500 ― ― 240 ― ― 300 ― ― 80 ― ― Output load 10pF, VDD=1.8 to 3.6V SIN input setup time ― tSS ns (slave mode) In the 500kHz oscillation mode* SIN input setup time tSS In the 2MHz oscillation mode* (master mode) 3 VDD=1.8 to 3.6V In the 500kHz oscillation mode* SIN input tSH hold time 2 In the 2MHz oscillation mode* 2 3 VDD=1.8 to 3.6V ns ns *1: Clock cycle selected with S0CK3–0 of the serial port 0 mode register (SIO0MOD1) *2: When 500kHz oscillation is selected with RCM of the frequency control register 0 (FCON0) *3: When 2MHz oscillation is selected with RCM of the frequency control register 0 (FCON0) tSCYC tSW tSW SCLK0 tSD tSD SOUT0 tSS tSH SIN0 *: Indicates the secondary function of the port 30/34 FEDL610409-08 ML610407/ML610408/ML610409 AC Characteristics (RC Oscillation A/D Converter) Condition for VDD=1.8 to 3.6V (VDD=1.8 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Parameter Oscillation resistor Oscillation frequency VDD = 3.0V RS to RT oscillation *1 frequency ratio VDD = 3.0V Min. Rating Typ. Max. CS0, CT0, CS1≥740pF 1 ― ― kΩ Resistor for oscillation=1kΩ Resistor for oscillation=10kΩ Resistor for oscillation=100kΩ RT0, RT0-1, RT1=1kΩ RT0, RT0-1, RT1=10kΩ RT0, RT0-1, RT1=100kΩ 457.3 53.48 5.43 7.972 0.981 0.099 525.2 58.18 5.89 9.028 1 0.101 575.1 62.43 6.32 9.782 1.019 0.104 kHz kHz kHz ⎯ ⎯ ⎯ Symbol Condition RS0,RS1,RT0, RT0-1,RT1 fOSC1 fOSC2 fOSC3 Kf1 Kf2 Kf3 Unit *1: Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the same conditions. fOSCX(RT0-1-CS0 oscillation) fOSCX(RS0-CS0 oscillation) IN0 CS0 RCT0 (Note 1) RT0 RS0 RS0 RT0 VIL RCM VDD CV VDDL RT0, RT0-1, RT1: 1kΩ/10kΩ/100kΩ RS0, RS1: 10kΩ CS0, CT0, CS1: 560pF CVR0, CVR1: 820pF IN1 CS1 RS1 RT1 Input pin VIH CVR1 RT0-1 CT0 CS0 CVR0 fOSCX(RT1-CS1 oscillation) fOSCX(RS1-CS1 oscillation) , RT1 , RS1 fOSCX(RT0-CS0 oscillation) fOSCX(RS0-CS0 oscillation) ( x = 1, 2, 3 ) CS1 Kfx = Frequency measurement (fOSCX) VSS CL *1: Input logic circuit to determine the specified measuring conditions. 31/34 FEDL610409-08 ML610407/ML610408/ML610409 Condition for VDD=1.25 to 3.6V (VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Parameter Min. Rating Typ. Max. CS0, CT0, CS1≥740pF 1 ― ― kΩ Resistor for oscillation=6kΩ Resistor for oscillation=15kΩ Resistor for oscillation=105kΩ RT0, RT0-1, RT1=1kΩ RT0, RT0-1, RT1=10kΩ RT0, RT0-1, RT1=100kΩ Resistor for oscillation=6kΩ Resistor for oscillation=15kΩ Resistor for oscillation=105kΩ RT0, RT0-1, RT1=1kΩ RT0, RT0-1, RT1=10kΩ RT0, RT0-1, RT1=100kΩ 81.93 35.32 5.22 2.139 0.973 0.142 85.28 35.72 5.189 2.227 0.982 0.141 93.16 38.75 5.65 2.381 1 0.147 94.58 38.87 5.622 2.432 1 0.145 101.2 41.48 6.03 2.632 1.028 0.152 103.3 41.78 6.012 2.626 1.018 0.149 kHz kHz kHz ⎯ ⎯ ⎯ kHz kHz kHz ⎯ ⎯ ⎯ Symbol Oscillation resistor Oscillation frequency VDD = 1.5V RS to RT oscillation *1 frequency ratio VDD = 1.5V Oscillation frequency VDD = 3.0V RS to RT oscillation *1 frequency ratio VDD = 3.0V Condition RS0,RS1,RT0, RT0-1,RT1 fOSC1 fOSC2 fOSC3 Kf1 Kf2 Kf3 fOSC1 fOSC2 fOSC3 Kf1 Kf2 Kf3 Unit *1: Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the same conditions. fOSCX(RT0-1-CS0 oscillation) fOSCX(RS0-CS0 oscillation) , IN0 CS0 RCT0 VIH , RA1 RT1 RA0 RT0 RS0 RS0 RT0 RT0, RT0-1, RT1: 1kΩ/10kΩ/100kΩ RA0, RA0-1, RA1: 5kΩ RS0, RS1: 15kΩ CS0, CT0, CS1: 560pF CVR0, CVR1: 820pF IN1 CS1 RS1 RT1 Frequency measurement (fOSCX) Input pin RCM (Note 1) fOSCX(RT1-CS1 oscillation) fOSCX(RS1-CS1 oscillation) CVR1 RT0-1 RA0-1 CT0 CS0 CVR0 RS1 fOSCX(RT0-CS0 oscillation) fOSCX(RS0-CS0 oscillation) ( x = 1, 2, 3 ) CS1 Kfx = VIL VDD CV VDDL VSS CL *1: Input logic circuit to determine the specified measuring conditions. Note: •Please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors and IN0/IN1 pin), including CVR0/CVR1. Especially, do not have long wiring between IN0/IN1 and RS0/RS1. The coupling capacitance on the wires may occur incorrect A/D conversion. Also, please do not have signals which may be a source of noise around the node. •When RT0/RT1 (Thermistor and etc.) requires long wiring due to the restricted placement, please have VSS(GND) trace next to the signal. •Please make wiring to components (capacitor, resistor, and so on) necessary for objective measurement. Wiring to reserved components may affect to the A/D conversion operation by noise the components itself may have. 32/34 FEDL610409-08 ML610407/ML610408/ML610409 REVESION HISTORY Document No. FEDL610409-01 FEDL610409-02 FEDL610409-03 FEDL610409-04 FEDL610409-05 FEDL610409-06 FEDL610409-07 FEDL610409-08 Date Mar.7,2011 Mar.30,2011 Mar.30,2011 Mar.27,2012 Jul.18,2012 Feb.13,2014 Apr.18,2014 May.23,2014 Page Previous Current Edition Edition – 23 23 21,26 20 – 23 23 21,26 20 21 3, 34 All 3 21 3, 34 All 4 2 2 3、5,6,7, 34 4 - 4 4 19 20 20 20 20 Description Formally edition 1 The supply current was changed. Correct the supply current. The value of capacitor CL was changed to 2.2uF. The termination of the TEST0 was changed from OPEN to VSS. The notes about CV, CL were added. The package dimension was changed. Change header and footer Change from "Shipment" to " Product name – Supported Function " Delete the description of LCD drivers 1/2 bias supported version Delete package products Correct the “Product name – Supported Function” Add Clock Generation Circuit Operating Conditions Change "RESET" to " Reset pulse width (PRST)" and " Power-on reset activation power rise time (TPOR )". Correct the CGL’s value and the CDL’s value of DC CHARACTERISTICS (1/5)’s note No.2 33/34 FEDL610409-08 ML610407/ML610408/ML610409 NOTES No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co., Ltd. The content specified herein is subject to change for improvement without notice. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. 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