TI1 DRV8801AQRMJRQ1 Dmos full-bridge motor driver Datasheet

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DRV8801A-Q1
SLVSC79C – JUNE 2014 – REVISED JULY 2016
DRV8801A-Q1 DMOS Full-Bridge Motor Drivers
1 Features
3 Description
•
•
•
•
•
•
•
•
The DRV8801A-Q1 device provides a versatile
motor-driver solution with a full H-bridge driver. The
device can drive a brushed DC motor or one winding
of a stepper motor, as well as other devices like
solenoids. A simple PHASE and ENABLE interface
allows easy interfacing to controller circuits.
1
Qualified for Automotive Applications
Low ON-Resistance (0.83 Ω) Outputs
Low-Power Sleep Mode
100% PWM Supported
6.5 to 36-V Operating Supply Voltage Range
Thermally Enhanced Surface-Mount Package
Configurable Overcurrent Limit
Protection Features
– VBB Undervoltage Lockout (UVLO)
– Overcurrent Protection (OCP)
– Short-to-Supply Protection
– Short-to-Ground Protection
– Overtemperature Warning (OTW)
– Overtemperature shutdown (OTS)
– Overcurrent and Overtemperature Fault
Conditions Indicated On Pin (nFAULT)
2 Applications
•
•
•
•
Automotive Body Systems
Door Locks
HVAC Actuators
Piezo Alarm
The output stages use N-channel power MOSFETs
configured as an H-bridge. The DRV8801A-Q1
device is capable of peak output currents up to ±2.8
A and operating voltages up to 36 V. An internal
charge pump generates required gate drive voltages.
A low-power sleep mode is provided which shuts
down internal circuitry to achieve very low quiescent
current draw. This sleep mode can be set using a
dedicated nSLEEP pin.
Internal
protection
functions
are
provided
undervoltage lockout, overcurrent protection, short-tosupply
protection,
short-to-ground
protection,
overtemperature warning, and overtemperature
shutdown. Overcurrent (including short-to-ground and
short-to-supply) and overtemperature fault conditions
are indicated via an nFAULT pin.
The DRV8801A-Q1 device is packaged in a 16-pin
WQFN package with wettable flanks and exposed
thermal pad (Eco-friendly: RoHS & no Sb/Br).
Device Information(1)
PART NUMBER
DRV8801A-Q1
PACKAGE
WQFN (16)
BODY SIZE (NOM)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Application Diagram
6.5 to 36 V
Controller
PH/EN
VPROPI
DRV8801A-Q1
Full-Bridge
Driver
M
nFAULT
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8801A-Q1
SLVSC79C – JUNE 2014 – REVISED JULY 2016
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
6
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Dissipation Ratings ...................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1
7.2
7.3
7.4
Overview ................................................................... 8
Functional Block Diagram ......................................... 8
Feature Description................................................... 9
Device Functional Modes........................................ 12
8
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application ................................................. 13
9
Power Supply Recommendations...................... 15
9.1 Bulk Capacitance .................................................... 15
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Example .................................................... 16
10.3 Power Dissipation ................................................. 16
11 Device and Documentation Support ................. 17
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
17
17
12 Mechanical, Packaging, And Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (June 2016) to Revision C
Page
•
Changed the TJ value for some test conditions for the output ON resistance parameter in the Electrical
Characteristics ....................................................................................................................................................................... 5
•
Added the Documentation Support, Receiving Notification of Documentation Updates, and Community Resources
sections ................................................................................................................................................................................ 17
Changes from Revision A (September 2014) to Revision B
Page
•
Changed the value of TJ from 125°C to 25°C in the test condition (source driver, IO = –2.8 A, VBB = 8 to 36 V) for the
output ON resistance parameter ............................................................................................................................................ 5
•
Added the UVLO hysteresis parameter in the Electrical Characteristics table ...................................................................... 6
•
Added MIN and MAX values for the overcurrent retry time parameter in the Electrical Characteristics table ...................... 6
•
Updated the Functional Block Diagram .................................................................................................................................. 8
•
Added tpd to the Overcurrent Control Timing image ............................................................................................................. 11
Changes from Original (June 2014) to Revision A
Page
•
Added TYPE column to the Pin Functions table ................................................................................................................... 3
•
Updated the Overcurrent Control Timing image................................................................................................................... 11
2
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5 Pin Configuration and Functions
12
GND
11
CP2
10
CP1
MODE_1
nFAULT
VPROPI
VCP
15
14
13
9
8
4
VBB
ENABLE
Pad
7
3
SENSE
nSLEEP
Thermal
6
2
OUTA
GND
5
1
MODE_2
PHASE
16
RMJ Package
16-Pin WQFN With Thermal Pad
Top View
OUTB
Not to scale
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
CP1
10
—
Charge-pump capacitor 1
CP2
11
—
Charge-pump capacitor 2
ENABLE
4
I
GND
2
12
PWR
Enables OUTA and OUTB drivers
Ground
MODE 1
16
I
Mode logic input
MODE 2
5
I
Mode 2 logic input
nFAULT
15
OD
nSLEEP
3
I
Logic low puts the device in a low-power sleep mode
OUTA
6
O
DMOS full-bridge output positive. H-Bridge output A
OUTB
9
O
DMOS full-bridge output negative. H-Bridge output B
PHASE
1
I
Phase logic input for direction control
SENSE
7
IO
VBB
8
PWR
VCP
13
—
Charge-pump reservoir capacitor pin
VPROPI
14
O
Winding current proportional voltage output
—
Exposed pad for thermal dissipation; connect to GND pins.
Thermal pad
Fault open-drain output. A logic low indicates fault a condition
Sense power return
Driver supply voltage
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Power supply voltage (2)
VBB
–0.3
40
V
Charge pump voltage
VCP, CP1, and CP2
–0.3
VBB + 7
V
Digital pin voltage
PHASE, ENABLE, MODE1, MODE2, nSLEEP, nFAULT
–0.3
7
V
VBB to OUTx voltage
OUTA and OUTB
–0.3
36
V
OUTx to GND voltage
OUTA and OUTB
–0.3
36
V
Sense pin voltage
SENSE
–0.5
0.5
V
H-bridge output current
OUTA, OUTB, and SENSE
2.8
A
VPROPI pin voltage
VPROPI
–0.3
Maximum junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
–40
3.6
V
150
°C
125
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic
discharge
Charged-device model (CDM), per AEC Q100-011
UNIT
±2000
All pins
±500
Corner pins (1, 4, 5, 8, 9, 12,
13, and 16)
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
MAX
UNIT
VBB
Power supply voltage
6.5
36
VCC
Logic supply voltage
0
5.5
V
ƒ(PWM)
Applied PWM signal (PHASE and ENABLE)
0
100
kHz
IO
H-bridge peak output current
TA
Ambient temperature
4
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V
0
2.8
A
–40
125
°C
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6.4 Thermal Information
DRV8801A-Q1
THERMAL METRIC (1)
RMJ (WQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
36.8
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
43.4
°C/W
RθJB
Junction-to-board thermal resistance
14.7
°C/W
ψJT
Junction-to-top characterization parameter
0.7
°C/W
ψJB
Junction-to-board characterization parameter
14.7
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
4.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
TA = 25°C, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
POWER SUPPLIES (VBB)
VBB
VBB operating supply voltage
IBB
VBB operating supply current
IBB(Q)
VBB sleep-mode supply current
6.5
ƒPWM < 50 kHz
36
6
Charge pump on, Outputs disabled
mA
3.2
nSLEEP = 0, TJ = 25°C
V
10
μA
CONTROL INPUTS (PHASE, ENABLE, MODE1, MODE2, nSLEEP)
VIL
Input logic low voltage
VIH
Input logic high voltage
IIL
Input logic low current
IIH
Input logic high current
IIL
Input logic low current
IIH
Input logic high current
VIL
Input logic low voltage
VIH
Input logic high voltage
IIL
Input logic low current
IIH
Input logic high current
0.8
PHASE, ENABLE,
MODE1, MODE2
PHASE, ENABLE,
MODE1, MODE2
ENABLE
2
≤ –2
20
<1
20
VI = 0.8 V
16
40
VI = 2 V
40
100
VI = 0.8 V
–20
VI = 2 V
0.8
nSLEEP
2.7
VI = 0.8 V
VI = 2 V
<1
10
27
50
V
µA
μA
V
μA
CONTROL OUTPUTS (nFAULT)
VOL
Output logic low voltage
IO = 1 mA
0.4
V
DMOS DRIVERS (OUTA, OUTB, SENSE, VPROPI)
rDS(on)
Output ON resistance
Source driver, IO = –2.8 A, TJ = 25°C , VBB = 6.5 to 36 V
0.48
Source driver, IO = –2.8 A, TJ = 125°C, VBB = 8 to 36 V
0.74
0.85
Source driver, IO = –2.8 A, TJ = 125°C, VBB = 6.5 to 8 V
0.74
0.9
Sink driver, IO = 2.8 A, TJ = 25°C, VBB = 6.5 to 36 V
0.35
Sink driver, IO = 2.8 A, TJ = 125°C, VBB = 8 to 36 V
0.52
0.7
0.52
0.75
500
550
Sink driver, IO = 2.8 A, TJ = 125°C, VBB = 6.5 to 8 V
V(TRIP)
SENSE trip voltage
Vf
Body diode forward voltage
tpd
Propagation delay time
tCOD
Crossover delay
GD(a)
Differential amplifier gain
R(SENSE) between SENSE and GND
450
Source diode, If = –2.8 A
1.4
Sink diode, If = 2.8 A
1.4
Input edge to source or sink ON
600
Input edge to source or sink OFF
100
4.8
VBB = 6.5 to 8 V; SENSE = 0.1 to 0.3 V
4.8
5
mV
V
ns
500
VBB = 8 to 36 V; SENSE = 0.1 to 0.4 V
Ω
ns
5.2
V/V
5.2
V/V
PROTECTION CIRCUITS
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Electrical Characteristics (continued)
TA = 25°C, over recommended operating conditions (unless otherwise noted)
PARAMETER
VUV
TEST CONDITIONS
MIN
VBB increasing
UVLO threshold
5.5
V
5.7
500
Overcurrent protection trip level
UNIT
6.4
VBB decreasing
UVLO hysteresis
I(OCP)
TYP MAX
VBB = 8 to 36 V
3
VBB = 6.5 to 8 V
2.8
850
mV
A
A
t(DEG)
Overcurrent deglitch time
3
t(OCP)
Overcurrent retry time
T(OTW)
Thermal warning temperature
Die temperature TJ
160
°C
Thys(OTW)
Thermal warning hysteresis
Die temperature TJ
15
°C
T(OTS)
Thermal shutdown temperature
Die temperature TJ
175
°C
Thys(OTS)
Thermal shutdown hysteresis
Die temperature TJ
15
°C
0.5
µs
1.2
3
ms
6.6 Dissipation Ratings
PACKAGE
RθJA
TA = 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
RMJ
36.8
3W
27 mW/C
6.7 Typical Characteristics
1400
5.35
Output ON resistance (m:)
1200
Differential Amplifier Gain (V/V)
TA = 40qC
TA = 25qC
TA = 85qC
1300
1100
1000
900
800
700
600
500
400
5.25
5.2
5.15
5.1
5.05
5
6
9
12
15
18
21
24
27
Power Supply Voltage (V)
30
33
36
0
0.2
D001
Figure 1. rDS(on) Over Voltage
6
TA = 40qC
TA = 25qC
TA = 85qC
5.3
0.4
0.6
0.8
1
Output Current (A)
1.2
1.4
1.6
D002
Figure 2. VPROPI Over Output Current
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Typical Characteristics (continued)
60
VCP Pin Voltage, Unloaded (V)
55
50
45
40
35
30
25
20
15
10
6
9
12
15
18
21
24
27
Power Supply Voltage (V)
30
33
36
D003
Figure 3. VCP Voltage vs VBB
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7 Detailed Description
7.1 Overview
The DRV8801A-Q1 device is an integrated motor driver solutions for brushed-DC motors. The device integrates
a DMOS H-bridge and current sense and protection circuitry. The device can be powered with a supply voltage
between 6.5 V and 36 V, and is capable of providing an output current up to 2.8-A peak.
A simple PHASE and ENABLE interface allows control of the motor speed and direction.
A shunt amplifier output is provided for accurate current measurements by the system controller. The VPROPI
pin outputs a voltage that is five-times the voltage seen at the SENSE pin.
A low-power sleep mode is included which allows the system to save power when not driving the motor.
7.2 Functional Block Diagram
VCP
VBB
VBB
+
0.1 µF
100 µF
0.1 µF
VCP
Predrive
CP2
OUTA
Charge Pump
0.1 µF
CP1
VCP
BDC
VBB
PHASE
Logic
PreDrive
OUTB
ENABLE
SENSE
MODE1
VPROPI
x5
MODE2
R(SENSE)
VCC
nSLEEP
R(VPROPI)
100 kŸ
Undervoltage
VCC
1000 pF
nFAULT
Temperature
Sensor
GND
8
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PPAD
GND
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7.3 Feature Description
7.3.1 Power Supervisor
The control input, nSLEEP, is used to minimize power consumption when the DRV8801A-Q1 device is not in
use. The nSLEEP input disables much of the internal circuitry, including the internal voltage rails and charge
pump. nSLEEP is asserted logic low. A logic high on this input pin results in normal operation. When switching
from low to high, the user should allow a 1-ms delay before applying PWM signals. This time is needed for the
charge pump to stabilize.
7.3.2 Bridge Control
The following table shows the logic for the DRV8801A-Q1:
nSLEEP
PHASE
ENABLE
MODE1
MODE2
OUTA
OUTB
OPERATION
0
X
X
X
X
Z
Z
Sleep mode
1
0
1
X
X
L
H
Reverse
1
1
1
X
X
H
L
Forward
1
0
0
0
X
H
L
Fast decay
1
1
0
0
X
L
H
Fast decay
1
X
0
1
0
L
L
Low-side Slow
decay
1
X
0
1
1
H
H
High-side Slow
decay
To prevent reversal of current during fast-decay synchronous rectification, outputs go to the high impedance
state as the current approaches 0 A.
The path of current flow for each of the states in the above logic table is shown in Figure 4.
7.3.2.1 MODE 1
Input MODE 1 is used to toggle between fast-decay mode and slow-decay mode. A logic high puts the device in
slow-decay mode.
7.3.2.2 MODE 2
MODE 2 is used to select which set of drivers (high side versus low side) is used during the slow-decay
recirculation. MODE 2 is meaningful only when MODE 1 is asserted high. A logic high on MODE 2 has current
recirculation through the high-side drivers. A logic low has current recirculation through the low-side drivers.
7.3.3 Fast Decay with Synchronous Rectification
This decay mode is equivalent to a phase change where the FETs opposite of the driving FETs are switched on
(2 in Figure 4). When in fast decay, the motor current is not allowed to go negative because this would cause a
change in direction. Instead, as the current approaches zero, the drivers turn off. See the Power Dissipation
section for an equation to calculate power.
7.3.4 Slow Decay with Synchronous Rectification (Brake Mode)
In slow-decay mode, both low-side and high-side drivers turn on, allowing the current to circulate through the
low-side and high-side body diodes of the H-bridge and the load (3 and 4 in Figure 4). See the Power Dissipation
section for equations to calculate power for both high-side and low-side slow decay.
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VM
4
1 Drive
1
xOUTA
xOUTB
3
2
Fast decay with synchronous rectification
3 Low-side slow decay with synchronous rectification
2
4 High-side slow decay with synchronous rectification
xISEN
R(SENSE)
Figure 4. H-Bridge Operation Modes
7.3.5 Charge Pump
The charge pump is used to generate a supply above VBB to drive the source-side DMOS gates. A 0.1-μF
ceramic monolithic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.1-μF
ceramic monolithic capacitor should be connected between VCP and VBB to act as a reservoir to run the highside DMOS devices.
7.3.6 SENSE
A low-value resistor can be placed between the SENSE pin and ground for current-sensing purposes. To
minimize ground-trace IR drops in sensing the output current level, the current-sensing resistor should have an
independent ground return to the star ground point. This trace should be as short as possible. For low-value
sense resistors, the IR drops in the PCB can be significant, and should be taken into account.
To set a manual overcurrent trip threshold, place a resistor between the SENSE pin and GND. When the SENSE
pin rises above 500 mV, the H-bridge output is disabled (hi-Z). The device automatically retries with a period of
t(OCP).
The overcurrent trip threshold can be calculated using Equation 1.
I(trip) = 500 mV/R
(1)
The overcurrent trip level selected cannot be greater than I(OCP).
10
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V(OUTx)
Hi-Z
I(PEAK)
I(OUTx)
I(OCP)
Enable,
Source
or Sink
t(DEG)
tpd
t(OCP)
nFAULT
Motor Lead
Short Condition
Normal DC
No Fault Condition
Figure 5. Overcurrent Control Timing
7.3.7 VPROPI
The VPROPI output is equal to approximately five times the voltage present on the SENSE pin. VPROPI is
meaningful only if there is a resistor connected to the SENSE pin. If the SENSE pin is connected to ground,
VPROPI measures 0 V. Also note that during slow decay (brake), VPROPI measures 0 V. VPROPI can output a
maximum of 2.5 V, because at 500 mV on SENSE, the H-bridge is disabled.
7.3.8 Protection Circuits
The DRV8801A-Q1 device is fully protected against VBB undervoltage, overcurrent, and overtemperature events.
FAULT
ERROR REPORT
H-BRIDGE
CHARGE PUMP
RECOVERY
VBB undervoltage (UVLO)
No error report – nFAULT
is hi-Z
Disabled
Shut Down
VBB > VUVLO RISING
Overcurrent (OCP)
nFAULT pulled low
Disabled
Operating
Retry time, t(OCP)
Overtemperature Warning
(OTW)
nFAULT pulled low
Enabled
Operating
TJ < T(OTW) – Thys(OTW)
Overtemperature
Shutdown (OTS)
nFAULT remains pulled
low (set during OTW)
Disabled
Shut Down
TJ < T(OTS) – Thys(OTS)
7.3.8.1 VBB Undervoltage Lockout (UVLO)
If at any time the voltage on the VBB pin falls below the undervoltage lockout threshold voltage, all FETs in the Hbridge are disabled and the charge pump is disabled. The nFAULT pin does not report the UVLO fault condition
and remains hi-Z. Operation resumes when VBB rises above the UVLO threshold.
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7.3.8.2 Overcurrent Protection (OCP)
The current flowing through the high-side and low-side drivers is monitored to ensure that the motor lead is not
shorted to supply or ground. If a short is detected, all FETs in the H-bridge are disabled, nFAULT is driven low,
and a t(OCP) fault timer is started. After this period, t(OCP), the device is then allowed to follow the input commands
and another turn-on is attempted (nFAULT releases during this attempt). If there is still a fault condition, the cycle
repeats. If the short condition is not present after t(OCP) expires, normal operation resumes and nFAULT is
released.
7.3.8.3 Overtemperature Warning (OTW)
If the die temperature increases past the thermal warning threshold the nFAULT pin is driven low. When the die
temperature has fallen below the hysteresis level, the nFAULT pin is released. If the die temperature continues to
increase, the device enters overtemperature shutdown as described in the Overtemperature Shutdown (OTS)
section.
7.3.8.4 Overtemperature Shutdown (OTS)
If the die temperature exceeds the thermal shutdown temperature, all FETs in the H-bridge are disabled and the
charge pump shuts down. The nFAULT pin remains pulled low during this fault condition. When the die
temperature falls below the hysteresis threshold, operation automatically resumes.
7.4 Device Functional Modes
The DRV8801A-Q1 device is active unless the nSLEEP pin is brought logic low. In sleep mode the charge pump
is disabled and the H-bridge FETs are disabled hi-Z. The DRV8801A-Q1 device is brought out of sleep mode
automatically if nSLEEP is brought logic high.
12
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8 Application and Implementation
8.1 Application Information
The DRV8801A-Q1 device is used in medium voltage brushed-DC motor control applications.
8.2 Typical Application
100 k
VDD
ANA_VPROPI
VBB
VCP
0.1 µF
50 V
VPROPI
PHASE
nFAULT
VDD
MODE1
3.3 k
1000 pF
GND
3.3 k
GND
CP2
DRV8801A-Q1
OUTB
VBB
M
SENSE
ENABLE
OUTA
CP1
MODE2
nSLEEP
0.1 µF
50 V
0.1 µF
50 V
R(SENSE)
100 µF
50 V
Figure 6. Typical Application Diagram
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Typical Application (continued)
8.2.1 Design Requirements
The example supply voltage for this design is VBB = 18 V.
8.2.2 Detailed Design Procedure
8.2.2.1 Drive Current
This current path is through the high-side sourcing DMOS driver, motor winding, and low-side sinking DMOS
driver. Power dissipation I2R loses in one source and one sink DMOS driver, as shown in Equation 2.
PD = I 2 (rDS(on)Source + rDS(on)Sink )
(2)
8.2.2.2 Slow-Decay SR (Brake Mode)
In slow-decay mode, both low-side sinking drivers turn on, allowing the current to circulate through the low side
of the H-bridge (two sink drivers) and the load. Power dissipation I2R loses in the two sink DMOS drivers as
shown in Equation 3
PD = I 2 (2 ´ rDS(on)Sink )
(3)
8.2.3 Application Curves
OUTA
OUTA
OUTB
OUTB
IO
IO
Figure 7. 75% Drive, 25% Slow Decay; ƒ(PWM) = 5 kHz
14
Figure 8. 75% Drive, 25% Fast Decay; ƒ(PWM) = 5 kHz
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9 Power Supply Recommendations
The DRV8801A-Q1 device is designed to operate from an input-voltage supply (VBB) range between 6.5 V and
36 V. One 0.1-µF ceramic capacitor rated for VBB must be placed as close as possible to the VBB pin. In addition
to the local decoupling caps, additional bulk capacitance is required and must be sized accordingly to the
application requirements.
9.1 Bulk Capacitance
Bulk capacitance sizing is an important factor in motor drive system design. This sizing is dependent on a variety
of factors including:
• Type of power supply
• Acceptable supply voltage ripple
• Parasitic inductance in the power supply wiring
• Type of motor (brushed DC, brushless DC, stepper)
• Motor startup current
• Motor braking method
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. Size the bulk capacitance to meet acceptable voltage ripple
levels.
The data sheet generally provides a recommended value but system-level testing is required to determine the
appropriate sized bulk capacitor.
External Power Supply
Parasitic Wire
Inductance
Motor Drive System
VBB
+
±
Motor
Driver
GND
Power Supply
Bulk Cap
Local
Bulk Cap
Local
Filter Cap
Figure 9. Bulk Capacitance
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10 Layout
10.1 Layout Guidelines
The printed circuit board (PCB) should use a heavy ground plane. For optimum electrical and thermal
performance, the DRV8801A-Q1 device must be soldered directly onto the board. On the bottom side of the
DRV8801A-Q1 device is a thermal pad, which provides a path for enhanced thermal dissipation. The thermal pad
should be soldered directly to an exposed surface on the PCB. Thermal vias are used to transfer heat to other
layers of the PCB. For more information on this technique, refer to QFN/SON PCB Attachment.
The load supply pin, VBB, should be decoupled with an electrolytic capacitor (typically 100 μF) in parallel with a
ceramic capacitor placed as close as possible to the device. In order to minimize lead inductance, the ceramic
capacitors between the VCP and VBB pins, connected to the REG pin, and the capacitors between the CP1 and
CP2 pins should be as close to the pins of the device as possible.
10.2 Layout Example
GND
GND
1
GND
PHASE
8
2
VBB
GND
7
3
SENSE
nSLEEP
6
GND
(PPAD)
16
MODE1
15
nFAULT
14
VPROPI
13
VCP
0.1 µF
10
11
12
OUTB
CP1
CP2
GND
VBB
+
9
OUTB
OUTA
4
R(SENSE)
5
ENABLE
OUTA
MODE2
0.1 µF
100 µF
GND
0.1 µF
Figure 10. DRV8801A-Q1 Layout
10.3 Power Dissipation
First-order approximation of power dissipation in the DRV8801A-Q1 device can be calculated by examining the
power dissipation in the full-bridge during each of the operation modes. The DRV8801A-Q1 device uses
synchronous rectification. During the decay cycle, the body diode is shorted by the low-rDS(on) driver, which in turn
reduces power dissipation in the full-bridge. In order to prevent shoot through (high-side and low-side drivers on
the same side are ON at the same time), the DRV8801A-Q1 device implements a 500-ns typical crossover delay
time. During this period, the body diode in the decay current path conducts the current until the DMOS driver
turns on. High-current and high-ambient-temperature applications should take this into consideration. In addition,
motor parameters and switching losses can add power dissipation that could affect critical applications.
16
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
QFN/SON PCB Attachment
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, And Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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6-Jul-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
DRV8801AQRMJRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
WQFN
RMJ
16
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
DRV8801
ARMJQ1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Jul-2016
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Jul-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DRV8801AQRMJRQ1
Package Package Pins
Type Drawing
WQFN
RMJ
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
330.0
12.4
Pack Materials-Page 1
4.25
B0
(mm)
K0
(mm)
P1
(mm)
4.25
1.15
8.0
W
Pin1
(mm) Quadrant
12.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Jul-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV8801AQRMJRQ1
WQFN
RMJ
16
3000
367.0
367.0
35.0
Pack Materials-Page 2
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