Revised March 2000 DM7490A Decade and Binary Counters General Description Features The DM7490A monolithic counter contains four masterslave flip-flops and additional gating to provide a divide-bytwo counter and a three-stage binary counter for which the count cycle length is divide-by-five. ■ Typical power dissipation 145 mW ■ Count frequency 42 MHz The counter has a gated zero reset and also has gated setto-nine inputs for use in BCD nine’s complement applications. To use the maximum count length (decade or four-bit binary), the B input is connected to the QA output. The input count pulses are applied to input A and the outputs are as described in the appropriate Function Table. A symmetrical divide-by-ten count can be obtained from the counters by connecting the QD output to the A input and applying the input count to the B input which gives a divideby-ten square wave at output QA. Ordering Code: Order Number DM7490AN Package Number N14A Package Description 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram © 2000 Fairchild Semiconductor Corporation DS006533 www.fairchildsemi.com DM7490A Decade and Binary Counters August 1986 DM7490A Function Tables Logic Diagram BCD Count Sequence (Note 1) Count Outputs QD QC QB 0 L L L QA L 1 L L L H 2 L L H L 3 L L H H 4 L H L L 5 L H L H 6 L H H L 7 L H H H 8 H L L L 9 H L L H BCD Bi-Quinary (5-2) (Note 2) Count Outputs QA QD QC 0 L L L QB L 1 L L L H 2 L L H L 3 L L H H 4 L H L L 5 H L L L 6 H L L H 7 H L H L 8 H L H H 9 H H L L Reset/Count Function Table Reset Inputs R0(1) R0(2) H H Outputs QD QC QB The J and K inputs shown without connection are for reference only and are functionally at a HIGH level. QA R9(1) R9(2) H L X L L L L H X L L L L L X X H H H L L H X L X L COUNT L X L X COUNT L X X L COUNT X L L X COUNT H = HIGH Level L = LOW Level X = Don’t Care Note 1: Output QA is connected to input B for BCD count. Note 2: Output QD is connected to input A for bi-quinary count www.fairchildsemi.com 2 Supply Voltage Note 3: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 7V Input Voltage 5.5V 0°C to +70°C Operating Free Air Temperature Range −65°C to +150°C Storage Temperature Range Recommended Operating Conditions Symbol Parameter Min Nom Max 4.75 5 5.25 Units VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −0.8 mA IOL LOW Level Output Current 16 mA fCLK Clock Frequency A 0 32 (Note 4) B 0 16 Pulse Width A 15 (Note 4) B 30 Reset 15 tW V 2 tREL Reset Release Time (Note 4) 25 TA Free Air Operating Temperature 0 V MHz ns ns °C 70 Note 4: TA = 25°C and VCC = 5V. DC Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = −12 mA VOH HIGH Level VCC = Min, IOH = Max VOL II IIH IIL Min 2.4 Output Voltage VIL = Max, VIH = Min LOW Level VCC = Min, IOL = Max Output Voltage VIH = Min, VIL = Max (Note 6) Typ (Note 5) Max Units −1.5 V 3.4 0.2 Input Current @ Max Input Voltage VCC = Max, VI = 5.5V V 0.4 V 1 mA HIGH Level VCC = Max A 80 Input Current VI = 2.7V Reset 40 B 120 LOW Level VCC = Max A −3.2 Input Current VI = 0.4V Reset −1.6 B −4.8 IOS Short Circuit Output Current VCC = Max (Note 7) ICC Supply Current VCC = Max (Note 8) −18 29 µA mA −57 mA 42 mA Note 5: All typicals are at VCC = 5V, TA = 25°C. Note 6: QA outputs are tested at IOL = Max plus the limit value of IIL for the B input. This permits driving the B input while maintaining full fan-out capability. Note 7: Not more than one output should be shorted at a time. Note 8: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V, and all other inputs grounded. 3 www.fairchildsemi.com DM7490A Absolute Maximum Ratings(Note 3) DM7490A AC Switching Characteristics at VCC = 5V and TA = 25°C Symbol fMAX tPLH Parameter Min Maximum Clock A to QA 32 Frequency B to QB 16 Propagation Delay Time Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPHL RL = 400Ω, CL = 15 pF To (Output) LOW-to-HIGH Level Output tPHL From (Input) Units MHz A to QA 16 ns A to QA 18 ns A to QD 48 ns A to QD 50 ns B to QB 16 ns B to QB 21 ns B to QC 32 ns B to QC 35 ns B to QD 32 ns B to QD 35 ns SET-9 to QA, QD 30 ns SET-9 to QB, QC 40 ns 40 ns Propagation Delay Time SET-0 HIGH-to-LOW Level Output Any Q www.fairchildsemi.com Max 4 DM7490A Decade and Binary Counters Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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