Cypress CY8C20334-12LQXI Psocâ® mixed-signal array Datasheet

CY8C20534, CY8C20434
CY8C20334, CY8C20234
PSoC® Mixed-Signal Array
Features
■
Low Power CapSense Block
❐ Configurable Capacitive Sensing Elements
❐ Supports Combination of CapSense Buttons, Sliders, Touchpads, and Proximity Sensors
■
Powerful Harvard Architecture Processor
❐ M8C Processor Speeds Running up to 12 MHz
❐ Low Power at High Speed
❐ 2.4V to 5.25V Operating Voltage
❐ Industrial Temperature Range: -40°C to +85°C
■
Flexible On-Chip Memory
❐ 8K Flash Program Storage
50,000 Erase/Write Cycles
❐ 512 Bytes SRAM Data Storage
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ Interrupt Controller
❐ In-System Serial Programming (ISSP)
■
■
Precision, Programmable Clocking
❐ Internal ±5.0% 6/12 MHz Main Oscillator
❐ Internal Low Speed Oscillator at 32 kHz for Watchdog and Sleep
■
Programmable Pin Configurations
❐ Pull Up, High Z, Open Drain, and CMOS Drive Modes on All
GPIO
❐ Up to 28 Analog Inputs on GPIO
❐ Configurable Inputs on All GPIO
❐ Selectable, Regulated Digital IO on Port 1
• 3.0V, 20 mA Total Port 1 Source Current
• 5 mA Strong Drive Mode on Port 1 Versatile Analog Mux
❐ Common Internal Analog Bus
❐ Simultaneous Connection of IO Combinations
❐ Comparator Noise Immunity
❐ Low Dropout Voltage Regulator for the Analog Array
■
Additional System Resources
❐ Configurable Communication Speeds
• I2C: Selectable to 50 kHz, 100 kHz, or 400 kHz
• SPI: Configurable between 46.9 kHz and 3 MHz
❐ I2C™ Slave
❐ SPI Master and SPI Slave
❐ Watchdog and Sleep Timers
❐ Internal Voltage Reference
❐ Integrated Supervisory Circuit
Complete Development Tools
❐ Free Development Tool (PSoC Designer™)
❐ Full Featured, In-Circuit Emulator, and
Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Trace Memory
Logic Block Diagram
Port 3
Port 2
Port 1
Port 0
Config LDO
PSoC
CORE
System Bus
Global Analog Interconnect
SRAM
512 Bytes
SROM
Flash 8K
CPU Core
(M8C)
Interrupt
Controller
Sleep and
Watchdog
6/12 MHz Internal Main Oscillator
ANALOG
SYSTEM
I2C Slave/SPI
Master-Slave
CapSense
Block
Analog
Ref.
POR and LVD
Analog
Mux
System Resets
SYSTEM RESOURCES
Cypress Semiconductor Corporation
Document Number: 001-05356 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 12, 2007
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PSoC Functional Overview
ID AC
Analog Global Bus
The PSoC® family consists of many Mixed Signal Arrays with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU based system components
with one low cost single chip programmable component. A
PSoC device includes configurable analog and digital blocks
and programmable interconnect. This architecture enables the
user to create customized peripheral configurations to match
the requirements of each individual application. Additionally, a
fast CPU, Flash program memory, SRAM data memory, and
configurable IO are included in a range of convenient pinouts.
Figure 1. Analog System Block Diagram
Vr
The PSoC architecture for this device family, as shown in
Figure 1, is comprised of three main areas: the Core, the System Resources, and the CapSense Analog System. A common
versatile bus enables connection between IO and the analog
system. Each CY8C20x34 PSoC device includes a dedicated
CapSense block that provides sensing and scanning control circuitry for capacitive sensing applications. Depending on the
PSoC package, up to 28 general purpose IO (GPIO) are also
included. The GPIO provide access to the MCU and analog
mux.
R eferenc e
Buffer
C internal
C om parator
Mu x
Mu x
R efs
C ap Sens e C ounters
The PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, IMO (Internal
Main Oscillator), and ILO (Internal Low speed Oscillator). The
CPU core, called the M8C, is a powerful processor with speeds
up to 12 MHz. The M8C is a two MIPS, 8-bit Harvard architecture microprocessor.
System Resources provide additional capability such as a configurable I2C slave or SPI master-slave communication interface and various system resets supported by the M8C.
The Analog System is composed of the CapSense PSoC block
and an internal 1.8V analog reference. Together they support
capacitive sensing of up to 28 inputs.
The CapSense Analog System
The Analog System contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware performs capacitive sensing and scanning without requiring external components. Capacitive sensing is configurable on each
GPIO pin. Scanning of enabled CapSense pins is completed
quickly and easily across multiple ports.
Document Number: 001-05356 Rev. *D
CSC LK
IMO
C apSense
C loc k Selec t
R elaxation
O sc illator
(RO)
The Analog Multiplexer System
The Analog Mux Bus connects to every GPIO pin. Pins are connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with the
CapSense block comparator.
Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other
multiplexer applications include:
■
Complex capacitive sensing interfaces such as sliders and
touch pads
■
Chip-wide mux that enables analog input from any IO pin
■
Crosspoint connection between any IO pin combinations
When designing capacitive sensing applications, refer to the latest signal-to-noise signal level requirements Application Notes,
http://www.cypress.com
>>
DESIGN
found
under
RESOURCES >> Application Notes. In general, unless otherwise noted in the relevant Application Notes, the minimum signal-to-noise ratio (SNR) requirement for CapSense applications
is 5:1.
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Additional System Resources
Technical Training Modules
System Resources provide additional capability useful to complete systems. Additional resources include low voltage detection and power on reset. Brief statements describing the merits
of each system resource are presented below.
Free PSoC technical training modules are available for new
users to PSoC. Training modules cover designing, debugging,
advanced
analog,
and
CapSense.
Go
to
http://www.cypress.com/techtrain.
■
The I2C slave or SPI master-slave module provides 50/100/400
kHz communication over two wires. SPI communication over
three or four wires run at speeds of 46.9 kHz to 3 MHz (lower
for a slower system clock).
■
Low Voltage Detection (LVD) interrupts signal the application
of falling voltage levels, while the advanced POR (Power On
Reset) circuit eliminates the need for a system supervisor.
■
An internal 1.8V reference provides an absolute reference for
capacitive sensing.
■
The 5V maximum input, 3V fixed output, low dropout regulator
(LDO) provides regulation for IOs. A register controlled bypass
mode enables the user to disable the LDO.
Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to http://www.cypress.com, click on Design
Support located on the left side of the web page and select
CYPros Consultants.
Technical Support
PSoC application engineers take pride in fast and accurate
response. They are available with a four hour guaranteed
response at http://www.cypress.com/support/login.cfm.
Getting Started
To understand the PSoC silicon read this datasheet and use the
PSoC Designer Integrated Development Environment (IDE).
This datasheet is an overview of the PSoC integrated circuit
and presents specific pin, register, and electrical specifications.
For in depth information, along with detailed programming information, refer to the PSoC Mixed Signal Array Technical Reference Manual on the web at http://www.cypress.com/psoc.
For up to date Ordering, Packaging, and Electrical Specification
information, refer to the latest PSoC device datasheets on the
web at http://www.cypress.com.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at
http://www.cypress.com, click the Online Store shopping cart
icon at the bottom of the web page and click PSoC (Programmable System-on-Chip) to view a current list of available items.
Application Notes
A long list of application notes assist you in every aspect of your
design effort. To view the PSoC application notes, go to the
http://www.cypress.com and select Application Notes under the
Design Resources list located in the center of the web page.
Application notes are sorted by date by default.
Development Tools
PSoC Designer is a Microsoft® Windows based, integrated
development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE and
application runs on Windows NT 4.0, Windows 2000, Windows
Millennium (Me), or Windows XP. For more information, see
Figure 2 on page 4.
PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
PSoC Designer also supports a high level C language compiler
developed specifically for the devices in the family.
Document Number: 001-05356 Rev. *D
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Figure 2. PSoC Designer Subsystems
Graphical Designer
Interface
Context
Sensitive
Help
Results
Commands
PSoC
Designer
Application
Database
PSoC
Designer
Core
Engine
Project
Database
The macro assembler enables the assembly code for seamless
merging with C code. The link libraries automatically use absolute addressing or are compiled in relative mode and linked with
other software modules to get absolute addressing.
C Language Compiler
C language compiler supports the PSoC family of devices. It
quickly enables you to create complete C programs for the
PSoC family devices.
Importable
Design
Database
Device
Database
Assembler
PSoC
Configuration
Sheet
Manufacturing
Information
File
User
Modules
Library
The embedded optimizing C compiler provides all the features
of C language tailored to the PSoC architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math
functionality.
Debugger
PSoC Designer Software Subsystems
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, enabling the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands enable the designer to read the
program, read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints,
and provide program run, halt, and step control. The debugger
also enables the designer to create a trace buffer of registers
and memory locations of interest.
Device Editor
Online Help System
The device editor subsystem enables the user to select different
on board analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
The online help system displays online and context sensitive
help for the user. Designed for procedural and quick reference,
each functional subsystem has its own context sensitive help.
This system also provides tutorials and links to FAQs and an
Online Support Forum to aid the designer to get started.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic reconfiguration enables changing configurations at run time.
PSoC Designer sets up power on initialization tables for
selected PSoC block configurations and creates source code
for an application framework. The framework contains software
to operate the selected components. If the project uses more
than one operating configuration, then it contains routines to
switch between different sets of PSoC block configurations at
run time. PSoC Designer prints out a configuration sheet for a
given project configuration for use during application programming in conjunction with the device datasheet. Once the framework is generated, the user adds application specific code to
flesh out the framework. It is also possible to change the
selected components and regenerate the framework.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability
to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
Application Editor
Application Editor edits C language and Assembly language
source code. It also assembles, compiles, links, and builds.
Document Number: 001-05356 Rev. *D
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Designing with User Modules
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture
a unique flexibility. It pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources are called PSoC Blocks. They
implement a wide variety of user selectable functions. Each
block has several registers to determine their function and connectivity to other blocks, multiplexers, buses, and to the IO pins.
Iterative development cycles permit you to adapt the hardware
and the software. This substantially lowers the risk of selecting
a different part to meet the final design requirements.
To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of
pre-built and pre-tested hardware peripheral functions called as
User Modules. User modules make selecting and implementing
peripheral devices simple. They come in analog, digital, and
mixed signal varieties.
Each user module establishes the basic register settings to
implement the selected function. It also provides parameters to
tailor its precise configuration to a particular application. For
example, a Pulse Width Modulator user module configures one
or more digital PSoC blocks, one for each 8-bits of resolution.
The user module parameters permit you to establish the pulse
width and duty cycle. User modules also provide tested software to cut the development time. The user module application
programming interface (API) provides high level functions to
control and respond to hardware events at run time. The API
also provides optional interrupt service routines to adapt as
needed.
The API functions are documented in user module datasheets
that are viewed directly in the PSoC Designer IDE. These
datasheets explain the internal operation of the user module
and provide performance specifications. Each datasheet
describes the use of each user module parameter and documents the setting of each register controlled by the user module.
The development process starts when you open a new project
and bring up the Device Editor, a graphical user interface (GUI)
for configuring the hardware. Select the user modules you need
for your project and map them on to the PSoC blocks with
point-and-click simplicity. Then, build signal chains by interconnecting the user modules to each other and the IO pins. At this
stage, configure the clock source connections and enter parameter values directly or by selecting values from the drop down
menus. When the hardware configuration is ready for testing or
moves on to developing code for the project, perform the “Generate Application” step. The PSoC Designer generates the
source code that automatically configures the device to your
specification and provides the high level user module API functions.
Document Number: 001-05356 Rev. *D
Figure 3. User Module and Source Code Development Flows
Device Editor
User
Module
Selection
Placement
and
Parameter
-ization
Source
Code
Generator
Generate
Application
Application Editor
Project
Manager
Source
Code
Editor
Build
Manager
Build
All
Debugger
Interface
to ICE
Storage
Inspector
Event &
Breakpoint
Manager
Now write the main program and any sub-routines using PSoC
Designer’s Application Editor subsystem. The Application Editor includes a Project Manager that enables to open the project
source code files (including all generated code files) from a
hierarchal view. The source code editor provides syntax coloring and advanced edit features for both C and assembly language. File search capabilities include simple string searches
and recursive “grep-style” patterns. A single mouse click
invokes the Build Manager. It employs a professional strength
“makefile” system to automatically analyze all file dependencies
and run the compiler and assembler as necessary. Project level
options control optimization strategies used by the compiler and
linker. Syntax errors are displayed in a console window. Double
click the error message to show the offending line of source
code. When all is correct, the linker builds a HEX file image suitable for programming.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it
runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single step,
run-to-breakpoint, and watch variable features, the Debugger
provides a large trace buffer. This enables to define complex
breakpoint events such as monitoring address and data bus
values, memory locations, and external signals.
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Document Conventions
Units of Measure
Acronyms Used
A units of measure table is located in the Electrical Specifications section. Table 6 on page 13 lists all the abbreviations used
to measure the PSoC devices.
The following table lists the acronyms that are used in this document.
Numeric Naming
Acronym
Description
AC
alternating current
API
application programming interface
CPU
central processing unit
DC
direct current
GPIO
general purpose IO
GUI
graphical user interface
ICE
in-circuit emulator
ILO
internal low speed oscillator
IMO
internal main oscillator
IO
input or output
LSb
least significant bit
LVD
low voltage detect
MSb
most significant bit
POR
power on reset
PPOR
precision power on reset
PSoC®
Programmable System-on-Chip™
SLIMO
slow IMO
SRAM
static random access memory
Document Number: 001-05356 Rev. *D
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers are also represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (For example, 01010100b or
01000011b). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimals.
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Pinouts
This section describes, lists, and illustrates the CY8C20234, CY8C20334, CY8C20434, and CY8C20534 PSoC device pins and
pinout configurations.
The CY8C20x34 PSoC device is available in a variety of packages that are listed and shown in the following tables. Every port pin
(labeled with a “P”) is capable of Digital IO and connection to the common analog bus. However, Vss, Vdd, and XRES are not capable of Digital IO.
16-Pin Part Pinout
P0[1], AI
P0[3], AI
P0[7], AI
Vdd
15
14
13
12
7
8
Vss
9
AI, DATA, I2C SDA, P1[0]
6
Q FN
11
(Top View ) 10
5
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SD A, SPI M ISO , P1[5]
1
2
3
4
AI, SPI CLK, P1[3]
AI, P2[1]
CLK, I2C SCL, SPI MOSI P1[1]
AI, P2[5]
16
Figure 4. CY8C20234 16-Pin PSoC Device
P0[4], AI
XRES
P1[4], AI, EXTCLK
P1[2], AI
Table 1. 16-Pin Part Pinout (QFN[2])
Type
Name
Description
Digital
Analog
1
IO
I
P2[5]
2
IO
I
P2[1]
3
IOH
I
P1[7]
I2C SCL, SPI SS.
4
IOH
I
P1[5]
I2C SDA, SPI MISO.
5
IOH
I
P1[3]
SPI CLK.
6
IOH
I
P1[1]
CLK[1], I2C SCL, SPI MOSI.
7
Power
Vss
Ground connection.
8
IOH
I
P1[0]
DATA[1], I2C SDA.
9
IOH
I
P1[2]
10
IOH
I
P1[4]
Optional external clock input (EXTCLK).
11
Input
XRES
Active high external reset with internal pull down.
12
IO
I
P0[4]
13
Power
Vdd
Supply voltage.
14
IO
I
P0[7]
15
IO
I
P0[3]
Integrating input.
16
IO
I
P0[1]
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive
Pin No.
Notes
1. These are the ISSP pins, that are not High Z at POR (Power On Reset). See the PSoC Mixed Signal Array Technical Reference Manual for details.
2. The center pad on the QFN package is connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it is electrically
floated and not connected to any other signal.
Document Number: 001-05356 Rev. *D
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24-Pin Part Pinout
20
19
10
11
12
P0[7], AI
Vdd
P0[6], AI
P0[1], AI
P0[3], AI
P0[5], AI
23
22
21
18
17
16
15
14
13
P0[4], AI
P0[2], AI
P0[0], AI
P2[0], AI
XRES
P1[6], AI
AI, EXTCLK, P1[4]
Vss
AI, DATA*, I2C SDA, P1[0]
AI, P1[2]
7
8
9
1
2
QFN
3
4 (Top View)
5
6
NC
P2[5]
P2[3]
P2[1]
P1[7]
P1[5]
P1[3]
AI, CLK*, I2C SCL
SPI MOSI, P1[1]
AI,
AI,
AI,
AI, I2C SCL, SPI SS,
AI, I2C SDA, SPI MISO,
AI, SPI CLK,
24
Figure 5. CY8C20334 24-Pin PSoC Device
Table 2. 24-Pin Part Pinout (QFN [2])
Pin No.
Digital
IO
IO
IO
IOH
IOH
IOH
IOH
Type
Analog
I
I
I
I
I
I
I
Name
Description
1
P2[5]
2
P2[3]
3
P2[1]
4
P1[7]
I2C SCL, SPI SS.
5
P1[5]
I2C SDA, SPI MISO.
6
P1[3]
SPI CLK.
7
P1[1]
CLK[1], I2C SCL, SPI MOSI.
8
NC
No connection.
9
Power
Vss
Ground connection.
10
IOH
I
P1[0]
DATA[1], I2C SDA.
11
IOH
I
P1[2]
12
IOH
I
P1[4]
Optional external clock input (EXTCLK).
13
IOH
I
P1[6]
14
Input
XRES
Active high external reset with internal pull down.
15
IO
I
P2[0]
16
IO
I
P0[0]
17
IO
I
P0[2]
18
IO
I
P0[4]
19
IO
I
P0[6]
Analog bypass.
20
Power
Vdd
Supply voltage.
21
IO
I
P0[7]
22
IO
I
P0[5]
23
IO
I
P0[3]
Integrating input.
24
IO
I
P0[1]
CP
Power
Vss
Center pad is connected to ground.
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive
Document Number: 001-05356 Rev. *D
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28-Pin Part Pinout
Figure 6. CY8C20534 28-Pin PSoC Device
A, I, M, P0[7]
A, I, M, P0[5]
A, I, M, P0[3]
A, I, M, P0[1]
M,P2[7]
M,P2[5]
M, P2[3]
M, P2[1]
Vss
M,I2C SCL,P1[7]
M,I2C SDA, P1[5]
M,P1[3]
M,I2C SCL,P1[1]
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
P0[0], A, I, M
P2[6],M
P2[4],M
P2[2],M
P2[0],M
XRES
P1[6],M
P1[4], EXTCLK,M
P1[2],M
P1[0],I2C SDA, M
Table 3. 28-Pin Part Pinout (SSOP )
Type
Name
Description
Digital
Analog
1
IO
I, M
P0[7]
Analog column mux input.
2
IO
I, M
P0[5]
Analog column mux input and column output.
3
IO
I, M
P0[3]
Analog column mux input and column output, integrating input.
4
IO
I, M
P0[1]
Analog column mux input, integrating input.
5
IO
M
P2[7]
6
IO
M
P2[5]
7
IO
I, M
P2[3]
Direct switched capacitor block input.
8
IO
I, M
P2[1]
Direct switched capacitor block input.
9
Power
Vss
Ground connection.
10
IO
M
P1[7]
I2C Serial Clock (SCL).
11
IO
M
P1[5]
I2C Serial Data (SDA).
12
IO
M
P1[3]
13
IO
M
P1[1]
I2C Serial Clock (SCL), ISSP-SCLK[1].
14
Power
Vss
Ground connection.
15
IO
M
P1[0]
I2C Serial Data (SDA), ISSP-SDATA[1].
16
IO
M
P1[2]
17
IO
M
P1[4]
Optional External Clock Input (EXTCLK).
18
IO
M
P1[6]
19
Input
XRES
Active high external reset with internal pull down.
20
IO
I, M
P2[0]
Direct switched capacitor block input.
21
IO
I, M
P2[2]
Direct switched capacitor block input.
22
IO
M
P2[4]
23
IO
M
P2[6]
24
IO
I, M
P0[0]
Analog column mux input.
25
IO
I, M
P0[2]
Analog column mux input.
26
IO
I, M
P0[4]
Analog column mux input
27
IO
I, M
P0[6]
Analog column mux input.
28
Power
Vdd
Supply voltage.
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive.
Pin No.
Document Number: 001-05356 Rev. *D
Page 9 of 34
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CY8C20534, CY8C20434
CY8C20334, CY8C20234
32-Pin Part Pinout
Vdd
P0[6], AI
P0[4], AI
P0[2], AI
27
26
25
P0[7], AI
29
28
Vss
P0[3], AI
P0[5], AI
31
30
14
15
16
AI, P1[2]
AI, EXTCLK, P1[4]
AI, P1[6]
12
Vss
13
11
AI, CLK*, I2C SCL, SPI MOSI, P1[1]
24
23
22
21
20
19
18
17
AI, DATA*, I2C SDA, P1[0]
9
A I, I2 C S C L
Q FN
(T o p V ie w )
10
A I, P 3 [1 ]
S P I S S , P 1 [7 ]
1
2
3
4
5
6
7
8
AI, SPI CLK, P1[3]
P 0 [1 ]
P 2 [7 ]
P 2 [5 ]
P 2 [3 ]
P 2 [1 ]
P 3 [3 ]
AI, I2C SDA, SPI MISO, P1[5]
A I,
A I,
A I,
A I,
A I,
A I,
32
Figure 7. CY8C20434 32-Pin PSoC Device
P 0 [0 ], A I
P 2 [6 ], A I
P 2 [4 ], A I
P 2 [2 ], A I
P 2 [0 ], A I
P 3 [2 ], A I
P 3 [0 ], A I
XRES
Table 4. 32-Pin Part Pinout (QFN [2])
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Digital
IO
IO
IO
IO
IO
IO
IO
IOH
IOH
IOH
IOH
Power
IOH
IOH
IOH
IOH
Input
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Type
Analog
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Name
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P3[3]
P3[1]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
P1[0]
P1[2]
P1[4]
P1[6]
XRES
P3[0]
P3[2]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Document Number: 001-05356 Rev. *D
Description
I2C SCL, SPI SS.
I2C SDA, SPI MISO.
SPI CLK.
CLK[1], I2C SCL, SPI MOSI.
Ground connection.
DATA[1], I2C SDA.
Optional external clock input (EXTCLK).
Active high external reset with internal pull down.
Analog bypass.
Page 10 of 34
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CY8C20334, CY8C20234
Table 4. 32-Pin Part Pinout (QFN [2]) (continued)
28
Power
Vdd
Supply voltage.
29
IO
I
P0[7]
30
IO
I
P0[5]
31
IO
I
P0[3]
Integrating input.
32
Power
Vss
Ground connection.
CP
Power
Vss
Center pad is connected to ground.
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive.
48-Pin OCD Part Pinout
The 48-Pin QFN part table and pin diagram is for the CY8C20000 On-Chip Debug (OCD) PSoC device. This part is only used for
in-circuit debugging. It is NOT available for production.
NC
NC
38
37
OCDO
Vdd
P0[6], AI
NC
OCDE
42
41
40
39
P0[7], AI
43
P0[5], AI
45
44
46
1
2
3
4
5
6
7
8
9
10
11
12
OCD
QFN
36
35
34
33
32
31
30
29
28
27
26
25
P0[4], AI
P0[2], AI
P0[0], AI
P2[6], AI
P2[4], AI
P2[2], AI
P2[0], AI
P3[2], AI
P3[0], AI
XRES
P1[6], AI
P1[4], EXTCLK, AI
NC
NC
22
23
24
NC
AI, P1[2]
20
21
AI, DATA*, I2C SDA, P1[0]
HCLK
18
19
CCLK
17
15
16
AI, SPI CLK, P1[3]
AI, CLK*, I2C SCL, SPI MOSI, P1[1]
Vss
13
14
(Top View)
NC
NC
NC
AI, P0[1]
AI, P2[7]
AI, P2[5]
AI, P2[3]
AI, P2[1]
AI, P3[3]
AI, P3[1]
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
NC
NC
48
47
NC
Vss
P0[3], AI
Figure 8. CY8C20000 OCD PSoC Device
Table 5. 48-Pin OCD Part Pinout (QFN [2])
Pin No.
Digital
Analog
1
Name
NC
Description
No connection.
2
IO
I
P0[1]
3
IO
I
P2[7]
4
IO
I
P2[5]
5
IO
I
P2[3]
6
IO
I
P2[1]
7
IO
I
P3[3]
8
IO
I
P3[1]
9
IOH
I
P1[7]
I2C SCL, SPI SS.
10
IOH
I
P1[5]
I2C SDA, SPI MISO.
Document Number: 001-05356 Rev. *D
Page 11 of 34
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CY8C20334, CY8C20234
Table 5. 48-Pin OCD Part Pinout (QFN [2]) (continued)
Pin No.
11
Digital
IO
Analog
I
Name
Description
P0[1]
12
NC
No connection.
13
NC
No connection.
14
NC
No connection.
15
NC
No connection.
16
IOH
I
P1[3]
SPI CLK.
17
IOH
I
P1[1]
CLK[1], I2C SCL, SPI MOSI.
18
Power
Vss
Ground connection.
19
CCLK
OCD CPU clock output.
20
HCLK
OCD high speed clock output.
DATA[1], I2C SDA.
21
IOH
I
P1[0]
22
IOH
I
P1[2]
23
NC
No connection.
24
NC
No connection.
25
NC
No connection.
26
IOH
I
P1[4]
Optional external clock input (EXTCLK).
27
IOH
I
P1[6]
28
Input
29
IO
I
P3[0]
30
IO
I
P3[2]
31
IO
I
P2[0]
32
IO
I
P2[2]
33
IO
I
P2[4]
34
IO
I
P2[6]
35
IO
I
P0[0]
36
IO
I
P0[2]
XRES
Active high external reset with internal pull down.
37
NC
No connection.
38
NC
No connection.
NC
No connection.
P0[6]
Analog bypass.
Vdd
Supply voltage.
OCDO
OCD odd data output.
OCDE
OCD even data IO.
39
40
IO
41
Power
I
42
43
44
IO
I
P0[7]
45
IO
I
P0[5]
46
IO
I
P0[3]
Integrating input.
47
Power
Vss
Ground connection.
NC
No connection.
Vss
Center pad is connected to ground.
48
CP
Power
A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive.
Document Number: 001-05356 Rev. *D
Page 12 of 34
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CY8C20534, CY8C20434
CY8C20334, CY8C20234
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C20234, CY8C20334, CY8C20434, and CY8C20534 PSoC
devices. For the latest electrical specifications, check the most recent datasheet by visiting the web at http://www.cypress.com/psoc.
Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC as specified, except where mentioned.
Refer to Table 16 on page 19 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.
Figure 9. Voltage versus CPU Frequency and IMO Frequency Trim Options
5.25
5.25
SLIMO SLIMO SLIMO
Mode=1 Mode=1 Mode=0
4.75
Vdd Voltage
Vdd Voltage
lid ng
Va rati n
pe gio
Re
O
4.75
3.60
SLIMO SLIMO
Mode=1 Mode=0
3.00
3.00
2.70
2.70
2.40
2.40
750 kHz
3 MHz
6 MHz
SLIMO
Mode=1
750 kHz
12 MHz
3 MHz
6 MHz
SLIMO
Mode=0
12 MHz
IMO Frequency
CPU Frequency
Table 6 lists the units of measure that are used in this section.
Table 6. Units of Measure
Symbol
o
C
dB
fF
Hz
KB
Kbit
kHz
kΩ
MHz
MΩ
μA
μF
μH
μs
μV
μVrms
Unit of Measure
degree Celsius
decibels
femto farad
hertz
1024 bytes
1024 bits
kilohertz
kilohm
megahertz
megaohm
microampere
microfarad
microhenry
microsecond
microvolts
microvolts root-mean-square
Document Number: 001-05356 Rev. *D
Symbol
μW
mA
ms
mV
nA
ns
nV
W
pA
pF
pp
ppm
ps
sps
s
V
Unit of Measure
microwatts
milliampere
millisecond
millivolts
nanoampere
nanosecond
nanovolts
ohm
picoampere
picofarad
peak-to-peak
parts per million
picosecond
samples per second
sigma: one standard deviation
volts
Page 13 of 34
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CY8C20334, CY8C20234
Absolute Maximum Ratings
Table 7. Absolute Maximum Ratings
Symbol
TSTG
Description
Storage Temperature
Min
-55
Typ
25
Max
+100
TA
Vdd
VIO
Ambient Temperature with Power Applied
Supply Voltage on Vdd Relative to Vss
DC Input Voltage
–
–
–
VIOZ
DC Voltage Applied to Tri-state
IMIO
ESD
LU
Maximum Current into any Port Pin
Electro Static Discharge Voltage
Latch up Current
-40
-0.5
Vss 0.5
Vss 0.5
-25
2000
–
+85
+6.0
Vdd +
0.5
Vdd +
0.5
+50
–
200
–
–
–
–
Units
C
o
Notes
Higher storage temperatures reduces
data retention time. Recommended
storage temperature is +25oC ± 25oC.
Extended duration storage temperatures above 65oC degrades reliability.
o
C
V
V
V
mA
V
mA
Human Body Model ESD.
Operating Temperature
Table 8. Operating Temperature
Symbol
TA
TJ
Description
Ambient Temperature
Junction Temperature
Document Number: 001-05356 Rev. *D
Min
-40
-40
Typ
–
–
Max
+85
+100
Units
Notes
oC
oC
The temperature rise from ambient to
junction is package specific. See
Table 14 on page 17. The user must
limit the power consumption to comply
with this requirement.
Page 14 of 34
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CY8C20334, CY8C20234
DC Electrical Characteristics
DC Chip Level Specifications
Table 9 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤
TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V,
3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 9. DC Chip Level Specifications
Symbol
Vdd
IDD12
Supply Voltage
Supply Current, IMO = 12 MHz
2.40
–
–
1.5
5.25
2.5
V
mA
IDD6
Supply Current, IMO = 6 MHz
–
1
1.5
mA
ISB27
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and Internal Slow Oscillator
Active. Mid Temperature Range.
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and Internal Slow Oscillator
Active.
–
2.6
4.
μA
See Table 14 on page 17.
Conditions are Vdd = 3.0V, TA = 25oC,
CPU = 12 MHz.
Conditions are Vdd = 3.0V, TA = 25oC,
CPU = 6 MHz.
Vdd = 2.55V, 0oC ≤ TA ≤ 40oC.
–
2.8
5
μA
Vdd = 3.3V, -40oC ≤ TA ≤ 85oC.
ISB
Description
Min
Typ
Max
Units
Notes
DC General Purpose IO Specifications
Unless otherwise noted, the Table 10 lists guaranteed maximum and minimum specifications for the voltage and temperature
ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C. These are for design guidance only.
Table 10. 5V and 3.3V DC GPIO Specifications
Symbol
Description
RPU
Pull Up Resistor
VOH1
High Output Voltage
Port 0, 2, or 3 Pins
VOH2
High Output Voltage
Port 0, 2, or 3 Pins
VOH3
High Output Voltage
Port 1 Pins with LDO Regulator Disabled
VOH4
High Output Voltage
Port 1 Pins with LDO Regulator Disabled
VOH5
High Output Voltage
Port 1 Pins with 3.0V LDO Regulator Enabled
VOH6
High Output Voltage
Port 1 Pins with 3.0V LDO Regulator Enabled
VOH7
High Output Voltage
Port 1 Pins with 2.4V LDO Regulator Enabled
VOH8
High Output Voltage
Port 1 Pins with 2.4V LDO Regulator Enabled
VOH9
High Output Voltage
Port 1 Pins with 1.8V LDO Regulator Enabled
Document Number: 001-05356 Rev. *D
Min
Typ
5.6
–
Max
8
–
Units
kΩ
V
–
–
V
–
–
V
–
–
V
3.0
3.2
V
2.2
–
–
V
2.1
2.4
2.5
V
2.0
–
–
V
1.6
1.8
1.95
V
4
Vdd 0.2
Vdd 0.9
Vdd 0.2
Vdd 0.9
2.75
Notes
IOH < 10 μA, Vdd > 3.0V, maximum of
20 mA source current in all IOs.
IOH = 1 mA, Vdd > 3.0V, maximum of
20 mA source current in all IOs.
IOH < 10 μA, Vdd > 3.0V, maximum of
10 mA source current in all IOs.
IOH = 5 mA, Vdd > 3.0V, maximum of
20 mA source current in all IOs.
IOH < 10 μA, Vdd > 3.1V, maximum of
4 IOs all sourcing 5 mA.
IOH = 5 mA, Vdd > 3.1V, maximum of
20 mA source current in all IOs.
IOH < 10 μA, Vdd > 3.0V, maximum of
20 mA source current in all IOs.
IOH < 200 μA, Vdd > 3.0V, maximum
of 20 mA source current in all IOs.
IOH < 10 μA.
3.0V ≤ Vdd ≤ 3.6V.
0oC ≤ TA ≤ 85oC.
Maximum of 20 mA source current in
all IOs.
Page 15 of 34
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CY8C20334, CY8C20234
Table 10. 5V and 3.3V DC GPIO Specifications (continued)
VOH10
High Output Voltage
1.5
Port 1 Pins with 1.8V LDO Regulator Enabled
–
–
V
VOL
Low Output Voltage
–
–
0.75
V
VIL
VIH
VH
IIL
CIN
Input Low Voltage
Input High Voltage
Input Hysteresis Voltage
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
–
2.0
–
–
0.5
–
–
140
1
1.7
0.8
–
–
5
V
V
mV
nA
pF
COUT
Capacitive Load on Pins as Output
0.5
1.7
5
pF
IOH < 100 μA.
3.0V ≤ Vdd ≤ 3.6V.
0oC ≤ TA ≤ 85oC.
Maximum of 20 mA source current in
all IOs.
IOL = 20 mA, Vdd > 3.0V, maximum of
60 mA sink current on even port pins
(for example, P0[2] and P1[4]) and 60
mA sink current on odd port pins (for
example, P0[3] and P1[5]).
3.6V ≤ Vdd ≤ 5.25V.
3.6V ≤ Vdd ≤ 5.25V.
Gross tested to 1 μA.
Package and pin dependent Temperature = 25oC.
Package and pin dependent Temperature = 25oC.
Table 11. 2.7V DC GPIO Specifications
Symbol
RPU
VOH1
VOL
Description
Pull Up Resistor
High Output Voltage
Port 1 Pins with LDO Regulator Disabled
High Output Voltage
Port 1 Pins with LDO Regulator Disabled
Low Output Voltage
4
Vdd 0.2
Vdd 0.5
–
VOLP1
Low Output Voltage Port 1 Pins
VIL
VIH1
VIH2
VH
IIL
CIN
COUT
VOH2
Typ
5.6
–
8
–
–
–
–
0.75
–
–
0.4
Input Low Voltage
Input High Voltage
Input High Voltage
Input Hysteresis Voltage
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
–
1.4
1.6
–
–
0.5
–
–
–
60
1
1.7
0.75
–
–
–
–
5
Capacitive Load on Pins as Output
0.5
1.7
5
Document Number: 001-05356 Rev. *D
Min
Max
Units
Notes
kΩ
V
IOH < 10 μA, maximum of 10 mA
source current in all IOs.
V
IOH = 2 mA, maximum of 10 mA source
current in all IOs.
V
IOL = 10 mA, maximum of 30 mA sink
current on even port pins (for example,
P0[2] and P1[4]) and 30 mA sink
current on odd port pins (for example,
P0[3] and P1[5]).
V
IOL=5 mA
Maximum of 50 mA sink current on
even port pins (for example, P0[2] and
P3[4]) and 50 mA sink current on odd
port pins (for example, P0[3] and
P2[5]).
2.4V ≤ Vdd < 3.6V.
V
2.4V ≤ Vdd < 3.6V.
V
2.4V ≤ Vdd < 2.7V.
V
2.7V ≤ Vdd < 3.6V.
mV
nA
Gross tested to 1 μA.
pF
Package and pin dependent Temperature = 25oC.
pF
Package and pin dependent Temperature = 25oC.
Page 16 of 34
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CY8C20334, CY8C20234
DC Analog Mux Bus Specifications
Table 12 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 12. DC Analog Mux Bus Specifications
Symbol
RSW
Description
Switch Resistance to Common Analog Bus
Min
Typ
–
–
Max
400
800
Units
W
W
Notes
Vdd ≥ 2.7V
2.4V ≤ Vdd ≤ 2.7V
DC Low Power Comparator Specifications
Table 13 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V at 25°C. These are for design guidance only.
Table 13. DC Low Power Comparator Specifications
Symbol
VREFLPC
ISLPC
VOSLPC
Description
Low power comparator (LPC) reference
voltage range
LPC supply current
LPC voltage offset
Min
0.2
–
Typ
Max
Units
Vdd – 1 V
–
–
10
2.5
40
30
Notes
μA
mV
DC POR and LVD Specifications
Table 14 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 14. DC POR and LVD Specifications
Symbol
Description
Min
Typ
Max
Units
VPPOR0
VPPOR1
VPPOR2
Vdd Value for PPOR Trip
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
–
–
–
2.36
2.60
2.82
2.40
2.65
2.95
V
V
V
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.39
2.54
2.75
2.85
2.96
–
–
4.52
2.45
2.71
2.92
3.02
3.13
–
–
4.73
2.51[3]
2.78[4]
2.99[5]
3.09
3.20
–
–
4.83
V
V
V
V
V
V
V
V
Notes
Vdd is greater than or equal to 2.5V
during startup, reset from the XRES
pin, or reset from Watchdog.
Notes
3. Always greater than 50 mV above VPPOR (PORLEV = 00) for falling supply.
4. Always greater than 50 mV above VPPOR (PORLEV = 01) for falling supply.
5. Always greater than 50 mV above VPPOR (PORLEV = 10) for falling supply.
Document Number: 001-05356 Rev. *D
Page 17 of 34
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CY8C20334, CY8C20234
DC Programming Specifications
Table 15 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 15. DC Programming Specifications
Symbol
Description
VddIWRITE Supply Voltage for Flash Write Operations
IDDP
Supply Current During Programming or Verify
VILP
Input Low Voltage During Programming or
Verify
VIHP
Input High Voltage During Programming or
Verify
IILP
Input Current when Applying Vilp to P1[0] or
P1[1] During Programming or Verify
IIHP
Input Current when Applying Vihp to P1[0] or
P1[1] During Programming or Verify
VOLV
Output Low Voltage During Programming or
Verify
VOHV
Output High Voltage During Programming or
Verify
FlashENPB Flash Endurance (per block)
FlashENT Flash Endurance (total)[6]
FlashDR
Flash Data Retention
Min
2.70
–
–
–
5
–
Typ
Max
–
25
0.8
Units
V
mA
V
2.2
–
–
V
–
–
0.2
mA
–
–
1.5
mA
–
–
V
Vdd
–1.0
50,000
1,800,0
00
10
–
Vss +
0.75
Vdd
–
–
–
–
–
–
–
–
Years
Notes
Driving internal pull down
resistor.
Driving internal pull down
resistor.
V
Erase/write cycles per block.
Erase/write cycles.
Note
6. A maximum of 36 x 50,000 block endurance cycles is allowed. This is balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of
25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees
more than 50,000 cycles).
Document Number: 001-05356 Rev. *D
Page 18 of 34
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AC Electrical Characteristics
AC Chip Level Specifications
Table 16, Table 17, and Table 18 list guaranteed maximum and minimum specifications for the voltage and temperature ranges:
4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 16. 5V and 3.3V AC Chip-Level Specifications
Symbol
FCPU1
F32K1
FIMO12
Description
Min
CPU Frequency (3.3V Nominal)
0.75
Internal Low Speed Oscillator Frequency
15
Internal Main Oscillator Stability for 12 MHz 11.4
(Commercial Temperature)[7]
Typ
–
32
12
Max
12.6
64
12.6
Units
MHz
kHz
MHz
FIMO6
Internal Main Oscillator Stability for 6 MHz
(Commercial Temperature)
5.70
6.0
6.30
MHz
DCIMO
TRAMP
TXRST
Duty Cycle of IMO
Supply Ramp Time
External Reset Pulse Width
40
0
10
50
–
–
60
–
–
%
μs
μs
Description
CPU Frequency (2.7V Nominal)
Internal Low Speed Oscillator Frequency
Internal Main Oscillator Stability for 12
MHz
(Commercial Temperature)[7]
Internal Main Oscillator Stability for 6 MHz
(Commercial Temperature)
Min
0.75
8
11.0
Typ
–
32
12
Max
3.25
96
12.9
Units
MHz
kHz
MHz
5.60
6.0
6.40
MHz
Duty Cycle of IMO
Supply Ramp Time
External Reset Pulse Width
40
0
10
50
–
–
60
–
–
%
μs
μs
Max
6.3
96
12.9
Units
MHz
kHz
MHz
Notes
12 MHz only for SLIMO Mode = 0.
Trimmed for 3.3V operation using
factory trim values.
See Figure 2-1b, SLIMO Mode = 0.
Trimmed for 3.3V operation using
factory trim values.
See Figure 2-1b, SLIMO Mode = 1.
Table 17. 2.7V AC Chip Level Specifications
Symbol
FCPU1
F32K1
FIMO12
FIMO6
DCIMO
TRAMP
TXRST
Notes
Trimmed for 2.7V operation using
factory trim values.
See Figure 2-1b, SLIMO Mode = 0.
Trimmed for 2.7V operation using
factory trim values.
See Figure 2-1b, SLIMO Mode = 1.
Table 18. 2.7V AC Chip Level Specifications
Symbol
FCPU1
F32K1
FIMO12
Description
Min
CPU Frequency (2.7V Minimum)
0.75
Internal Low Speed Oscillator Frequency
8
Internal Main Oscillator Stability for 12 MHz 11.0
(Commercial Temperature)[7]
Typ
–
32
12
Notes
Trimmed for 2.7V operation using
factory trim values.
See Figure 2-1b, SLIMO Mode = 0.
Note
7. 0 to 70 °C ambient, Vdd = 3.3 V.
Document Number: 001-05356 Rev. *D
Page 19 of 34
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Table 18. 2.7V AC Chip Level Specifications (continued)
Symbol
FIMO6
Description
Internal Main Oscillator Stability for 6 MHz
(Commercial Temperature)
Min
5.60
Typ
6.0
Max
6.40
Units
MHz
DCIMO
TRAMP
TXRST
Duty Cycle of IMO
Supply Ramp Time
External Reset Pulse Width
40
0
10
50
–
–
60
–
–
%
μs
μs
Notes
Trimmed for 2.7V operation using
factory trim values.
See Figure 2-1b, SLIMO Mode = 1.
AC General Purpose IO Specifications
Table 19 and Table 20 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 19. 5V and 3.3V AC GPIO Specifications
Symbol
Description
FGPIO
GPIO Operating Frequency
TRise023 Rise Time, Strong Mode, Cload = 50 pF
Ports 0, 2, 3
TRise1
Rise Time, Strong Mode, Cload = 50 pF
Port 1
TFall
Fall Time, Strong Mode, Cload = 50 pF
All Ports
Min
Typ
Max
0
15
–
–
6
80
Units
MHz
ns
Notes
Normal Strong Mode, Port 1.
Vdd = 3.0 to 3.6V and 4.75V to 5.25V,
10% - 90%
Vdd = 3.0 to 3.6V, 10% - 90%
10
–
50
ns
10
–
50
ns
Vdd = 3.0 to 3.6V and 4.75V to 5.25V,
10% - 90%
Min
0
15
–
–
Max
1.5
100
Units
MHz
ns
Notes
Normal Strong Mode, Port 1.
Vdd = 2.4 to 3.0V, 10% - 90%
10
–
70
ns
Vdd = 2.4 to 3.0V, 10% - 90%
10
–
70
ns
Vdd = 2.4 to 3.0V, 10% - 90%
Table 20. 2.7V AC GPIO Specifications
Symbol
Description
FGPIO
GPIO Operating Frequency
TRise023 Rise Time, Strong Mode, Cload = 50 pF
Ports 0, 2, 3
TRise1
Rise Time, Strong Mode, Cload = 50 pF
Port 1
TFall
Fall Time, Strong Mode, Cload = 50 pF
All Ports
Typ
Figure 10. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRise023
TRise1
Document Number: 001-05356 Rev. *D
TFall
Page 20 of 34
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AC Comparator Amplifier Specifications
Table 21 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 21. AC Operational Amplifier Specifications
Symbol
TCOMP
Description
Comparator Response Time, 50 mV Overdrive
Min
Typ
Max
100
200
Units
ns
ns
Notes
Vdd ≥ 3.0V.
2.4V < Vcc < 3.0V.
AC Analog Mux Bus Specifications
Table 22 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 22. AC Analog Mux Bus Specifications
Symbol
FSW
Description
Switch Rate
Min
–
Typ
–
Max
3.17
Units
Notes
MHz
AC Low Power Comparator Specifications
Table 23 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V at 25°C. These are for design guidance only.
Table 23. AC Low Power Comparator Specifications
Symbol
TRLPC
Description
LPC response time
Min
–
Typ
–
Max
50
Units
μs
Notes
≥ 50 mV overdrive comparator
reference set within VREFLPC.
AC External Clock Specifications
Table 24, Table 25, Table 26, and Table 27 list guaranteed maximum and minimum specifications for the voltage and temperature
ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 24. 5V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
FOSCEXT
Frequency
0.750
–
12.6
MHz
–
High Period
38
–
5300
ns
–
Low Period
38
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
Document Number: 001-05356 Rev. *D
Notes
Page 21 of 34
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Table 25. 3.3V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
FOSCEXT
Frequency with CPU Clock divide by 1
0.750
–
12.6
MHz
–
High Period with CPU Clock divide by 1
41.7
–
5300
ns
–
Low Period with CPU Clock divide by 1
41.7
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
Notes
Maximum CPU frequency is 12 MHz
at 3.3V. With the CPU clock divider
set to 1, the external clock must
adhere to the maximum frequency
and duty cycle requirements.
Table 26. 2.7V (Nominal) AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
FOSCEXT
Frequency with CPU Clock divide by 1
0.750
–
3.080
MHz
Maximum CPU frequency is 3 MHz at
2.7V. With the CPU clock divider set
to 1, the external clock must adhere to
the maximum frequency and duty
cycle requirements.
FOSCEXT
Frequency with CPU Clock divide by 2 or
greater
0.15
–
6.35
MHz
If the frequency of the external clock
is greater than 3 MHz, the CPU clock
divider is set to 2 or greater. In this
case, the CPU clock divider ensures
that the fifty percent duty cycle
requirement is met.
–
High Period with CPU Clock divide by 1
160
–
5300
ns
–
Low Period with CPU Clock divide by 1
160
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
Table 27. 2.7V (Minimum) AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
FOSCEXT
Frequency with CPU Clock divide by 1
0.750
–
6.30
FOSCEXT
Frequency with CPU Clock divide by 2 or
greater
0.15
–
12.6
MHz
–
High Period with CPU Clock divide by 1
160
–
5300
ns
–
Low Period with CPU Clock divide by 1
160
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
Document Number: 001-05356 Rev. *D
Notes
MHz
Maximum CPU frequency is 6 MHz at
2.7V. With the CPU clock divider set
to 1, the external clock must adhere to
the maximum frequency and duty
cycle requirements.
If the frequency of the external clock
is greater than 6 MHz, the CPU clock
divider is set to 2 or greater. In this
case, the CPU clock divider ensures
that the fifty percent duty cycle
requirement is met.
Page 22 of 34
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AC Programming Specifications
Table 28 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 28. AC Programming Specifications
Symbol
TRSCLK
TFSCLK
TSSCLK
THSCLK
FSCLK
TERASEB
TWRITE
TDSCLK
TDSCLK3
TDSCLK2
Description
Rise Time of SCLK
Fall Time of SCLK
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
Flash Erase Time (Block)
Flash Block Write Time
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
Min
1
1
40
40
0
–
–
–
–
–
Typ
–
–
–
–
–
15
30
–
–
–
Max
20
20
–
–
8
–
–
45
50
70
Units
ns
ns
ns
ns
MHz
ms
ms
ns
ns
ns
Notes
3.6 < Vdd
3.0 ≤ Vdd ≤ 3.6
2.4 ≤ Vdd ≤ 3.0
AC SPI Specifications
Table 29 and Table 30 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 29. 5V and 3.3V AC SPI Specifications
Symbol
Description
Min
Typ
Max
Units
FSPIM
Maximum Input Clock Frequency Selection, –
Master
–
6.3
MHz
FSPIS
Maximum Input Clock Frequency Selection, –
Slave
–
2.05
MHz
TSS
Width of SS_ Negated Between Transmissions
–
–
ns
50
Notes
Output clock frequency is half of input
clock rate
Table 30. 2.7V AC SPI Specifications
Symbol
Description
Min
Typ
Max
Units
FSPIM
Maximum Input Clock Frequency Selection, –
Master
–
3.15
MHz
FSPIS
Maximum Input Clock Frequency Selection, –
Slave
–
1.025
MHz
TSS
Width of SS_ Negated Between Transmissions
–
–
ns
Document Number: 001-05356 Rev. *D
50
Notes
Output clock frequency is half of input
clock rate
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AC I2C Specifications
Table 31 and Table 32 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 31. AC Characteristics of the I2C SDA and SCL Pins for Vdd ≥ 3.0V
Symbol
FSCLI2C
THDSTAI2C
TLOWI2C
THIGHI2C
TSUSTAI2C
THDDATI2C
TSUDATI2C
TSUSTOI2C
TBUFI2C
TSPI2C
Standard Mode
Fast Mode
Min
Max
Min
Max
SCL Clock Frequency
0
100
0
400
Hold Time (repeated) START Condition. After this 4.0
–
0.6
–
period, the first clock pulse is generated
LOW Period of the SCL Clock
4.7
–
1.3
–
HIGH Period of the SCL Clock
4.0
–
0.6
–
Setup Time for a Repeated START Condition
4.7
–
0.6
–
Data Hold Time
0
–
0
–
Data Setup Time
250
–
100[8] –
Setup Time for STOP Condition
4.0
–
0.6
–
Bus Free Time Between a STOP and START
4.7
–
1.3
–
Condition
Pulse Width of spikes are suppressed by the input –
–
0
50
filter
Description
Units
Notes
kHz
μs
μs
μs
μs
μs
ns
μs
μs
ns
Note
8. A Fast Mode I2C bus device is used in a Standard Mode I2C bus system but the requirement tSU; DAT Š 250 ns is met. This automatically is the case if the device
does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax
+ tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard Mode I2C bus specification) before the SCL line is released.
Document Number: 001-05356 Rev. *D
Page 24 of 34
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Table 32. 2.7V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported)
Symbol
FSCLI2C
THDSTAI2C
TLOWI2C
THIGHI2C
TSUSTAI2C
THDDATI2C
TSUDATI2C
TSUSTOI2C
TBUFI2C
TSPI2C
Standard Mode
Fast Mode
Min
Max
Min
Max
SCL Clock Frequency.
0
100
–
–
Hold Time (repeated) START Condition. After 4.0
–
–
–
this period, the first clock pulse is generated.
LOW Period of the SCL Clock.
4.7
–
–
–
HIGH Period of the SCL Clock
4.0
–
–
–
Setup Time for a Repeated START Condition. 4.7
–
–
–
Data Hold Time.
0
–
–
–
Data Setup Time.
250
–
–
–
Setup Time for STOP Condition.
4.0
–
–
–
Bus Free Time Between a STOP and START 4.7
–
–
–
Condition.
Pulse Width of spikes are suppressed by the –
–
–
–
input filter.
Description
Units
Notes
kHz
μs
μs
μs
μs
μs
ns
μs
μs
ns
Figure 11. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
T LOWI2C
T SPI2C
T SUDATI2C
T HDSTAI2C
T BUFI2C
SCL
S
T HDSTAI2C T HDDATI2C T HIGHI2C
Document Number: 001-05356 Rev. *D
T SUSTAI2C
Sr
T SUSTOI2C
P
S
Page 25 of 34
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Packaging Dimensions
This section illustrates the packaging specifications for the CY8C20234, CY8C20334, CY8C20434, and CY8C20534 PSoC devices
along with the thermal impedances for each package.
It is important to note that emulation tools require a larger area on the target PCB than the chip’s footprint. For a detailed description
of the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Figure 12. 16-Pin (3x3 mm x 0.6 MAX) QFN
001-09116 *C
Document Number: 001-05356 Rev. *D
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Figure 13. 24-Pin (4x4 x 0.6 mm) QFN
001-13937 *A
Figure 14. 28-Lead (210-Mil) SSOP
51-85079 *C
Document Number: 001-05356 Rev. *D
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Figure 15. 32-Pin (5x5 mm 0.60 MAX) QFN
001-06392 *A
Document Number: 001-05356 Rev. *D
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Figure 16. 48-Pin (7x7 mm) QFN
001-12919 *A
For information on the preferred dimensions for mounting the QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
It is important to note that pinned vias for thermal conduction are not required for the low power 24-, 32-, and 48-pin QFN PSoC
devices.
Document Number: 001-05356 Rev. *D
Page 29 of 34
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Thermal Impedances
Table 33. Thermal Impedances Per Package
Package
Typical θJA [9]
46 C/W
25 oC/W
96 oC/W
27 oC/W
28 oC/W
o
16 QFN
24 QFN[10]
28 SSOP[10]
32 QFN[10]
48 QFN[10]
Solder Reflow Peak Temperature
Table 34 illustrates the minimum solder reflow peak temperature to achieve good solderability.
Table 34. Solder Reflow Peak Temperature
Package
Minimum Peak
Temperature [11]
Maximum Peak
Temperature
line of code. Users work directly with application objects such
as LEDs, switches, sensors, and fans. PSoC Express is available free of charge at http://www.cypress.com/psocexpress.
PSoC Programmer
PSoC Programmer is flexible enough and is used on the bench
in development and also suitable for factory programming.
PSoC Programmer works either as a standalone programming
application or operates directly from PSoC Designer or PSoC
Express. PSoC Programmer software is compatible with both
PSoC ICE Cube In-Circuit Emulator and PSoC MiniProg. PSoC
programmer
is
available
free
of
charge
at
http://www.cypress.com/psocprogrammer.
CY3202-C iMAGEcraft C Compiler
CY3202 is the optional upgrade to PSoC Designer that enables
the iMAGEcraft C compiler. It is available at the Cypress Online
Store. At http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page and click PSoC
(Programmable System-on-Chip) to view a current list of available items.
16 QFN
240oC
260oC
24 QFN
240oC
260oC
28 SSOP 240oC
260oC
Development Kits
32 QFN
240oC
260oC
All development kits are sold at the Cypress Online Store.
48 QFN
240oC
260oC
CY3215-DK Basic Development Kit
Development Tool Selection
Software
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface enables users to run, halt, and single step the processor and view the content of specific memory locations. PSoC
Designer supports the advance emulation features also. The kit
includes:
PSoC Designer™
■
PSoC Designer Software CD
At the core of the PSoC development software suite is PSoC
Designer. This is used by thousands of PSoC developers. This
robust software is facilitating PSoC designs for half a decade.
PSoC Designer is available free of charge at
http://www.cypress.com under DESIGN RESOURCES >> Software and Drivers.
■
ICE-Cube In-Circuit Emulator
■
ICE Flex-Pod for CY8C29x66 Family
■
Cat-5 Adapter
■
Mini-Eval Programming Board
■
110 ~ 240V Power Supply, Euro-Plug Adapter
PSoC Express™
■
iMAGEcraft C Compiler (Registration Required)
As the latest addition to the PSoC development software suite,
PSoC Express is the first visual embedded system design tool
that enables a user to create an entire PSoC project and generate a schematic, BOM, and datasheet without writing a single
■
ISSP Cable
■
USB 2.0 Cable and Blue Cat-5 Cable
■
2 CY8C29466-24PXI 28-PDIP Chip Samples
Notes
9. TJ = TA + Power x θJA.
10. To achieve the thermal impedance specified for the ** package, the center thermal pad is soldered to the PCB ground plane.
11. Higher temperatures is required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu paste. Refer
to the solder manufacturer specifications.
Document Number: 001-05356 Rev. *D
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CY3210-ExpressDK PSoC Express Development Kit
CY3210-PSoCEval1
The CY3210-ExpressDK is for advanced prototyping and development with PSoC Express (used with ICE-Cube In-Circuit
Emulator). It provides access to I2C buses, voltage reference,
switches, upgradeable modules, and more. The kit includes:
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit
includes:
■
PSoC Express Software CD
■
Express Development Board
■
Four Fan Modules
■
Two Proto Modules
■
MiniProg In-System Serial Programmer
■
MiniEval PCB Evaluation Board
■
Jumper Wire Kit
■
USB 2.0 Cable
CY3214-PSoCEvalUSB
■
Serial Cable (DB9)
■
110 ~ 240V Power Supply, Euro-Plug Adapter
■
2 CY8C24423A-24PXI 28-PDIP Chip Samples
■
2 CY8C27443-24PXI 28-PDIP Chip Samples
■
2 CY8C29466-24PXI 28-PDIP Chip Samples
The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. Special
features of the board include both USB and capacitive sensing
development and debugging support. This evaluation board
also includes an LCD module, potentiometer, LEDs, an enunciator and plenty of bread boarding space to meet all of your evaluation needs. The kit includes:
■
Evaluation Board with LCD Module
■
MiniProg Programming Unit
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
■
PSoCEvalUSB Board
■
LCD Module
■
MIniProg Programming Unit
■
Mini USB Cable
CY3210-MiniProg1
■
PSoC Designer and Example Projects CD
The CY3210-MiniProg1 kit enables the user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
■
Getting Started Guide
■
Wire Pack
■
MiniProg Programming Unit
Device Programmers
■
MiniEval Socket Programming and Evaluation Board
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
All device programmers are purchased from the Cypress Online
Store.
■
28-Pin CY8C27443-24PXI PDIP PSoC Device Sample
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
Evaluation Tools
All evaluation tools are sold at the Cypress Online Store.
Document Number: 001-05356 Rev. *D
CY3216 Modular Programmer
The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
■
Modular Programmer Base
■
3 Programming Module Cards
■
MiniProg Programming Unit
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
Page 31 of 34
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CY8C20534, CY8C20434
CY8C20334, CY8C20234
CY3207ISSP In-System Serial Programmer (ISSP)
The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than
the MiniProg in a production programming environment.
Note that CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes:
■
CY3207 Programmer Unit
■
PSoC ISSP Software CD
■
110 ~ 240V Power Supply, Euro-Plug Adapter
■
USB 2.0 Cable
Accessories (Emulation and Programming)
Table 35. Emulation and Programming Accessories
Part Number
Pin
Package
CY8C20234-12LKXI
16 SOIC
CY8C20334-12LQXI
24 QFN
CY8C20534-12PVXI
28 SSOP
CY8C20434-12LKXI
32 QFN
Flex-Pod Kit [12]
CY3250-20334QFN
CY3250-20434QFN
Foot Kit [13]
Prototyping
Module
CY3250-16QFN-FK
CY3210-0X34
CY3250-24QFN-FK
CY3210-0X34
CY3250-28SSOP-FK
CY3210-0X34
CY3250-32QFN-FK
CY3210-0X34
Adapter [14]
AS-24-28-01ML-6
AS-32-28-03ML-6
Third Party Tools
Build a PSoC Emulator into Your Board
Several tools are specially designed by the following third party
vendors to accompany PSoC devices during development and
production. Specific details of each of these tools are found at
http://www.cypress.com under DESIGN RESOURCES >> Evaluation Boards.
For details on emulating the circuit before going to volume production using an on-chip debug (OCD) non-production PSoC
device, see Application Note “Debugging - Build a PSoC Emulator
into
Your
Board
AN2323”
at
http://www.cypress.com/design/AN2323.
Notes
12. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
13. Foot kit includes surface mount feet that is soldered to the target PCB.
14. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters is found at
http://www.emulation.com.
Document Number: 001-05356 Rev. *D
Page 32 of 34
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CY8C20534, CY8C20434
CY8C20334, CY8C20234
Ordering Information
Table 36 lists the CY8C20234, CY8C20334, CY8C20434, and CY8C20534 PSoC device’s key package features and ordering
codes.
Table 36. PSoC Device Key Features and Ordering Information
Package
Ordering
Code
Flash
(Bytes)
SRAM
(Bytes)
Digital CapSense
Blocks
Blocks
Digital
IO
Pins
Analog
Inputs
[15]
Analog
Outputs
XRES
Pin
16-Pin (3x3 mm 0.60
MAX) QFN
CY8C20234-12LKXI
8K
512
0
1
13
13[15]
0
Yes
16-Pin (3x3 mm 0.60
MAX) QFN
(Tape and Reel)
CY8C20234-12LKXIT 8K
512
0
1
13
13[15]
0
Yes
24-Pin (4x4 mm 0.60
MAX) QFN
CY8C20334-12LQXI
8K
512
0
1
20
20[15]
0
Yes
24-Pin (4x4 mm 0.60
MAX) QFN
(Tape and Reel)
CY8C20334-12LQXIT 8K
512
0
1
20
20[15]
0
Yes
28-Pin (210-Mil) SSOP CY8C20534-PVXI
8K
512
0
1
24
24
0
Yes
28-Pin (210-Mil) SSOP CY8C20534-PVXIT
(Tape and Reel)
8K
512
0
1
24
24
0
Yes
32-Pin (5x5 mm 0.60
MAX) QFN
CY8C20434-12LKXI
8K
512
0
1
28
28[15]
0
Yes
32-Pin (5x5 mm 0.60
MAX) QFN
(Tape and Reel)
CY8C20434-12LKXIT 8K
512
0
1
28
28[15]
0
Yes
48-Pin OCD QFN[16]
CY8C20000-12LFXI
512
0
1
28
28[15]
0
Yes
8K
Figure 17. Ordering Code Definitions
CY 8 C 20 xxx- 12 xx
Package Type:
Thermal Rating:
PX = PDIP Pb-Free
C = Commercial
SX = SOIC Pb-Free
I = Industrial
PVX = SSOP Pb-Free
E = Extended
LFX = QFN Pb-Free
LKX/LQX = QFN Pb-Free
AX = TQFP Pb-Free
Speed: 12 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Notes
15. Dual function Digital IO Pins also connect to the common analog mux.
16. This part may be used for in-circuit debugging. It is NOT available for production.
Document Number: 001-05356 Rev. *D
Page 33 of 34
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CY8C20534, CY8C20434
CY8C20334, CY8C20234
Document History Page
Document Title: CY8C20234, CY8C20334, CY8C20434, CY8C20534 PSoC® Mixed-Signal Array
Document Number: 001-05356
Revision
ECN
Orig. of
Change
Description of Change
**
404571
HMT
New silicon and document (Revision **).
*A
418513
HMT
Updated Electrical Specifications, including Storage Temperature and Maximum Input Clock
Frequency. Updated Features and Analog System Overview. Modified 32-pin QFN E-PAD
dimensions. Added new 32-pin QFN. Add High Output Drive indicator to all P1[x] pinouts.
Updated trademarks.
*B
490071
HMT
Made datasheet “Final”. Added new Development Tool section. Added OCD pinout and
package diagram. Added 16-pin QFN. Updated 24-pin and 32-pin QFN package diagrams to
0.60 MAX thickness. Changed from commercial to industrial temperature range. Updated
Storage Temperature specification and notes. Updated thermal resistance data. Added development tool kit part numbers. Finetuned features and electrical specifications.
*C
788177
HMT
Added CapSense SNR requirement reference. Added Low Power Comparator (LPC) AC/DC
electrical specifications tables. Added 2.7V minimum specifications. Updated figure
standards. Updated Technical Training paragraph. Added QFN package clarifications and
dimensions. Updated ECN-ed Amkor dimensioned QFN package diagram revisions.
*D
1356805
HMT/SFVTMP Updated 24-pin QFN Theta JA. Added External Reset Pulse Width, TXRST, specification.
3/HCL/SFV
Fixed 48-pin QFN.vsd. Updated the table introduction and high output voltage description in
section two. The sentence: "Exceeding maximum ratings may shorten the battery life of the
device.” does not apply to all data sheets. Therefore, the word "battery" is changed to "useful.”
Took out tabs after table and figure numbers in titles and added two hard spaces. Updated
the section, DC General Purpose IO Specifications on page 15 with new text. Updated VOH5
and VOH6 to say, ”High Output Voltage, Port 1 Pins with 3.0V LDO Regulator Enabled.”
Updated VOH7 and VOH8 with the text, “maximum of 20 mA source current in all IOs.”Added
28-pin SSOP part, pinout, package. Updated specs. Modified dev. tool part numbers.
© Cypress Semiconductor Corporation, 2005-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-05356 Rev. *D
Revised November 12, 2007
Page 34 of 34
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
trademarks referenced herein are property of the respective corporations.Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the
Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.All products and company names
mentioned in this document may be the trademarks of their respective holders.
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