Fujitsu MB15C02 Single serial input pll frequency synthesizer on-chip prescaler Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
DS04–21348–3E
ASSP
Single Serial Input
PLL Frequency Synthesizer
On-Chip prescaler
MB15C02
■ DESCRIPTION
The Fujitsu MB15C02 is a serial input Phase Locked Loop (PLL) frequency synthesizer with a prescaler. A 64/65
division is available for the prescaler that enables pulse swallow operation.
This operates with a supply voltage of 1.0 V (min.).
MB15C02 is suitable for mobile communications, such as paging systems.
■ FEATURES
• High frequency operation: 220 MHz max @VDD = 1.0 V to 1.5 V
330 MHz max @VDD = 1.2 V to 1.5 V
450 MHz max @VDD = 1.3 V to 1.5 V
• Single power supply : VDD = 1.0 to 1.5 V
• Power saving function
• Pulse swallow function: 64/65
• Serial input 14-bit programmable reference divider: R = 5 to 16,383
• Serial input 18-bit programmable divider consisting of:
- Binary 6-bit swallow counter: 0 to 63
- Binary 12-bit programmable counter: 5 to 4,095
• Wide operating temperature: Ta = –20 to 60°C
■ PACKAGES
16-pin, Plastic SSOP
20-pin, Plastic SSOP
(FPT-16P-M05)
(FPT-20P-M03)
1
MB15C02
■ PIN ASSIGNMENTS
SSOP-20 pin
VDD
1
20
VSS
Clock
2
19
OSCIN
NC
3
18
NC
Data
4
17
OSCOUT
LE
5
Top
View 16
fin
6
15
FC
PS
7
14
φP
NC
8
13
NC
LD
9
12
φR
Do
10
11
Vp
TEST
(FPT-20P-M03)
SSOP-16 pin
VDD
1
16
VSS
Clock
2
15
OSCIN
Data
3
14
OSCOUT
LE
4
13
TEST
fin
5
12
FC
PS
6
11
φP
LD
7
10
φR
Do
8
9
Vp
Top
View
(FPT-16P-M05)
2
MB15C02
■ PIN DESCRIPTIONS
Pin no.
SSOP SSOP
16
20
Pin
name
I/O
Descriptions
1
1
VDD
–
Power supply voltage
2
2
Clock
I
Clock input for the shift register.(Schmitt trigger input)
Data is shifted into the shift register on the rising edge of the clock.
–
3
NC
–
No connection
3
4
Data
I
Serial data input using binary code.(Schmitt trigger input)
4
5
LE
I
Load enable signal input (Schmitt trigger input)
When LE is high, the data in the shift register is transferred to a latch,
according to the control bit in the serial data.
5
6
fin
I
Prescaler input.
A bias circuit and amplifier are at input port. Connection with an external
VCO should be done by AC coupling.
6
7
PS
I
Power saving mode control. This pin must be set at “L” at Power-ON.
PS = “H” ; Normal mode
PS = “L” ; Power saving mode
–
8
NC
–
No connection
7
9
LD
O
Lock detector signal output.
When a PLL is locking, LD outputs “H”.
When a PLL is not locking, LD outputs “L”.
8
10
Do
O
Charge pump output.
Phase of the charge pump can be reversed by FC input. The Do output
may be inverted by FC input. The relationships between the programmable
reference divider output (fr) and the programmable divider output (fp) are
shown below;
fr > fp :“H” level (FC = “L”), “L” level (FC = “H”)
fr = fp : High impedance
fr < fp :“L” level (FC = “L”), “H” level (FC = “H”)
9
11
Vp
–
Power supply for the charge pump.
10
12
φR
O
Phase comparator output pin (for external charge pump). Relation between
the programmable reference divider output (fr) and the programmable divider
output (fp) are shown below;
When FC = “L”
fr > fp : φR = “L” level, φP = “L” level
fr = fp : φR = “L” level, φP = High impedance
fr < fp : φR = “H” level, φP = High impedance
When FC = “H”
fr > fp : φR = “H” level, φP = High impedance
fr = fp : φR = “L” level, φP = High impedance
fr < fp : φR = “L” level, φP = “L” level
–
13
NC
–
No connection
11
14
φP
O
Phase comparator output pin (for external charge pump). Refer to Pin
description for φR. φP pin is a Nch open drain output.
12
15
FC
I
Phase comparator input select pin.
13
16
TEST
I
Test mode select pin. (Pull down resistor)
Please set this pin to ground or open usually.
(Continued)
3
MB15C02
(Continued)
Pin no.
SSOP SSOP
16
20
4
Pin
name
I/O
Descriptions
14
17
OSCOUT
O
Oscillator output.
Connection for an external crystal.
–
18
NC
–
No connection
15
19
OSCIN
I
Programmable reference divider input.
Oscillator input.
Clock can be input to OSCIN from outside. In the case, please leave OSCOUT
pin open and make connection with OSCIN as AC coupling.
16
20
VSS
–
Ground pin.
MB15C02
■ BLOCK DIAGRAM
Crystal
oscillator
circuit
VDD
Programmable
reference divider
VSS
OSCIN
Binary 14-bit
reference counter
Intermittent
mode control
circuit
14
OSCOUT
14-bit latch
Clock
fr
Phase
comparator
fp
14
18-bit shift register
Data
TEST
Control
register
FC
Output
control
circuit
φP
Output
control
circuit
φR
18
LE
18-bit latch
6
12
fin
PS
Prescaler
Binary 6-bit
swallow
counter
Binary 12-bit
programmable counter
Charge
pump
VP
LD
Lock detector
Control circuit
Do
5
MB15C02
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Power supply voltage
Rating
Unit
Min.
Max.
VDD, VP
GND–0.5
+2.0
V
VIN
GND–0.5
VDD +0.5
V
Output voltage
VOUT
GND–0.5
VDD +0.5
V
Output current
IOUT
–10
+10
mA
Storage temperature
Tstg
–40
+125
°C
Input voltage
Remark
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Power supply voltage
Symbol
VDD, VP
Value
Min.
Typ.
Max.
1.0
–
1.5
1.2
–
1.5
1.3
–
1.5
Unit
Remark
For 220 MHz
V
For 330 MHz
VDD = VP
For 450 MHz
Input voltage
VIN
GND
–
VDD
V
Operating temperature
Ta
–20
–
+60
°C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
6
MB15C02
■ ELECTRICAL CHARACTERISTICS
(For 220 MHz :VDD = Vp = 1.0 to 1.5 V, Ta = –20 to +60°C)
(For 330 MHz :VDD = Vp = 1.2 to 1.5 V, Ta = –20 to +60°C)
(For 450 MHz :VDD = Vp = 1.3 to 1.5 V, Ta = –20 to +60°C)
Parameter
Symbol
Condition
Value
Min.
Typ.*3
Max.*4
Unit
Power supply current
Active Mode
IDD *1
(VDD=1.0V/220MHz)
(VDD=1.2V/330MHz)
(VDD=1.3V/450MHz)
–
–
–
0.6
1.0
1.3
1.2
1.8
2.2
mA
Power saving current
Power saving mode
IDDS *2
(VDD=1.0V)
(VDD=1.2V)
(VDD=1.3V)
–
–
–
50
70
80
250
300
350
µA
10
10
10
–
–
–
220
330
450
5
–
20
MHz
fin
fin
Programmable divider
(VDD=1.0 to 1.5V)
(VDD=1.2 to 1.5V)
(VDD=1.3 to 1.5V)
OSCIN
fOSC
Programmable
reference divider
fin
Vfin
AC coupling
–2.0
–
–
dBm
OSCin
VOSC
AC coupling
–2.0
–
–
dBm
Operating frequency
Input sensitivity
Input voltage
Input current
Output voltage
MHz
Except for
fin and
OSCin
H level
VIH
–
VDD –
0.2
–
–
L level
VIL
–
–
–
0.2
Except for
fin, OSCin
and TEST
H level
IIH
VIN=VDD
–
–
+1.0
L level
IIL
VIN=GND
–1.0
–
–
Except for
OSCOUT
and φP
H level
VOH
IOH = –0.2 mA
VDD –
0.2
–
–
L level
VOL
IOL = 0.2 mA
–
–
0.2
φP
L level
VOL
IOL = 0.2 mA
–
–
0.2
V
IOFF1
VOUT = GND to VP
–100
–
100
nA
IOFF2
VOUT = VDD
–
–
100
nA
High impedance Do
cutoff current
φP
V
µA
V
*1: Conditions; Inputs except for fin, OSCIN and TEST are grounded, Outputs are opened.
Specifying the current flowing in VDD and Vp at operating state under conditions of VDD = Vp, fin =
220 MHz, or 330 MHz, and OSCIN = 12.8 MHz.
The current at locking state shows IDD Supply current (P.20).
*2: Conditions; PS = Low, Inputs except for fin, OSCIN and TEST are grounded, Outputs are opened.
*3: Condition; Ta = 25°C
*4: Condition; Ta = –20 to +60°C
7
MB15C02
■ FUNCTION DESCRIPTIONS
1. Pulse Swallow Function
The divide ratio can be calculated using the following equation:
fVCO = [(M × N) + A] × fOSC ÷ R (A < N)
fVCO
N
A
fOSC
R
M
:
:
:
:
:
:
Output frequency of external voltage controlled oscillator (VCO)
Preset divide ratio of binary 12-bit programmable counter (5 to 4,095)
Preset divide ratio of binary 6-bit swallow counter (0 to 63)
Output frequency of the reference frequency oscillator
Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383)
Preset modulus of dual modulus prescaler (64)
2. Circuit Description
(1) Intermittent operation
The intermittent operation of the MB15C02 refers to the process of activating and deactivating its internal circuit
thus saving power dissipation otherwise consumed by the circuit. If the circuit is simply restarted from the power
saving state, however, the phase relation between the reference frequency (fr) and the programmable frequency
(fp), which are the input to the phase comparator, is not stable even when they are of the same value. This may
cause the phase comparator to generate an excessively large error signal, resulting in an out-of-synth lock frequency
To preclude the occurrence of this problem, the MB15C02 has an intermittent mode control circuit which forces the
frequencies into phase with each other when the IC is reactivated, thus minimizing the error signal and resultant
lock frequency fluctuations. The intermittent mode control circuit is controlled by the PS pin. Setting pin PS high
provides the normal operation mode and setting the pin low provides the power saving mode. The MB15C02 behavior
in the active and power saving modes is summarized below.
Active mode (PS = “H”)
All MB15C02 circuits are active and provide the normal operation.
Power saving mode (PS = “L”)
The MB15C02 stops any circuits that consume power heavily as well as cause little inconvenience when deactivated
and enters the low-power dissipation state. Do, φR, φP, and LD pins take the same state as when the PLL is locked.
Do pin becomes a high-impedance state and the input voltage to the voltage control oscillator (VCO) is maintained
at the same level as in active mode(that is, locked state) according to a time constant of a low pass filter (LPF).
Consequently , the output frequency from the VCO (fvco) is maintained at approximately the lock frequency.
Applying the intermittent operation by alternating the active and power saving modes, and also forcing the phases
of fr and fp to synchronize when it switches from stand by to active modes, the MB15C02 can keep the power
dissipation of its entire circuitry to the minimum.
(2) Programmable divider
The fvco input through fin pin is divided by the programmable divider and then output to the phase comparator as
fp. It consists of a dual modulus prescaler, a 6-bit binary swallow counter, a 12-bit binary programmable counter,
and a controller which controls the divide ratio of the prescaler
8
MB15C02
Divide ratio range:
Prescaler : M = 64, M+1=65
Swallow counter : A = 0 to 63
Programmable counter : N = 5 to 4095
The MB15C02 uses the pulse swallow method; consequently, the divide rations of the swallow and programmable
counters must satisfy the relationship N>A.
The total divide ratio of the programmable divider is calculated as follows:
Total divide ratio = (M + 1) × A + M × (N – A) = M × N + A = 64 × N + A
When N is set within 5<N<63, the possible divide ratio A of the swallow counter can take values 0<A<N-1 because
N must be greater than A. For example, 0<A<19 is allowed when N=20 but 20<A<63 is not allowed in that case.
Consequently, N>64 must be satisfied for the total divider to be set within 0<A<63.
The fp and fin have the following relation:
fp = fin / (64 × N + A)
(3) Programmable reference divider
The programmable reference divider divides the reference oscillation frequency(fosc) from the crystal oscillator
connected between OSCin and OSCout pins or from the external oscillator input taken in directly through OSCin,
pin and then, sends the resultant fr to the phase comparator. It consists of a 14-bit binary programmable reference
counter. When the output from the external oscillator is to be input directly to OSCin, pin the connection must be
AC coupled and OSCout pin is left open. Also, to prevent OSCout from malfunctioning, its traces on the printed
circuit board must be kept minimal or eliminated entirely; whenever possible, it must be free of any form of load.
The following divider is used:
Programmable reference counter : R = 5 to 16383
The fr and fosc have the following relation:
fr = fosc / R
(4) Phase comparator
The phase comparator detects the phase difference between the outputs fr and fp from the dividers and generates
an error signal that is proportional to phase difference. The outputs from the phase comparator include 1) Do which
takes on one of the three states, namely, “L” (low), “H” (high), and “Z” (high impedance), and is sent to the LPF,
2)φR, 3)φP, 4)LD which indicates the PLL lock or unlock states.
(a) Phase comparator
The phase comparator detects the phase error between fr and fp, then generates an error signal that is
proportional to the phase error. The roles of the fr and fp supplied to the phase comparator may be reversed
by switching the logical input level of pin FC. This inverts the logical level of the Do output. The logical level of
Do output may be selected according to the characteristics of the external LPF and the VCO. (Refer to Table 1.)
Table. 1 Phase comparator inputs/output relationships
FC = “L”
FC = “H”
Output
Phase
relation
fr > fp
Do
φR
φP
Do
φR
φP
H
L
L
L
H
Z
fr = fp
Z
L
Z
Z
L
Z
fr < fp
L
H
Z
H
L
L
9
MB15C02
(b) Charge pump
The charge pump is available in two forms: internal external.
Internal charge pump output (Do)
External charge pump outputs (φR, φP)
(c) Phase comparator input/output waveforms
The phase comparator outputs logic levels summarized in Table 1, according to the phase error between fr
and fp. Note that φP is an Nch open drain output. The pulse width of the phase comparator outputs are identical
and equal to the phase error between fr and fp as shown in Figure 1.
fr
fp
When FC = “L”
High Z
Do
φR
φP
High Z
When FC = “H”
High Z
Do
φR
φP
High Z
High Z : High impedance state
fp
: Nch open output
Figure 1. Phase comparator input/output waveform
10
MB15C02
(d) Lock detector
The lock detector detects the lock and unlock states of the PLL. The lock detector outputs “H” when the PLL
enters the lock state and outputs “L” when the PLL enters the unlock state as shown in Figure 2. When PS =
“L”, the lock detector outputs “H” compulsorily.
fr
fp
LD
Figure 2. Phase comparator input/output waveforms (Lock detector)
11
MB15C02
4. Setting the Divide Ratio
(1) Serial data format
The format of the serial data is shown is Figure 3. The serial data is composed of a control bit and divide ratio
setting data. The control bit selects the programmable divider or programmable reference divider.
In case of the programmable divider, serial data consists of 18 bits(6 bits for the swallow counter and 12 bits for the
programmable counter) and 1 control bit as shown in Figure 3.1. In case of the programmable reference divider,
the serial data consists of 14 divider bits and 1 control bit as shown in Figure 3.2.
The control bit is set to 0 to identify the serial data for the programmable divider and to 1 to select the serial data
for the programmable reference divider.
Figure 3. Serial data format
MSB
LSB
Direction of data input
C
A
0
A
1
A
2
A
3
A
4
A
5
N
0
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
Programmable counter
Swallow counter
control bit
Figure 3.1. Divide ratio for the programmable divider
LSB
MSB
Direction of data input
C
R
0
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
10
R
11
R
12
R
13
Programmable reference counter
control bit
Figure 3.2. Divide ratio for the programmable reference divider
12
N
10
N
11
MB15C02
(2) The flow of serial data
Serial data is received via data pin in synchronization with the clock input and loaded into shift register which contains
the divide ratio setting data and into the control register which contains the control bit. The logical product (through
the AND gate in Figure 4) of LE and the control register output (i.e., control bit) is fed to the enable input of the
latches. Accordingly, when LE is set high, the latch for the divider identified by the control bit is enabled and the
divide ratio data from the shift register is loaded into the selected counter (s).
Programmable
reference divider
14-bit binary programmable reference counter
14
14-bit latch
AND
14
Data
18-bit shift register
C*
Clock
LE
18
18-bit latch
AND
6
12
Programmable
divider
6-bit binary swallow counter 12-bit binary programmable
counter
Prescaler
* : Control register
Figure 4. The flow of serial data
(3) Setting the divide ratio for the programmable divider
Columns A0 to A5 of Table 2.1 represent the divide ratio of the swallow counter and columns N0 to N11 of Table2.2
represent the divide ratio of programmable counter.
Table. 2 Divide ratio for the programmable divider
Table.2.1 Swallow counter divider A
Table2.2 Programmable counter divider N
Divide
ratio
(A)
A
0
A
1
A
2
A
3
A
4
A
5
Divide
ratio
(N)
N
0
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N N
10 11
0
0
0
0
0
0
0
5
1
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
6
0
1
1
0
0
0
0
0
0
0
0
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
63
1
1
1
1
1
1
4095
1
1
1
1
1
1
1
1
1
1
1
1
Note: Less than 5 is prohibited.
13
MB15C02
(4) Setting the divide ratio for the programmable reference divider
Columns R0-R13 of Table 3 represent the divide ratio of the programmable reference counter. The control bit is set
to 1.
Table.3 Divide ratio for the programmable reference divider
Divide
ratio
(R)
R
0
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
10
R
11
R
12
R
13
5
1
0
1
0
0
0
0
0
0
0
0
0
0
0
6
0
1
1
0
0
0
0
0
0
0
0
0
0
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(5) Setting data input timing
The MB15C02 uses 19 bits of serial data for the programmable divider and 15 bits for the programmable reference
divider. When more bits of serial data than defined for the target divider are received, only the last valid serial data
bits are effective.
To set the divide ratio for the MB15C02 dividers, it is necessary to supply the Data, Clock, and LE signals at the
timing shown in Figure 5.
t1 (>1 µs): Data setup time
t2 (>1 µs): Data hold time
t4 (>1 µs): LE setup time to the rising edge of last clock
t3 (> µs): Clock pulse width
t5 (>1 µs): LE pulse width
Data
Clock
LE
t2
t3
t1
t5
Figure 5. Serial data input timing
14
t4
MB15C02
Since the divide rations are unpredictable when the MB15C02 is turned on, it is necessary to initialize the divide
ratio for both dividers at power-on time. As shown in Figure 6, after setting the divide ratio for one of the dividers
(e.g., programmable reference divider), set LE to “H” level before setting the divide ratio for the other dividers (e.g.,
programmable divider). To change the divide ratio of one of the divider after initialization, input the serial data only
for that divider (the divide ratio for the other divider is preserved).
Data
Serial data for programmable reference divider
15 clocks
1*
Serial data for programmable divider
0*
19 clocks
Clock
LE
* : Control bit
Figure 6. Inputting serial data(Setting divisors)
15
MB15C02
■ TYPICAL CHARACTERISTICS
1. fin Input Sensitivity
fin input frequency vs. Input sensitivity
20.0
Ta = +25°C
10.0
Input sensitivity (dBm)
0.0
−10.0
−20.0
−30.0
−40.0
V DD = 1.0 V
V DD = 1.2 V
V DD = 1.3 V
V DD = 1.5 V
−50.0
−60.0
0
100
200
300
400
500
600
700
800
900
1000
fin input frequency (MHz)
2. OSCIN Input Sensitivity
OSC IN input frequency vs. Input sensitivity
20.0
Ta = +25°C
10.0
Input sensitivity (dBm)
0.0
−10.0
−20.0
−30.0
−40.0
V DD = 1.0 V
V DD = 1.2 V
V DD = 1.3 V
V DD = 1.5 V
−50.0
−60.0
0
50
100
150
200
250
300
OSC IN input frequency (MHz)
16
350
400
450
500
MB15C02
3. fin Power Supply Voltage
Power supply voltage vs. fin input frequency
(MHz)
1000
900
Ta = +25°C
Vfin = −2.0 (dBm)
Input frequency (MHz)
800
700
600
500
400
300
200
100
0
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
Power supply voltage (V)
4. OSCIN Power Supply Voltage
Power supply voltage vs. OSC IN input frequency
500
450
Ta = +25°C
Vfin = −2.0 (dBm)
400
Input frequency (MHz)
350
300
250
200
150
100
50
0
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
Power supply voltage (V)
17
MB15C02
5. IDD Power Supply Current
Input frequency vs. power supply current
5.0
Ta = +25°C
4.5
4.0
I DD (mA)
3.5
3.0
2.5
2.0
1.5
V DD = 1.0 V
V DD = 1.2 V
V DD = 1.3 V
V DD = 1.5 V
1.0
0.5
0.0
0
100
200
300
400
500
600
Input frequency (MHz)
18
700
800
900
1000
MB15C02
6. Do (Charge Pump) Power Supply Voltage
V DD (V p) vs. I OL
(at V OL = 0.2 V)
5.0
Ta = +25°C
4.5
4.0
I OL (mA)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
V DD (V)
V DD (V p) vs. I OH
(at V OH = V DD – 0.2 V)
–5.0
Ta = +25°C
–4.5
–4.0
–3.5
I OH (mA)
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0.0
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
V DD (V)
19
MB15C02
7. Spectrum Wave Form
ATTEN 10 dB
RL 0 dBm
∆MKR −85.50 dB
25.0 kHz
UAUG 16
10dB/
• LOCK Frequency : 286.0 MHz
(fr = 25 kHz)
• V DD = 1.2 V, V p = 1.2 V
Ta = +25°C
∆MKR
D 25.0 kHz
S −85.50 dB
CENTER 286.0000 MHz
*RBW 1.0 kHz
VBW 1.0 kHz
ATTEN 10 dB
RL 0 dBm
SPAN 200.0 kHz
*SWP 1.00 s
∆MKR −53.84 dB
800 Hz
UAUG 50
10dB/
• LOCK Frequency : 286.0 MHz
( fr = 25 kHz)
• VDD = 1.2 V, V p = 1.2 V
Ta = +25°C
∆MKR
D 800 Hz
S −53.84 dB
CENTER 286.00000 MHz
*RBW 100 Hz
VBW 100 kHz
SPAN 20.00 kHz
*SWP 3.00 s
• Test circuit
DO
VT (to VCO)
15 kΩ
4.3 kΩ
6800 pF
20
4700 pF
68000 pF
* VCO : K V = 6 MHz/v
MB15C02
8. Lock Up Time
• LOCK Frequency: 290.0 MHz to 286.0 MHz
(fr = 25 kHz)
• VDD = 1.2 V, VP = 1.2 V, Ta = +25°C
290.0 MHz → 286.0 MHz, within ± 1 kHz
4.00 ms
∆MKr x : 3.99999984 ms
y : −4.00100 MHz
A euts N/A
286.0050
MHz
2.00
kHz/div
285.9950
MHz
0 s
10.0000000 ms
• LOCK Frequency: 286.0 MHz to 290.0 MHz
(fr = 25 kHz)
• VDD = 1.2 V, VP = 1.2 V, Ta = +25°C
286.0 MHz → 290.0 MHz, within ± 1 kHz
6.20 ms
∆MKr x : 6.19999943 ms
y : 4.00082 MHz
A euts N/A
290.0050
MHz
2.00
kHz/div
289.9950
MHz
0 s
10.0000000 ms
(Continued)
21
MB15C02
(Continued)
• LOCK Frequency: PS on to 286.0 MHz
(fr = 25 kHz)
• VDD = 1.2 V, VP = 1.2 V, Ta = +25°C
PS ON → 286.0 MHz, within ± 1 kHz
2.00 ms
∆MKr x : 1.99999978 ms
y : −680 Hz
A euts N/A
286.0050
MHz
2.00
kHz/div
285.9950
MHz
0 s
PS
8.0000000 ms
1V
0V
■ USAGE PRECAUTIONS
• This device should be transported and stored in anti-static containers.
• This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are
properly grounded. Cover workbenches with grounded conductive mats.
• Always turn the power supply off before inserting or removing the device from its socket.
• Protect leads with a conductive sheet when handling or transporting PC boards with devices.
■ ORDERING INFORMATION
Parts number
22
Package
MB15C02PFV1
16-pin Plastic SSOP
(FPT-16P-M05)
MB15C02PFV2
20-pin Plastic SSOP
(FPT-20P-M03)
Remarks
MB15C02
■ PACKAGE DIMENSIONS
16 pins, Plastic SSOP
(FPT-16P-M05)
*: These dimensions do not include resin protrusion.
+0.20
* 5.00±0.10(.197±.004)
1.25 –0.10
+.008
.049 –.004
(Mounting height)
0.10(.004)
INDEX
*4.40±0.10
(.173±.004)
0.65±0.12
(.0256±.0047)
4.55(.179)REF
C
1994 FUJITSU LIMITED F16013S-2C-4
+0.10
0.22 –0.05
+.004
.009 –.002
5.40(.213)
NOM
6.40±0.20
(.252±.008)
"A"
+0.05
0.15 –0.02
+.002
.006 –.001
Details of "A" part
0.10±0.10(.004±.004)
(STAND OFF)
0
10°
0.50±0.20
(.020±.008)
Dimensions in mm (inches)
(Continued)
23
MB15C02
(Continued)
20 pins, Plastic SSOP
(FPT-20P-M03)
*: These dimensions do not include resin protrusion.
+0.20
* 6.50±0.10(.256±.004)
1.25 –0.10
+.008
.049 –.004
(Mounting height)
0.10(.004)
INDEX
*4.40±0.10 6.40±0.20
(.173±.004) (.252±.008)
0.65±0.12
(.0256±.0047)
5.85(.230)REF
C
24
1994 FUJITSU LIMITED F20012S-2C-4
+0.10
0.22 –0.05
+.004
.009 –.002
"A"
5.40(.213)
NOM
+0.05
0.15 –0.02
+.002
.006 –.001
Details of "A" part
0.10±0.10(.004±.004)
(STAND OFF)
0
10°
0.50±0.20
(.020±.008)
Dimensions in mm (inches)
MB15C02
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
http://www.fmap.com.sg/
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and
measurement equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded
(such as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have an inherent chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.
F9902
 FUJITSU LIMITED Printed in Japan
25