Catalyst CAT25C32U20SA-1.8TE13 32k/64k-bit spi serial cmos eeprom Datasheet

(Not recommended for new design,
replace with CAT25320)
H
EE
GEN FR
ALO
CAT25C32/64
32K/64K-Bit SPI Serial CMOS EEPROM
LE
FEATURES
A D F R E ETM
■ 1,000,000 program/erase cycles
■ 10 MHz SPI compatible
■ 100 year data tetention
■ 1.8 to 6.0 volt operation
■ Self-timed write cycle
■ Hardware and software protection
■ 8-pin DIP/SOIC, 14-pin TSSOP and 20-pin
■ Low power CMOS technology
TSSOP
■ SPI modes (0,0 &1,1)
■ 64-Byte page write buffer
■ Commercial, industrial and automotive
■ Block write protection
temperature ranges
– Protect 1/4, 1/2 or all of EEPROM array
DESCRIPTION
The CAT25C32/64 is a 32K/64K-Bit SPI Serial CMOS
EEPROM internally organized as 4Kx8/8Kx8 bits.
Catalyst’s advanced CMOS Technology substantially
reduces device power requirements. The CAT25C32/
64 features a 64-byte page write buffer. The device
operates via the SPI bus serial interface and is enabled
though a Chip Select (CS). In addition to the Chip Select,
the clock input (SCK), data in (SI) and data out (SO) are
required to access the device. The HOLD pin may be
used to suspend any serial communication without
resetting the serial sequence. The CAT25C32/64 is
designed with software and hardware write protection
features including Block write protection. The device is
available in 8-pin DIP, 8-pin SOIC, 14-pin TSSOP and
20-pin TSSOP packages.
PIN CONFIGURATION
DIP Package (P, L)
CS
SO
WP
VSS
1
2
3
8
7
6
VCC
HOLD
SCK
4
5
SI
SOIC Package (S, V)
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
TSSOP Package (U14, Y14)
CS
SO
NC
NC
NC
WP
VSS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
HOLD
NC
NC
NC
SCK
SI
BLOCK DIAGRAM
TSSOP Package (U20, Y20)
NC
CS
SO
SO
NC
NC
WP
VSS
NC
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
VCC
HOLD
HOLD
NC
NC
SCK
SI
NC
NC
SENSE AMPS
SHIFT REGISTERS
WORD ADDRESS
BUFFERS
CS
WP
HOLD
SCK
I/O
CONTROL
SPI
CONTROL
LOGIC
BLOCK
PROTECT
LOGIC
PIN FUNCTIONS
Pin Name
CONTROL LOGIC
SO
SI
COLUMN
DECODERS
XDEC
E2PROM
ARRAY
DATA IN
STORAGE
HIGH VOLTAGE/
TIMING CONTROL
STATUS
REGISTER
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Function
SO
Serial Data Output
SCK
Serial Clock
WP
Write Protect
VCC
+1.8V to +6.0V Power Supply
VSS
Ground
CS
Chip Select
SI
Serial Data Input
HOLD
Suspends Serial Input
NC
No Connect
Doc No. 1001, Rev. G
CAT25C32/64
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum
rating for extended periods may affect device performance and reliability.
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to VSS1) ................... –2.0V to +VCC +2.0V
VCC with Respect to VSS ................................ –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
NEND
(3)
Parameter
Min.
Endurance
Max.
Units
1,000,000
Cycles/Byte
TDR(3)
Data Retention
100
Years
VZAP(3)
ESD Susceptibility
2000
Volts
ILTH(3)(4)
Latch-Up
100
mA
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
ICC1
Power Supply Current
(Operating Write)
10
mA
VCC = 5V @ 10MHz
SO=open; CS=Vss
ICC2
Power Supply Current
(Operating Read)
2
mA
VCC = 5.0V
FCLK = 10MHz
ISB(5)
Power Supply Current
(Standby)
1
µA
CS = VCC
VIN = VSS or VCC
ILI
Input Leakage Current
2
µA
ILO
Output Leakage Current
3
µA
VIL(3)
Input Low Voltage
-1
VCC x 0.3
V
VIH(3)
Input High Voltage
VCC x 0.7
VCC + 0.5
V
VOL1
Output Low Voltage
0.4
V
VOH1
Output High Voltage
VOL2
Output Low Voltage
VOH2
Output High Voltage
VCC - 0.8
V
0.2
VCC-0.2
VOUT = 0V to VCC,
CS = 0V
4.5V≤VCC<5.5V
IOL = 3.0mA
IOH = -1.6mA
V
1.8V≤VCC<2.7V
V
IOL = 150µA
IOH = -100µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) Maximum standby current (ISB ) = 10µA for the Automotive and Extended Automotive temperature range.
Doc. No. 1001, Rev. G
2
CAT25C32/64
PIN CAPACITANCE (1)
Applicable over recommended operating range from TA=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).
Symbol
Test Conditions
Max.
Units
Conditions
COUT
Output Capacitance (SO)
8
pF
VOUT=0V
CIN
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
VIN=0V
A.C. CHARACTERISTICS
Limits
Vcc=
1.8V-6.0V
SYMBOL PARAMETER
Min.
VCC =
2.5V-6.0V
Max.
Min.
Max.
VCC =
4.5V-5.5V
Min.
Max.
Test
UNITS Conditions
tSU
Data Setup Time
50
50
20
ns
tH
Data Hold Time
50
50
20
ns
tWH
SCK High Time
250
125
40
ns
tWL
SCK Low Time
250
125
40
ns
fSCK
Clock Frequency
DC
tLZ
HOLD to Output Low Z
50
tRI(1)
Input Rise Time
tFI(1)
Input Fall Time
tHD
HOLD Setup Time
100
100
40
ns
tCD
HOLD Hold Time
100
100
40
ns
tWC
Write Cycle Time
10
10
5
ms
tV
Output Valid from Clock Low
250
250
80
ns
tHO
Output Hold Time
tDIS
Output Disable Time
250
250
75
ns
tHZ
HOLD to Output High Z
150
100
50
ns
tCS
CS High Time
500
250
200
ns
tCSS
CS Setup Time
500
250
100
ns
tCSH
CS Hold Time
500
250
100
ns
1
DC
10
MHz
50
50
ns
2
2
2
µs
2
2
2
µs
0
3
0
DC
0
CL = 50pF
ns
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
3
Doc. No. 1001, Rev. G
CAT25C32/64
FUNCTIONAL DESCRIPTION
PIN DESCRIPTION
The CAT25C32/64 supports the SPI bus data
transmission protocol. The synchronous Serial Peripheral
Interface (SPI) helps the CAT25C32/64 to interface
directly with many of today’s popular microcontrollers.
The CAT25C32/64 contains an 8-bit instruction register.
(The instruction set and the operation codes are detailed
in the instruction set table)
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C32/64. Input data is latched on the rising edge of the
serial clock.
SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the 25C32/64. During a read cycle,
data is shifted out on the falling edge of the serial clock.
After the device is selected with CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
the operation to be performed.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchronize
Figure 1. Sychronous Data Timing
tCS
VIH
CS
VIL
tCSH
tCSS
VIH
tWH
SCK
VIL
tH
tSU
VIH
tWL
VALID IN
SI
VIL
tRI
tFI
tV
VOH
SO
tHO
tDIS
HI-Z
HI-Z
VOL
Note: Dashed Line= mode (1, 1) — — — —
INSTRUCTION SET
Instruction
Opcode
Operation
WREN
0000 0110
Enable Write Operations
WRDI
0000 0100
Disable Write Operations
RDSR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register
READ
0000 0011
Read Data from Memory
WRITE
0000 0010
Write Data to Memory
Power-Up Timing(1)(2)
Symbol
Parameter
Max.
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Doc. No. 1001, Rev. G
4
CAT25C32/64
will interrupt a write to the status register. If the internal
write cycle has already been initiated, WP going low will
have no effect on any write operation to the status
register. The WP pin function is blocked when the WPEN
bit is set to 0.
the communication between the microcontroller and the
25C32/64. Opcodes, byte addresses, or data present on
the SI pin are latched on the rising edge of the SCK. Data
on the SO pin is updated on the falling edge of the SCK.
CS
CS: Chip Select
HOLD
HOLD: Hold
The HOLD pin is used to pause transmission to the
CAT25C32/64 while in the middle of a serial sequence
without having to re-transmit entire sequence at a later
time. To pause, HOLD must be brought low while SCK
is low. The SO pin is in a high impedance state during the
time the part is paused, and transitions on the SI pins will
be ignored. To resume communication, HOLD is brought
high, while SCK is low. (HOLD should be held high any
time this function is not being used.) HOLD may be tied
high directly to Vcc or tied to Vcc through a resistor.
Figure 9 illustrates hold timing sequence.
CS is the Chip select pin. CS low enables the CAT25C32/
64 and CS high disables the CAT25C32/64. CS high
takes the SO output pin to high impedance and forces
the devices into a Standby Mode (unless an internal
write operation is underway). The CAT25C32/64 draws
ZERO current in the Standby mode. A high to low
transition on CS is required prior to any sequence being
initiated. A low to high transition on CS after a valid write
sequence is what initiates an internal write cycle.
WP
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When WP is tied low and the WPEN bit in the status
register is set to “1”, all write operations to the status
register are inhibited. WP going low while CS is still low
STATUS REGISTER
7
6
5
4
3
2
1
0
WPEN
X
X
X
BP1
BP0
WEL
RDY
BLOCK PROTECTION BITS
Status Register Bits
BP1
BP0
Array Address
Protected
Protection
0
0
None
No Protection
0
1
25C32: 0C00-0FFF
25C64:1800-1FFF
Quarter Array Protection
1
0
25C32: 800-0FFF
25C64:1000-1FFF
Half Array Protection
1
1
25C32: 0000-0FFF
25C64:0000-1FFF
Full Array Protection
WRITE PROTECT ENABLE OPERATION
WPEN
WP
WEL
Protected
Blocks
Unprotected
Blocks
Status
Register
0
X
0
Protected
Protected
Protected
0
X
1
Protected
Writable
Writable
1
Low
0
Protected
Protected
Protected
1
Low
1
Protected
Writable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writable
Writable
5
Doc. No. 1001, Rev. G
CAT25C32/64
The WPEN (Write Protect Enable) is an enable bit for the
WP pin. The WP pin and WPEN bit in the status register
control the programmable hardware write protect feature.
Hardware write protection is enabled when WP is low and
WPEN bit is set to high. The user cannot write to the status
register (including the block protect bits and the WPEN
bit) and the block protected sections in the memory array
when the chip is hardware write protected. Only the
sections of the memory array that are not block protected
can be written. Hardware write protection is disabled
when either WP pin is high or the WPEN bit is zero.
STATUS REGISTER
The Status Register indicates the status of the device.
The RDY (Ready) bit indicates whether the CAT25C32/
64 is busy with a write operation. When set to 1 a write
cycle is in progress and when set to 0 the device
indicates it is ready. This bit is read only.
The WEL (Write Enable) bit indicates the status of the
write enable latch . When set to 1, the device is in a
Write Enable state and when set to 0 the device is in a
Write Disable state. The WEL bit can only be set by the
WREN instruction and can be reset by the WRDI
instruction.
DEVICE OPERATION
Write Enable and Disable
The CAT25C32/64 contains a write enable latch. This
latch must be set before any write operation. The device
powers up in a write disable state when Vcc is applied.
WREN instruction will enable writes (set the latch) to
thedevice. WRDI instruction will disable writes (reset the
latch) to the device. Disabling writes will protect the
device against inadvertent writes.
The BP0 and BP1 (Block Protect) bits indicate which
blocks are currently protected. These bits are set by the
user issuing the WRSR instruction. The user is allowed
to protect quarter of the memory, half of the memory or
the entire memory by setting these bits. Once protected
the user may only read from the protected portion of the
array. These bits are non-volatile.
Figure 2. WREN Instruction Timing
CS
SK
SI
0
0
0
0
0
1
1
0
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) — — — —
Figure 3. WRDI Instruction Timing
CS
SK
SI
SO
0
0
0
0
0
0
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) — — — —
Doc. No. 1001, Rev. G
1
6
0
CAT25C32/64
READ Sequence
The part is selected by pulling CS low. The 8-bit read
instruction is transmitted to the CAT25C32/64, followed by the 16-bit address(the three Most Significant
Bits are don’t care for 25C64 and four most significant
bits are don't care for 25C32).
After the correct read instruction and address are sent,
the data stored in the memory at the selected address
is shifted out on the SO pin. The data stored in the
memory at the next address can be read sequentially
by continuing to provide clock pulses. The internal
address pointer is automatically incremented to the
next higher address after each byte of data is shifted
out. When the highest address (1FFFh for 25C64 and
FFFh for 25C32) is reached, the address counter rolls
over to 0000h allowing the read cycle to be continued
indefinitely. The readoperation is terminated by pulling
the CS high.
sent. The contents of the status register are shifted out on
the SO line. The status register may be read at any time
even during a write cycle. Read sequece is illustrated in
Figure 4. Reading status register is illustrated in Figure 5.
WRITE Sequence
The CAT25C32/64 powers up in a Write Disable state. Prior
to any write instructions, the WREN instruction must be
sent to CAT25C32/64. The device goes into Write enable
state by pulling the CS low and then clocking the WREN
instruction into CAT25C32/64. The CS must be brought
high after the WREN instruction to enable writes to the
device. If the write operation is initiated immediately after
the WREN instruction without CS being brought high, the
data will not be written to thearray because the write enable
latch will not have been properly set. Also, for a successful
write operation the address of the memory location(s) to be
programmed must be outside the protected address field
location selected by the block protection level.
To read the status register, RDSR instruction should be
Figure 4. Read Instruction Timing
CS
0
1
2
3
4
5
6
7
8
9
10
20
21
22
23
24
25
26
27
28
29
30
2
1
SK
OPCODE
SI
0
0
0
0
0
0
1
BYTE ADDRESS*
1
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
0
MSB
*Please check the instruction set table for address
Note: Dashed Line= mode (1, 1) — — — —
Figure 5. RDSR Instruction Timing
CS
0
1
2
3
4
5
6
7
1
0
1
8
9
10
11
7
6
5
4
12
13
14
2
1
SCK
OPCODE
SI
0
0
0
0
0
DATA OUT
SO
HIGH IMPEDANCE
3
0
MSB
Note: Dashed Line= mode (1, 1) — — — —
7
Doc. No. 1001, Rev. G
CAT25C32/64
Byte Write
Once the device is in a Write Enable state, the user
may proceed with a write sequence by setting the CS
low, issuing a write instruction via the SI line, followed
by the 16-bit address (the three Most Significant Bits
are don’t care for 25C64 and four most significant bits
are don't care for 25C32), and then the data to be
written. Programming will start after the CS is brought
high. Figure 6 illustrates byte write sequence.
are internally incremented by one; the high order bits of
address will remain constant. The only restriction is that the
64 bytes must reside on the same page. If the address
counter reaches the end of the page and clock continues,
the counter will “roll over” to the first address of the page
and overwrite any data that may have been written. The
CAT25C32/64 is automatically returned to the write disable
state at the completion of the write cycle. Figure 8 illustrates
the page write sequence.
During an internal write cycle, all commands will be
ignored except the RDSR (Read Status Register)
instruction.
To write to the status register, the WRSR instruction should
be sent. Only Bit 2, Bit 3 and Bit 7 of the status register can
be written using the WRSR instruction. Figure 7 illustrates
the sequence of writing to status register.
The Status Register can be read to determine if the
write cycle is still in progress. If Bit 0 of the Status
Register is set at 1, write cycle is in progress. If Bit 0
is set at 0, the device is ready for the next instruction.
DESIGN CONSIDERATIONS
The CAT25C32/64 powers up in a write disable state and
in a low power standby mode. A WREN instruction must be
issued to perform any writes to the device after power up.
Also,on power up CS should be brought low to enter a ready
state and receive an instruction. After a successful byte/
page write or status register write the CAT25C32/64 goes
into a write disable mode. CS must be set high after the
Page Write
The CAT25C32/64 features page write capability.
After the first initial byte the host may continue to write
up to 64 bytes of data to the CAT25C32/64. After each
byte of data is received, six lower order address bits
Figure 6. Write Instruction Timing
CS
0
1
2
3
4
5
6
7
8
21
22
23
24
25
26
27
28
29
30
31
SK
OPCODE
SI
0
0
0
0
0
DATA IN
0
1
0
D7 D6 D5 D4 D3 D2 D1 D0
ADDRESS
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – –
Figure 7. WRSR Instruction Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
1
7
6
5
4
12
13
14
15
2
1
0
SCK
OPCODE
SI
0
0
0
0
0
DATA IN
0
0
MSB
SO
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) — — — —
Doc. No. 1001, Rev. G
8
3
CAT25C32/64
proper number of clock cycles to start an internal write
cycle. Access to the array during an internal write cycle
is ignored and program-ming is continued. On power up,
SO is in a high impedance.
When powering down, the supply should be taken down
to 0V, so that the CAT25C32/64 will be reset when
power is ramped back up. If this is not possible, then,
following a brown-out episode, the CAT25C32/64 can
be reset by refreshing the contents of the Status Register (See Application Note AN10).
Figure 8. Page Write Instruction Timing
CS
0
1
2
3
4
5
6
7
8
21
22
23 24-31
32-39
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
SK
DATA IN
OPCODE
SI
0
0
0
0
0
0
1
0
ADDRESS
Data
Byte 1
Data
Byte 2
Data
Byte 3
Data Byte N
0
7..1
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1) – – – –
Figure 9. HOLD Timing
CS
tCD
tCD
SCK
tHD
tHD
HOLD
tHZ
HIGH IMPEDANCE
SO
tLZ
Note: Dashed Line= mode (1, 1) — — — —
9
Doc. No. 1001, Rev. G
CAT25C32/64
ORDERING INFORMATION
Prefix
Device #
CAT
Optional
Company ID
Suffix
25C64
Product
Number
25C32: 32K
25C64: 64K
S
-1.8
I
Temperature Range
Blank = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)
A = Automotive (-40°C to +105°C)
E = Extended (-40°C to +125°C)
Package
P = 8-Pin PDIP
S = 8-Pin SOIC
U14= 14-Pin TSSOP
U20 = 20-Pin TSSOP
L = PDIP (Lead free, Halogen free)
V = SOIC, JEDEC (Lead free, Halogen free)
Y14 = TSSOP (Lead free, Halogen free)
Y20 = TSSOP (Lead free, Halogen free)
TE13
Tape & Reel
TE13: 2000/Reel
Operating Voltage
Blank = 2.5 to 6.0V
1.8 = 1.8 to 6.0V
Notes:
(1) The device used in the above example is a 25C64SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage,
Tape & Reel)
Doc. No. 1001, Rev. G
10
REVISION HISTORY
Date
Rev.
Reason
8/4/2004
F
Updated Features
Updated DC Operating Characteristics table & notes
03/29/05
G
Update Reliability Characteristics
Update Instruction Set - Power-Up Timing
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catalyst-semiconductor.com
Publication #:
Revison:
Issue date:
1001
G
03/29/05
Similar pages