MCNIX MX23L3254 32m-bit low voltage, serial mask rom memory with 50mhz spi bus interface Datasheet

MX23L3254
32M-BIT Low Voltage, Serial Mask ROM Memory with
50MHz SPI Bus Interface
FEATURES
DESCRIPTION
•
•
•
•
The MX23L3254 is a 32Mbit (4M x 8) Serial Mask ROM
accessed by a high speed SPI-compatible bus.
32Mbit of Mask ROM
2.7 to 3.6V Single Supply Voltage
SPI Bus Compatible Serial Interface
50MHz Clock Rate (maximum)
PIN DESCRIPTION
PIN CONFIGURATIONS
16-PIN SOP (300 mil)
HOLD#
VCC
NC
NC
NC
NC
S#
Q
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SYMBOL
C
D
Q
S#
HOLD#
VCC
VSS
C
D
NC
NC
NC
NC
VSS
NC
DESCRIPTION
Serial Clock
Serial Data Input
Serial Data Output
Chip Select
Hold
Supply Voltage
Ground
Note:
1. NC=No Connection
2. See page 16 (onwards) for package dimensions, and
how to identify pin-1.
ORDER INFORMATION
Part No.
MX23L3254MC-20
MX23L3254MC-20G
MX23L3254MI-20G
Speed
20ns
20ns
20ns
Package
16-SOP
16-SOP
16-SOP
Remark
Pb-free
Pb-free (Industrial Grade)
Note:
* Industrial grade operating temperature: -25 ~ 85 ° C
Commercial grade operating temperature: 0 ~ 70 ° C
P/N: PM1167
1
REV. 1.2, JUN. 08, 2005
MX23L3254
MEMORY ORGANIZATION
The memory is organized as:
- 4M bytes (8 bits each)
BLOCK DIAGRAM
HOLD#
Control Logic
S#
C
D
I/O Shift Register
Q
Address Register
and Counter
256 Byte
Data Buffer
Y Decoder
Size of the
read-only
memory area
X Decoder
P/N: PM1167
2
REV. 1.2, JUN. 08, 2005
MX23L3254
SIGNAL DESCRIPTION
Serial Data Output (Q). This output signal is used to
transfer data serially out of the device. Data is shifted out
on the falling edge of Serial Clock (C).
device is deselected. Driving Chip Select (S#) Low enables the device, placing it in the active power mode.
After Power-up, a falling edge on Chip Select (S#) is
required prior to the start of any instruction.
Serial Data Input (D). This input signal is used to transfer
data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are
latched on the rising edge of Serial Clock (C).
Hold (HOLD#). The Hold (HOLD#) signal is used to pause
any serial communications with the device without
deselecting the device.
Serial Clock (C). This input signal provides the timing of
the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising
edge of Serial Clock (C). Data on Serial Data Output (Q)
changes after the falling edge of Serial Clock (C).
During the Hold condition, the Serial Data Output (Q) is high
impedance, and Serial Data Input (D) and Serial Clock (C)
are Don't Care.
Chip Select (S#). When this input signal is High, the
To start the Hold condition, the device must be selected,
with Chip Select (S#) driven Low.
P/N: PM1167
3
REV. 1.2, JUN. 08, 2005
MX23L3254
SPI MODES
These devices can be driven by a microcontroller with its
SPI peripheral running in either of the two following modes:
the falling edge of Serial Clock (C).
- CPOL=0, CPHA=0
- CPOL=1, CPHA=1
The difference between the two modes, as shown in Figure
2, is the clock polarity when the bus master is in Stand-by
mode and not transferring data:
For these two modes, input data is latched in on the rising
edge of Serial Clock (C), and output data is available from
- C remains at 0 for (CPOL=0, CPHA=0)
- C remains at 1 for (CPOL=1, CPHA=1)
Figure 1. Bus Master and Memory Devices on the SPI Bus
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
C Q D
C Q D
C Q D
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
Bus Master
(ST6, ST7, ST9,
ST10, Others)
CS3
CS2
CS1
S#
HOLD#
S#
HOLD#
S#
HOLD#
Note: 1. Hold (HOLD#) signals should be driven, High or Low as appropriate.
Figure 2. SPI Modes Supported
CPOL
CPHA
0
0
C
1
1
C
D
MSB
Q
MSB
P/N: PM1167
4
REV. 1.2, JUN. 08, 2005
MX23L3254
OPERATING FEATURES
Active Power, Stand-by Power
The Hold condition starts on the falling edge of the Hold
(HOLD) signal, provided that this coincides with Serial
Clock (C) being Low (as shown in Figure 3).
When Chip Select (S#) is Low, the device is enabled, and
in the Active Power mode. When Chip Select (S#) is High,
the device is disabled, but could remain in the Active
Power mode until all internal cycles have completed. The
device then goes in to the Stand-by Power mode. The
device consumption drops to ICC1 .
The Hold condition ends on the rising edge of the Hold
(HOLD#) signal, provided that this coincides with Serial
Clock (C) being Low.
If the falling edge does not coincide with Serial Clock (C)
being Low, the Hold condition starts after Serial Clock (C)
next goes Low. Similarly, if the rising edge does not
coincide with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes Low. (This is
shown in Figure 2).
Protection Modes
The environments where non-volatile memory devices are
used can be very noisy. No SPI device can operate
correctly in the presence of excessive noise. To help
combat this, the MX23L3254 boasts the following data
protection mechanisms:
During the Hold condition, the Serial Data Output (Q) is
high impedance, and Serial Data Input (D) and Serial Clock
(C) are Don't Care.
- Power-On Reset and an internal timer (tPUW) can provide
protection against inadvertant changes while the power
supply is outside the operating specification.
Normally, the device is kept selected, with Chip Select
(S#) driven Low, for the whole duration of the Hold condition. This is to ensure that the state of the internal logic
remains unchanged from the moment of entering the Hold
condition.
Hold Condition
The Hold (HOLD#) signal is used to pause any serial
communications with the device without resetting the
clocking sequence.
If Chip Select (S#) goes High while the device is in the Hold
condition, this has the effect of resetting the internal logic
of the device. To restart communication with the device,
it is necessary to drive Hold (HOLD#) High, and then to
drive Chip Select (S#) Low. This prevents the device from
going back to the Hold condition.
To enter the Hold condition, the device must be selected,
with Chip Select (S#) Low.
Figure 3. Hold Condition Activation (for data output only)
C
HOLD#
Q2
Q
Q0
Q2
Q1
Q3
Q4
Q5
C
HOLD#
Q2
Q
Q0
Q1
Q2
P/N: PM1167
5
Q3
Q4
Q5
Q6
REV. 1.2, JUN. 08, 2005
MX23L3254
INSTRUCTIONS
All instructions, addresses and data are shifted in and out
of the device, most significant bit first.
Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be
followed by address bytes, or by data bytes, or by both or
none.
Serial Data Input (D) is sampled on the first rising edge of
Serial Clock (C) after Chip Select (S#) is driven Low. Then,
the one-byte instruction code must be shifted in to the
device, most significant bit first, on Serial Data Input (D),
each bit being latched on the rising edges of Serial Clock
(C).
In the case of a Read Data Bytes (READ), Read Data
Bytes at Higher Speed (Fast_Read), the shifted-in instruction sequence is followed by a data-out sequence. Chip
Select (S#) can be driven High after any bit of the data-out
sequence is being shifted out.
The instruction set is listed in Table 1.
Table 1. Instruction Set
Instruction
READ
FAST_READ
Description
One-byte Instruction Code
Address
Bytes
Dummy
Bytes
Data
Bytes
Read Data Bytes
0000 0011
03h
3
0
1 to ∞
Read Data Bytes at Higher Speed
0000 1011
0Bh
3
1
1 to ∞
P/N: PM1167
6
REV. 1.2, JUN. 08, 2005
MX23L3254
Figure 4. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence
S#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-Bit Address
23 22 21
D
3
2
1
0
MSB
Data Out 1
High Impedance
7
Q
6
5
4
3
2
Data Out 2
1
0
7
MSB
Note: 1. Address bits A23,A22 is Don't Care.
Read Data Bytes (READ)
The device is first selected by driving Chip Select (S#) Low.
The instruction code for the Read Data Bytes (READ)
instruction is followed by a 3-byte address (A23-A0), each
bit being latched-in during the rising edge of Serial Clock
(C). Then the memory contents, at that address, is shifted
out on Serial Data Output (Q), each bit being shifted out, at
a maximum frequency fR, during the falling edge of Serial
Clock (C).
The instruction sequence is shown in Figure 4. The first
byte addressed can be at any location. The address is
automatically incremented to the next higher address after
each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ)
instruction.When the highest address is reached, the
address counter rolls over to 000000h, allowing the read
sequence to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by
driving Chip Select (S#) High. Chip Select (S#) can be
driven High at any time during data output.
P/N: PM1167
7
REV. 1.2, JUN. 08, 2005
MX23L3254
Figure 5. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out
Sequence
S#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
C
Instruction
24 BIT ADDRESS
D
Q
23 22 21
3
2
1
0
High Impedance
S#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Dummy Byte
D
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
Q
7
6
5
4
3
2
1
0
7
MSB
MSB
6
5
4
3
2
1
0
7
MSB
automatically incremented to the next higher address after
each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes at Higher
Speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h,
allowing the read sequence to be continued indefinitely.
Read Data Bytes at Higher Speed (FAST_READ)
The device is first selected by driving Chip Select (S#)
Low. The instruction code for the Read Data Bytes at
Higher Speed (FAST_READ) instruction is followed by a 3byte address (A23-A0) and a dummy byte, each bit being
latched-in during the rising edge of Serial Clock (C). Then
the memory contents, at that address, is shifted out on
Serial Data Output (Q), each bit being shifted out, at a
maximum frequency fC, during the falling edge of Serial
Clock (C).
The Read Data Bytes at Higher Speed (FAST_READ)
instruction is terminated by driving Chip Select (S#) High.
Chip Select (S#) can be driven High at any time during data
output.
The instruction sequence is shown in Figure 5. The first
byte addressed can be at any location. The address is
P/N: PM1167
8
REV. 1.2, JUN. 08, 2005
MX23L3254
POWER-UP AND POWER-DOWN
If the delay, tVSL, has elapsed, after VCC has risen
above VCC (min), the device can be selected for READ
instructions even if the tPUW delay is not yet fully
elapsed.
At Power-up and Power-down, the device must not be
selected (that is Chip Select (S#) must follow the voltage
applied on VCC ) until VCC reaches the correct value:
At Power-up, the device is in the following state:
- The device is in the Standby mode.
- VCC(min) at Power-up, and then for a further delay of
tVSL
- VSS at Power-down
Usually a simple pull-up resistor on Chip Select (S#) can
be used to insure safe and proper Power-up and Powerdown.
Normal precautions must be taken for supply rail
decoupling, to stablise the VCC feed. Each device in a
system should have the VCC rail decoupled by a suitable
capacitor close to the package pins.
To avoid data corruption and inadvertent write operations
during power up, a Power On Reset (POR) circuit is
included. The logic inside the device is held reset while
VCC is less than the POR threshold value, VWI -- all
operations are disabled, and the device does not respond
to any instruction.
(Generally, this capacitor is of the order of 0.1uF).
At Power-down, when VCC drops from the operating
voltage, to below the POR threshold value, VWI , all
operations are disabled and the device does not respond
to any instruction.
These values are specified in Table 2.
Figure 6. Power-up Timing
VCC
VCC(max)
Chip Selection Not Allowed
VCC(min)
tVSL
Reset State
of the
Device
Read Access allowed
Device fully
accessible
VWI
tPUW
time
P/N: PM1167
9
REV. 1.2, JUN. 08, 2005
MX23L3254
Table 2. Power-Up Timing
Symbol
tVSL1
Parameter
Min.
VCC(min) to S# low
Max.
Unit
30
us
Note: 1. These parameters are characterized only.
MAXIMUM RATING
Stressing the device above the rating listed in the"Absolute
Maximum Ratings" table may cause permanent damage to
the device. These are stress ratings only and operation of
the device at these or any other conditions above those
indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Table 3. Absolute Maximum Ratings
Symbol
Parameter
TSTG
Storage Temperature
TLEAD
Lead Temperature during Soldering 1
Min.
Max.
Unit
- 65
150
˚C
260 2
˚C
VIO
Input and Output Voltage (with respect to Ground)
- 0.6
4.0
V
VCC
Supply Voltage
- 0.6
4.0
V
VESD
Electrostatic Discharge Voltage (Human Body model) 3
- 2000
2000
V
Note: 1. Compliant with the ECOPACK ® 7191395 specifiication for lead-free soldering processes
2. Not exceeding 250˚C for more than 30 seconds, and peaking at 260˚C
3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
P/N: PM1167
10
REV. 1.2, JUN. 08, 2005
MX23L3254
DC AND AC PARAMETERS
tables that follow are derived from tests performed under
the Measurement Conditions summarized in the relevant
tables. Designers should check that the operating conditions in their circuit match the measurement conditions
when relying on the quoted parameters.
This section summarizes the operating and mea-surement
conditions, and the DC and AC characteristics of the
device. The parameters in the DC and AC Characteristic
Table 4. Operating Conditions
Symbol
VCC
TA
Parameter
Min.
Max.
Unit
Supply Voltage
2.7
3.6
V
Ambient Operating Temperature
-25
85
˚C
Min.
Max.
Unit
Table 5. AC Measurement Conditions
Symbol
CL
Parameter
Load Capacitance
30
Input Rise and Fall Times
pF
5
ns
Input Pulse Voltages
0.2VCC to 0.8VCC
V
Input Timing Reference Voltages
0.3VCC to 0.7VCC
V
V CC / 2
V
Output Timing Reference Voltages
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 7. AC Measurement I/O Waveform
Input Levels
Input and Output
Timing Reference Levels
0.8VCC
0.7VCC
0.5VCC
0.3VCC
0.2VCC
Table 6. Capacitance
Symbol
COUT
CIN
Parameter
Output Capacitance (Q)
Input Capacitance (other pins)
Test Condition
Min.
Max.
Unit
VOUT = 0V
8
pF
VIN = 0V
6
pF
Note: Sampled only, not 100% tested, at TA=25˚C and a frequency of 20 MHz.
P/N: PM1167
11
REV. 1.2, JUN. 08, 2005
MX23L3254
Table 7. DC Characteristics
Symbol
Parameter
Test Condition
(in addition to those in Table 8)
Min.
Max.
Unit
ILI
Input Leakage Current
±2
uA
ILO
Output Leakage Current
±2
uA
ICC1
Standby Current
S # = VCC, VIN = VSS or VCC
50
uA
C = 0.1VCC / 0.9.VCC at 50MHz,
Q = open
8
mA
C = 0.1VCC / 0.9.VCC at 20MHz,
Q = open
4
mA
ICC2
Operating Current (READ)
VIL
Input Low Voltage
- 0.5
0.3VCC
V
VIH
Input High Voltage
0.7VCC
VCC+0.4
V
VOL
Output Low Voltage
IOL = 1.6mA
0.4
V
VOH
Output High Voltage
IOH = -100 uA
P/N: PM1167
12
VCC- 0.2
V
REV. 1.2, JUN. 08, 2005
MX23L3254
Table 8. AC Characteristics
Test conditions specified in Table 4 and Table 5
Symbol
Alt.
fC
fC
fR
Parameter
Min.
Typ.
Max.
Unit
Clock Frequency for the following instructions:
FAST_READ
D.C.
50
MHz
Clock Frequency for READ instructions
D.C.
20
MHz
tCH 1
tCLH
Clock High Time
9
ns
tCL 1
tCLL
Clock Low Time
9
ns
tCLCH 2
Clock Rise Time3 (peak to peak)
0.1
V/ns
tCHCL 2
Clock Fall Time3 (peak to peak)
0.1
V/ns
S# Active Setup Time (relative to C)
5
ns
S# Not Active Hold Time (relative to C)
5
ns
tSLCH
tCSS
tCHSL
tDVCH
tDSU
Data In Setup Time
2
ns
tCHDX
tDH
Data In Hold Time
5
ns
tCHSH
S# Active Hold Time (relative to C)
5
ns
tSHCH
S# Not Active Setup Time (relative to C)
5
ns
100
tSHSL
tCSH
S# Deselect Time
tSHQZ 2
tDIS
Output Disable Time
8
ns
tCLQV
tV
Clock Low to Output Valid
8
ns
tCLQX
tHO
ns
Output Hold Time
0
ns
tHLCH
HOLD# Setup Time (relative to C)
5
ns
tCHHH
HOLD# Hold Time (relative to C)
5
ns
tHHCH
HOLD Setup Time (relative to C)
5
ns
tCHHL
HOLD Hold Time (relative to C)
5
ns
tHHQX 2
tLZ
HOLD to Output Low-Z
8
ns
tHLQZ 2
tHZ
HOLD# to Output High-Z
8
ns
Note: 1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
P/N: PM1167
13
REV. 1.2, JUN. 08, 2005
MX23L3254
Figure 8. Serial Input Timing
tSHSL
S#
tCHSL
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCHDX
tCLCH
LSB IN
MSB IN
D
High Impedance
Q
Figure 9. Hold Timing
S#
tHLCH
tCHHL
tHHCH
C
tCHHH
tHLQZ
tHHQX
Q
D
HOLD#
P/N: PM1167
14
REV. 1.2, JUN. 08, 2005
MX23L3254
Figure 10. Output Timing
S#
tCH
C
tCLQV
tCLQX
tCL
tCLQV
tSHQZ
tCLQX
LSB OUT
Q
tQLQH
tQHQL
D
ADDR.LSB IN
P/N: PM1167
15
REV. 1.2, JUN. 08, 2005
MX23L3254
PACKAGE INFORMATION
P/N: PM1167
16
REV. 1.2, JUN. 08, 2005
MX23L3254
REVISION HISTORY
Revision
1.0
1.1
1.2
Description
1. Removed "Preliminary" on page 1
1. Added "Industrial Grade"
1. Output timing waveform description modified
P/N: PM1167
17
Page
P1
P1,11
P15
Date
MAR/02/2005
MAR/09/2005
JUN/08/2005
REV. 1.2, JUN. 08, 2005
MX23L3254
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