ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E ® Data Sheet October 18, 2007 ±16.5kV ESD Protected, +125°C, 3.0V to 5.5V, SOT-23/TDFN Packaged, 20Mbps, Full Fail-safe, Low Power, RS-485/RS-422 Receivers FN6543.2 Features • IEC61000 ESD Protection on RS-485 Inputs . . . ±16.5kV - Class 3 ESD Level on all Other Pins . . . . . . >5kV HBM • Pb-Free (RoHS Compliant) The Intersil ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E are ±16.5kV IEC61000 ESD Protected, 3.0V to 5.5V powered, single receivers that meet both the RS-485 and RS-422 standards for balanced communication. These receivers have very low bus currents (+125µA/-100µA), so they present a true “1/8 unit load” to the RS-485 bus. This allows up to 256 receivers on the network without violating the RS-485 specification’s 32 unit load maximum and without using repeaters. • Wide Supply Range . . . . . . . . . . . . . . . . . . . 3.0V to 5.5V • Specified for +125°C Operation • Logic Supply Pin (VL) Eases Operation in Mixed Supply Systems (ISL3282E, ISL3284E, ISL3285E Only) • Full Fail-safe (Open, Short, Terminated/Undriven) • True 1/8 Unit Load Allows up to 256 Devices on the Bus • High Data Rates . . . . . . . . . . . . . . . . . . . . . up to 20Mbps Receiver inputs feature a “Full Fail-Safe” design, which ensures a logic high Rx output if Rx inputs are floating, shorted, or terminated but undriven. • Low Quiescent Supply Current . . . . . . . . . . 500µA (Max) - Very Low Shutdown Supply Current . . . . . . 20µA (Max) • -7V to +12V Common Mode Input Voltage Range The ISL3280E and ISL3284E feature an always enabled Rx; the ISL3281E and ISL3285E feature an active high Rx enable pin, and the ISL3282E and ISL3283E include an active low enable pin. All versions are offered in Industrial and Extended Industrial (-40°C to +125°C) temperature ranges. • Tri-statable Rx Available (Active Low or High EN Input) • 5V Tolerant Logic Inputs When VCC ≤ 5V Applications • Clock Distribution A 26% smaller footprint is available with the ISL3282E and ISL3285E TDFN package. These devices, plus the ISL3284E, also feature a logic supply pin (VL) that sets the VOH level of the RO output (and the switching points of the RE / RE input) to be compatible with another supply voltage in mixed voltage systems. • High Node Count Systems • Space Constrained Systems • Security Camera Networks • Building Environmental Control/Lighting Systems For companion single RS-485 transmitters in micro packages, please see the ISL3293E, ISL3294E, ISL3295E, ISL3296E, ISL3297E, ISL3298E data sheet. • Industrial/Process Control Networks TABLE 1. SUMMARY OF FEATURES PART NUMBER FUNCTION DATA RATE (Mbps) # DEVICES ON BUS RX ENABLE? VL PIN? QUIESCENT ICC (µA) LOW POWER SHUTDOWN? LEAD COUNT ISL3280E 1 Rx 20 256 NO NO 350 NO 5-SOT ISL3281E 1 Rx 20 256 ACTIVE HIGH NO 350 YES 6-SOT ISL3282E 1 Rx 20 256 ACTIVE LOW YES 350 YES 8-TDFN ISL3283E 1 Rx 20 256 ACTIVE LOW NO 350 YES 6-SOT ISL3284E 1 Rx 20 256 NO YES 350 NO 6-SOT ISL3285E 1 Rx 20 256 ACTIVE HIGH YES 350 YES 8-TDFN 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E Pinouts ISL3281E (6 LD SOT-23) TOP VIEW ISL3280E (5 LD SOT-23) TOP VIEW VCC 1 5 GND 2 A VCC R RO 3 4 B 1 6 A GND 2 5 RE 4 B 6 A 5 RE 4 B ISL3283E (6 LD SOT-23) TOP VIEW ISL3282E (8 LD TDFN) TOP VIEW RO 1 GND 2 R 8 B 7 RE NC 3 6 VL VCC 4 5 A VCC 1 GND 2 1 GND 2 R RO 3 2 R RO 3 ISL3285E (8 LD TDFN) TOP VIEW ISL3284E (6 LD SOT-23) TOP VIEW VCC R RO 3 6 A 5 VL 4 B RO 1 8 B GND 2 7 RE NC 3 6 VL VCC 4 5 A R FN6543.2 October 18, 2007 ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E Ordering Information PART NUMBER (Notes 1, 2) PART MARKING (Note 3) TEMP. RANGE (°C) PACKAGE (Tape and Reel) (Pb-Free) PKG. DWG. # ISL3280EFHZ-T 280F -40 to +125 5 Ld SOT-23 P5.064 ISL3280EIHZ-T 280I -40 to +85 5 Ld SOT-23 P5.064 ISL3281EFHZ-T 281F -40 to +125 6 Ld SOT-23 P6.064 ISL3281EIHZ-T 281I -40 to +85 6 Ld SOT-23 P6.064 ISL3282EFRTZ-T 82F -40 to +125 8 Ld TDFN L8.2x3A ISL3282EIRTZ-T 82I -40 to +85 8 Ld TDFN L8.2x3A ISL3283EFHZ-T 283F -40 to +125 6 Ld SOT-23 P6.064 ISL3283EIHZ-T 283I -40 to +85 6 Ld SOT-23 P6.064 ISL3284EFHZ-T 284F -40 to +125 6 Ld SOT-23 P6.064 ISL3284EIHZ-T 284I -40 to +85 6 Ld SOT-23 P6.064 ISL3285EFRTZ-T 85F -40 to +125 8 Ld TDFN L8.2x3A ISL3285EIRTZ-T 85I -40 to +85 8 Ld TDFN L8.2x3A NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Please refer to TB347 for details on reel specifications. 3. SOT-23 “PART MARKING” is branded on the bottom side. 3 FN6543.2 October 18, 2007 ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E Truth Table RECEIVING INPUTS OUTPUT RE, RE A-B RO 1, 0 ≥ -0.05V 1 1, 0 ≤ -0.2V 0 1, 0 Inputs Open/Shorted 1 0, 1 X High-Z* NOTE: *Shutdown Mode, except for ISL3280E, ISL3284E Pin Descriptions PIN NAME FUNCTION RO Receiver output: If A - B ≥ -50mV, RO is high; If A - B ≤ -200mV, RO is low; RO = High if A and B are unconnected (floating) or shorted. RE, RE Receiver output enable. RO is enabled when RE/RE is high / low; RO is high impedance when RE/RE is low/high. If the Rx enable function isn’t used, connect RE directly to GND, or connect RE through a 1kΩ, or greater, resistor to VCC. RE/RE are internally pulled low/high. GND Ground connection. This is also the potential of the TDFN thermal pad. A ±16.5kV IEC61000 ESD Protected RS-485, RS-422 level, noninverting receiver input. B ±16.5kV IEC61000 ESD Protected RS-485, RS-422 level, inverting receiver input. VCC System power supply input (3.0V to 5.5V). On devices with a VL pin, power-up VCC first. VL Logic-Level Supply which sets the VIL / VIH levels for the RE (ISL3282E only) and RE (ISL3285E only) pins, and sets the VOH level of the RO output (ISL3282E, ISL3284E, ISL3285E only). Power-up this supply after VCC, and keep VL ≤ VCC. NC No Connection. Typical Operating Circuits NETWORK WITH ENABLES +3.3V TO 5V +3.3V + 1 0.1µF 0.1µF + 2 VCC VCC ISL3281E 3 RO R ISL329xE A 6 B 4 RT 6 Y 4 Z D 5 RE DI 1 DE 3 GND GND 2 5 4 FN6543.2 October 18, 2007 ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E Typical Operating Circuits (Continued) NETWORK WITHOUT ENABLES +3.3V TO 5V +3.3V + 0.1µF 1 VCC 0.1µF + 2 R 3 VCC ISL3280E 3 RO 1kΩ TO 3kΩ ISL329xE A 5 B 4 RT 6 Y 4 Z DE D GND GND 2 5 DI 1 NETWORK WITH VL PIN FOR INTERFACE TO LOWER VOLTAGE LOGIC DEVICES 1.8V +3.3V TO 5V +3.3V + 4 6 VCC 0.1µF 0.1µF 8 VCC VL 1 RO R 1 VCC ISL3282E LOGIC DEVICE (µP, ASIC, UART) 2.5V + VL ISL3298E A 5 B 8 RT 6 Y 7 Z D 7 RE DI 3 DE 2 GND 2 5 VCC LOGIC DEVICE (μP, ASIC, UART) GND 4, 5 FN6543.2 October 18, 2007 ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E Absolute Maximum Ratings Thermal Information VCC to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V VL to GND (ISL3282E, ISL3284E, ISL3285E Only). . -0.3V to (VCC +0.3V) Input Voltages RE, RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V Input/Output Voltages A, B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -8V to +13V RO (Not ISL3282E, ISL3284E, ISL3285E). . -0.3V to (VCC +0.3V) RO (ISL3282E, ISL3284E, ISL3285E) . . . . . . -0.3V to (VL +0.3V) Short Circuit Duration RO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Indefinite ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 5 Ld SOT-23 Package (Note 4) . . . . . . 190 N/A 6 Ld SOT-23 Package (Note 4) . . . . . . 177 N/A 8 Ld TDFN Package (Notes 5, 6). . . . . 65 8 Maximum Junction Temperature (Plastic Package) . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range F Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C I Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications PARAMETER Test Conditions: VCC = 3.0V to 5.5V; VL = VCC (ISL3282E, ISL3284E, ISL3285E only); Typicals are at TA = +25°C (Note 11); Unless Otherwise Specified (Note 7). SYMBOL TEST CONDITIONS TEMP MIN TYP MAX (°C) (Note 10) (Note 11) (Note 10) UNITS DC CHARACTERISTICS VIH1 Input High Voltage (RE, RE) (Notes 8, 9) VIH2 Input Low Voltage (RE, RE) (Notes 8, 9) VL = VCC if ISL3282E, or ISL3285E VCC ≤ 3.6V Full 2 - - V VCC ≤ 5.5V Full 2.4 - - V ISL3282E and ISL3285E Only Full 1.7 - - V Full 1.6 - - V VIH3 2.7V ≤ VL < 3.0V VIH4 2.3V ≤ VL < 2.7V VIH5 1.6V ≤ VL < 2.3V Full 0.72*VL - - V VIH6 1.35V ≤ VL < 1.6V 25 - 0.5*VL - V VIL1 VL = VCC if ISL3282E or ISL3285E Full - - 0.7 V VIL2 VL ≥ 2.7V Full - - 0.7 V VIL3 2.3V ≤ VL < 2.7V Full - - 0.6 V VIL4 1.6V ≤ VL < 2.3V Full - - 0.25*VL V ISL3282E and ISL3285E Only VIL5 1.35V ≤ VL < 1.6V 25 - 0.33*VL - V Logic Input Current (Note 8) IIN1 RE = RE = 0V or VCC Full -15 ±9 15 µA Input Current (A, B) IIN2 VCC = 0V, 3.6V, or 5.5V Receiver Differential Threshold Voltage VTH VIN = 12V Full - 80 125 µA VIN = -7V Full -100 -50 - µA Full -200 -125 -50 mV -7V ≤ VCM ≤ 12V Receiver Input Hysteresis ΔVTH VCM = 0V 25 - 15 - mV Receiver Input Resistance RIN -7V ≤ VCM ≤ 12V Full - 150 - kΩ Receiver Short-Circuit Current IOSR 0V ≤ VO ≤ VCC Full ±7 ±30 ±85 mA Receiver Output High Voltage VOH1 IO = -3.5mA, VID = -50mV (VL = VCC if ISL3282E, ISL3284E, ISL3285E) Full VCC - 0.4 - - V VOH2 IO = -1mA, VL ≥ 1.6V Full VL - 0.4 - - V VOH3 IO = -500µA, VL = 1.5V Full 1.2 - - V VOH4 IO = -150µA, VL = 1.35V Full 1.15 - - V VOH5 IO = -100µA, VL ≥ 1.35V Full VL - 0.1 - - V 6 ISL3282E, ISL3284E, and ISL3285E Only FN6543.2 October 18, 2007 ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E Electrical Specifications Test Conditions: VCC = 3.0V to 5.5V; VL = VCC (ISL3282E, ISL3284E, ISL3285E only); Typicals are at TA = +25°C (Note 11); Unless Otherwise Specified (Note 7). (Continued) TEMP MIN TYP MAX (°C) (Note 10) (Note 11) (Note 10) UNITS PARAMETER SYMBOL TEST CONDITIONS Receiver Output Low Voltage VOL1 IO = 4mA, VID = -200mV, VL ≥ 2.2V if ISL3282E, ISL3284E, ISL3285E Full - 0.2 0.4 V VOL2 IO = 2mA, VL ≥ 1.5V Full - 0.2 0.4 V VOL3 IO = 1mA, VL ≥ 1.35V VOL4 IO = 500µA, VL ≥ 1.35V IOZR ISL3282E, ISL3284E, and ISL3285E Only Full - 0.1 0.4 V 25 - 0.1 - V 0V ≤ VO ≤ VCC Full -1 0.015 1 µA ICC RE/RE = VCC/0V Full - 400 500 µA ISHDN RE/RE = 0V/VCC Full - - 20 µA Three-State (high impedance) Receiver Output Current (Notes 8, 9) SUPPLY CURRENT No-Load Supply Current Shutdown Supply Current (Note 8) ESD PERFORMANCE RS-485 Pins (A, B) All Pins IEC61000-4-2, Air-Gap Discharge Method 25 - ±16.5 - kV IEC61000-4-2, Contact Discharge Method 25 - ±9 - kV Human Body Model, From Bus Pins to GND 25 - ±16.5 - kV HBM, per MIL-STD-883 Method 3015 25 - ±5 - kV MM 25 - ±250 - V VID = ±2V, VCM = 0V (Figure 1 and Table 2) (Note 11) Full 20 30, 24 - Mbps VID = ±2V, VCM = 0V (Figure 1) Full 20 36 60 ns VL ≥ 1.5V (Figure 1) 25 - 44 - ns RECEIVER SWITCHING CHARACTERISTICS Maximum Data Rate Receiver Input to Output Delay fMAX tPLH, tPHL Receiver Skew | tPLH - tPHL | ISL3282E, ISL3284E, and ISL3285E Only VCC = 3.3V ±10% (Figure 1) VL = VCC if ISL3282E, VCC = 5V ±10% (Figure 1) ISL3284E, or ISL3285E Full - 1 5.5 ns tSK2 Full - 2 7.5 ns tSK3 VL ≥ 1.8V (Figure 1) - 2 - ns VL = 1.5V (Figure 1) ISL3282E, ISL3284E, and ISL3285E Only 25 tSK4 25 - 4 - ns Receiver Enable to Output High (Note 8) tZH RL = 1kΩ, CL = 15pF, SW = GND (Figure 2) Note 11 Full - 240, 90 500 ns VL ≥ 1.5V, Note 11 25 - 250, 120 - ns Receiver Enable to Output Low (Note 8) tZL RL = 1kΩ, CL = 15pF, SW = VCC (Figure 2) Note 11 Full - 240, 90 500 ns 25 - 250, 120 - ns Receiver Disable from Output High (Note 8) tHZ RL = 1kΩ, CL = 15pF, SW = GND (Figure 2) Full - 10 20 ns Receiver Disable from Output Low (Note 8) tLZ RL = 1kΩ, CL = 15pF, SW = VCC (Figure 2) tSK1 VL ≥ 1.5V, Note 11 VL ≥ 1.5V, Note 11 VL ≥ 1.5V, Note 11 25 - 24, 20 - ns Full - 10 20 ns 25 - 24, 20 - ns NOTES: 7. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. 8. Does not apply to the ISL3280E or ISL3284E. 9. If the Rx enable function isn’t needed, connect the enable pin to the appropriate supply, as described in the “Pin Descriptions” table. 10. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested. 11. Typical values are at 3.3V, 5V. Parameters with a single entry in the “TYP” column apply to 3.3V and 5V. 7 FN6543.2 October 18, 2007 ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E Test Circuits and Waveforms RE VCC 0V B R A +1V B RE GND 15pF RO 0V -1V A tPLH tPHL VCC OR VL SIGNAL GENERATORS 50% RO 50% 0V FIGURE 1A. TEST CIRCUIT FIGURE 1B. MEASUREMENT POINTS FIGURE 1. RECEIVER PROPAGATION DELAY AND DATA RATE 3V RE OR RE GND B A 1kΩ RO R VCC OR VL SW SIGNAL GENERATOR RE (INVERT FOR RE) 1.5V 0V GND tZH 15pF OUTPUT HIGH A SW tHZ +1.5V GND tLZ -1.5V VCC OR VL tZH +1.5V GND tZL -1.5V V VOH - 0.25V OH 0V tZL RO tLZ VCC OR VL 50% OUTPUT LOW VCC OR VL FIGURE 2A. TEST CIRCUIT tHZ 50% RO PARAMETER 1.5V VOL + 0.25V V OL FIGURE 2B. MEASUREMENT POINTS FIGURE 2. RECEIVER ENABLE AND DISABLE TIMES (EXCEPT ISL3280E AND ISL3284E) Application Information Receiver Features RS-485 and RS-422 are differential (balanced) data transmission standards for use in long haul or noisy environments. RS-422 is a subset of RS-485, so RS-485 transceivers are also RS-422 compliant. RS-422 is a point-to-multipoint (multidrop) standard, which allows only one driver and up to 10 (assuming one unit load devices) receivers on each bus. RS-485 is a true multipoint standard, which allows up to 32 one unit load devices (any combination of drivers and receivers) on each bus. These devices utilize a differential input receiver for maximum noise immunity and common mode rejection. Input sensitivity is better than ±200mV, as required by the RS-422 and RS-485 specifications. Another important advantage of RS-485 is the extended common mode range (CMR), which specifies that the driver outputs and receiver inputs withstand signals that range from +12V to -7V. RS-422 and RS-485 are intended for runs as long as 4000’, so the wide CMR is necessary to handle ground potential differences, as well as voltages induced in the cable by external fields. 8 Receiver input resistance of 96kΩ surpasses the RS-422 specification of 4kΩ and is eight times the RS-485 “Unit Load (UL)” requirement of 12kΩ minimum. Thus, these products are known as “one-eighth UL” transceivers and there can be up to 256 of these devices on a network while still complying with the RS-485 loading specification. Receiver inputs function with common mode voltages as great as +9V/-7V outside the power supplies (i.e., +12V and -7V), making them ideal for long networks where induced voltages, and ground potential differences are realistic concerns. FN6543.2 October 18, 2007 ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E All the receivers include a “full fail-safe” function that guarantees a high level receiver output if the receiver inputs are unconnected (floating), shorted together, or connected to a terminated but undriven bus. Fail-safe with shorted inputs is achieved by setting the Rx upper switching point to -50mV, thereby ensuring that the Rx sees 0V differential as a high input level. All receivers easily support a 20Mbps data rate, and all receiver outputs (except on the ISL3280E and ISL3284E) are tri-statable via the active low RE input or by the active high RE input. TABLE 2. VIH, VIL AND DATA RATE vs VL FOR VCC = 3.3V OR 5V VL (V) VIH (V) VIL (V) DATA RATE (Mbps) 1.35 0.55 0.5 11 1.6 0.7 0.6 16 1.8 0.8 0.7 23 2.3 1 0.9 27 2.7 1.1 1 30 3.3 1.3 1.2 30 5.5 (i.e., VCC) 2 1.8 24 VCC = +3.3V RO RE VCC = +2V VOH = 3.3V RXD VOH ≤ 2V ISL3283E RXEN GND UART/PROCESSOR VCC = +3.3V TO 5V VCC = +2V VL RO RE GND The ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E are designed to operate with a wide range of supply voltages from 3.0V to 5.5V. These devices meet the RS-422 and RS-485 specifications over this full range. Logic Supply (VL Pin, ISL3282E, ISL3284E, ISL3285E Only) Note: Power-up VCC before powering up the VL supply. The ISL3282E, ISL3284E, and ISL3285E include a VL pin that powers the logic input (RE or RE) and / or the Rx output. These pins interface with “logic” devices such as UARTs, ASICs, and microcontrollers and today most of these devices use power supplies significantly lower than 3.3V. Thus, a 3.3V output level from a 3.3V powered RS-485 IC might seriously overdrive and damage the logic device input. Similarly, the logic device’s low VOH might not exceed the VIH of a 3.3V or 5V powered RE input. Connecting the VL pin to the power supply of the logic device (as shown in Figure 3) limits the ISL3282E, ISL3284E, ISL3285E’s Rx output VOH to VL (see Figures 6 through 10), and reduces the RE / RE input switching point to a value compatible with the logic device’s output levels. Tailoring the logic pin input switching point and output levels to the supply voltage of the UART, ASIC, or microcontroller eliminates the need for a level shifter/translator between the two ICs. VL can be anywhere from VCC down to 1.35V, but the input switching points may not provide enough noise margin when VL < 1.6V. Table 2 indicates typical VIH, VIL, and data rate values for various VL settings so the user can ascertain whether or not a particular VL voltage meets his/her needs. The quiescent, RO unloaded, VL supply current (IL) is typically less than 60µA for VL ≤ 3.3V, as shown in Figure 5. VIH ≥ 2V GND ESD DIODE Wide Supply Range VOH = 2V RXD VIH = 1V VOH ≤ 2V ISL3282E ESD DIODE RXEN GND UART/PROCESSOR ESD Protection All pins on these devices include class 3 (>4kV) Human Body Model (HBM) ESD protection structures, but the RS-485 pins (receiver inputs) incorporate advanced structures allowing them to survive ESD events in excess of ±16.5kV HBM and ±16.5kV IEC61000. The RS-485 pins are particularly vulnerable to ESD damage because they typically connect to an exposed port on the exterior of the finished product. Simply touching the port pins, or connecting a cable, can cause an ESD event that might destroy unprotected ICs. These new ESD structures protect the device whether or not it is powered up, and without degrading the RS-485 common mode range of -7V to +12V. This built-in ESD protection eliminates the need for board level protection structures (e.g., transient suppression diodes), and the associated, undesirable capacitive load they present. FIGURE 3. USING VL PIN TO ADJUST LOGIC LEVELS 9 FN6543.2 October 18, 2007 ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E IEC61000-4-2 Testing The IEC61000 test method applies to finished equipment, rather than to an individual IC. Therefore, the pins most likely to suffer an ESD event are those that are exposed to the outside world (the RS-485 pins in this case), and the IC is tested in its typical application configuration (power applied) rather than testing each pin-to-pin combination. The lower current limiting resistor coupled with the larger charge storage capacitor yields a test that is much more severe than the HBM test. The extra ESD protection built into this device’s RS-485 pins allows the design of equipment meeting level 4 criteria without the need for additional board level protection on the RS-485 port. AIR-GAP DISCHARGE TEST METHOD For this test method, a charged probe tip moves toward the IC pin until the voltage arcs to it. The current waveform delivered to the IC pin depends on approach speed, humidity, temperature, etc., so it is difficult to obtain repeatable results. The A and B RS-485 pins withstand ±16.5kV air-gap discharges. CONTACT DISCHARGE TEST METHOD During the contact discharge test, the probe contacts the tested pin before the probe tip is energized, thereby eliminating the variables associated with the air-gap discharge. The result is a more repeatable and predictable test, but equipment limits prevent testing devices at voltages higher than ±9kV. The ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E survive ±9kV contact discharges on the RS-485 pins. Data Rate, Cables, and Terminations RS-485, RS-422 are intended for network lengths up to 4000’, but the maximum system data rate decreases as the Typical Performance Curves transmission length increases. Networks operating at 20Mbps are limited to lengths less than 100’, while a 250kbps network that uses slew rate limited transmitters can operate at that data rate over lengths of several thousand feet. Twisted pair is the cable of choice for RS-485, RS-422 networks. Twisted pair cables tend to pick up noise and other electromagnetically induced voltages as common mode signals, which are effectively rejected by the differential receiver in these ICs. To minimize reflections, proper termination is imperative for high data rate networks. Short networks using slew rate limited transmitters need not be terminated, but terminations are recommended unless power dissipation is an overriding concern. In point-to-point, or point-to-multipoint (single driver on bus) networks, the main cable should be terminated in its characteristic impedance (typically 120Ω) at the end farthest from the driver. In multi-receiver applications, stubs connecting receivers to the main cable should be kept as short as possible. Multipoint (multi-driver) systems require that the main cable be terminated in its characteristic impedance at both ends. Stubs connecting a transmitter or receiver to the main cable should be kept as short as possible. Low Power Shutdown Mode These BiCMOS receivers all use a fraction of the power required by their bipolar counterparts, and the versions with output enable functions include a shutdown feature that reduces the already low quiescent ICC to a 20µA trickle. These versions enter shutdown whenever the receiver disables (RE = VCC or RE = GND). CL = 15pF, TA = +25°C; Unless Otherwise Specified. 0.50 250 VCC = 5V OR 3.3V VCC = VL = 5V 0.45 0.40 200 VCC = VL = 3.3V 0.30 IL (μA) ICC (mA) 0.35 0.25 0.20 150 VL = 5V, VCC = 5V ONLY 100 0.15 VL ≤ 1.8V 0.10 50 VL = 3.3V 0.05 0 -40 RE = VCC, RE = 0V -15 10 60 35 TEMPERATURE (°C) 85 110 125 FIGURE 4. SUPPLY CURRENT vs TEMPERATURE 10 0 VL = 2.5V 0 1 2 3 4 5 6 7 7.5 RE VOLTAGE (V) FIGURE 5. VL SUPPLY CURRENT vs ENABLE PIN VOLTAGE FN6543.2 October 18, 2007 ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E Typical Performance Curves 30 VCC = VL = 5V 50 VOL, +25°C VOH, +25°C VOL, +85°C VOL, +125°C 40 VOH, +125°C 30 VOH, +85°C 20 10 RECEIVER OUTPUT CURRENT (mA) RECEIVER OUTPUT CURRENT (mA) 60 CL = 15pF, TA = +25°C; Unless Otherwise Specified. (Continued) VOL, +25°C 25 VOL, +85°C VOH, +25°C VOL, +125°C 20 15 VOH, +85°C VOH, +125°C 10 5 VCC = 5V OR 3.3V, VL = 3.3V 0 1 0 2 3 4 0 5 0 0.5 FIGURE 6. RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT VOLTAGE VOL, +25°C VOL, +85°C 16 14 VOL, +125°C 12 VOH, +25°C 10 8 VOH, +85°C VOH, +125°C 6 4 2 0 VCC = 5V OR 3.3V, VL = 1.8V 2.5 3.0 3.3 VOL, +25°C 8 VOL, +85°C 7 VOL, +125°C 6 5 4 VOH, +25°C VOH, +85°C 3 VOH, +125°C 2 1 0 0 0.5 1.0 1.5 2.0 0 2.5 0.5 RECEIVER OUTPUT VOLTAGE (V) 1.0 1.5 1.8 RECEIVER OUTPUT VOLTAGE (V) FIGURE 8. RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT VOLTAGE FIGURE 9. RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT VOLTAGE 55 5.0 VCC = 5V VCC = 5V or 3.3V, VL = 1.5V 4.5 VOL, +85°C VOL, +25°C 4.0 VOL, +125°C 3.5 3.0 2.5 2.0 VOH, +25°C VOH, +85°C 1.5 VOH, +125°C 1.0 PROPAGATION DELAY (ns) RECEIVER OUTPUT CURRENT (mA) 2.0 9 VCC = 5V OR 3.3V, VL = 2.5V 18 1.5 FIGURE 7. RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT VOLTAGE RECEIVER OUTPUT CURRENT (mA) RECEIVER OUTPUT CURRENT (mA) 20 1.0 RECEIVER OUTPUT VOLTAGE (V) RECEIVER OUTPUT VOLTAGE (V) 50 VL = 1.5V 45 VL = 1.8V 40 VL = 2.5V 35 0.5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.5 RECEIVER OUTPUT VOLTAGE (V) FIGURE 10. RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT VOLTAGE 11 30 -40 -15 10 35 60 85 110 125 TEMPERATURE (°C) FIGURE 11. RECEIVER PROPAGATION DELAY vs TEMPERATURE FN6543.2 October 18, 2007 ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E Typical Performance Curves 5.0 CL = 15pF, TA = +25°C; Unless Otherwise Specified. (Continued) |tPLH - tPHL| 55 VCC = 5V VCC = 3.3V 4.5 4.0 PROPAGATION DELAY (ns) VL = 1.5V SKEW (ns) 3.5 3.0 2.5 VL = 2.5V 2.0 VL = 1.8V 1.5 1.0 50 VL = 1.5V 45 VL = 1.8V 40 VL = 2.5V 35 0.5 0 -40 -15 10 35 60 85 110 30 -40 125 -15 10 TEMPERATURE (°C) |tPLH - tPHL| VCC = 3.3V 3.5 VL = 1.5V 2.0 RECEIVER OUTPUT (V) SKEW (ns) 3.0 2.5 1.5 VL = 1.8V 1.0 VL = 2.5V 0.5 VL = 1.8V 0 -40 -15 10 35 60 85 110 VCC = 5V 0 A-B -2.0 VL = 5V 5.0 4.0 VL = 2.5V 3.0 2.0 VL = 1.5V 1.0 0 125 TIME (20ns/DIV) FIGURE 14. RECEIVER SKEW vs TEMPERATURE RECEIVER INPUT (V) 110 125 85 2.0 TEMPERATURE (°C) RECEIVER OUTPUT (V) 60 FIGURE 13. RECEIVER PROPAGATION DELAY vs TEMPERATURE RECEIVER INPUT (V) FIGURE 12. RECEIVER SKEW vs TEMPERATURE 4.0 35 TEMPERATURE (°C) VCC = 3.3V 2.0 0 FIGURE 15. RECEIVER WAVEFORMS Die Characteristics SUBSTRATE AND TDFN THERMAL PAD POTENTIAL (POWERED UP): A-B -2.0 GND 4.0 VL = 3.3V 140 3.0 2.0 TRANSISTOR COUNT: VL = 2.5V VL = 1.5V 1.0 PROCESS: Si Gate BiCMOS 0 TIME (20ns/DIV) FIGURE 16. RECEIVER WAVEFORMS 12 FN6543.2 October 18, 2007 ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E Small Outline Transistor Plastic Packages (SOT23-5) P5.064 D VIEW C e1 5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES 5 SYMBOL 4 E CL 1 2 CL 3 e E1 b CL α 0.20 (0.008) M C C CL A A2 SEATING PLANE A1 -C- WITH b PLATING b1 c c1 MILLIMETERS MAX MIN MAX NOTES A 0.036 0.057 0.90 1.45 - A1 0.000 0.0059 0.00 0.15 - A2 0.036 0.051 0.90 1.30 - b 0.012 0.020 0.30 0.50 - b1 0.012 0.018 0.30 0.45 c 0.003 0.009 0.08 0.22 6 c1 0.003 0.008 0.08 0.20 6 D 0.111 0.118 2.80 3.00 3 E 0.103 0.118 2.60 3.00 - E1 0.060 0.067 1.50 1.70 3 e 0.0374 Ref 0.95 Ref - e1 0.0748 Ref 1.90 Ref - L 0.10 (0.004) C MIN 0.014 0.022 0.35 0.55 L1 0.024 Ref. 0.60 Ref. L2 0.010 Ref. 0.25 Ref. N 5 5 4 5 R 0.004 - 0.10 - R1 0.004 0.010 0.10 0.25 α 0o 8o 0o 8o Rev. 2 9/03 NOTES: BASE METAL 1. Dimensioning and tolerance per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC-74 and JEDEC MO178AA. 4X θ1 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. R1 4. Footlength L measured at reference to gauge plane. 5. “N” is the number of terminal positions. R GAUGE PLANE SEATING PLANE L C L1 α L2 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only. 4X θ1 VIEW C 13 FN6543.2 October 18, 2007 ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E Small Outline Transistor Plastic Packages (SOT23-6) 0.20 (0.008) M P6.064 VIEW C C 6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE CL INCHES e b SYMBOL 6 5 4 CL CL E1 E 1 2 3 e1 C D CL A A2 SEATING PLANE A1 -C- WITH b PLATING b1 c c1 MILLIMETERS MAX MIN MAX NOTES A 0.036 0.057 0.90 1.45 - A1 0.000 0.0059 0.00 0.15 - A2 0.036 0.051 0.90 1.30 - b 0.012 0.020 0.30 0.50 - b1 0.012 0.018 0.30 0.45 c 0.003 0.009 0.08 0.22 6 c1 0.003 0.008 0.08 0.20 6 D 0.111 0.118 2.80 3.00 3 E 0.103 0.118 2.60 E1 0.060 0.068 1.50 3.00 - 1.75 3 e 0.0374 Ref 0.95 Ref - e1 0.0748 Ref 1.90 Ref - L 0.10 (0.004) C MIN 0.014 0.022 0.35 0.55 L1 0.024 Ref. 0.60 Ref. L2 0.010 Ref. 0.25 Ref. N 6 6 4 5 R 0.004 - 0.10 - R1 0.004 0.010 0.10 0.25 α 0o 8o 0o 8o Rev. 3 9/03 BASE METAL NOTES: 1. Dimensioning and tolerance per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC-74 and JEDEC MO178AB. 4X θ1 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. R1 4. Footlength L measured at reference to gauge plane. R 5. “N” is the number of terminal positions. GAUGE PLANE SEATING PLANE L C L1 α L2 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only 4X θ1 VIEW C 14 FN6543.2 October 18, 2007 ISL3280E, ISL3281E, ISL3282E, ISL3283E, ISL3284E, ISL3285E Thin Dual Flat No-Lead Plastic Package (TDFN) L8.2x3A 2X 0.15 C A A D 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE 2X MILLIMETERS 0.15 C B SYMBOL E MIN A 0.70 A1 - 6 A3 INDEX AREA b TOP VIEW D2 0.20 0.10 SIDE VIEW C SEATING PLANE D2 (DATUM B) 0.08 C A3 7 0.75 0.80 - - 0.05 - 0.25 0.32 1.50 1.65 1.75 1 7,8 3.00 BSC - 8 1.65 e 1.80 1.90 7,8 0.50 BSC - k 0.20 - - - L 0.30 0.40 0.50 8 N 8 Nd 4 D2/2 6 INDEX AREA 5,8 C E2 A NOTES 2.00 BSC E // MAX 0.20 REF D B NOMINAL 2 3 Rev. 0 6/04 2 NX k NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd refers to the number of terminals on D. (DATUM A) E2 4. All dimensions are in millimeters. Angles are in degrees. E2/2 5. Dimension b applies to the metallized terminal and is measured between 0.25mm and 0.30mm from the terminal tip. NX L 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. N N-1 NX b e 8 5 0.10 (Nd-1)Xe REF. M C A B 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. BOTTOM VIEW CL (A1) NX (b) L 5 SECTION "C-C" C C TERMINAL TIP e FOR EVEN TERMINAL/SIDE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 15 FN6543.2 October 18, 2007