ON NB2308AC4DTR2G 3.3 v zero delay clock buffer Datasheet

NB2308A
3.3 V Zero Delay
Clock Buffer
The NB2308A is a versatile, 3.3 V zero delay buffer designed to
distribute high−speed clocks. It is available in a 16 pin package. The
part has an on−chip PLL which locks to an input clock presented on
the REF pin. The PLL feedback is required to be driven to FBK pin,
and can be obtained from one of the outputs. The input−to−output
propagation delay is guaranteed to be less than 250 ps, and the
output−to−output skew is guaranteed to be less than 200 ps.
The NB2308A has two banks of four outputs each, which can be
controlled by the select inputs as shown in the Select Input Decoding
Table. If all the output clocks are not required, Bank B can be
three−stated. The select input also allows the input clock to be directly
applied to the outputs for chip and system testing purposes.
Multiple NB2308A devices can accept the same input clock and
distribute it. In this case the skew between the outputs of the two
devices is guaranteed to be less than 700 ps.
The NB2308A is available in five different configurations (Refer to
NB2308A Configurations Table). The NB2308Ax1* is the base part,
where the output frequencies equal the reference if there is no counter
in the feedback path. The NB2308Ax1H is the high−drive version of
the −1 and the rise and fall times on this device are much faster.
The NB2308Ax2 allows the user to obtain 2X and 1X frequencies
on each output bank. The exact configuration and output frequencies
depends on which output drives the feedback pin. The NB2308Ax3
allows the user to obtain 4X and 2X frequencies on the outputs.
The NB2308Ax4 enables the user to obtain 2X clocks on all outputs.
Thus, the part is extremely versatile, and can be used in a variety of
applications.
The NB2308Ax5H is a high−drive version with REF/2 on both
banks.
Features
• Zero Input − Output Propagation Delay, Adjustable by Capacitive
•
•
•
•
•
•
•
•
•
•
•
Load on FBK Input
Multiple Configurations − Refer to NB2308A Configurations Table
Input Frequency Range: 15 MHz to 133 MHz
Multiple Low−Skew Outputs
Output−Output Skew Less than 200 ps
Device−Device Skew Less than 700 ps
Two banks of four outputs, three−stateable by two select inputs
Less than 200 ps Cycle−to−Cycle Jitter
Available in 16−pin SOIC and TSSOP Packages
3.3V operation
Advanced 0.35 CMOS Technology
These are Pb−Free Devices**
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MARKING
DIAGRAMS*
16
16
XXXXXXXXXG
AWLYWW
1
SOIC−16
D SUFFIX
CASE 751B
1
16
16
1
TSSOP−16
DT SUFFIX
CASE 948F
1
XXXX
XXXX
ALYWG
G
XXXX = Device Code
A
= Assembly Location
WL, L = Wafer Lot
Y
= Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
*x = C for Commercial; I for Industrial.
**For additional information on our Pb−Free strategy and soldering details,
please download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 3
1
Publication Order Number:
NB2308A/D
NB2308A
FBK
B2
PLL
REF
B2
CLKA1
Extra Divider (−3, −4)
MUX
CLKA2
Extra Divider (−5H)
CLKA3
S2
CLKA4
SELECT INPUT
DECODING
S1
B2
CLKB1
Extra Divider (−2, −3)
CLKB2
CLKB3
CLKB4
Figure 1. Block Diagram
(see Figures 11, 12, 13, 14 and 15 for device specific Block Diagrams)
Table 1. CONFIGURATIONS (x = C for Commercial; I for Industrial)
Feedback From
Device
Bank A Frequency
Bank B Frequency
NB2308Ax1
Bank A or Bank B
Reference
Reference
NB2308Ax1H
Bank A or Bank B
Reference
Reference
NB2308Ax2
Bank A
Reference
Reference B2
NB2308Ax2
Bank B
2 X Reference
Reference
NB2308Ax3
Bank A
2 X Reference
Reference or Reference (Note 1)
NB2308Ax3
Bank B
4 X Reference
2 X Reference
NB2308Ax4
Bank A or Bank B
2 X Reference
2 X Reference
NB2308Ax5H
Bank A or Bank B
Reference B2
Reference B2
1. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the NB2308Ax2.
Table 2. SELECT INPUT DECODING
S2
S1
Clock A1 − A4
Clock B1 − B4
Output Source
PLL ShutDown
0
0
Three−state
Three−state
PLL
Y
0
1
Driven
Three−state
PLL
N
1
0
Driven (Note 2)
Driven
Reference
Y
1
1
Driven
Driven
PLL
N
2. Outputs inverted on 2308−2 and 2308−3 in bypass mode, S2 = 1 and S1 = 0.
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2
NB2308A
REF
1
16
FBK
CLKA1
2
15
CLKA4
CLKA2
3
14
CLKA3
VDD
4
13
VDD
GND
5
12
GND
CLKB1
6
11
CLKB4
CLKB2
7
10
CLKB3
S2
8
9
S1
NB2308A
Figure 2. Pin Configuration
Table 3. PIN DESCRIPTION
Pin #
Pin Name
Description
1
REF (Note 3)
2
CLKA1 (Note 4)
Buffered clock output, Bank A.
3
CLKA2 (Note 4)
Buffered clock output, Bank A.
Input reference frequency, 5 V tolerant input.
4
VDD
3.3 V supply.
5
GND
Ground.
6
CLKB1 (Note 4)
Buffered clock output, Bank B.
7
CLKB2 (Note 4)
Buffered clock output, Bank B.
8
S2 (Note 5)
Select input, bit 2.
9
S1 (Note 5)
Select input, bit 1.
10
CLKB3 (Note 4)
Buffered clock output, Bank B.
11
CLKB4 (Note 4)
Buffered clock output, Bank B.
12
GND
Ground.
13
VDD
3.3 V supply.
14
CLKA3 (Note 4)
Buffered clock output, Bank A.
15
CLKA4 (Note 4)
Buffered clock output, Bank A.
16
FBK
PLL feedback input.
3. Weak pulldown.
4. Weak pulldown on all outputs.
5. Weak pullup on these inputs.
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3
NB2308A
Table 4. MAXIMUM RATINGS
Parameter
Min
Max
Unit
Supply Voltage to Ground Potential
−0.5
+7.0
V
DC Input Voltage (Except REF)
−0.5
VDD + 0.5
V
DC Input Voltage (REF)
−0.5
7
V
Storage Temperature
−65
+150
°C
Maximum Soldering Temperature (10 sec)
260
°C
Junction Temperature
150
°C
>2000
V
Static Discharge Voltage (per MIL−STD−883, Method 3015)
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
Table 5. OPERATING CONDITIONS FOR COMMERCIAL AND INDUSTRIAL TEMPERATURE DEVICES
Parameter
Description
Min
Max
Unit
3.0
3.6
V
0
−40
70
85
°C
VDD
Supply Voltage
TA
Operating Temperature (Ambient Temperature)
CL
Load Capacitance, below 100 MHz
30
pF
CL
Load Capacitance, from 100 MHz to 133 MHz
15
pF
CIN
Input Capacitance (Note 6)
7
pF
Commercial
Industrial
6. Applies to both REF Clock and FBK.
Table 6. ELECTRICAL CHARACTERISTICS FOR COMMERCIAL AND INDUSTRIAL TEMPERATURE DEVICES
Parameter
Description
Test Conditions
Min
Max
Unit
0.8
V
VIL
Input LOW Voltage
VIH
Input HIGH Voltage
IIL
Input LOW Current
VIN = 0 V
50.0
A
IIH
Input HIGH Current
VIN = VDD
100.0
A
VOL
Output LOW Voltage
IOL = 8 mA (−1, −2, −3, −4)
IOL = 12 mA (−1H, −5H)
0.4
V
VOH
Output HIGH Voltage
IOH = −8 mA (−1, −2, −3, −4)
IOH = −12 mA (−1H, −5H)
IDD
Supply Current (Note 7)
Unloaded outputs 100 MHz REF
−2, −3, −4
49
mA
Select inputs at VDD or GND
−1H, −5H
60
mA
Unloaded outputs, 66 MHz REF
(−1, −2, −3, −4)
34
mA
Unloaded outputs, 33 MHz REF
(−1, −2, −3, −4)
18
mA
2.0
7. Supply currents are measured for PLL−Bypass Mode (S2 = 1, S1 = 0).
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4
V
2.4
V
NB2308A
Table 7. SWITCHING CHARACTERISTICS FOR COMMERCIAL AND INDUSTRIAL TEMPERATURE DEVICES
Parameter
Description
Test Conditions
Min
Typ
Unit
100
133.3
133.3
MHz
%
t1
Output Frequency
30 pF load (all devices)
15 pF load (−1H, −5H)
15 pF load (−1, −2, −3, −4)
t1
Duty Cycle = (t2 / t1) * 100
(all devices)
Measured at 1.4 V, FOUT = < 66.66 MHz
30 pF load
40.0
50.0
60.0
Measured at 1.4 V, FOUT = < 50 MHz
15 pF load
45.0
50.0
55.0
t3
Output Rise Time
(−1, −2, −3, −4)
15
15
15
Max
ns
Measured between 0.8 V and 2.0 V
30 pF load
2.20
Measured between 0.8 V and 2.0 V
15 pF load
1.50
Output Rise Time
(−1H, −5H)
Measured between 0.8 V and 2.0 V
30 pF load
1.50
Output Fall Time
(−1, −2, −3, −4)
Measured between 2.0 V and 0.8 V
30 pF load
2.20
Measured between 0.8 V and 2.0 V
15 pF load
1.50
Output Fall Time
(−1H, −5H)
Measured between 2.0 V and 0.8 V
30 pF load
1.25
Output−to−Output Skew on same Bank
(−1, −2, −3, −4)
All outputs equally loaded
200
Output−to−Output Skew
(−1H, −5H)
All outputs equally loaded
200
Output Bank A−to−Output Bank B Skew
(−1, −4, −5H)
All outputs equally loaded
200
Output Bank A−to−Output Bank B Skew
(−2, −3)
All outputs equally loaded
400
t6
Delay, REF Rising Edge to FBK
Rising Edge
Measured at VDD/2
0
±250
ps
t7
Device−to−Device Skew
Measured at VDD/2 on the FBK pins of the
device
0
700
ps
tJ
Cycle−to−Cycle Jitter
(−1, −1H, −4, −5H)
Measured at 66.67 MHz, loaded outputs,
15 pF load
200
ps
Measured at 66.67 MHz, loaded outputs,
30 pF load
200
Measured at 133.3 MHz, loaded outputs
15 pF load
100
Measured at 66.67 MHz, loaded outputs,
30 pF load
400
Measured at 66.67 MHz, loaded outputs,
15 pF load
400
Stable power supply, valid clock presented
on REF and FBK pins
1.0
t4
t5
Cycle−to−Cycle Jitter
(−2, −3)
tLOCK
PLL Lock Time
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5
ns
ps
ms
NB2308A
Zero Delay and Skew Control
To close the feedback loop of the NB2308A, the FBK pin
can be driven from any of the eight available output pins.
The output driving the FBK pin will be driving a total load
of 7 pF plus any additional load that it drives. The relative
loading of this output (with respect to the remaining outputs)
can adjust the input−output delay. This is shown in Figure 3.
For applications requiring zero input−output delay, all
outputs including the one providing feedback should be
equally loaded. If input−output delay adjustments are
required, use the above graph to calculate loading
differences between the feedback output and remaining
outputs. For zero output−output skew, be sure to load outputs
equally.
All outputs should be uniformly loaded to achieve Zero
Delay between input and output.
REF INPUT TO CLKA/CLKB DELAY (ps)
1500
1000
500
0
−500
−1000
−1500
−30 −25 −20 −15 −10
−5
0
5
10
15
20
25
30
OUTPUT LOAD DIFFERENCE: FBK LOAD − CLKA/CLKB LOAD (pF)
Figure 3. REF Input to CLKA/CLKB Delay vs.
Difference in Loading between FBK Pin and
CLKA/CLKB Pins
SWITCHING WAVEFORMS
t1
t2
1.4 V
1.4 V
0.8 V
0.8 V
OUTPUT
t3
Figure 4. Duty Cycle Timing
OUTPUT
0V
t4
Figure 5. All Outputs Rise/Fall Time
1.4 V
V DD
2
INPUT
1.4 V
OUTPUT
3.3 V
2.0 V
2.0 V
1.4 V
V DD
2
OUTPUT
t6
t5
Figure 6. Output − Output Skew
Figure 7. Input − Output Propagation Delay
V DD
2
FBK_Device 1
V DD
2
FBK_Device 2
t7
Figure 8. Device − Device Skew
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NB2308A
TEST CIRCUITS
VDD
VDD
0.1 F
OUTPUTS
VDD
CLKOUT
0.1 F
CLOAD
OUTPUTS
1 k
VDD
0.1 F
1 k
10 pF
VDD
GND
0.1 F
GND
Figure 9. Test Circuit #1
GND
GND
Figure 10. Test Circuit #2
For parameter t8 (output slew rate) on −1H devices
BLOCK DIAGRAMS
FBK
FBK
CLKA1
CLKA1
CLKA2
CLKA2
REF
PLL
REF
MUX
PLL
MUX
CLKA3
CLKA3
S2
SELECT INPUT
DECODING
SELECT INPUT
DECODING
S1
CLKA4
S2
CLKA4
S1
B2
CLKB1
CLKB1
CLKB2
CLKB2
CLKB3
CLKB3
CLKB4
CLKB4
Figure 11. NB2308Ax1 and NB2308Ax1H
Figure 12. NB2308Ax2
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NB2308A
BLOCK DIAGRAMS
FBK
FBK
B2
CLKA1
B2
CLKA1
CLKA2
REF
PLL
CLKA2
MUX
CLKA3
REF
PLL
MUX
CLKA3
CLKA4
S2
CLKA4
S2
SELECT INPUT
DECODING
SELECT INPUT
DECODING
B2
S1
S1
CLKB1
CLKB1
CLKB2
CLKB2
CLKB3
CLKB3
CLKB4
CLKB4
Figure 13. NB2308Ax3
Figure 14. NB2308Ax4
FBK
CLKA1
CLKA2
REF
B2
PLL
MUX
CLKA3
CLKA4
S2
SELECT INPUT
DECODING
S1
CLKB1
CLKB2
CLKB3
CLKB4
Figure 15. NB2308Ax5H
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8
NB2308A
ORDERING INFORMATION
Marking
Operating Range
Package
Shipping†
NB2308AC1DG
2308AC1G
Commercial
SOIC−16
(Pb−Free)
48 Units / Rail
NB2308AC1DR2G
2308AC1G
Commercial
SOIC−16
(Pb−Free)
2500 Tape & Reel
NB2308AI1DG
2308AI1G
Industrial
SOIC−16
(Pb−Free)
48 Units / Rail
NB2308AI1DR2G
2308AI1G
Industrial
SOIC−16
(Pb−Free)
2500 Tape & Reel
NB2308AC1HDG
2308AC1HG
Commercial
SOIC−16
(Pb−Free)
48 Units / Rail
NB2308AC1HDR2G
2308AC1HG
Commercial
SOIC−16
(Pb−Free)
2500 Tape & Reel
NB2308AI1HDG
2308AI1HG
Industrial
SOIC−16
(Pb−Free)
48 Units / Rail
NB2308AI1HDR2G
2308AI1HG
Industrial
SOIC−16
(Pb−Free)
2500 Tape & Reel
NB2308AC1DTG
2308AC1
Commercial
TSSOP−16
(Pb−Free)
96 Units / Rail
NB2308AC1DTR2G
2308AC1
Commercial
TSSOP−16
(Pb−Free)
2500 Tape & Reel
NB2308AI1DTG
2308AI1
Industrial
TSSOP−16
(Pb−Free)
96 Units / Rail
NB2308AI1DTR2G
2308AI1
Industrial
TSSOP−16
(Pb−Free)
2500 Tape & Reel
NB2308AC1HDTG
2308AI1H
Commercial
TSSOP−16
(Pb−Free)
96 Units / Rail
NB2308AC1HDTR2G
2308AI1H
Commercial
TSSOP−16
(Pb−Free)
2500 Tape & Reel
NB2308AI1HDTG
2308AI1H
Industrial
TSSOP−16
(Pb−Free)
96 Units / Rail
NB2308AI1HDTR2G
2308AI1H
Industrial
TSSOP−16
(Pb−Free)
2500 Tape & Reel
NB2308AC2DG
2308AC2G
Commercial
SOIC−16
(Pb−Free)
48 Units / Rail
NB2308AC2DR2G
2308AC2G
Commercial
SOIC−16
(Pb−Free)
2500 Tape & Reel
NB2308AI2DG
2308AI2G
Industrial
SOIC−16
(Pb−Free)
48 Units / Rail
NB2308AI2DR2G
2308AI2G
Industrial
SOIC−16
(Pb−Free)
2500 Tape & Reel
NB2308AC2DTG
2308AC2
Commercial
TSSOP−16
(Pb−Free)
96 Units / Rail
NB2308AC2DTR2G
2308AC2
Commercial
TSSOP−16
(Pb−Free)
2500 Tape & Reel
NB2308AI2DTG
2308AI2
Industrial
TSSOP−16
(Pb−Free)
96 Units / Rail
NB2308AI2DTR2G
2308AI2
Industrial
TSSOP−16
(Pb−Free)
2500 Tape & Reel
Device
Availability
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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9
NB2308A
ORDERING INFORMATION
Marking
Operating Range
Package
Shipping†
NB2308AC3DG
2308AC3G
Commercial
SOIC−16
(Pb−Free)
48 Units / Rail
NB2308AC3DR2G
2308AC3G
Commercial
SOIC−16
(Pb−Free)
2500 Tape & Reel
NB2308AI3DG
2308AI3G
Industrial
SOIC−16
(Pb−Free)
48 Units / Rail
NB2308AI3DR2G
2308AI3G
Industrial
SOIC−16
(Pb−Free)
2500 Tape & Reel
NB2308AC3DTG
2308AC3
Commercial
TSSOP−16
(Pb−Free)
96 Units / Rail
NB2308AC3DTR2G
2308AC3
Commercial
TSSOP−16
(Pb−Free)
2500 Tape & Reel
NB2308AI3DTG
2308AI3
Industrial
TSSOP−16
(Pb−Free)
96 Units / Rail
NB2308AI3DTR2G
2308AI3
Industrial
TSSOP−16
(Pb−Free)
2500 Tape & Reel
NB2308AC4DG
2308AC4G
Commercial
SOIC−16
(Pb−Free)
48 Units / Rail
NB2308AC4DR2G
2308AC4G
Commercial
SOIC−16
(Pb−Free)
2500 Tape & Reel
NB2308AI4DG
2308AI4G
Industrial
SOIC−16
(Pb−Free)
48 Units / Rail
NB2308AI4DR2G
2308AI4G
Industrial
SOIC−16
(Pb−Free)
2500 Tape & Reel
NB2308AC4DTG
2308AC4
Commercial
TSSOP−16
(Pb−Free)
96 Units / Rail
NB2308AC4DTR2G
2308AC4
Commercial
TSSOP−16
(Pb−Free)
2500 Tape & Reel
NB2308AI4DTG
2308AI4
Industrial
TSSOP−16
(Pb−Free)
96 Units / Rail
NB2308AI4DTR2G
2308AI4
Industrial
TSSOP−16
(Pb−Free)
2500 Tape & Reel
NB2308AC5HDG
2308AC5HG
Commercial
SOIC−16
(Pb−Free)
48 Units / Rail
NB2308AC5HDR2G
2308AC5HG
Commercial
SOIC−16
(Pb−Free)
2500 Tape & Reel
NB2308AI5HDG
2308AI5HG
Industrial
SOIC−16
(Pb−Free)
48 Units / Rail
NB2308AI5HDR2G
2308AI5HG
Industrial
SOIC−16
(Pb−Free)
2500 Tape & Reel
NB2308AC5HDTG
2308AC5H
Commercial
TSSOP−16
(Pb−Free)
96 Units / Rail
NB2308AC5HDTR2G
2308AC5H
Commercial
TSSOP−16
(Pb−Free)
2500 Tape & Reel
NB2308AI5HDTG
2308AI5H
Industrial
TSSOP−16
(Pb−Free)
96 Units / Rail
NB2308AI5HDTR2G
2308AI5H
Industrial
TSSOP−16
(Pb−Free)
2500 Tape & Reel
Device
Availability
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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10
NB2308A
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE A
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
K
ÉÉ
ÇÇ
ÇÇ
ÉÉ
ÇÇ
ÉÉ
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
8
1
N
0.15 (0.006) T U
S
0.25 (0.010)
A
−V−
M
N
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
G
H
DETAIL E
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11
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
−−−
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
NB2308A
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE J
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
Licensed under US patent Nos 5,488,627, 6,646,463 and 5,631,920.
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NB2308A/D