Fairchild FOD2200TV Low input current logic gate optocoupler Datasheet

LOW INPUT CURRENT
LOGIC GATE OPTOCOUPLERS
FOD2200
DESCRIPTION
The FOD2200 is an optically coupled logic gate that combine an AlGaAs LED
and an integrated high gain photo detector. The detector has a three state
output stage and has a detector threshold with hysteresis. The three state
output eliminates the need for a pullup resistor and allows for direct drive of
data busses. The hysteresis provides differential mode noise immunity and
eliminates the potential for output signal chatter.
The Electrical and Switching Characteristics of the FOD2200 are guaranteed
over the temperature range of 0°C to 85°C and a VCC range of 4.5 volts to 20
volts. Low IF and wide VCC range allow compatibility with TTL, LSTTL, and
CMOS logic and result in lower power consumption compared to other high
speed optocouplers. Logic signals are transmitted with a maximum propagation delay of 300 nsec. The FOD2200 is useful for isolating high speed logic
interfaces, buffering of input and output lines, and implementing isolated line
receivers in high noise environments.
FEATURES
APPLICATION
• 1 kV/µs Minimum Common Mode
Rejection
• Compatible with LSTTL, TTL, and CMOS
Logic
• Wide VCC Range (4.5 to 20 V)
• 2.5 Mbd Guaranteed over Temperature
• Low Input Current (1.6 mA)
• Three State Output (No Pullup Resistor
Required)
• Guaranteed Performance from 0°C to 85°C
• Hysteresis
• Safety Approvals Pending – UL, CSA, VDE
• VISO = 5kVRMS
•
•
•
•
•
•
•
8
1
8
8
1
Isolation of High Speed Logic Systems
Computer-Peripheral Interfaces
Microprocessor System Interfaces
Ground Loop Elimination
Pulse Transformer Replacement
Isolated Buss Driver
High Speed Line Receiver
1
8 VCC
NC 1
ANODE 2
7 VO
CATHODE 3
6 VE
NC 4
SHIELD
5 GND
Schematic
ICC
8
IF
+
VF
IO
2
7
IE
–
6
3
SHIELD
5
VCC
VO
VE
GND
TRUTH TABLE (Positive Logic)
LED
Enable
Output
On
H
Z
Off
H
Z
On
L
H
Off
L
L
© 2004 Fairchild Semiconductor Corporation
Page 1 of 14
7/7/04
LOW INPUT CURRENT
LOGIC GATE OPTOCOUPLERS
FOD2200
ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise specified)
Parameter
Symbol
Value
Units
Storage Temperature
TSTG
-40 to +125
°C
Operating Temperature
TOPR
-40 to +85
°C
Lead Solder Temperature (1.6mm below seating
plane)
TSOL
260 for 10 sec
°C
IF (PK)
1.0
A
Average Forward Input Current
IF
10
mA
Reverse Input Voltage
VR
5.0
V
Output Power Dissipation
(No derating required up to 85°C)
PD
45
mW
VCC
0 to 20
V
EMITTER
Peak Transient Input Current (≤1µs PW, 300 pps)
DETECTOR
Supply Voltage
Average Output Current
IO
25
mA
Three State Enable Voltage
VE
-0.5 to 20
V
Output Voltage
VO
-0.5 to 20
V
Output Power Dissipation
(No derating required up to 85°C)
PD
150
mW
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
1.6*
Forward Input Current
IF(ON)
Forward Input Current
IF(OFF)
Supply Voltage, Output
VCC
Enable Voltage, Low Level
Enable Voltage, High Level
Max
Units
5
mA
0.1
mA
4.5
20
V
VEL
0
0.8
V
VEH
2.0
20
V
Operating Temperature
TA
0
+85
°C
Fan Out (TTL load)
N
4
*The initial switching threshold is 1.6mA or less. It is recommended that 2.2 mA be used to permit at least a 20% CTR degradation
guardband.
© 2004 Fairchild Semiconductor Corporation
Page 2 of 14
7/7/04
LOW INPUT CURRENT
LOGIC GATE OPTOCOUPLERS
FOD2200
ELECTRICAL CHARACTERISTICS (TA = 0°C to +85°C, VCC = 4.5V to 20V, IF(ON) = 1.6mA to 5mA,
VEH = 2V to 20V, VEL = 0V to 0.8V, IF(OFF) = 0 mA to 0.1 mA Unless otherwise specified.) See Note 1.
INDIVIDUAL COMPONENT CHARACTERISTICS
Parameter
EMITTER
Input Forward Voltage
Input Reverse Breakdown Voltage
Input Capacitance
Input Diode Temperature Coefficient
DETECTOR
High Level Supply Current
Low Level Supply Current
Low Level Enable Current
High Level Enable Current
Test Conditions
Symbol
Min
(IF = 5 mA)
VF
TA =25°C
(IR = 10 µA)
BVR
(Pins 2 & 3) (VF = 0, f = 1 MHz)
CIN
(IF = 5 mA) ∆VF/∆TA
(IF = 5 mA) VCC = 5.5V
(IO = Open, VE = Don’t care) VCC = 20V
(IF = 0 ) VCC = 5.5V
(IO = Open, VE = Don’t care) VCC = 20V
VE = 0.4 V
VE = 2.7 V
VE = 5.5 V
VE = 20 V
High Level Enable Voltage
Low Level Enable Voltage
Typ**
Max
Unit
1.40
1.75
1.7
V
5.0
V
pF
mV/°C
60
-1.4
3.5
4.0
4.4
5.2
-0.1
ICCH
ICCL
IEL
IEH
0.005
VEH
VEL
4.5
6.0
6.0
7.5
-0.32
20
100
250
mA
mA
mA
µA
2.0
V
V
0.8
SWITCHING CHARACTERISTICS (TA = 0°C to +85°C, IF(ON) = 1.6mA to 5mA, IF(OFF) = 0 to 0.1 mA,
VCC = 4.5 to 20V Unless otherwise specified.)
AC Characteristics
Propagation Delay Time
to Output High Level
Propagation Delay Time
to Output Low Level
Test Conditions Symbol
(Note 2, 4)
(Fig. 1) With Peaking Capacitor
(Note 3, 4)
(Fig. 1) With Peaking Capacitor
(Note 5) (Fig. 1)
(Note 6) (Fig. 1)
Output Rise Time (10-90%)
Output Fall Time (90-10%)
Enable Propagation Delay Time
(Fig. 2)
to Output High Level
Enable Propagation Delay Time
(Fig. 2)
to Output Low Level
Disable Propagation Delay Time from Output High Level
(Fig. 2)
Disable Propagation Delay Time from Output Low Level
(Fig. 2)
Common Mode
(TA =25°C)
Transient Immunity
(IF = 1.6 mA, VOH (Min.) = 2.0 V) |VCM| = 50 V
(at Output High Level)
VCC = 5V (Note 7)(Fig. 3)
Common Mode
(TA =25°C)
Transient Immunity
(IF = 0 mA, VOL (Max.) = 0.8 V) |VCM| = 50 V
VCC = 5V (Note 8)(Fig. 3)
(at Output Low Level)
** Typical values at TA = 25°C, VCC = 5V, IF(ON) = 3 mA unless otherwise specified.
© 2004 Fairchild Semiconductor Corporation
Page 3 of 14
Min
Typ**
Max
Unit
TPLH
120
300
ns
TPHL
180
300
ns
tr
tf
80
25
ns
ns
tPZH
40
ns
tPZL
50
ns
TPHZ
TPLZ
95
80
ns
ns
|CMH|
1000
V/µs
|CML|
1000
V/µs
7/7/04
LOW INPUT CURRENT
LOGIC GATE OPTOCOUPLERS
FOD2200
TRANSFER CHARACTERISTICS (TA = 0°C to +85°C, VCC = 4.5V to 20V, IF(ON) = 1.6mA to 5mA,
VEH = 2V to 20V, VEL = 0V to 0.8V, IF(OFF) = 0mA to 0.1mA Unless otherwise specified.) See Note 1.
DC Characteristics
Output Leakage Current (VOUT > VCC)
Low Level Output Voltage
Input Threshold Current
Logic High Output Voltage
High Impedance State Output Current
Test Conditions Symbol
(VCC = 4.5 V) VO = 5.5V
(IF = 5 mA) VO = 20V
(VCC = 4.5 V, IF = 0 mA)
(VE = 0.4 V, IOL = 6.4 mA) (Note 2)
Min
Typ**
Max
2.0
100
2.5
500
0.33
0.5
V
1.6
mA
IOHH
VOL
µA
(VCC = 4.5 V, VO = 0.5 V,
VE = 0.4 V, IOL = 6.4 mA)
IFT
IOH = -2.6 mA
VOH
VO = 0.4 V, VEN = 2 V, IF = 5 mA
IOZL
-20
µA
20
µA
IOZH
100
µA
500
µA
2.4
VCC-1.8
VO = 2.4 V, VEN = 2 V, IF = 5 mA
VO = 5.5 V, VEN = 2 V, IF = 5 mA
VO = 20 V, VEN = 2 V, IF = 5 mA
Logic Low Short Circuit Output Current
Note 10
VO = VCC = 5.5 V, IF = 0 mA
Logic High Short Circuit Output Current
Note 10
VCC = 5.5 V, IF = 5 mA, VO = GND
Input Current Hysteresis
Unit
VO = VCC = 20 V, IF = 0 mA
VCC = 20 V, IF = 5 mA, VO = GND
VCC = 4.5 V
V
25
IOSL
IOSH
IHYS
mA
40
mA
-10
mA
-25
mA
0.03
mA
ISOLATION CHARACTERISTICS (TA = -40°C to +85°C Unless otherwise specified.)
Characteristics
Withstand Insulation Test Voltage
Resistance (Input to Output)
Capacitance (Input to Output)
Test Conditions
Symbol
Min
Typ**
Max
Unit
(RH < 50%, TA = 25°C)
t = 1 min (Note 9)
VISO
5000
(VI-O = 500 VDC) (Note 9)
RI-O
1012
Ω
(VI-O = 0V, f = 1 MHz) (Note 9)
CI-O
0.6
pF
VRMS
** Typical values at TA = 25°C, VCC = 5V, IF(ON) = 3 mA unless otherwise stated.
© 2004 Fairchild Semiconductor Corporation
Page 4 of 14
7/7/04
LOW INPUT CURRENT
LOGIC GATE OPTOCOUPLERS
FOD2200
NOTES
1. The VCC supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic or solid
tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package VCC
and GND pins of each device.
2. tPLH - Propagation delay is measured from the 50% level on the LOW to HIGH transition of the input current pulse to the
1.3V level on the LOW to HIGH transition of the output voltage pulse.
3. tPHL - Propagation delay is measured from the 50% level on the HIGH to LOW transition of the input current pulse to the 1.3V
level on the HIGH to LOW transition of the output voltage pulse.
4. When the peaking capacitor is omitted, propagation delay times may increase by 100 ns.
5. tr - Rise time is measured from the 10% to the 90% levels on the LOW to HIGH transition of the output pulse.
6. tf - Fall time is measured from the 90% to the 10% levels on the HIGH to LOW transition of the output pulse.
7. CMH - The maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the high state (i.e.,
VOUT > 2.0 V).
8. CML - The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the low state (i.e.,
VOUT < 0.8 V).
9. Device considered a two-terminal device: Pins 1,2,3 and 4 shorted together, and Pins 5,6,7 and 8 shorted together.
10. Duration of output short circuit time should not exceed 10 ms.
© 2004 Fairchild Semiconductor Corporation
Page 5 of 14
7/7/04
LOW INPUT CURRENT
LOGIC GATE OPTOCOUPLERS
FOD2200
PULSE GEN.
tr = tf = 5 ns
f = 100 kHz
10 % DUTY
CYCLE
VO = 5 V
IF
INPUT
MONITORING
NODE
R1
VCC
OUTPUT VO
MONITORING
NODE
FOD2200
1
VCC 8
2
7
3
6
5V
619 Ω
D1
D2
C2 =
15 pF
GND 5
4
C1 =
120 pF
D3
5 kΩ
D4
THE PROBE AND JIG CAPACITANCES
ARE INCLUDED IN C1 AND C2.
2.15 kΩ 1.10 kΩ 681 Ω
RI
5 mA
IF (ON) 1.6 mA 3 mA
ALL DIODES ARE 1N916 OR 1N3064.
IF (ON)
50 % IF (ON)
0 mA
INPUT IF
tPLH
tPHL
VOH
1.3 V
VOL
OUTPUT
VO
Fig. 1. T
Test Circuit and Waveforms for tPLH, tPHL, tr and tf.
CL= 15 pF INCLUDING PROBE
PULSE
AND JIG CAPACITANCES.
GENERATOR
VCC
ZO = 50 Ω
tr = tf = 5 ns
VO
FOD2200
+5 V
S1
VCC 8
1
D1
IF
2
7
3
6
GND 5
4
619 Ω
D2
CL
5 kΩ
INPUT VC
MONITORING
NODE
D3
D4
S2
D1-4 ARE 1N916 OR 1N3064.
INPUT
VE
tPZL
OUTPUT S1 CLOSED
VO
S2 OPEN
tPZH
OUTPUT
VO
S1 OPEN
S2 CLOSED
tPLZ
1.3 V
3.0 V
1.3 V
0V
S1 AND
S2 CLOSED
0.5 V
0.5 V
1.3 V
0V
tPHZ
VOL
VOH
≈1.5 V
S1 AND
S2 CLOSED
Fig. 2. T
Test Circuit and Waveforms for tPHZ, tPZH, tPLZ, and tPZL
© 2004 Fairchild Semiconductor Corporation
Page 6 of 14
7/7/04
LOW INPUT CURRENT
LOGIC GATE OPTOCOUPLERS
FOD2200
VCC
FOD2200
A
1
VCC 8
B
2
7
3
6
RIN
VFF
4
GND
PULSE GENERATOR +
OUTPUT VO
MONITORING
NODE
0.1 µF
BYPASS
5
VCM
–
50 V
VCM
0V
SWITCH AT A: IF = 1.6 mA
VOH
VO (MIN.)*
SWITCH AT B: IF = 0 mA
VO (MAX.)*
OUTPUT
VO
VOL
* SEE NOTE 6.
Fig. 3. Test Circuit and Typical Waveforms for Common Mode Transient Immunity
VCC1
(+5 V)
VCC1
(+5 V)
120 pF
DATA
INPUT
1
VCC 8
2
7
3
TTL OR
LSTTL
TOTEM
POLE
OUTPUT
GATE
DATA
OUTPUT
UP TO 16
LSTTL
LOADS
OR 4 TTL
LOADS
6
GND
4
5
FOD2200
1.1
kΩ
FOD2200
1.1
kΩ
DATA
INPUT
2
DATA
INPUT
TTL OR
LSTTL
7
1
VCC 8
2
7
3
6
CMOS
DATA
OUTPUT
6
GND
4
5
RL
1.1 K
2.37 K
3.83 K
5.11 K
2
120 pF (OPTIONAL*)
1.1
kΩ
FOD2200
1.1 kΩ
2
RL
Figure 5. LSTTL to CMOS Interface Circuit.
VCC (+5 V)
VCC1 (+5 V)
VCC 8
VCC2
5V
10 V
15 V
20 V
1
Figure 4. Recommended LSTTL to LSTTL Circuit.
1
3
TTL OR
LSTTL
TOTEM
POLE
OUTPUT
GATE
1
VCC2
(4.5 TO 20 V)
120 pF (OPTIONAL*)
VCC2
(+5 V)
FOD2200
1
VCC 8
2
7
4.7 kΩ
D1
4
GND
5
DATA
INPUT
OPEN
COLLECTOR
GATE
3
TTL OR
LSTTL
4
6
GND
5
D1 (1N4150) REQUIRED FOR
ACTIVE PULL-UP DRIVER.
Figure 6. Recommended LED Drive Circuit.
Figure 7. Series LED Drive with Open Collector Gate
(4.7 kΩ Resistor Shunts IOH from the LED).
*The 120pF capacitor may be omitted in applications where 500ns propagation delay is sufficient.
© 2004 Fairchild Semiconductor Corporation
Page 7 of 14
7/7/04
LOW INPUT CURRENT
LOGIC GATE OPTOCOUPLERS
FOD2200
TYPICAL PERFORMANCE CURVES
Figure 8. Input Forward Current vs Forward Voltage
Figure 9. Output Voltage vs. Input Forward Current
100
5
10
4
VO - Output Voltage (V)
IF - Forward Current (mA)
VCC = 4.5V
TA = 25°C
TA = 85°C
TA = 70°C
1
TA = -40°C
TA = 25°C
TA = 0°C
0.1
0.01
3
IO = -2.6mA
2
IF(OFF)
IF(ON)
1
IO = 6.4mA
0
0.001
0.9
1.0
1.1
VF
1.2
1.3
1.4
1.5
- Forward Voltage (V)
1.6
0.0
1.7
1.0
1.2
0.8
VOL - Logic Low Output Voltage (V)
VCC = 5V, 20V
Input Current Threshold (mA)
0.4
0.6
0.8
IF - Input Forward Current (mA)
Figure 11. Logic Low Output Voltage vs. Ambient Temperature
Figure 10. Input Threshold Current vs. Ambient Temperature
1.2
1.0
0.8
IF(ON)
0.6
IF(OFF)
0.4
0.2
0.0
-40
VCC = 4.5V
IF = 0 mA
IO = 6.4 mA
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-20
0
20
40
60
TA - Ambient Temperature (°C)
80
100
-40
-20
0
20
40
60
TA - Ambient Temperature (°C)
80
100
Figure 13. Logic High Output Current vs. Ambient Temperature
Figure 12. Logic High Output Voltage vs. Supply Voltage
0
IOH - Logic High Output Current (mA)
20
VOH - Logic High Output Voltage (V)
0.2
IO = -2.6 mA
TA = 25°C
IF ≥ IF (ON)
16
12
8
4
0
0
4
8
12
VCC - Supply Voltage (V)
© 2004 Fairchild Semiconductor Corporation
16
-2
VO = 2.7V
-3
-4
VO = 2.4V
-5
-6
-7
-40
20
Page 8 of 14
VCC = 4.5V
IF = 5 mA
-1
-20
0
20
40
60
TA - Ambient Temperature (°C)
80
100
7/7/04
LOW INPUT CURRENT
LOGIC GATE OPTOCOUPLERS
FOD2200
TYPICAL PERFORMANCE CURVES
Figure 14. Propagation Delay vs Ambient Temperature
Figure 15. Rise, Fall Time vs Ambient Temperature
200
VCC = 5V
C1 (120 pF) Peaking Capacitor Is Used.
See Figure 1.
220
VCC = 5V
IF = 1.6mA
tf, tr - Rise, Fall Time (µs)
tP - Propagation Delay (µs)
260
tPHL, IF = 5 mA
180
tPHL, IF = 3 mA
140
tPHL, IF = 1.6 mA
tPLH, IF = 1.6 - 5 mA
100
60
160
120
tr
80
40
tf
0
-40
-20
0
20
40
60
TA - Ambient Temperature (°C)
© 2004 Fairchild Semiconductor Corporation
80
-40
100
Page 9 of 14
-20
0
20
40
60
TA - Ambient Temperature (°C)
80
100
7/7/04
LOW INPUT CURRENT
LOGIC GATE OPTOCOUPLERS
FOD2200
Package Dimensions (Through Hole)
Package Dimensions (0.4"Lead Spacing)
PIN 1
ID.
4
4
3
2
3
2
0.270 (6.86)
0.250 (6.35)
5
6
0.270 (6.86)
0.250 (6.35)
8
7
5
0.390 (9.91)
0.370 (9.40)
0.020 (0.51) MIN
0.200 (5.08)
0.140 (3.55)
0.154 (3.90)
0.120 (3.05)
0.022 (0.56)
0.016 (0.41)
6
7
8
0.390 (9.91)
0.370 (9.40)
0.070 (1.78)
0.045 (1.14)
SEATING PLANE
SEATING PLANE
PIN 1
ID.
1
1
0.016 (0.40)
0.008 (0.20)
0.100 (2.54) TYP
0.070 (1.78)
0.045 (1.14)
0.004 (0.10) MIN
0.200 (5.08)
0.140 (3.55)
15° MAX
0.154 (3.90)
0.120 (3.05)
0.300 (7.62)
TYP
0.022 (0.56)
0.016 (0.41)
0.016 (0.40)
0.008 (0.20)
0.100 (2.54) TYP
Package Dimensions (Surface Mount)
0° to 15°
0.400 (10.16)
TYP
8 - Pin Dip
0.390 (9.91)
0.370 (9.40)
4
3
2
1
PIN 1
ID.
0.070 (1.78)
0.270 (6.86)
0.250 (6.35)
0.060 (1.52)
5
6
7
8
0.070 (1.78)
0.045 (1.14)
0.300 (7.62)
TYP
0.020 (0.51)
MIN
0.022 (0.56)
0.016 (0.41)
0.100 (2.54)
TYP
Lead Coplanarity : 0.004 (0.10) MAX
0.100 (2.54)
0.016 (0.41)
0.008 (0.20)
0.295 (7.49)
0.415 (10.54)
0.030 (0.76)
0.045 [1.14]
0.315 (8.00)
MIN
0.405 (10.30)
MIN
NOTE
All dimensions are in inches (millimeters)
© 2004 Fairchild Semiconductor Corporation
Page 10 of 14
7/7/04
LOW INPUT CURRENT
LOGIC GATE OPTOCOUPLERS
FOD2200
Carrier Tape Specifications
P0
t
K0
P2
D0
E
F
A0
W1
W
B0
d
Description
Tape Width
Tape Thickness
P
User Direction of Feed
D1
Symbol
Dimension in mm
W
16.0 ± 0.3
t
0.30 ± 0.05
Sprocket Hole Pitch
P0
4.0 ± 0.1
Sprocket Hole Diameter
D0
1.55 ± 0.05
Sprocket Hole Location
E
1.75 ± 0.10
F
7.5 ± 0.1
Pocket Location
P2
4.0 ± 0.1
P
12.0 ± 0.1
A0
10.30 ±0.20
Pocket Dimensions
B0
10.30 ±0.20
K0
4.90 ±0.20
Cover Tape Width
W1
1.6 ± 0.1
d
0.1 max
Pocket Pitch
Cover Tape Thickness
Max. Component Rotation or Tilt
Min. Bending Radius
© 2004 Fairchild Semiconductor Corporation
10°
R
Page 11 of 14
30
7/7/04
LOW INPUT CURRENT
LOGIC GATE OPTOCOUPLERS
FOD2200
ORDERING INFORMATION
Example: FOD2200
X
X
Packaging Option
S:
Surface Mount Lead Bend
SD: Surface Mount, Tape and Reel
T:
0.4" Lead Spacing
V:
VDE 0884
TV: VDE 0884, 0.4" Lead Spacing
SV: VDE 0884, Surface Mount
SDV: VDE 0884, Surface Mount, Tape and Reel
MARKING INFORMATION
1
2200
XX YY B
V
3
4
2
6
5
Definitions
1
Fairchild logo
2
Device number
3
VDE mark (Note: Only appears on parts ordered with VDE
option – See order entry table)
4
Two digit year code, e.g., ‘03’
5
Two digit work week ranging from ‘01’ to ‘53’
6
Assembly package code
© 2004 Fairchild Semiconductor Corporation
Page 12 of 14
7/7/04
LOW INPUT CURRENT
LOGIC GATE OPTOCOUPLERS
FOD2200
Reflow Profile
245 C, 10–30 s
Temperature (°C)
300
260 C peak
250
200
150
Time above 183C, <160 sec
100
50
Ramp up = 2–10C/sec
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Time (Minute)
• Peak reflow temperature: 260 C (package surface temperature)
• Time of temperature higher than 183 C for 160 seconds or less
• One time soldering reflow is recommended
© 2004 Fairchild Semiconductor Corporation
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LOW INPUT CURRENT
LOGIC GATE OPTOCOUPLERS
FOD2200
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
© 2004 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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