MPS MP5010B 3v-18v, 1a-5a programmable-current- limit switch with over-voltage clamp Datasheet

MP5010B
3V-18V, 1A-5A Programmable-CurrentLimit Switch with Over-Voltage Clamp
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP5010B is a protection device designed to
protect circuitry on the output (source) from
transients on the input (VCC). It also protects the
input from undesired shorts and transients
coming from the source.
A small capacitor on the dv/dt pin controls the
slew rate that limit the inrush current at the
source. For instance, a 1nF capacitor results in a
source ramp-up time of 3ms.
The maximum load at the source is current
limited using a sense FET topology. An external
resistor between the I-Limit pin and the Source
pins controls the magnitude of the current limit.
An internal charge pump drives the gate of the
power device, allowing the DMOS power FET to
have a very low ON-resistance of just 40mΩ.
The MP5010B also protects the source from the
input being too low or too high. Under-voltage
lockout ensures that the input remains above the
minimum operating threshold before the power
device turns on. If the input rises above the high
output threshold, the MP5010B limits the source
voltage.
•
•
•
•
•
•
•
Wide 3V-to-18V Operating Input Range
5.7V Output Over-Voltage Clamp
Integrated 40mΩ Power FET
Enable/Fault Pin
Adjustable Output Voltage Slew Rate
Adjustable Current Limit
Thermal Protection
APPLICATIONS
•
•
•
•
Hot-Swappable Devices
Wireless Modem Data Cards
PC Cards
Laptops
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Products, Quality Assurance page.
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks
of Monolithic Power Systems, Inc.
TYPICAL APPLICATION
VIN
6
7
EN
8
9
10
11
VCC
N/C
I-Limit
Source
Source
MP5010B
5
4
VOUT
3
Enable/Fault
Source
dv/dt
Source
GND
Source 1
2
MP5010B Rev. 1.0
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MP5010B – 3V-18V, 1A-5A PROGRAMMABLE CURRENT LIMIT SWITCH
ORDERING INFORMATION
Part Number*
MP5010BDQ
Package
QFN10 (3mm×3mm)
Top Marking
AFN
* For Tape & Reel, add suffix –Z (e.g. MP5010BDQ–Z).
For RoHS compliant packaging, add suffix –LF (e.g. MP5010BDQ-LF-Z).
PACKAGE REFERENCE
1
10
2
9
3
8
4
7
5
6
ABSOLUTE MAXIMUM RATINGS (1)
VCC, SOURCE, I-LIMIT ..................–0.3V to 22V
dv/dt, ENABLE/FAULT ....................–0.3V to 6V
Storage Temperature.............. –65°C to +155°C
Junction Temperature................................ +150°C
Lead Temperature .................................... +260°C
(2)
Continuous Power Dissipation (TA=+25°C)
................................................................... 2.5W
Recommended Operating Conditions
(3)
Input Voltage Operating Range ......... 3V to 18V
Operating Junction Temp. (TJ)...... -40°C to +125°C
Thermal Resistance
(4)
θJA
θJC
QFN10 (3mmx3mm) ...............50 ...... 12 ... °C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX) ， the junction-toambient thermal resistance θJA，and the ambient temperature
TA, the maximum allowable power dissipation at any ambient
temperature is calculated using: PD(MAX)=(TJ(MAX)-TA)/ θJA.
Exceeding the maximum allowable power dissipation will
cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
o
Reduce 0.2 Watts for every 10 C ambient temperature
increasing
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7 4-layer board.
MP5010B Rev. 1.0
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MP5010B – 3V-18V, 1A-5A PROGRAMMABLE CURRENT LIMIT SWITCH
ELECTRICAL CHARACTERISTICS
VCC = 5V, RLIMIT=22Ω, Capacitive Load= 10μF, TA=25°C, unless otherwise noted.
Parameters
Power FET
Symbol
Delay Time
τDLY
ON Resistance
RDSon
OFF-State Output Voltage
VOFF
Continuous Current
Thermal Latch
Shutdown Temperature(5)
Under/Over-Voltage Protection
Output Clamp Voltage
ID
Condition
Min
Enabling of chip to
ID=40mA with a 5Ω
resistive load
TJ=25°C
TJ=85°C(5)
VCC=18V, VEN=0V,
RL=500Ω
40
52
0.5 in2 pad, TA=25°C
4.2
minimum copper, TA=80°C
2.3
Max
44
55
5.5
Under-Voltage Lockout
VUVLO
2.65
Under-Voltage Lockout (UVLO)
VHYST
Hysteresis
(6)
Current Limit (For Direct Current-Sense, refer to typical application in Figure 5)
0Ω Short Resistance,
Hold Current
ILIM-SS
2.2
RLIM=22Ω
Trip Current
ILIM-OL
RLIM=22Ω
Current Limit (6) (For Kelvin Sense, refer to typical application in Figure 4)
0Ω Short Resistance,
0.77
Hold Current
ILIM-SS
RLIM=22Ω
Trip Current
ILIM-OL
RLIM=22Ω
dv/dt Circuit
Rise Time (7)
τr
Cdv/dt =1nF
2
Enable/Fault
Low-Level Input Voltage
VIL
Output Disabled
Thermal Fault, Output
Intermediate-Level Input Voltage
VI (INT)
0.82
Disabled
High-Level Input Voltage
VIH
Output Enabled
2.5
HIGH-State Maximum Voltage
VI (MAX)
Pull-Up Current (Source)
IIL
VENABLE=0V
15
Maximum number of chips
Maximum Fanout for Fault Signal
for simultaneous shutdown
Maximum Voltage on EN(8)
VMAX
mΩ
mV
A
175
Over-Voltage Protection
VCC=8V
Rising Edge
Units
μs
120
TSD
VCLAMP
Typ
°C
5.7
5.9
V
2.8
2.9
V
0.15
2.8
V
3.4
4.3
1.10
A
1.43
2.18
3
1.4
4.95
25
MP5010B Rev. 1.0
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A
A
A
4
ms
0.5
V
1.95
V
35
V
V
μA
3
Units
VCC
V
3
MP5010B – 3V-18V, 1A-5A PROGRAMMABLE CURRENT LIMIT SWITCH
ELECTRICAL CHARACTERISTICS (continued)
VCC = 5V, RLIMIT=22Ω, Capacitive Load= 10μF, TA=25°C, unless otherwise noted.
Parameters
Total Device
Symbol
Condition
Bias Current
IBIAS
Device Operational
Thermal Shutdown
Minimum Operating Voltage for
UVLO
VMIN
Enable<0.5V
Min
Typ
Max
Units
860
580
950
650
μA
2.5
V
Notes:
5) Guaranteed by design.
6) Guaranteed by Characterization Test.
7) Measured from 10% to 90%.
8) Maximum Input Voltage on Enable pin to be ≤6V if Vcc ≥ 6V. Maximum Input Voltage on Enable pin to be Vcc if Vcc ≤ 6V.
MP5010B Rev. 1.0
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MP5010B – 3V-18V, 1A-5A PROGRAMMABLE CURRENT LIMIT SWITCH
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 5V, VEN=5V, RLIMIT=22Ω, COUT=10μF, Cdv/dt =1nF, TA=25°C, unless otherwise noted.
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
20 30 40 50 60 70 80 90 100
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
1000
950
900
850
800
750
700
650
600
0 10 20 30 40 50 60 70 80 90100110
550
600
60
140
550
55
120
500
50
450
45
400
40
350
35
3
3.5
4
4.5
5
5.5
0
0.5
1
1.5
2
2.5
100
80
60
300
3
3.5
4
4.5
5
5.5
4
3.5
40
20
0
30
3
3.5
4
4.5
5
5.5
5.5
15
5
12
4.5
9
4
6
3.5
3
3
2.5
2
3
3.5
4
4.5
5
5.5
3
0
3
3.5
4
4.5
5
5.5
4
8
12
MP5010B Rev. 1.0
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20
5
MP5010B – 3V-18V, 1A-5A PROGRAMMABLE CURRENT LIMIT SWITCH
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, VEN=5V, RLIMIT=22Ω, COUT=10μF, Cdv/dt =1nF, TA=25°C, unless otherwise noted.
VOUT
2V/div
VOUT
2V/div
VOUT
2V/div
VIN
5V/div
EN
5V/div
IOUT
1A/div
VIN
5V/div
EN
5V/div
IOUT
1A/div
VIN
5V/div
EN
5V/div
IOUT
1A/div
VOUT
2V/div
VOUT
2V/div
VOUT
2V/div
VIN
5V/div
EN
5V/div
IOUT
1A/div
VIN
5V/div
EN
5V/div
IOUT
1A/div
VIN
5V/div
EN
5V/div
IOUT
2A/div
VOUT
2V/div
VIN
5V/div
EN
5V/div
VOUT
2V/div
VIN
5V/div
EN
5V/div
VOUT
2V/div
IOUT
1A/div
IOUT
1A/div
VIN
5V/div
EN
5V/div
IOUT
2A/div
MP5010B Rev. 1.0
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MP5010B – 3V-18V, 1A-5A PROGRAMMABLE CURRENT LIMIT SWITCH
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, VEN=5V, RLIMIT=22Ω, COUT=10μF, Cdv/dt =1nF, TA=25°C, unless otherwise noted.
MP5010B Rev. 1.0
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MP5010 – PROGRAMMABLE CURRENT 12V/5A ELECTRONIC FUSE
PIN FUNCTIONS
Pin #
1-5
6
7
8
9
10
11
Exposed Pad
Name
SOURCE
N/C
Description
Source. Internal power FET source. IC output.
DO NOT CONNECT—leave floating.
Current Limit. Using a resistor between this pin and Source to set the overload
I-Limit
and short-circuit current-limit levels.
Enable/Fault. A tri-state, bi-directional interface. Leave floating to enable the
output. Pull to ground (using an open drain or open collector device) to disable
Enable/Fault
the output. If a thermal fault occurs, this voltage enters an intermediate state to
signal that the device is in thermal shutdown.
Slew Rate. The internal dv/dt circuit controls the slew rate of the output voltage
dv/dt
at turn-on.
GND
Ground. Internal IC reference.
VCC
Input. Positive input voltage.
MP5010B Rev. 1.0
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MP5010 – PROGRAMMABLE CURRENT 12V/5A ELECTRONIC FUSE
BLOCK DIAGRAM
VCC
5V
Charge
Pump
U1
25 A
Enable/
Fault
2.5V
2V Hys
U3
D1
R1
28k
M1
U2
RESET
Source
Latch
Control Logic
SET
Current Limit
Thermal
Shutdown
VCC UVLO
Voltage
Clamp
dv /dt
Control
I-Limit
dv/dt
GND
Figure 1: Functional Block Diagram
MP5010B Rev. 1.0
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MP5010B – 3V-18V, 1A-5A PROGRAMMABLE CURRENT LIMIT SWITCH
OPERATION
The MP5010B limits the inrush current to the
load when a circuit card connects to a live
backplane power source, thereby limiting the
backplane’s voltage drop and the dV/dt of the
voltage to the load. It offers an integrated solution
to monitor the input voltage, output voltage,
output current, and die temperature, eliminating
the external current-sense power resistor, power
MOSFET, and thermal sensor.
Under-Voltage Lockout Operation
If the supply (input) is below the UVLO threshold,
the output is disabled, and the EN/Fault line is
driven low.
When the supply rises above the UVLO threshold,
the output is enabled and the EN/Fault is pulled
high through a 25μA current source without an
external pull-up resistor. The pull-up voltage is
limited to 4.95V.
Output Over-Voltage Protection
If the input voltage exceeds the over-voltage
protection (OVP) threshold, the output is clamped
at 5.7V (typ).
Current Limiting
When the chip is active, if load reaches the overcurrent protection (OCP) threshold (trip current)
or a short is present, the part switches to
constant-current mode (hold current). The chip
shuts down only if the over-current condition
eventually triggers thermal protection. However,
when the part is powered up by VCC or EN, the
load current should be smaller than the hold
current. Otherwise, the part can’t be fully turned
on.
In a typical application with a current-limiting
resistor of 22Ω, the trip current is 2.18A for Kelvin
current sensing and 4.3A for direct current
sensing. If the device is in normal operation and
passing 2.0A, it will only need to dissipate
160mW with the low ON resistance of 40mΩ. For
a package dissipation of 50°C/Watt, the
temperature rise is +8°C. Given a 25°C ambient
temperature, the typical package temperature is
33°C.
The MP5010B requires a heat sink during
constant-current mode (such as from a shortcircuit) to prevent unwanted shutdown: In
constant-current mode, the chip must dissipate
the power from a 5V drop. Without additional
heat dissipation at 50°C/Watt, the temperature
would exceed the thermal threshold (+175°C)
and the MP5010B will shutdown to force the
temperature to drop below a hysteresis level.
Without a heat sink, maintain the current below
600mA at + 25°C and below 360mA at +85°C to
prevent thermal shutdown.
Thermal Protection
If the temperature exceeds the thermal threshold,
the MP5010B disables its output and drives the
Enable/Fault line to the middle (MID) level (read
the following Enable/Fault Pin section for more
information). The thermal fault condition is
latched, and the part remains OFF until the
Enable/Fault line goes low. Cycling the power
below the UVLO threshold will also reset the fault
flag.
Fault and Enable Pin
The Enable/Fault pin is a bi-directional, threelevel I/O with a weak pull-up current (25μA, typ.).
The three levels are LOW, MID, and HIGH. It
functions to enable/disable the part and to relay
fault information.
Enable/Fault as an input:
1.
2.
LOW and MID disable the part.
LOW, in addition to disabling the part,
clears the fault flag.
3. HIGH enables the part (if the fault flag is
clear).
Enable/Fault as an output:
1. The pull-up current will allow a “wired
nor” pull-up to enable the part (if not
overridden).
2. An under-voltage condition will cause a
LOW on the Enable/Fault pin, and will
clear the fault flag.
3. A thermal fault will set a MID on the
Enable/Fault pin, and will set the fault
flag
MP5010B Rev. 1.0
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MP5010B – 3V-18V, 1A-5A PROGRAMMABLE CURRENT LIMIT SWITCH
The Enable/Fault line must remain above the
MID level for the output to turn ON.
The fault flag is an internal flip-flop that can be
set or reset under the following conditions:
1.
2.
3.
4.
Thermal Shutdown: set fault flag
Under-Voltage: reset fault flag
LOW on Enable/Fault pin: reset fault
flag
MID on Enable/Fault pin: no effect
Given a fault, the Enable/Fault pin is driven to
MID.
There are 4 types of faults, and each fault has a
direct and indirect effect on the Enable/Fault pin
and the internal fault flag. In a typical
application there are one or more of the
MP5010B chips in a system. The Enable/Fault
lines are typically be connected together.
Table 1—Fault Function Influence in Application
Fault description
Short/Over
Current
Internal action
Effect on Fault Pin
Effect on Flag
Effect on secondary Part
Limit current
none
none
none
Under Voltage
Output turns OFF
Flag is reset
Disables secondary output,
and resets fault flag.
Over Voltage
Limit output voltage
Shutdown. The part
is latched OFF until
a UVLO or
externally driven to
ground.
None
None
Flag is Set
Disables secondary part
output.
Thermal
Shutdown
Internally drives
Enable/Fault pin to
logic LOW
None
Internally drives
Enable/Fault pin
to MID
MP5010B Rev. 1.0
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MP5010B – 3V-18V, 1A-5A PROGRAMMABLE CURRENT LIMIT SWITCH
APPLICATION INFORMATION
Current Limit
Rise Time
The rise time is a function of the capacitor (Cdv/dt)
on the dv/dt pin. Table 4 lists typical rise times as
a function of capacitance.
The current limit is a function of the external
current-limit resistor. Table 2 and Table 3 list
examples of current values as a function of the
resistor value for both Kelvin current sensing and
direct current sensing.
Table 2: Current Limit vs. Current Limit Resistor (VCC=5V, Kelvin Current Sensing)
10
22
51
75
100
Trip Current (A)
2.31
2.18
2.05
2.00
1.99
Hold Current (A)
1.45
1.10
0.71
0.56
0.47
RLIMIT (Ω)
Table 3: Current Limit vs. Current Limit Resistor (VCC=5V, Direct Current Sensing)
RLIMIT (Ω)
Trip Current (A)
Hold Current (A)
22
51
75
100
220
4.31
2.79
3.10
1.29
2.69
0.91
2.52
2.43
2.31
0.40
Table 4: Rise Time vs. Cdv/dt
Cdv/dt
Rise Time
(typ., ms)
330pF
1nF
3.3nF
6.8nF
1.1
3
9.4
19.2
* Notes: Rise Time = KRT*(50pF+Cdv/dt), KRT =2.8E6
The “rise time” is measured by from 10% to 90%
of output voltage.
U
Input
Output
90%
Enable
10%
Rise Time
t
Figure 2—Rise Time
MP5010B Rev. 1.0
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MP5010B – 3V-16V, 3A PROGRAMMABLE CURRENT LIMIT SWITCH
PCB Layout
PCB layout is very important to achieve stable
operation. Please follow these guidelines and
use Figure 3 as reference.
•
Place RLIMIT close to the I-limit pin
•
Place Cdv/dt close to dv/dt pin
•
Place the input capacitor close to the VCC
pin.
•
Leave the N/C pin floating.
•
Place vias in the thermal pad and provide
enough copper area near the VCC pin and
Source pin for thermal dissipation.
Design Example
Below is a direct-current-sensing design example
following the application guidelines for the given
specifications:
Table 5: Design Example
VIN
Trip Current
Hold Current
5V
4.3A
2.8A
Figure 5 shows the application schematic. The
Typical Performance Characteristics section
shows the circuit waveforms. For more device
applications, please refer to the related
Evaluation Board Datasheet.
GND
EN/ FAULT
C4
RLIMIT
6
7
4 SOURCE
EN/ FAULT
8
3 SOURCE
dv/dt
9
2 SOURCE
GND
10
Cdv/dt
N/C
I_LIMIT
VIN
5 SOURCE
1 SOURCE
C3
C2
VIN
VOUT
Top Layer
VIN
Bottom Layer
Figure 3: PCB Layout
MP5010B Rev. 1.0
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MP5010B – 3V-18V, 1A-5A PROGRAMMABLE CURRENT LIMIT SWITCH
TYPICAL APPLICATION CIRCUITS
R1
VIN
11
6
7
8
EN
C1
1nF
VCC
N/C
I-Limit
Source
MP5010B
Enable/Fault
9 dv/dt
10
Source
Source
Source
5
4
VOUT
3
2
Source 1
GND
Figure 4: Typical Application Schematic with Kelvin Current Sensing
R1
VIN
11
6
7
8
EN
C1
1nF
VCC
N/C
I-Limit
Source
MP5010B
Enable/Fault
9 dv/dt
10
Source
GND
Source
Source
5
4
VOUT
3
2
Source 1
Figure 5: Typical Application Schematic with Direct Current Sensing
MP5010B Rev. 1.0
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MP5010B – 3V-18V, 1A-5A PROGRAMMABLE CURRENT LIMIT SWITCH
PACKAGE INFORMATION
QFN10 (3mm × 3mm)
2.90
3.10
0.30
0.50
PIN 1 ID
MARKING
0.18
0.30
2.90
3.10
PIN 1 ID
INDEX AREA
1.45
1.75
PIN 1 ID
SEE DETAIL A
10
1
2.25
2.55
0.50
BSC
5
6
TOP VIEW
BOTTOM VIEW
PIN 1 ID OPTION A
R0.20 TYP.
PIN 1 ID OPTION B
R0.20 TYP.
0.80
1.00
0.20 REF
0.00
0.05
SIDE VIEW
DETAIL A
NOTE:
2.90
0.70
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX.
4) DRAWING CONFORMS TO JEDEC MO-229, VARIATION VEED-5.
5) DRAWING IS NOT TO SCALE.
1.70
0.25
2.50
0.50
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP5010B Rev. 1.0
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