2M x 32-Bit Dynamic RAM Module HYM 322160S/GS-60/-70 Advanced Information • 2 097 152 words by 32-Bit organization (alternative 4 194 304 words by 16-Bit) • Fast access and cycle time 60 ns access time 110 ns cycle time (-60 version) 70 ns access time 130 ns cycle time (-70 version) • Fast page mode capability with 40 ns cycle time (-60 version) 45 ns cycle time (-70 version) • Single + 5 V (± 10 %) supply • Low power dissipation max. 4840 mW active (-60 version) max. 4400 mW active (-70 version) CMOS – 88 mW standby TTL – 176 mW standby • CAS-before-RAS refresh RAS-only-refresh Hidden-refresh • 8 decoupling capacitors mounted on substrate • All inputs, outputs and clocks fully TTL compatible • 72 pin double-sided Single in-Line Memory Module with 25.4 mm (1000 mil) height • Utilizes sixteen 1M × 4 DRAMs in 300 mil SOJ packages • 1024 refresh cycles / 16 ms • Tin-Lead contact pads (S - version) • Gold contact pads (GS - version) Ordering Information Type Ordering Code Package Description HYM 322160S-60 Q67100-Q2014 L-SIM-72-11 DRAM Module (access time 60 ns) HYM 322160S-70 Q67100-Q2015 L-SIM-72-11 DRAM Module (access time 70 ns) HYM 322160GS-60 Q67100-Q2016 L-SIM-72-11 DRAM Module (access time 60 ns) HYM 322160GS-70 Q67100-Q2017 L-SIM-72-11 DRAM Module (access time 70 ns) Semiconductor Group 551 09.94 HYM 322160S/GS-60/-70 2M x 32-Bit The HYM322160S/GS-60/-70 is a 8 MByte DRAM module organized as 2 097 152 words by 32-Bit in a 72-pin single-in-line package comprising sixteen HYB514400BJ 1M × 4 DRAMs in 300 mil wide SOJ-packages mounted together with eight 0.2 µF ceramic decoupling capacitors on a PC board. The HYM322160S/GS-60/-70 can also be used as a 4 194 304 words by 16-Bits dynamic RAM module by means of connecting DQ0 and DQ16, DQ1 and DQ17, DQ2 and DQ18, …, DQ15 and DQ31, respectively. Each HYB514400BJ is described in the data sheet and is fully electrical tested and processed according to SIEMENS standard quality procedure prior to module assembly. After assembly onto the board, a further set of electrical tests is performed. The speed of the module can be detected by the use of four presence detect pins. The common I/O feature on the HYM 322160S/GS-60/-70 dictates the use of early write cycles. Pin Definitions and Functions Pin No. Function A0-A9 Address Inputs DQ0-DQ31 Data Input/Output CAS0 - CAS3 Column Address Strobe RAS0 - RAS3 Row Address Strobe WE Read/Write Input VCC Power (+ 5 V) VSS Ground PD Presence Detect Pin N.C. No Connection Presence Detect Pins -60 -70 PD0 N.C. N.C. PD1 N.C. N.C. PD2 N.C. VSS PD3 N.C. N.C. Semiconductor Group 552 HYM 322160S/GS-60/-70 2M x 32-Bit Pin Configuration (top view) Semiconductor Group 553 HYM 322160S/GS-60/-70 2M x 32-Bit Block Diagram Semiconductor Group 554 HYM 322160S/GS-60/-70 2M x 32-Bit Absolute Maximum Ratings Operation temperature range ......................................................................................... 0 to + 70 ˚C Storage temperature range......................................................................................... – 55 to 125 ˚C Soldering temperature ............................................................................................................ 260 ˚C Soldering time ............................................................................................................................. 10 s Input/output voltage ........................................................................................................ – 1 to + 7 V Power supply voltage...................................................................................................... – 1 to + 7 V Power dissipation..................................................................................................................... 6.2 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics1) TA = 0 to 70 ˚C, VCC = 5 V ± 10 % Parameter Symbol Limit Values min. max. Unit Input high voltage VIH 2.4 5.5 V Input low voltage VIL – 1.0 0.8 V Output high voltage (IOUT = – 5 mA) VOH 2.4 – V Output low voltage (IOUT = 4.2 mA) VOL – 0.4 V Input leakage current (0 V < VIN < 6.5 V, all other pins = 0 V) II(L) – 20 20 µA Output leakage current (DO is disabled, 0 V < VOUT < 5.5 V) IO(L) – 20 20 µA – – 880 800 mA mA ICC2 – 32 mA Average VCC supply current ICC3 during RAS only refresh cycles (RAS cycling, CAS = VIH, tRC = tRC min) -60 version -70 version – – 880 800 mA mA ICC1 Average VCC supply current (RAS, CAS, address cycling, tRC = tRC min) -60 version -70 version Standby VCC supply current (RAS = CAS = VIH) Semiconductor Group 555 Test Condition 2) , 3) 2) HYM 322160S/GS-60/-70 2M x 32-Bit DC Characteristics1) (cont’d) Parameter Symbol Limit Values Unit Test Condition 2) min. max. – – 560 560 mA mA ICC5 – 16 mA Average VCC supply current ICC6 during CAS-before-RAS refresh mode (RAS, CAS cycling, tRC = tRC min) -60 version -70 version – – 880 800 mA mA Average VCC supply current ICC4 during fast page mode (RAS = VIL, CAS, address cycling, tPC = tPC min) -60 version -70 version Standby VCC supply current (RAS = CAS = VCC – 0.2 V) , 3) 2) Capacitance TA = 0 to 70 ˚C, VCC = 5 V ± 10 %, f = 1 MHz Parameter Symbol Limit Values min. max. Unit Input capacitance (A0 to A9, WE) CI1 – 120 pF Input capacitance (RAS0-RAS2, CAS0-CAS3) CI2 – 40 pF I/O capacitance (DQ0-DQ31) CIO1 – 29 pF Semiconductor Group 556 HYM 322160S/GS-60/-70 2M x 32-Bit AC Characteristics 4) 5) TA = 0 to 70 ˚C, VCC = 5 V ± 10 %, tT = 5 ns Parameter Symbol Limit Values HYM 322160S/GS-60 Unit HYM 322160S/GS-70 min. max. min. max. Random read or write cycle time tRC 110 – 130 – ns Fast page mode cycle time tPC 40 – 45 – ns Access time from RAS 6) 11) 12) tRAC – 60 – 70 ns Access time from CAS 6) 11) tCAC – 15 – 20 ns tAA – 30 – 35 ns tCPA – 35 – 40 ns Access time from column address Access time from CAS precharge 6) 12) 6) CAS to output in low-Z 6) tCLZ 0 – 0 – ns Output buffer turn-off delay 7) tOFF 0 20 0 20 ns Transition time (rise and fall) 5) tT 3 50 3 50 ns RAS precharge time tRP 40 – 50 – ns RAS pulse width tRAS 60 10000 70 10000 ns RAS pulse width tRASP 60 200000 70 200000 ns CAS precharge to RAS delay tRHCP 35 – 40 – ns RAS hold time tRSH 15 – 20 – ns CAS hold time tCSH 60 – 70 – ns CAS pulse width tCAS 15 10000 20 10000 ns tRCD 20 45 20 50 ns tRAD 15 30 15 35 ns CAS to RAS precharge time tCRP 5 – 5 – ns CAS precharge time (fast page mode) tCP 10 – 10 – ns Row address setup time tASR 0 – 0 – ns Row address hold time tRAH 10 – 10 – ns Column address setup time tASC 0 – 0 – ns Column address hold time tCAH 15 – 15 – ns (fast page mode) RAS to CAS delay time RAS to column address delay time Semiconductor Group 11) 12) 557 HYM 322160S/GS-60/-70 2M x 32-Bit AC Characteristics4) 5) (cont’d) TA = 0 to 70 ˚C, VCC = 5 V ± 10 %, tT = 5 ns Parameter Symbol Limit Values HYM 322160S/GS-60 Unit HYM 322160S/GS-70 min. max. min. max. 30 – 35 – ns tRCS 0 – 0 – ns tRCH 0 – 0 – ns tRRH 0 – 0 – ns Write command hold time tWCH 10 – 15 – ns Write command pulse width tWP 10 – 15 – ns Write command to RAS lead time tRWL 15 – 20 – ns Write command to CAS lead time tCWL 15 – 20 – ns Column address to RAS lead time tRAL Read command setup time Read command hold time Read command hold time ref. to RAS 8) 8) Data setup time 9) tDS 0 – 0 – ns Data hold time 9) tDH 15 – 15 – ns tREF – 16 – 16 ms Write command setup time 10) tWCS 0 – 0 – ns CAS setup time 13) tCSR 5 – 5 – ns CAS hold time 13) tCHR 15 – 15 – ns RAS to CAS precharge time tRPC 0 – 0 – ns CAS precharge time tCP 10 – 10 – ns Refresh period Write to RAS precharge time 13) tWRP 10 – 10 – ns Write hold time ref. to RAS 13) tWRH 10 – 10 – ns Semiconductor Group 558 HYM 322160S/GS-60/-70 2M x 32-Bit Notes: 1) All voltages are referenced to VSS . 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles out of which at least one cycle has to be a refresh cycle before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 5) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL . 6) Measured with a load equivalant of 2 TTL loads and 100 pF. 7) tOFF (max.) defines the time at which the output achieves the open-circuit condition and is not referenced to output voltage levels. 8) Either tRCH or tRRH must be satisfied for a read cycle. 9) These parameters are referenced to the CAS leading edge. 10) tWCS is not a restrictive operating parameter. This is included in the data sheet as electrical characteristic only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance). 11) Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC . 12) Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA . 13)For CAS-before-RAS cycles only. Semiconductor Group 559