14-Output Clock Generator
AD9516-5
FEATURES
APPLICATIONS
Low jitter, low phase noise clock distribution
10/40/100 Gb/sec networking line cards, including SONET,
Synchronous Ethernet, OTU2/3/4
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
GENERAL DESCRIPTION
The AD9516-51 provides a multi-output clock distribution function
with subpicosecond jitter performance, along with an on-chip PLL
that can be used with an external VCO/VCXO of up to 2.4 GHz.
The AD9516-5 emphasizes low jitter and phase noise to
maximize data converter performance, and it can benefit other
applications with demanding phase noise and jitter requirements.
FUNCTIONAL BLOCK DIAGRAM
CP
REFIN
REF2
CLK
STATUS
MONITOR
PLL
REF1
REFIN
SWITCHOVER
AND MONITOR
DIVIDER
AND MUXes
CLK
DIV/Φ
LVPECL
DIV/Φ
LVPECL
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
LVPECL
∆t
∆t
∆t
∆t
SERIAL CONTROL PORT
AND
DIGITAL LOGIC
LVDS/CMOS
LVDS/CMOS
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
AD9516-5
07972-001
Low phase noise, phase-locked loop (PLL)
External VCO/VCXO to 2.4 GHz optional
1 differential or 2 single-ended reference inputs
Reference monitoring capability
Automatic revertive and manual reference
switchover/holdover modes
Accepts LVPECL, LVDS, or CMOS references to 250 MHz
Programmable delays in path to PFD
Digital or analog lock detect, selectable
Six 1.6 GHz LVPECL outputs, arranged in 3 groups
Each group shares a 1-to-32 divider with coarse phase delay
Additive output jitter: 225 fs rms
Channel-to-channel skew paired outputs of <10 ps
Four 800 MHz LVDS outputs, arranged in 2 groups
Each group has 2 cascaded 1-to-32 dividers with coarse
phase delay
Additive output jitter: 275 fs rms
Fine delay adjust (Δt) on each LVDS output
Each LVDS output can be reconfigured as two 250 MHz
CMOS outputs
Automatic synchronization of all outputs on power-up
Manual output synchronization available
Available in 64-lead LFCSP
Figure 1.
The AD9516-5 features six LVPECL outputs (in three pairs)
and four LVDS outputs (in two pairs). Each LVDS output can
be reconfigured as two CMOS outputs. The LVPECL outputs
operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and
the CMOS outputs operate to 250 MHz.
Each pair of outputs has dividers that allow both the divide ratio
and coarse delay (or phase) to be set. The range of division for
the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow
a range of divisions up to a maximum of 1024.
The AD9516-5 is available in a 64-lead LFCSP and can be
operated from a single 3.3 V supply. An external VCO, which
requires an extended voltage range, can be accommodated by
connecting the charge pump supply (VCP) to 5.5 V. A separate
LVPECL power supply can be from 2.375 V to 3.6 V (nominal).
The AD9516-5 is specified for operation over the industrial
range of −40°C to +85°C.
For applications requiring an integrated EEPROM, or needing
additional outputs, the AD9520-5 and AD9522-5 are available.
1
AD9516 is used throughout the data sheet to refer to all members of the AD9516
family. However, when AD9516-5 is used, it refers to that specific member of the
AD9516 family.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2009–2011 Analog Devices, Inc. All rights reserved.
AD9516-5
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ........................................... 18
Applications....................................................................................... 1
Terminology .................................................................................... 23
General Description ......................................................................... 1
Detailed Block Diagram ................................................................ 24
Functional Block Diagram .............................................................. 1
Theory of Operation ...................................................................... 25
Revision History ............................................................................... 3
Operational Configurations...................................................... 25
Specifications..................................................................................... 4
Lock Detect ................................................................................. 31
Power Supply Requirements ....................................................... 4
Clock Distribution ..................................................................... 35
PLL Characteristics ...................................................................... 4
Reset Modes ................................................................................ 43
Clock Inputs .................................................................................. 6
Power-Down Modes .................................................................. 43
Clock Outputs ............................................................................... 6
Serial Control Port ......................................................................... 44
Clock Output Additive Phase Noise (Distribution Only;
VCO Divider Not Used) .............................................................. 7
Serial Control Port Pin Descriptions....................................... 44
Clock Output Absolute Time Jitter (Clock Generation
Using External VCXO) ................................................................ 8
Instruction Word (16 Bits)........................................................ 45
Clock Output Additive Time Jitter (VCO Divider
Not Used)....................................................................................... 8
Thermal Performance.................................................................... 48
Clock Output Additive Time Jitter (VCO Divider Used) ....... 9
Register Maps.................................................................................. 49
Delay Block Additive Time Jitter................................................ 9
Register Map Overview ............................................................. 49
Serial Control Port ..................................................................... 10
Register Map Descriptions........................................................ 52
PD, RESET, and SYNC Pins ..................................................... 10
Applications Information .............................................................. 71
LD, STATUS, and REFMON Pins............................................ 11
Power Dissipation....................................................................... 11
Timing Characteristics .............................................................. 13
Absolute Maximum Ratings.......................................................... 15
Thermal Resistance .................................................................... 15
ESD Caution................................................................................ 15
Pin Configuration and Function Descriptions........................... 16
General Operation of Serial Control Port............................... 44
MSB/LSB First Transfers ........................................................... 45
Frequency Planning Using the AD9516 .................................. 71
Using the AD9516 Outputs for ADC Clock Applications .... 71
LVPECL Clock Distribution ..................................................... 72
LVDS Clock Distribution .......................................................... 72
CMOS Clock Distribution ........................................................ 73
Outline Dimensions ....................................................................... 74
Ordering Guide .......................................................................... 74
Rev. A | Page 2 of 76
AD9516-5
REVISION HISTORY
8/11—Rev. 0 to Rev. A
Changes to Features, Applications, and General Description ..... 1
Changes to CPRSET Pin Resistor Parameter, Table 1 .................. 4
Change to P = 2 DM (2/3) Parameter, Table 2 .............................. 5
Changes Test Conditions/Comments, Table 4 .............................. 6
Moved Table 5 to End of Specifications and Renumbered
Sequentially ...................................................................................... 13
Change to Shortest Delay Range Parameter,
Test Conditions/Comments, Table 14 .......................................... 13
Moved Timing Diagrams ............................................................... 14
Change to Endnote, Table 16 ......................................................... 15
Change to Caption, Figure 8 .......................................................... 18
Change to Captions, Figure 20 and Figure 21 ............................. 20
Moved Figure 23 and Figure 24 ..................................................... 21
Added Figure 31; Renumbered Sequentially ............................... 22
Change to Mode 1—Clock Distribution or External VCO <
1600 MHz Section ..........................................................................25
Changes to Mode 2 (High Frequency Clock Distribution)—
CLK or External VCO > 1600 MHz; Change to Table 22 .......... 26
Change to Charge Pump (CP) Section ......................................... 28
Changes to PLL Reference Inputs and Reference Switchover
Sections ............................................................................................. 29
Changes to Prescaler Section and Table 24 .................................. 30
Changes to A and B Counters, Digital Lock Detect (DLD),
and Current Source Digital Lock Detect (CSDLD) Sections .... 31
Change to Holdover Section .......................................................... 32
Changes to Automatic/Internal Holdover Mode ........................ 34
Changes to Clock Distribution Section........................................ 35
Changes to Channel Dividers—LVDS/CMOS Outputs
Section .............................................................................................. 37
Change to the Instruction Word (16 Bits) Section ..................... 45
Change to Figure 53 ........................................................................ 46
Changes to θJA and ΨJT Parameters, Table 46 ............................... 48
Changes to Register Address 0x003 and
Register Address 0x01C, Table 47 ................................................. 49
Changes to Register Address 0x003, Table 48 ............................. 52
Changes to Register Address 0x016, Bits[2:0], Table 49 ............ 54
Changes to Register Address 0x01C, Bits[4:3], Table 49 ........... 57
Changes to Register Address 0x191, Register Address 0x194,
and Register Address 0x197, Bit 5, Table 53 ................................ 66
Added Frequency Planning Using the AD9516 Section ............ 71
Changes to LVPECL Clock Distribution and LVDS Clock
Distribution Sections; Changes to Figure 59, Figure 60, and
Figure 61 ........................................................................................... 72
1/09—Revision 0: Initial Version
Rev. A | Page 3 of 76
AD9516-5
SPECIFICATIONS
Typical is given for VS = VS_LVPECL = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted.
Minimum and maximum values are given over full VS and TA (−40°C to +85°C) variation.
POWER SUPPLY REQUIREMENTS
Table 1.
Parameter
VS
VS_LVPECL
VCP
RSET Pin Resistor
CPRSET Pin Resistor
Min
3.135
2.375
VS
Typ
3.3
Max
3.465
VS
5.25
2.7
4.12
5.1
10
Unit
V
V
V
kΩ
kΩ
Min
Typ
Max
Unit
Test Conditions/Comments
3.3 V ± 5%
Nominally 2.5 V to 3.3 V ± 5%
Nominally 3.3 V to 5.0 V ± 5%
Sets internal biasing currents; connect to ground
Sets internal CP current range, nominally 4.8 mA
(CP_lsb = 600 μA); actual current can be calculated by:
CP_lsb = 3.06/CPRSET; connect to ground
Test Conditions/Comments
PLL CHARACTERISTICS
Table 2.
Parameter
REFERENCE INPUTS
Differential Mode (REFIN, REFIN)
Input Frequency
0
Input Sensitivity
Self-Bias Voltage, REFIN
Self-Bias Voltage, REFIN
Input Resistance, REFIN
Input Resistance, REFIN
Dual Single-Ended Mode (REF1, REF2)
Input Frequency (AC-Coupled)
Input Frequency (DC-Coupled)
Input Sensitivity (AC-Coupled)
Input Logic High
Input Logic Low
Input Current
Input Capacitance
250
250
1.35
1.30
4.0
4.4
1.60
1.50
4.8
5.3
20
0
CHARGE PUMP (CP)
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
CPRSET Range
ICP High Impedance Mode Leakage
Sink-and-Source Current Matching
ICP vs. CPV
ICP vs. Temperature
1.75
1.60
5.9
6.4
V
V
kΩ
kΩ
250
250
MHz
MHz
V p-p
V
V
μA
pF
2.0
0.8
+100
2
PHASE/FREQUENCY DETECTOR (PFD)
PFD Input Frequency
Antibacklash Pulse Width
mV p-p
0.8
−100
MHz
100
45
1.3
2.9
6.0
MHz
MHz
ns
ns
ns
4.8
0.60
2.5
2.7/10
1
2
1.5
2
mA
mA
%
kΩ
nA
%
%
%
Rev. A | Page 4 of 76
Differential mode (can accommodate single-ended
input by ac grounding undriven input)
Frequencies below about 1 MHz should be dc-coupled;
be careful to match VCM (self-bias voltage)
PLL figure of merit (FOM) increases with increasing slew
rate; see Figure 13
Self-bias voltage of REFIN 1
Self-bias voltage of REFIN1
Self-biased1
Self-biased1
Two single-ended CMOS-compatible inputs
Slew rate > 50 V/μs
Slew rate > 50 V/μs; CMOS levels
Should not exceed VS p-p
Each pin, REFIN/REFIN (REF1/REF2)
Antibacklash pulse width = 1.3 ns, 2.9 ns
Antibacklash pulse width = 6.0 ns
Register 0x017[1:0] = 01b
Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b
Register 0x017[1:0] = 10b
Programmable
With CPRSET = 5.1 kΩ
CPV = VCP/2
0.5 < CPV < VCP − 0.5 V
0.5 < CPV < VCP − 0.5 V
VCP = VCP/2 V
AD9516-5
Parameter
PRESCALER (PART OF N DIVIDER)
Prescaler Input Frequency
P = 1 FD
P = 2 FD
P = 3 FD
P = 2 DM (2/3)
P = 4 DM (4/5)
P = 8 DM (8/9)
P = 16 DM (16/17)
P = 32 DM (32/33)
Prescaler Output Frequency
PLL DIVIDER DELAYS
000
001
010
011
100
101
110
111
NOISE CHARACTERISTICS
In-Band Phase Noise of the Charge
Pump/Phase Frequency Detector
(In-Band Is Within the LBW of the PLL)
At 500 kHz PFD Frequency
At 1 MHz PFD Frequency
At 10 MHz PFD Frequency
At 50 MHz PFD Frequency
PLL Figure of Merit (FOM)
Min
Typ
Off
330
440
550
660
770
880
990
Max
Unit
300
600
900
200
1000
2400
3000
3000
300
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
1
2
A, B counter input frequency (prescaler input frequency
divided by P)
Register 0x019: R, Bits[5:3]; N, Bits[2:0]; see Table 49
ps
ps
ps
ps
ps
ps
ps
ps
The PLL in-band phase noise floor is estimated by
measuring the in-band phase noise at the output of
the VCO and subtracting 20 log(N) (where N is the
value of the N divider)
−165
−162
−151
−143
−220
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
3.5
7.5
3.5
ns
ns
ns
Reference slew rate > 0.25 V/ns; FOM + 10 log(fPFD) is
an approximation of the PFD/CP in-band phase noise
(in the flat region) inside the PLL loop bandwidth; when
running closed-loop, the phase noise, as observed at
the VCO output, is increased by 20 log(N)
Signal available at the LD, STATUS, and REFMON pins
when selected by appropriate register settings
Selected by Register 0x017[1:0] and Register 0x018[4]
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
7
15
11
ns
ns
ns
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
PLL DIGITAL LOCK DETECT WINDOW 2
Required to Lock (Coincidence of Edges)
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
To Unlock After Lock (Hysteresis)2
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
Test Conditions/Comments
See the VCXO/VCO Feedback Divider N—P, A, B section
The REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition.
For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
Rev. A | Page 5 of 76
AD9516-5
CLOCK INPUTS
Table 3.
Parameter
CLOCK INPUTS (CLK, CLK)
Input Frequency
Min
Typ
01
01
Input Sensitivity, Differential
1
Unit
2.4
1.6
GHz
GHz
150
mV p-p
Input Level, Differential
Input Common-Mode Voltage, VCM
Input Common-Mode Range, VCMR
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
Max
1.3
1.3
3.9
1.57
150
4.7
2
2
V p-p
1.8
1.8
V
V
mV p-p
kΩ
pF
5.7
Test Conditions/Comments
Differential input
High frequency distribution (VCO divider enabled)
Distribution only (VCO divider bypassed; this is the
frequency range supported by the channel divider)
Measured at 2.4 GHz; jitter performance is
improved with slew rates > 1 V/ns
Larger voltage swings may turn on the
protection diodes and may degrade jitter
performance
Self-biased; enables ac coupling
With 200 mV p-p signal applied; dc-coupled
CLK ac-coupled; CLK ac-bypassed to RF ground
Self-biased
Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM.
CLOCK OUTPUTS
Table 4.
Parameter
LVPECL CLOCK OUTPUTS
OUT0, OUT1, OUT2, OUT3, OUT4,
OUT5
Output Frequency, Maximum
Min
Typ
Max
2400
Unit
Test Conditions/Comments
Termination = 50 Ω to VS_LVPECL − 2 V
Differential (OUT, OUT)
MHz
Using direct to output; see Figure 20 for peak-topeak differential amplitude
Measured at dc using the default amplitude setting;
see Figure 20 for amplitude vs. frequency
Measured at dc using the default amplitude setting;
see Figure 20 for amplitude vs. frequency
VOH − VOL for each leg of a differential pair for
default amplitude setting with driver not toggling;
see Figure 20 for variation over frequency
Differential termination 100 Ω at 3.5 mA
Differential (OUT, OUT)
The AD9516 outputs can toggle at higher
frequencies, but the output amplitude may not
meet the VOD specification; see Figure 21
VOH − VOL measurement across a differential pair
at the default amplitude setting with output
driver not toggling; see Figure 21 for variation
over frequency
This is the absolute value of the difference between
VOD when the normal output is high vs. when the
complementary output is high
(VOH + VOL)/2 across a differential pair at the
default amplitude setting with output driver not
toggling
This is the absolute value of the difference between
VOS when the normal output is high vs. when the
complementary output is high
Output shorted to GND
Output High Voltage (VOH)
VS_LVPECL − 1.12
VS_LVPECL − 0.98
VS_LVPECL − 0.84
V
Output Low Voltage (VOL)
VS_LVPECL − 2.03
VS_LVPECL − 1.77
VS_LVPECL − 1.49
V
Output Differential Voltage (VOD)
550
790
980
mV
LVDS CLOCK OUTPUTS
OUT6, OUT7, OUT8, OUT9
Output Frequency, Maximum
Differential Output Voltage (VOD)
800
247
MHz
360
Delta VOD
Output Offset Voltage (VOS)
1.125
1.24
Delta VOS
Short-Circuit Current (ISA, ISB)
CMOS CLOCK OUTPUTS
OUT6A, OUT6B, OUT7A, OUT7B,
OUT8A, OUT8B, OUT9A, OUT9B
Output Frequency
Output Voltage High (VOH)
Output Voltage Low (VOL)
14
454
mV
25
mV
1.375
V
25
mV
24
mA
Single-ended; termination = 10 pF
250
VS_LVPECL − 0.1
0.1
Rev. A | Page 6 of 76
MHz
V
V
See Figure 22
At 1 mA load
At 1 mA load
AD9516-5
CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED)
Table 5.
Parameter
CLK-TO-LVPECL ADDITIVE PHASE NOISE
CLK = 1 GHz, Output = 1 GHz
Divider = 1
At 10 Hz Offset
At 100 Hz Offset
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
At 100 MHz Offset
CLK = 1 GHz, Output = 200 MHz
Divider = 5
At 10 Hz Offset
At 100 Hz Offset
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
>10 MHz Offset
CLK-TO-LVDS ADDITIVE PHASE NOISE
CLK = 1.6 GHz, Output = 800 MHz
Divider = 2
At 10 Hz Offset
At 100 Hz Offset
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
At 100 MHz Offset
CLK = 1.6 GHz, Output = 400 MHz
Divider = 4
At 10 Hz Offset
At 100 Hz Offset
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
>10 MHz Offset
CLK-TO-CMOS ADDITIVE PHASE NOISE
CLK = 1 GHz, Output = 250 MHz
Divider = 4
At 10 Hz Offset
At 100 Hz Offset
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
>10 MHz Offset
Min
Typ
Max
−109
−118
−130
−139
−144
−146
−147
−149
Unit
Test Conditions/Comments
Distribution section only; does not include PLL input
slew rate > 1 V/ns
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Input slew rate > 1 V/ns
−120
−126
−139
−150
−155
−157
−157
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Distribution section only; does not include input slew
rate > 1 V/ns
−103
−110
−120
−127
−133
−138
−147
−149
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Input slew rate > 1 V/ns
−114
−122
−132
−140
−146
−150
−155
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Distribution section only; does not include PLL input
slew rate > 1 V/ns
−110
−120
−127
−136
−144
−147
−154
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Rev. A | Page 7 of 76
AD9516-5
Parameter
CLK = 1 GHz, Output = 50 MHz
Divider = 20
At 10 Hz Offset
At 100 Hz Offset
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
>10 MHz Offset
Min
Typ
Max
−124
−134
−142
−151
−157
−160
−163
Unit
Test Conditions/Comments
Input slew rate > 1 V/ns
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)
Table 6.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
Min
LVPECL = 245.76 MHz; PLL LBW = 125 Hz
Typ
Max
54
77
109
79
114
163
124
176
259
LVPECL = 122.88 MHz; PLL LBW = 125 Hz
LVPECL = 61.44 MHz; PLL LBW = 125 Hz
Unit
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
Test Conditions/Comments
Application example based on a typical setup using
an external 245.76 MHz VCXO (Toyocom TCO-2112);
reference = 15.36 MHz; R = 1
Integration bandwidth = 200 kHz to 5 MHz
Integration bandwidth = 200 kHz to 10 MHz
Integration bandwidth = 12 kHz to 20 MHz
Integration bandwidth = 200 kHz to 5 MHz
Integration bandwidth = 200 kHz to 10 MHz
Integration bandwidth = 12 kHz to 20 MHz
Integration bandwidth = 200 kHz to 5 MHz
Integration bandwidth = 200 kHz to 10 MHz
Integration bandwidth = 12 kHz to 20 MHz
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 7.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
CLK = 622.08 MHz; LVPECL = 622.08 MHz;
Divider = 1
CLK = 622.08 MHz; LVPECL = 155.52 MHz;
Divider = 4
CLK = 1.6 GHz; LVPECL = 100 MHz;
Divider = 16
CLK = 500 MHz; LVPECL = 100 MHz;
Divider = 5
LVDS OUTPUT ADDITIVE TIME JITTER
CLK = 1.6 GHz; LVDS = 800 MHz; Divider = 2
(VCO Divider Not Used)
CLK = 1 GHz; LVDS = 200 MHz; Divider = 5
CLK = 1.6 GHz; LVDS = 100 MHz; Divider = 16
Min
Typ
Max
Unit
40
fs rms
Test Conditions/Comments
Distribution section only; does not include PLL;
uses rising edge of clock signal
Bandwidth = 12 kHz to 20 MHz
80
fs rms
Bandwidth = 12 kHz to 20 MHz
215
fs rms
245
fs rms
Calculated from SNR of ADC method; DCC not used
for even divides
Calculated from SNR of ADC method; DCC on
85
fs rms
Distribution section only; does not include PLL;
uses rising edge of clock signal
Bandwidth = 12 kHz to 20 MHz
113
280
fs rms
fs rms
365
fs rms
CMOS OUTPUT ADDITIVE TIME JITTER
CLK = 1.6 GHz; CMOS = 100 MHz; Divider = 16
Rev. A | Page 8 of 76
Bandwidth = 12 kHz to 20 MHz
Calculated from SNR of ADC method; DCC not used
for even divides
Distribution section only; does not include PLL; uses
rising edge of clock signal
Calculated from SNR of ADC method; DCC not used
for even divides
AD9516-5
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 8.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
Min
Typ
CLK = 2.4 GHz; VCO Div = 2; LVPECL = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
LVDS OUTPUT ADDITIVE TIME JITTER
210
CLK = 2.4 GHz; VCO Div = 2; LVDS = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
CMOS OUTPUT ADDITIVE TIME JITTER
285
CLK = 2.4 GHz; VCO Div = 2; CMOS = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
350
Max
Unit
fs rms
Test Conditions/Comments
Distribution section only; does not include PLL;
uses rising edge of clock signal
Calculated from SNR of ADC method
fs rms
Distribution section only; does not include PLL;
uses rising edge of clock signal
Calculated from SNR of ADC method
fs rms
Distribution section only; does not include PLL;
uses rising edge of clock signal
Calculated from SNR of ADC method
DELAY BLOCK ADDITIVE TIME JITTER
Table 9.
Parameter
DELAY BLOCK ADDITIVE TIME JITTER 1
100 MHz Output
Delay (1600 μA, 0x1C) Fine Adjust 000000b
Delay (1600 μA, 0x1C) Fine Adjust 101111b
Delay (800 μA, 0x1C) Fine Adjust 000000b
Delay (800 μA, 0x1C) Fine Adjust 101111b
Delay (800 μA, 0x4C) Fine Adjust 000000b
Delay (800 μA, 0x4C) Fine Adjust 101111b
Delay (400 μA, 0x4C) Fine Adjust 000000b
Delay (400 μA, 0x4C) Fine Adjust 101111b
Delay (200 μA, 0x1C) Fine Adjust 000000b
Delay (200 μA, 0x1C) Fine Adjust 101111b
Delay (200 μA, 0x4C) Fine Adjust 000000b
Delay (200 μA, 0x4C) Fine Adjust 101111b
1
Min
Typ
Max
0.54
0.60
0.65
0.85
0.79
1.2
1.2
2.0
1.3
2.5
1.9
3.8
Unit
Test Conditions/Comments
Incremental additive jitter
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
This value is incremental; that is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter
should be added to this value using the root sum of the squares (RSS) method.
Rev. A | Page 9 of 76
AD9516-5
SERIAL CONTROL PORT
Table 10.
Parameter
CS (INPUT)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SCLK (INPUT)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO (WHEN INPUT)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage
Output Logic 0 Voltage
TIMING
Clock Rate (SCLK, 1/tSCLK)
Pulse Width High, tHIGH
Pulse Width Low, tLOW
SDIO to SCLK Setup, tDS
SCLK to SDIO Hold, tDH
SCLK to Valid SDIO and SDO, tDV
CS to SCLK Setup and Hold, tS, tH
CS Minimum Pulse Width High, tPWH
Min
Typ
Max
2.0
0.8
3
110
2
Unit
Test Conditions/Comments
CS has an internal 30 kΩ pull-up resistor
V
V
μA
μA
pF
SCLK has an internal 30 kΩ pull-down resistor
2.0
0.8
110
1
2
2.0
0.8
10
20
2
2.7
0.4
25
16
16
2
1.1
8
2
3
V
V
μA
μA
pF
V
V
nA
nA
pF
V
V
MHz
ns
ns
ns
ns
ns
ns
ns
PD, RESET, AND SYNC PINS
Table 11.
Parameter
INPUT CHARACTERISTICS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Capacitance
RESET TIMING
Pulse Width Low
SYNC TIMING
Pulse Width Low
Min
Typ
Max
2.0
0.8
110
1
2
Unit
Test Conditions/Comments
Each of these pins has an internal 30 kΩ pull-up resistor
V
V
μA
μA
pF
50
ns
1.5
High speed
clock cycles
Rev. A | Page 10 of 76
High speed clock is CLK input signal
AD9516-5
LD, STATUS, AND REFMON PINS
Table 12.
Parameter
OUTPUT CHARACTERISTICS
Min
Output Voltage High, VOH
Output Voltage Low, VOL
MAXIMUM TOGGLE RATE
2.7
Max
Unit
0.4
100
V
V
MHz
3
pF
On-chip capacitance; used to calculate RC time constant for
analog lock detect readback; use a pull-up resistor
1.02
MHz
8
kHz
Frequency above which the monitor always indicates the
presence of the reference
Frequency above which the monitor always indicates the
presence of the reference
ANALOG LOCK DETECT
Capacitance
REF1, REF2, AND CLK FREQUENCY STATUS
MONITOR
Normal Range
Extended Range
LD PIN COMPARATOR
Trip Point
Hysteresis
Typ
1.6
260
Test Conditions/Comments
When selected as a digital output (CMOS); there are other
modes in which these pins are not CMOS digital outputs; see
Table 49: Register 0x017, Register 0x01A, and Register 0x01B
Applies when mux is set to any divider or counter output or
PFD up/down pulse; also applies in analog lock detect mode;
usually debug mode only; beware that spurs may couple to
output when any of these pins are toggling
V
mV
POWER DISSIPATION
Table 13.
Parameter
POWER DISSIPATION, CHIP
Min
Typ
Max
Unit
Power-On Default
1.0
1.2
W
Full Operation; CMOS Outputs at 225 MHz
1.5
2.1
W
Full Operation; LVDS Outputs at 225 MHz
1.5
2.1
W
PD Power-Down
75
185
mW
PD Power-Down, Maximum Sleep
31
VCP Supply
4
AD9516 Core
220
mW
4.8
mW
mW
Test Conditions/Comments
The values in this table include all power supplies, unless
otherwise noted; the power deltas for individual drivers are
at dc; see Figure 7, Figure 8, and Figure 9 for power dissipation
vs. output frequency
No clock; no programming; default register values; does not
include power dissipated in external resistors; this configuration
has the following blocks already powered up: VCO divider,
six channel dividers, three LVPECL drivers, and two LVDS drivers
fCLK = 2.25 GHz; VCO divider = 2; all channel dividers on; six
LVPECL outputs at 562.5 MHz; eight CMOS outputs (10 pF load)
at 225 MHz; all four fine delay blocks on, maximum current;
does not include power dissipated in external resistors
fCLK = 2.25 GHz; VCO divider = 2; all channel dividers on; six
LVPECL outputs at 562.5 MHz; four LVDS outputs at 225 MHz;
all four fine delay blocks on: maximum current; does not include
power dissipated in external resistors
PD pin pulled low; does not include power dissipated in
terminations
PD pin pulled low; PLL power-down, Register 0x010[1:0] = 01b;
SYNC power-down, Register 0x230[2] = 1b; REF for distribution
power-down, Register 0x230[1] = 1b
PLL operating; typical closed-loop configuration (this
number is included in all other power measurements)
AD9516 core only, all drivers off, PLL off, VCO divider off, and
delay blocks off; the power consumption of the configuration
of the user can be derived from this number and the power
deltas that follow
Rev. A | Page 11 of 76
AD9516-5
Parameter
POWER DELTAS, INDIVIDUAL FUNCTIONS
VCO Divider
REFIN (Differential)
REF1, REF2 (Single-Ended)
Min
Typ
Max
Unit
30
20
4
mW
mW
mW
PLL
Channel Divider
LVPECL Channel (Divider Plus Output Driver)
75
30
120
mW
mW
mW
LVPECL Driver
90
mW
LVDS Channel (Divider Plus Output Driver)
140
mW
LVDS Driver
50
mW
CMOS Channel (Divider Plus Output Driver)
100
mW
CMOS Driver (Second in Pair)
0
mW
CMOS Driver (First in Second Pair)
30
mW
Fine Delay Block
50
mW
Test Conditions/Comments
Power delta when a function is enabled/disabled
VCO divider bypassed
All references off to differential reference enabled
All references off to REF1 or REF2 enabled; differential
reference not enabled
PLL off to PLL on, normal operation; no reference enabled
Divider bypassed to divide-by-2 to divide-by-32
No LVPECL output on to one LVPECL output on (that is, enabling
OUT0 with OUT1 off; Divider 0 enabled), independent of
frequency
Second LVPECL output turned on, same channel (that is,
enabling OUT0 with OUT1 already on)
No LVDS output on to one LVDS output on (that is, enabling
OUT8 with OUT9 off with Divider 4.1 enabled and Divider 4.2
bypassed); see Figure 8 for dependence on output frequency
Second LVDS output turned on, same channel (that is, enabling
OUT8 with OUT9 already on)
Static; no CMOS output on to one CMOS output on (that is,
enabling OUT8A starting with OUT8 and OUT9 off); see Figure 9
for variation over output frequency
Static; second CMOS output, same pair, turned on (that is,
enabling OUT8A with OUT8B already on)
Static; first output, second pair, turned on (that is, enabling
OUT9A with OUT9B off and OUT8A and OUT8B already on)
Delay block off to delay block enabled; maximum current
setting
Rev. A | Page 12 of 76
AD9516-5
TIMING CHARACTERISTICS
Table 14.
Parameter
LVPECL
Output Rise Time, tRP
Output Fall Time, tFP
PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUTPUT
High Frequency Clock Distribution Configuration
Clock Distribution Configuration
Variation with Temperature
OUTPUT SKEW, LVPECL OUTPUTS 1
LVPECL Outputs That Share the Same Divider
LVPECL Outputs on Different Dividers
All LVPECL Outputs Across Multiple Parts
LVDS
Output Rise Time, tRL
Output Fall Time, tFL
PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUTPUT
OUT6, OUT7, OUT8, OUT9
For All Divide Values
Variation with Temperature
OUTPUT SKEW, LVDS OUTPUTS1
LVDS Outputs That Share the Same Divider
LVDS Outputs on Different Dividers
All LVDS Outputs Across Multiple Parts
CMOS
Output Rise Time, tRC
Output Fall Time, tFC
PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUTPUT
For All Divide Values
Variation with Temperature
OUTPUT SKEW, CMOS OUTPUTS1
CMOS Outputs That Share the Same Divider
All CMOS Outputs on Different Dividers
All CMOS Outputs Across Multiple Parts
DELAY ADJUST 3
Shortest Delay Range 4
Zero Scale
Full Scale
Longest Delay Range4
Zero Scale
Quarter Scale
Full Scale
Delay Variation with Temperature
Short Delay Range5
Zero Scale
Full Scale
Long Delay Range 5
Zero Scale
Full Scale
Min
835
773
1.4
Typ
Max
Unit
70
70
180
180
ps
ps
995
933
0.8
1180
1090
ps
ps
ps/°C
5
13
15
40
220
ps
ps
ps
170
160
350
350
ps
ps
1.8
1.25
2.1
ns
ps/°C
6
25
62
150
430
ps
ps
ps
495
475
1000
985
ps
ps
2.1
2.6
2.6
ns
ps/°C
4
28
66
180
675
ps
ps
ps
Test Conditions/Comments
Termination = 50 Ω to VS_LVPECL − 2 V; default amplitude setting
(810 mV)
20% to 80%, measured differentially
80% to 20%, measured differentially
See Figure 34
See Figure 33
Termination = 100 Ω differential; 3.5 mA setting
20% to 80%, measured differentially 2
20% to 80%, measured differentially2
Delay off on all outputs
Delay off on all outputs
1.6
Termination = open
20% to 80%; CLOAD = 10 pF
80% to 20%; CLOAD = 10 pF
Fine delay off
Fine delay off
50
540
315
880
680
1180
ps
ps
200
1.72
5.7
570
2.31
8.0
950
2.89
10.1
ps
ns
ns
0.23
−0.02
ps/°C
ps/°C
0.3
0.24
ps/°C
ps/°C
1
LVDS and CMOS
Register 0x0A1 (0x0A4, 0x0A7, 0x0AA), Bits[5:0] = 101111b
Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 000000b
Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 101111b
Register 0x0A1 (0x0A4, 0x0A7, 0x0AA) Bits[5:0] = 000000b
Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 000000b
Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 001100b
Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 101111b
This is the difference between any two similar delay paths while operating at the same voltage and temperature.
Corresponding CMOS drivers set to OUTxA for noninverting and OUTxB for inverting; x = 6, 7, 8, or 9.
3
The maximum delay that can be used is a little less than one-half the period of the clock. A longer delay disables the output.
4
Incremental delay; does not include propagation delay.
5
All delays between zero scale and full scale can be estimated by linear interpolation.
2
Rev. A | Page 13 of 76
AD9516-5
Timing Diagrams
tCLK
CLK
DIFFERENTIAL
tPECL
80%
LVDS
tLVDS
tCMOS
tRL
tFL
07972-062
07972-060
20%
Figure 4. LVDS Timing, Differential
Figure 2. CLK/CLK to Clock Output Timing, Divider = 1
DIFFERENTIAL
SINGLE-ENDED
80%
80%
LVPECL
CMOS
10pF LOAD
20%
tFP
tRC
Figure 3. LVPECL Timing, Differential
tFC
Figure 5. CMOS Timing, Single-Ended, 10 pF Load
Rev. A | Page 14 of 76
07972-063
tRP
07972-061
20%
AD9516-5
ABSOLUTE MAXIMUM RATINGS
Table 15.
Parameter
VS, VS_LVPECL to GND
VCP to GND
REFIN, REFIN to GND
REFIN to REFIN
RSET to GND
CPRSET to GND
CLK, CLK to GND
CLK to CLK
SCLK, SDIO, SDO, CS to GND
OUT0, OUT0, OUT1, OUT1, OUT2, OUT2,
OUT3, OUT3, OUT4, OUT4, OUT5, OUT5,
OUT6, OUT6, OUT7, OUT7, OUT8, OUT8,
OUT9, OUT9 to GND
SYNC to GND
REFMON, STATUS, LD to GND
Temperature
Junction Temperature 1
Storage Temperature Range
Lead Temperature (10 sec)
1
Rating
−0.3 V to +3.6 V
−0.3 V to +5.8 V
−0.3 V to VS + 0.3 V
−3.3 V to +3.3 V
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
−1.2 V to +1.2 V
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Table 16.
Package Type1
64-Lead LFCSP (CP-64-4)
1
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
θJA
22
Unit
°C/W
Thermal impedance measurements were taken on a 4-layer board in still air
in accordance with EIA/JESD51-2.
ESD CAUTION
150°C
−65°C to +150°C
300°C
See Table 16 for θJA.
Rev. A | Page 15 of 76
AD9516-5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN 1
INDICATOR
AD9516-5
LVDS/CMOS
w/FINE DELAY ADJUST
LVPECL LVPECL
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
OUT6 (OUT6A)
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
GND
OUT2
OUT2
VS_LVPECL
OUT3
OUT3
VS
GND
OUT9 (OUT9B)
OUT9 (OUT9A)
OUT8 (OUT8B)
OUT8 (OUT8A)
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. EXPOSED DIE PAD MUST BE CONNECTED TO GND.
07972-003
CS
NC
NC
NC
SDO
SDIO
RESET
PD
OUT4
OUT4
VS_LVPECL
OUT5
OUT5
VS
VS
VS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
LVPECL LVPECL
LVDS/CMOS
w/FINE DELAY ADJUST
VS
REFMON
LD
VCP
CP
STATUS
REF_SEL
SYNC
NC
NC
VS
VS
CLK
CLK
NC
SCLK
LVPECL LVPECL
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
REFIN (REF1)
REFIN (REF2)
CPRSET
VS
VS
GND
RSET
VS
OUT0
OUT0
VS_LVPECL
OUT1
OUT1
VS
VS
VS
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 6. Pin Configuration
Table 17. Pin Function Descriptions
Pin No.
1, 11, 12, 30,
31, 32, 38,
49, 50, 51,
57, 60, 61
2
Input/
Output
I
Pin Type
Power
Mnemonic
VS
Description
3.3 V Power Pins.
O
3.3 V CMOS
REFMON
3
O
3.3 V CMOS
LD
4
5
I
O
Power
Loop filter
VCP
CP
6
O
3.3 V CMOS
STATUS
7
I
3.3 V CMOS
REF_SEL
8
I
3.3 V CMOS
SYNC
9, 10, 15, 18,
19, 20
13
N/A
NC
NC
Reference Monitor (Output). This pin has multiple selectable outputs;
see Table 49, Register 0x01B.
Lock Detect (Output). This pin has multiple selectable outputs; see Table 49,
Register 0x01A.
Power Supply for Charge Pump (CP); VS ≤ VCP ≤ 5.25 V.
Charge Pump (Output). This pin connects to an external loop filter. This pin can
be left unconnected if the PLL is not used.
Status (Output). This pin has multiple selectable outputs; see Table 49,
Register 0x017.
Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ
pull-down resistor.
Manual Synchronizations and Manual Holdover. This pin initiates a manual
synchronization and is also used for manual holdover. Active low. This pin has
an internal 30 kΩ pull-up resistor.
No Connection. These pins can be left floating.
I
CLK
Along with CLK, this is the differential input for the clock distribution section.
14
I
Differential
clock input
Differential
clock input
CLK
Along with CLK, this is the differential input for the clock distribution section.
If a single-ended input is connected to the CLK pin, connect a 0.1 μF bypass
capacitor from CLK to ground.
Rev. A | Page 16 of 76
AD9516-5
Pin No.
16
17
Input/
Output
I
I
Pin Type
3.3 V CMOS
3.3 V CMOS
Mnemonic
SCLK
CS
21
22
23
24
25
26
27, 41, 54
28
29
33
O
I/O
I
I
O
O
I
O
O
O
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
LVPECL
LVPECL
Power
LVPECL
LVPECL
LVDS or CMOS
SDO
SDIO
RESET
PD
OUT4
OUT4
VS_LVPECL
OUT5
OUT5
OUT8 (OUT8A)
34
O
LVDS or CMOS
OUT8 (OUT8B)
35
O
LVDS or CMOS
OUT9 (OUT9A)
36
O
LVDS or CMOS
OUT9 (OUT9B)
37, 44, 59,
EPAD
39
40
42
43
45
I
GND
GND
O
O
O
O
O
LVPECL
LVPECL
LVPECL
LVPECL
LVDS or CMOS
OUT3
OUT3
OUT2
OUT2
OUT7 (OUT7B)
46
O
LVDS or CMOS
OUT7 (OUT7A)
47
O
LVDS or CMOS
OUT6 (OUT6B)
48
O
LVDS or CMOS
OUT6 (OUT6A)
52
53
55
56
58
O
O
O
O
O
OUT1
OUT1
OUT0
OUT0
RSET
62
O
63
I
LVPECL
LVPECL
LVPECL
LVPECL
Current set
resistor
Current set
resistor
Reference
input
64
I
Reference
input
REFIN (REF1)
CPRSET
REFIN (REF2)
Description
Serial Control Port Data Clock Signal.
Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ pull-up
resistor.
Serial Control Port Unidirectional Serial Data Output.
Serial Control Port Bidirectional Serial Data Input/Output.
Chip Reset; Active Low. This pin has an internal 30 kΩ pull-up resistor.
Chip Power-Down; Active Low. This pin has an internal 30 kΩ pull-up resistor.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
Extended Voltage 2.5 V to 3.3 V LVPECL Power Pins.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended
CMOS Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended
CMOS Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended
CMOS Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended
CMOS Output.
Ground Pins, Including External Paddle (EPAD). The external die paddle on the
bottom of the package must be connected to ground for proper operation.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended
CMOS Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended
CMOS Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended
CMOS Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended
CMOS Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
A resistor connected to this pin sets internal bias currents. Nominal value = 4.12 kΩ.
A resistor connected to this pin sets the CP current range. Nominal value = 5.1 kΩ.
This resistor can be omitted if the PLL is not used.
Along with REFIN, this pin is the differential input for the PLL reference.
Alternatively, this pin is a single-ended input for REF2. This pin can be left
unconnected when the PLL is not used.
Along with REFIN, this pin is the differential input for the PLL reference.
Alternatively, this pin is a single-ended input for REF1. This pin can be left
unconnected when the PLL is not used.
Rev. A | Page 17 of 76
AD9516-5
TYPICAL PERFORMANCE CHARACTERISTICS
300
5.0
3 CHANNELS—6 LVPECL
280
4.5
CURRENT FROM CP PIN (mA)
260
220
200
3 CHANNELS—3 LVPECL
180
160
2 CHANNELS—2 LVPECL
140
4.0
3.5
PUMP DOWN
2.5
2.0
1.5
1.0
0.5
120
1 CHANNEL—1 LVPECL
500
1000
1500
2000
2500
3000
FREQUENCY (MHz)
0
0
1.0
1.5
2.0
2.5
3.0
VOLTAGE ON CP PIN (V)
Figure 7. Current vs. Frequency, Direct to Output, LVPECL Outputs
Figure 10. Charge Pump Characteristics at VCP = 3.3 V
180
5.0
4.5
2 CHANNELS—4 LVDS
CURRENT FROM CP PIN (mA)
160
140
2 CHANNELS—2 LVDS
120
100
400
600
800
PUMP DOWN
3.0
PUMP UP
2.5
2.0
1.5
1.0
FREQUENCY (MHz)
0
07972-008
200
3.5
0.5
1 CHANNEL—1 LVDS
80
0
4.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VOLTAGE ON CP PIN (V)
07972-012
CURRENT (mA)
0.5
07972-011
0
07972-007
100
Figure 11. Charge Pump Characteristics at VCP = 5.0 V
Figure 8. Current vs. Frequency—LVDS Outputs
(Includes Clock Distribution Current Draw)
240
PFD PHASE NOISE REFERRED TO PFD INPUT
(dBc/Hz)
–140
220
200
2 CHANNELS—8 CMOS
180
2 CHANNELS—2 CMOS
160
140
120
1 CHANNEL—2 CMOS
100
1 CHANNEL—1 CMOS
80
0
50
100
150
200
250
FREQUENCY (MHz)
Figure 9. Current vs. Frequency—CMOS Outputs with 10 pF Load
–145
–150
–155
–160
–165
–170
0.1
07972-009
CURRENT (mA)
PUMP UP
3.0
1
10
100
PFD FREQUENCY (MHz)
Figure 12. PFD Phase Noise Referred to PFD Input vs. PFD Frequency
Rev. A | Page 18 of 76
07972-013
CURRENT (mA)
240
AD9516-5
–210
0.4
DIFFERENTIAL OUTPUT (V)
PLL FIGURE OF MERIT (dBc/Hz)
–212
–214
–216
–218
–220
0.2
0
–0.2
0
0.5
1.0
1.5
2.0
2.5
SLEW RATE (V/ns)
–0.4
07972-136
–224
0
10
15
20
25
TIME (ns)
Figure 16. LVDS Output (Differential) at 100 MHz
Figure 13. PLL Figure of Merit vs. Slew Rate at REFIN/REFIN
1.0
0.4
DIFFERENTIAL OUTPUT (V)
0.2
–0.2
–0.6
–1.0
0
5
10
15
20
25
TIME (ns)
0.2
0
–0.2
–0.4
0
1
07972-017
0.6
07972-014
DIFFERENTIAL OUTPUT (V)
5
07972-016
–222
2
TIME (ns)
Figure 14. LVPECL Output (Differential) at 100 MHz
Figure 17. LVDS Output (Differential) at 800 MHz
1.0
DIFFERENTIAL OUTPUT (V)
0.2
–0.2
1.8
0.8
–0.2
–1.0
0
1
TIME (ns)
2
Figure 15. LVPECL Output (Differential) at 1600 MHz
0
20
40
60
TIME (ns)
Figure 18. CMOS Output at 25 MHz
Rev. A | Page 19 of 76
80
100
07972-018
–0.6
07972-015
DIFFERENTIAL OUTPUT (V)
2.8
0.6
AD9516-5
700
1.8
–0.2
0
2
4
6
8
10
12
TIME (ns)
500
07972-019
0.8
600
0
100
200
300
400
500
600
700
800
FREQUENCY (MHz)
Figure 19. CMOS Output at 250 MHz
07972-021
DIFFERENTIAL SWING (mV p-p)
OUTPUT (V)
2.8
Figure 21. LVDS Differential Swing vs. Frequency
(Using a Differential Probe Across the Output Pair)
1600
CL = 2pF
OUTPUT SWING (V)
1400
1200
CL = 10pF
2
CL = 20pF
1
0
800
0
1
2
FREQUENCY (GHz)
3
0
100
200
300
400
500
600
OUTPUT FREQUENCY (MHz)
Figure 22. CMOS Output Swing vs. Frequency and Capacitive Load
Figure 20. LVPECL Differential Swing vs. Frequency
(Using a Differential Probe Across the Output Pair)
Rev. A | Page 20 of 76
07972-133
1000
07972-020
DIFFERENTIAL SWING (mV p-p)
3
AD9516-5
–110
–120
–125
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–120
–130
–135
–140
–145
–150
–130
–140
–150
100
1k
10k
100k
1M
10M
–160
10
07972-026
100M
FREQUENCY (Hz)
–120
–110
PHASE NOISE (dBc/Hz)
100k
1M
10M
100M
–130
–140
–120
–130
–140
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
–150
10
07972-027
100
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
07972-130
PHASE NOISE (dBc/Hz)
–100
–150
Figure 27. Phase Noise (Additive) LVDS at 800 MHz, Divide-by-2
Figure 24. Phase Noise (Additive) LVPECL at 200 MHz, Divide-by-5
–120
–110
–130
PHASE NOISE (dBc/Hz)
–100
–120
–130
–140
–150
–160
–140
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
07972-128
PHASE NOISE (dBc/Hz)
10k
Figure 26. Phase Noise (Additive) LVDS at 200 MHz, Divide-by-1
–110
–150
10
1k
FREQUENCY (Hz)
Figure 23. Phase Noise (Additive) LVPECL at 245.76 MHz, Divide-by-1
–160
10
100
–170
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 28. Phase Noise (Additive) CMOS at 50 MHz, Divide-by-20
Figure 25. Phase Noise (Additive) LVPECL at 1600 MHz, Divide-by-1
Rev. A | Page 21 of 76
07972-131
–160
10
07972-142
–155
AD9516-5
1000
–100
OC-48 OBJECTIVE MASK
AD9516
–120
–130
–140
–160
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
07972-132
–150
–130
–140
–150
100k
1M
FREQUENCY (Hz)
10M
100M
07972-140
PHASE NOISE (dBc/Hz)
–120
10k
fOBJ
10
1
NOTE: 375UI MAX AT 10Hz OFFSET IS THE
MAXIMUM JITTER THAT CAN BE
GENERATED BY THE TEST EQUIPMENT.
FAILURE POINT IS GREATER THAN 375UI.
0.1
0.01
0.1
1
10
100
JITTER FREQUENCY (kHz)
Figure 31. GR-253 Jitter Tolerance Plot
Figure 29. Phase Noise (Additive) CMOS at 250 MHz, Divide-by-4
–160
1k
100
Figure 30. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112)
at 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz
Rev. A | Page 22 of 76
1000
07972-148
INPUT JITTER AMPLITUDE (UI p-p)
PHASE NOISE (dBc/Hz)
–110
AD9516-5
TERMINOLOGY
Phase Jitter and Phase Noise
An ideal sine wave can be thought of as having a continuous
and even progression of phase with time from 0° to 360° for
each cycle. Actual signals, however, display a certain amount
of variation from ideal phase progression over time. This
phenomenon is called phase jitter. Although many causes can
contribute to phase jitter, one major cause is random noise,
which is characterized statistically as being Gaussian (normal)
in distribution.
This phase jitter leads to a spreading out of the energy of the
sine wave in the frequency domain, producing a continuous
power spectrum. This power spectrum is usually reported as
a series of values whose units are dBc/Hz at a given offset in
frequency from the sine wave (carrier). The value is a ratio
(expressed in decibels, dB) of the power contained within
a 1 Hz bandwidth with respect to the power at the carrier
frequency. For each measurement, the offset from the carrier
frequency is also given.
It is meaningful to integrate the total power contained within
some interval of offset frequencies (for example, 10 kHz to
10 MHz). This is called the integrated phase noise over that
frequency offset interval and can be readily related to the time
jitter due to the phase noise within that offset frequency interval.
Phase noise has a detrimental effect on the performance of
ADCs, DACs, and RF mixers. It lowers the achievable dynamic
range of the converters and mixers, although they are affected
in somewhat different ways.
Time Jitter
Phase noise is a frequency domain phenomenon. In the time
domain, the same effect is exhibited as time jitter. When
observing a sine wave, the time of successive zero crossings
varies. In a square wave, the time jitter is a displacement of the
edges from their ideal (regular) times of occurrence. In both
cases, the variations in timing from the ideal are the time jitter.
Because these variations are random in nature, the time jitter is
specified in units of seconds root mean square (rms) or 1 sigma
of the Gaussian distribution.
Time jitter that occurs on a sampling clock for a DAC or an
ADC decreases the signal-to-noise ratio (SNR) and dynamic
range of the converter. A sampling clock with the lowest possible
jitter provides the highest performance from a given converter.
Additive Phase Noise
Additive phase noise is the amount of phase noise that is
attributable to the device or subsystem being measured. The phase
noise of any external oscillators or clock sources is subtracted.
This makes it possible to predict the degree to which the device
impacts the total system phase noise when used in conjunction
with the various oscillators and clock sources, each of which
contributes its own phase noise to the total. In many cases, the
phase noise of one element dominates the system phase noise.
When there are multiple contributors to phase noise, the total is
the square root of the sum of squares of the individual contributors.
Additive Time Jitter
Additive time jitter is the amount of time jitter that is attributable to
the device or subsystem being measured. The time jitter of any
external oscillators or clock sources is subtracted. This makes it
possible to predict the degree to which the device impacts the total
system time jitter when used in conjunction with the various
oscillators and clock sources, each of which contributes its own
time jitter to the total. In many cases, the time jitter of the external
oscillators and clock sources dominates the system time jitter.
Rev. A | Page 23 of 76
AD9516-5
DETAILED BLOCK DIAGRAM
REF_ SEL
VS
GND
RSET
REFMON
CPRSET VCP
DISTRIBUTION
REFERENCE
REFERENCE
SWITCHOVER
LD
REF1
REFIN (REF1)
STATUS
R
DIVIDER
STATUS
PLL
REFERENCE
REF2
LOCK
DETECT
PROGRAMMABLE
R DELAY
VCO STATUS
REFIN (REF2)
P, P + 1
PRESCALER
A/B
COUNTERS
PROGRAMMABLE
N DELAY
PHASE
FREQUENCY
DETECTOR
HOLD
CHARGE
PUMP
CP
N DIVIDER
STATUS
DIVIDE BY
2, 3, 4, 5, OR 6
CLK
CLK
1
0
OUT0
DIVIDE BY
1 TO 32
PD
SYNC
OUT0
LVPECL
OUT1
DIGITAL
LOGIC
OUT1
RESET
OUT2
DIVIDE BY
1 TO 32
OUT3
SERIAL
CONTROL
PORT
OUT3
OUT4
DIVIDE BY
1 TO 32
OUT4
LVPECL
OUT5
OUT5
OUT6 (OUT6A)
∆t
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
OUT6 (OUT6B)
LVDS/CMOS
OUT7 (OUT7A)
∆t
OUT7 (OUT7B)
OUT8 (OUT8A)
∆t
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
AD9516-5
OUT8 (OUT8B)
LVDS/CMOS
∆t
OUT9 (OUT9A)
OUT9 (OUT9B)
07972-002
SCLK
SDIO
SDO
CS
OUT2
LVPECL
Figure 32. Detailed Block Diagram
Rev. A | Page 24 of 76
AD9516-5
THEORY OF OPERATION
REF_SEL
VS
GND
RSET
REFMON
CPRSET VCP
DISTRIBUTION
REFERENCE
REFERENCE
SWITCHOVER
LD
REF1
REFIN (REF1)
STATUS
R
DIVIDER
STATUS
PLL
REFERENCE
REF2
LOCK
DETECT
PROGRAMMABLE
R DELAY
VCO STATUS
REFIN (REF2)
P, P + 1
PRESCALER
A/B
COUNTERS
PROGRAMMABLE
N DELAY
PHASE
FREQUENCY
DETECTOR
HOLD
CHARGE
PUMP
CP
N DIVIDER
STATUS
DIVIDE BY
2, 3, 4, 5, OR 6
CLK
CLK
1
0
OUT0
DIVIDE BY
1 TO 32
PD
SYNC
OUT0
LVPECL
OUT1
DIGITAL
LOGIC
OUT1
RESET
OUT2
DIVIDE BY
1 TO 32
SCLK
SDIO
SDO
CS
OUT2
LVPECL
OUT3
SERIAL
CONTROL
PORT
OUT3
OUT4
DIVIDE BY
1 TO 32
OUT4
LVPECL
OUT5
OUT5
OUT6 (OUT6A)
∆t
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
OUT6 (OUT6B)
LVDS/CMOS
OUT7 (OUT7A)
∆t
OUT7 (OUT7B)
OUT8 (OUT8A)
∆t
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
OUT8 (OUT8B)
LVDS/CMOS
AD9516-5
OUT9 (OUT9A)
OUT9 (OUT9B)
07972-028
∆t
Figure 33. Clock Distribution or External VCO < 1600 MHz (Mode 1)
OPERATIONAL CONFIGURATIONS
The AD9516 can be configured in several ways. These
configurations must be set up by loading the control registers
(see Table 47 and Table 48 through Table 57). Each section or
function must be individually programmed by setting the
appropriate bits in the corresponding control register or registers.
For clock distribution applications where the external clock is less
than 1600 MHz, use the register settings shown in Table 18.
Table 18. Settings for Clock Distribution < 1600 MHz
Register
0x010[1:0] = 01b
0x1E1[0] = 1b
Mode 1—Clock Distribution or External VCO < 1600 MHz
Mode 1 bypasses the VCO divider. Mode 1 can be used only
with an external clock source of <1600 MHz, due to the maximum
input frequency allowed at the channel dividers.
Description
PLL asynchronous power-down (PLL off )
Bypass the VCO divider as source for
distribution section
When using the internal PLL with an external VCO of <1600 MHz,
the PLL must be turned on.
Rev. A | Page 25 of 76
AD9516-5
Table 19. Settings for Using an Internal PLL with an External
VCO < 1600 MHz
Register
0x1E1[0] = 1b
0x010[1:0] = 00b
Description
Bypass the VCO divider as source for
distribution section
PLL normal operation (PLL on) along with other
appropriate PLL settings in Register 0x010 to
Register 0x01E
An external VCO/VCXO requires an external loop filter that
must be connected between CP and the tuning pin of the VCO/
VCXO. This loop filter determines the loop bandwidth and
stability of the PLL. Ensure that the correct PFD polarity is
selected for the VCO/VCXO that is being used.
The register settings shown in Table 21 are the default values
of these registers at power-up or after a reset operation. If the
contents of the registers are altered by prior programming after
power-up or reset, these registers can also be set intentionally to
these values.
Table 21. Default Settings of Some PLL Registers
Register
0x010[1:0] = 01b
0x1E0[2:0] = 010b
0x1E1[0] = 0b
Description
PLL asynchronous power-down (PLL off ).
Set VCO divider = 4.
Use the VCO divider.
When using the internal PLL with an external VCO, the PLL
must be turned on.
Table 20. Setting the PFD Polarity
Table 22. Settings When Using an External VCO
Register
0x010[7] = 0b
Register
0x010[1:0] = 00b
0x010 to 0x01D
0x010[7] = 1b
Description
PFD polarity positive (higher control voltage
produces higher frequency)
PFD polarity negative (higher control voltage
produces lower frequency)
After the appropriate register values are programmed,
Register 0x232 must be set to 0x01 for the values to take effect.
Mode 2 (High Frequency Clock Distribution)—CLK or
External VCO > 1600 MHz
The AD9516 power-up default configuration has the PLL
powered off and the routing of the input set so that the CLK/
CLK input is connected to the distribution section through the
VCO divider (divide-by-2/divide-by-3/divide-by-4/divide-by-5/
divide-by-6). This is a distribution-only mode that allows for an
external input of up to 2400 MHz (see Table 4). For divide ratios
other than 1, the maximum frequency that can be applied to the
channel dividers is 1600 MHz. Therefore, the VCO divider must
be used to divide down input frequencies that are greater than
1600 MHz before the channel dividers can be used for further
division. This input routing can also be used for lower input
frequencies, but the minimum divide is 2 before the channel
dividers.
0x1E1[1] = 0b
Description
PLL normal operation (PLL on).
PLL settings. Select and enable a reference
input. Set R, N (P, A, B), PFD polarity, and ICP
according to the intended loop configuration.
CLK selected as the source.
An external VCO requires an external loop filter that must be
connected between CP and the tuning pin of the VCO. This loop
filter determines the loop bandwidth and stability of the PLL.
Ensure that the correct PFD polarity is selected for the VCO
that is being used.
Table 23. Setting the PFD Polarity
Register
0x010[7] = 0b
0x010[7] = 1b
Description
PFD polarity positive (higher control
voltage produces higher frequency).
PFD polarity negative (higher control
voltage produces lower frequency).
After the appropriate register values are programmed,
Register 0x232 must be set to 0x01 for the values to take effect.
When the PLL is enabled, this routing also allows the use of
the PLL with an external VCO or VCXO with a frequency of
<2400 MHz. In this configuration, the external VCO/VCXO
feeds directly into the prescaler.
Rev. A | Page 26 of 76
AD9516-5
REF_SEL
VS
GND
RSET
REFMON
CPRSET VCP
DISTRIBUTION
REFERENCE
REFERENCE
SWITCHOVER
LD
REF1
REFIN (REF1)
STATUS
R
DIVIDER
STATUS
PLL
REFERENCE
REF2
LOCK
DETECT
PROGRAMMABLE
R DELAY
VCO STATUS
REFIN (REF2)
P, P + 1
PRESCALER
A/B
COUNTERS
PROGRAMMABLE
N DELAY
PHASE
FREQUENCY
DETECTOR
HOLD
CHARGE
PUMP
CP
N DIVIDER
STATUS
DIVIDE BY
2, 3, 4, 5, OR 6
CLK
CLK
1
0
OUT0
DIVIDE BY
1 TO 32
PD
SYNC
OUT0
LVPECL
OUT1
DIGITAL
LOGIC
OUT1
RESET
OUT2
DIVIDE BY
1 TO 32
OUT3
SERIAL
CONTROL
PORT
OUT3
OUT4
DIVIDE BY
1 TO 32
OUT4
LVPECL
OUT5
OUT5
OUT6 (OUT6A)
∆t
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
OUT6 (OUT6B)
LVDS/CMOS
OUT7 (OUT7A)
∆t
OUT7 (OUT7B)
OUT8 (OUT8A)
∆t
DIVIDE BY
1 TO 32
AD9516-5
DIVIDE BY
1 TO 32
OUT8 (OUT8B)
LVDS/CMOS
∆t
OUT9 (OUT9A)
OUT9 (OUT9B)
07972-029
SCLK
SDIO
SDO
CS
OUT2
LVPECL
Figure 34. High Frequency Clock Distribution—CLK or External VCO > 1600 MHz (Mode 2)
Rev. A | Page 27 of 76
AD9516-5
Phase-Locked Loop (PLL)
REF_SEL
VS
GND
RSET
REFMON
CPRSET
VCP
DIST
REF
REFERENCE
SWITCHOVER
LD
LOCK
DETECT
REF1
STATUS
REF2
PROGRAMMABLE
R DELAY
R DIVIDER
STATUS
PLL
REF
HOLD
REFIN (REF1)
REFIN (REF2)
N DIVIDER
P, P + 1
PRESCALER
A/B
COUNTERS
PROGRAMMABLE
N DELAY
PHASE
FREQUENCY
DETECTOR
CHARGE PUMP
CP
VCO STATUS
STATUS
DIVIDE BY
2, 3, 4, 5, OR 6
0
CLK
1
1
07972-064
CLK
0
Figure 35. PLL Functional Blocks
The AD9516 includes on-chip PLL blocks that can be used with
an external VCO or VCXO to create a complete phase-locked
loop. The PLL requires an external loop filter, which usually
consists of a small number of capacitors and resistors. The
configuration and components of the loop filter help to establish
the loop bandwidth and stability of the PLL.
The AD9516 PLL is useful for generating clock frequencies from a
supplied reference frequency. This includes conversion of reference
frequencies to much higher frequencies for subsequent division
and distribution. In addition, the PLL can be exploited to clean up
jitter and phase noise on a noisy reference. The exact choices of
PLL parameters and loop dynamics are very application specific.
The flexibility and depth of the PLL allow the part to be tailored
to function in many different applications and signal environments.
Configuration of the PLL
Configuration of the PLL is accomplished by programming
the various settings for the R divider, N divider, PFD polarity,
and charge pump current. The combination of these settings
determines the PLL loop bandwidth. These are managed through
programmable register settings (see Table 47 and Table 49) and
by the design of the external loop filter. Successful PLL operation
and satisfactory PLL loop performance are highly dependent upon
proper configuration of the PLL settings.
The design of the external loop filter is crucial to the proper
operation of the PLL. A thorough knowledge of PLL theory and
design is helpful.
ADIsimCLK™ (V1.2 or later) is a free program that can help
with the design and exploration of the capabilities and features
of the AD9516, including the design of the PLL loop filter. It is
available at www.analog.com/clocks.
Phase Frequency Detector (PFD)
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. The PFD includes a programmable
delay element that controls the width of the antibacklash pulse.
This pulse ensures that there is no dead zone in the PFD transfer
function and minimizes phase noise and reference spurs. The
antibacklash pulse width is set by Register 0x017[1:0].
An important limit to keep in mind is the maximum frequency
allowed into the PFD, which, in turn, determines the correct antibacklash pulse setting. The antibacklash pulse setting is specified
in the phase/frequency detector (PFD) parameter of Table 2.
Charge Pump (CP)
The charge pump is controlled by the PFD. The PFD monitors the
phase and frequency relationship between its two inputs, and tells
the CP to pump up or pump down to charge or discharge the
integrating node (part of the loop filter). The integrated and
filtered CP current is transformed into a voltage that drives the
tuning node of the external VCO to move the VCO frequency
up or down. The CP can be set (via Register 0x010[6:4]) for high
impedance (allows holdover operation), for normal operation
(attempts to lock the PLL loop), for pump-up, or for pump-down
(test modes). The CP current is programmable in eight steps from
(nominally) 600 μA to 4.8 mA.
The exact value of the CP current LSB is set by the CPRSET
resistor, which is nominally 5.1 kΩ. If the value of the resistor
connected to the CP_RSET pin is doubled, the resulting charge
pump current range becomes 300 μA to 2.4 mA.
Rev. A | Page 28 of 76
AD9516-5
PLL External Loop Filter
An example of an external loop filter for a PLL is shown in
Figure 36. A loop filter must be calculated for each desired PLL
configuration. The values of the components depend on the VCO
frequency, the KVCO, the PFD frequency, the charge pump current,
the desired loop bandwidth, and the desired phase margin. The
loop filter affects the phase noise, loop settling time, and loop
stability. A basic knowledge of PLL theory is helpful for understanding loop filter design. ADIsimCLK can help with calculation
of a loop filter according to the application requirements.
In differential mode, the reference input pins are internally selfbiased so that they can be ac-coupled via capacitors. It is possible to
dc couple to these inputs. If the differential REFIN is driven by a
single-ended signal, the unused side (REFIN) should be decoupled
via a suitable capacitor to a quiet ground. Figure 37 shows the
equivalent circuit of REFIN.
VS
85kΩ
REF1
AD9516-5
CLK/CLK
EXTERNAL
VCO/VCXO
VS
R2
CP
C1
C2
12kΩ
REFIN
R1
150Ω
C3
REFIN
07972-065
CHARGE
PUMP
10kΩ
150Ω
10kΩ
10kΩ
Figure 36. Example of External Loop Filter for PLL
VS
PLL Reference Inputs
REF2
The AD9516 features a flexible PLL reference input circuit that
allows a fully differential input or two separate single-ended
inputs. The input frequency range for the reference inputs is
specified in Table 2. Both the differential and the single-ended
inputs are self-biased, allowing for easy ac coupling of input signals.
The differential input and the single-ended inputs share two
pins, REFIN (REF1) and REFIN (REF2). The desired reference
input type is selected and controlled by Register 0x01C (see
Table 47 and Table 49).
When the differential reference input is selected, the self-bias
level of the two sides is offset slightly (see Table 2) to prevent
chattering of the input buffer when the reference is slow or missing.
The specification for this voltage level is found in Table 2. The input
hysteresis increases the voltage swing required of the driver to
overcome the offset. The differential reference input can be driven
by either ac-coupled LVDS or ac-coupled LVPECL signals.
The single-ended inputs can be driven by either a dc-coupled
CMOS level signal or an ac-coupled sine wave or square wave.
Each single-ended input can be independently powered down
when not needed to increase isolation and reduce power. Either
a differential or a single-ended reference must be specifically
enabled. All PLL reference inputs are off by default.
The differential reference input is powered down whenever the
PLL is powered down, or when the differential reference input
is not selected. The single-ended buffers power down when the
PLL is powered down and when their individual power-down
registers are set. When the differential mode is selected, the
single-ended inputs are powered down.
07972-066
85kΩ
Figure 37. REFIN Equivalent Circuit
Reference Switchover
The AD9516 supports dual single-ended CMOS inputs, as well as
a single differential reference input. In dual single-ended reference
mode, automatic and manual PLL reference clock switching
between REF1 (Pin REFIN) and REF2 (Pin REFIN) is supported.
This feature supports networking and other applications that
require smooth switching of redundant references. When used in
conjunction with the automatic holdover function, the AD9516
can achieve a worst-case reference input switchover with an
output frequency disturbance as low as 10 ppm.
When using reference switchover, the single-ended reference inputs
should be dc-coupled CMOS levels that are never allowed to go to
high impedance. If the inputs are allowed to go to high impedance,
noise may cause the buffer to chatter, causing false detection of
the presence of a reference. Reference switchover can be performed
manually or automatically. Manual switchover is performed
either through Register 0x01C or by using the REF_SEL pin.
Manual switchover requires the presence of a clock on the reference
input that is being switched to, or that the deglitching feature be
disabled (Register 0x01C[7]). The reference switching logic fails
if this condition is not met, and the PLL does not reacquire.
Rev. A | Page 29 of 76
AD9516-5
Automatic revertive switchover relies on the REFMON pin to
indicate when REF1 disappears. By programming Register 0x01B =
0xF7 and Register 0x01C = 0x26, the REFMON pin is programmed
to be high when REF1 is invalid, which commands the switch to
REF2. When REF1 is valid again, the REFMON pin goes low, and
the part again locks to REF1. The STATUS pin can also be used
for this function, and REF2 can be used as the preferred reference.
VCXO/VCO Feedback Divider N—P, A, B
A switchover deglitch feature ensures that the PLL does not receive
rising edges that are far out of alignment with the newly selected
reference. Automatic nonrevertive switching is not supported.
The prescaler of the AD9516 allows for two modes of operation:
a fixed divide (FD) mode of 1, 2, or 3, and a dual modulus (DM)
mode where the prescaler divides by P and (P + 1) {2 and 3, 4
and 5, 8 and 9, 16 and 17, or 32 and 33}. The prescaler modes
of operation are given in Table 49, Register 0x016[2:0]. Not all
modes are available at all frequencies (see Table 2).
Reference Divider R
The reference inputs are routed to the reference divider, R.
R (a 14-bit counter) can be set to any value from 0 to 16,383 by
writing to Register 0x011 and Register 0x012. (Both R = 0 and
R = 1 give divide-by-1.) The output of the R divider goes to one
of the PFD inputs to be compared with the VCO frequency divided
by the N divider. The frequency applied to the PFD must not
exceed the maximum allowable frequency, which depends on
the antibacklash pulse setting (see Table 2).
The R counter has its own reset. The R counter can be reset via
the shared reset bit of the R, A, and B counters. It can also be
reset by a SYNC operation.
The N divider is a combination of a prescaler (P) and two
counters, A and B. The total divider value is
N = (P × B) + A
where P can be 2, 4, 8, 16, or 32.
Prescaler
When operating the AD9516 in dual modulus mode, P/(P + 1),
the equation used to relate the input reference frequency to the
VCO output frequency is
fVCO = (fREF/R) × (P × B + A) = fREF × N/R
However, when operating the prescaler in FD Mode 1,
FD Mode 2, or FD Mode 3, the A counter is not used (A = 0)
and the equation simplifies to
fVCO = (fREF/R) × (P × B) = fREF × N/R
When A = 0, the divide is a fixed divide of P = 2, 4, 8, 16, or 32,
in which case, the previous equation also applies.
By using combinations of DM and FD modes, the AD9516
can achieve values of N all the way down to N = 1 and up to N =
26,2175. Table 24 shows how a 10 MHz reference input can be
locked to any integer multiple of N.
Table 24. Using a 10 MHz Reference to Generate Different VCO Frequencies
fREF (MHz)
10
10
10
10
10
10
10
10
R
1
1
1
1
1
1
1
1
P
1
2
1
1
1
2
2
2
A
X1
X1
X1
X1
X1
X1
0
1
B
1
1
3
4
5
3
3
3
N
1
2
3
4
5
6
6
7
fVCO (MHz)
10
20
30
40
50
60
60
70
Mode
FD
FD
FD
FD
FD
FD
DM
DM
10
10
10
10
10
10
10
10
1
1
1
1
1
10
1
1
2
2
8
8
16
32
8
16
2
1
6
7
7
6
0
14
3
4
18
18
9
47
25
16
8
9
150
151
151
1510
200
270
80
90
1500
1510
1510
1510
2000
2700
DM
DM
DM
DM
DM
DM
DM
DM
10
10
32
22
84
2710
2710
DM
1
Conditions/Comments
P = 1, B = 1 (A and B counters are bypassed).
P = 2, B = 1 (A and B counters are bypassed).
A counter is bypassed.
A counter is bypassed.
A counter is bypassed.
A counter is bypassed.
Maximum frequency into prescaler in P = 2/3 mode is 200 MHz.
If N = 7 or N = 11 is desired for prescaler input frequency of 200 MHz
to 300 MHz, use P = 1, and N = 7 or 11, respectively.
P = 8 is not allowed (2700 ÷ 8 > 300 MHz).
P = 32 is not allowed (A > B not allowed).
P = 32, A = 22, B = 84.
P = 16 is also permitted.
X = don’t care.
Rev. A | Page 30 of 76
AD9516-5
Note that the same value of N can be derived in different ways,
as illustrated by the case of N = 12. The user can choose a fixed
divide mode of P = 2 with B = 6; use the dual modulus mode of
2/3 with A = 0, B = 6; or use the dual modulus mode of 4/5 with
A = 0, B = 3.
A and B Counters
The B counter must be ≥3 or bypassed, and, unlike the R counter,
A = 0 is actually zero. When the prescaler is in dual modulus mode,
the A counter must be less than the B counter.
The maximum input frequency to the A or B counter is reflected
in the maximum prescaler output frequency (~300 MHz) that
is specified in Table 2. This is the prescaler input frequency
(external VCO or CLK) divided by P. For example, a dual
modulus mode of P = 8/9 mode is not allowed if the external
VCO frequency is greater than 2400 MHz because the frequency
going to the A or B counter is too high.
When the B counter is bypassed (B = 1), the A counter should
be set to 0, and the overall resulting divide is equal to the prescaler
setting, P. The possible divide ratios in this mode are 1, 2, 3, 4, 8,
16, and 32. This mode is useful only when an external VCO/VCXO
is used because the frequency range of the internal VCO requires
an overall feedback divider that is greater than 32.
lock detect counter (Register 0x018[6:5]). A lock is not indicated
until there is a programmable number of consecutive PFD cycles
with a time difference that is less than the lock detect threshold.
The lock detect circuit continues to indicate a lock until a time
difference greater than the unlock threshold occurs on a single
subsequent cycle. For the lock detect to work properly, the period
of the PFD frequency must be greater than the unlock threshold.
The number of consecutive PFD cycles required for lock is
programmable (Register 0x018[6:5]).
Analog Lock Detect (ALD)
The AD9516 provides an ALD function that can be selected for
use at the LD pin. There are two versions of ALD, as follows:
•
•
The analog lock detect function requires an R-C filter to
provide a logic level indicating lock/unlock.
Although manual reset is not normally required, the A and B
counters have their own reset bit. Alternatively, the A and B
counters can be reset using the shared reset bit of the R, A, and
B counters. Note that these reset bits are not self-clearing.
VS = 3.3V
AD9516-5
LD
ALD
R and N Divider Delays
Both the R and N dividers feature a programmable delay cell.
These delays can be enabled to allow adjustment of the phase
relationship between the PLL reference clock and the VCO or
CLK. Each delay is controlled by three bits. The total delay
range is about 1 ns. See Register 0x019 in Table 49.
LOCK DETECT
Digital Lock Detect (DLD)
By selecting the proper output through the mux on each pin, the
DLD function can be made available at the LD, STATUS, and
REFMON pins. The DLD circuit indicates a lock when the time
difference of the rising edges at the PFD inputs is less than a
specified value (the lock threshold). The loss of a lock is indicated
when the time difference exceeds a specified value (the unlock
threshold). Note that the unlock threshold is wider than the
lock threshold, which allows some phase error in excess of the
lock window to occur without chattering on the lock indicator.
The lock detect window timing depends on three settings: the
digital lock detect window bit (Register 0x018[4]), the antibacklash
pulse width setting (Register 0x017[1:0]), see Table 2), and the
R1
R2
VOUT
C
07972-067
R, A, and B Counters—SYNC Pin Reset
The R, A, and B counters can also be reset simultaneously via
the SYNC pin. This function is controlled by Register 0x019[7:6]
(see Table 49). The SYNC pin reset is disabled by default.
N-channel open-drain lock detect. This signal requires
a pull-up resistor to the positive supply, VS. The output is
normally high with short, low going pulses. Lock is indicated
by the minimum duty cycle of the low going pulses.
P-channel open-drain lock detect. This signal requires
a pull-down resistor to GND. The output is normally low
with short, high going pulses. Lock is indicated by the
minimum duty cycle of the high going pulses.
Figure 38. Example of Analog Lock Detect Filter, Using
N-Channel Open-Drain Driver
Current Source Digital Lock Detect (CSDLD)
During the PLL locking sequence, it is normal for the DLD
signal to toggle a number of times before remaining steady
when the PLL is completely locked and stable. There may be
applications where it is desirable to have DLD asserted only
after the PLL is solidly locked. This is made possible by using
the current source lock detect function. This function is set
when it is selected as the output from the LD pin control
(Register 0x01A[5:0]).
The current source lock detect provides a current of 110 μA
when DLD is true, and it shorts to ground when DLD is false.
If a capacitor is connected to the LD pin, it charges at a rate that
is determined by the current source during the DLD true time
but is discharged nearly instantly when DLD is false. By
monitoring the voltage at the LD pin (top of the capacitor), it is
possible to get a logic high level only after the DLD has been
true for a sufficiently long time. Any momentary DLD false
resets the charging. By selecting a properly sized capacitor, it is
possible to delay a lock detect indication until the PLL is locked
in a stable condition and the lock detect does not chatter.
Rev. A | Page 31 of 76
AD9516-5
The voltage on the capacitor can be sensed by an external
comparator connected to the LD pin. However, there is an
internal LD pin comparator that can be read at the REFMON
pin control (Register 0x01B[4:0]) or the STATUS pin control
(Register 0x017[7:2]) as an active high signal. It is also available
as an active low signal (REFMON, Register 0x01B[4:0] and
STATUS, Register 0x017[7:2]). The internal LD pin comparator
trip point and hysteresis are listed in Table 12.
AD9516-5
110µA
DLD
VOUT
LD
C
REFMON
OR
STATUS
Figure 39. Current Source Lock Detect
External VCXO/VCO Clock Input (CLK/CLK)
CLK is a differential input that can be used to drive the AD9516
clock distribution section. This input can receive up to 2.4 GHz.
The pins are internally self-biased, and the input signal should
be ac-coupled via capacitors.
CLOCK INPUT
STAGE
VS
CLK
CLK
2.5kΩ
2.5kΩ
07972-032
5kΩ
5kΩ
The AD9516 PLL has a holdover function. Holdover is
implemented by putting the charge pump into a high impedance
state. This is useful when the PLL reference clock is lost. Holdover
mode allows the VCO to maintain a relatively constant frequency
even though there is no reference clock. Without this function,
the charge pump is placed into a constant pump-up or pumpdown state, resulting in a large VCO frequency shift. Because
the charge pump is placed in a high impedance state, any leakage
that occurs at the charge pump output or the VCO tuning node
causes a drift of the VCO frequency. This can be mitigated by
using a loop filter that contains a large capacitive component
because this drift is limited by the current leakage induced slew
rate (ILEAK/C) of the VCO control voltage. For most applications,
the frequency is sufficient for 3 sec to 5 sec.
Both a manual holdover mode, using the SYNC pin, and an
automatic holdover mode are provided. To use either function,
the holdover function must be enabled (Register 0x01D[0] and
Register 0x01D[2]).
07972-068
LD PIN
COMPARATOR
Holdover
Figure 40. CLK Equivalent Input Circuit
The CLK/CLK input can be used either as a distribution only
input (with the PLL off), or as a feedback input for an external
VCO/VCXO using the PLL. The CLK/CLK input can be used
for frequencies up to 2.4 GHz.
Manual Holdover Mode
A manual holdover mode can be enabled that allows the user
to place the charge pump into a high impedance state when the
SYNC pin is asserted low. This operation is edge sensitive, not
level sensitive. The charge pump enters a high impedance state
immediately. To take the charge pump out of a high impedance
state, take the SYNC pin high. The charge pump then leaves the
high impedance state synchronously with the next PFD rising
edge from the reference clock. This prevents extraneous charge
pump events from occurring during the time between SYNC
going high and the next PFD event. This also means that the
charge pump stays in a high impedance state as long as there is
no reference clock present.
The B counter (in the N divider) is reset synchronously with the
charge pump leaving the high impedance state on the reference
path PFD event. This helps align the edges out of the R and N
dividers for faster settling of the PLL. Because the prescaler is
not reset, this feature works best when the B and R numbers are
close because this results in a smaller phase difference for the
loop to settle out.
When using this mode, set the channel dividers to ignore the
SYNC pin (at least after an initial SYNC event). If the dividers are
not set to ignore the SYNC pin, the distribution outputs turn off
each time SYNC is taken low to put the part into holdover.
Rev. A | Page 32 of 76
AD9516-5
Automatic/Internal Holdover Mode
PLL ENABLED
When enabled, this function automatically puts the charge pump
into a high impedance state when the loop loses lock. The
assumption is that the only reason that the loop loses lock is due
to the PLL losing the reference clock; therefore, the holdover
function puts the charge pump into a high impedance state to
maintain the VCO frequency as close as possible to the original
frequency before the reference clock disappears.
DLD == LOW
See Figure 41 for a flowchart of the internal/automatic holdover
function operation.
YES
The holdover function senses the logic level of the LD pin as a
condition to enter holdover. The signal at LD can be from the
DLD, ALD, or current source LD (CSDLD) mode. It is possible
to disable the LD comparator (Register 0x01D[3]), which causes
the holdover function to always sense LD as high. If DLD is
used, it is possible for the DLD signal to chatter somewhat while
the PLL is reacquiring lock. The holdover function may retrigger,
thereby preventing the holdover mode from ever terminating.
Use of the current source lock detect mode is recommended to
avoid this situation (see the Current Source Digital Lock Detect
section).
WAS
LD PIN == HIGH
WHEN DLD WENT
LOW?
NO
ANALOG LOCK DETECT PIN INDICATES
LOCK WAS PREVIOUSLY ACHIEVED.
REGISTER 0x1D[3] = 1: USE LD PIN
VOLTAGE WITH HOLDOVER.
REGISTER 0x1D[3] = 0: IGNORE LD PIN
VOLTAGE,TREAT LD PIN AS ALWAYS HIGH.
YES
CHARGE PUMP IS MADE
HIGH IMPEDANCE.
PLL COUNTERS CONTINUE
OPERATING NORMALLY.
HIGH IMPEDANCE
CHARGE PUMP
YES
NO
CHARGE PUMP REMAINS HIGH
IMPEDANCE UNTIL THE REFERENCE
HAS RETURNED.
REFERENCE
EDGE AT PFD?
YES
YES
TAKE CHARGE PUMP OUT OF
HIGH IMPEDANCE. PLL CAN
NOW RESETTLE.
RELEASE
CHARGE PUMP
HIGH IMPEDANCE
After leaving holdover, the loop then reacquires lock, and the
LD pin must charge (if Register 0x01D[3] = 1) before it can
re-enter holdover (CP high impedance).
The holdover function always responds to the state of the currently
selected reference (Register 0x01C). If the loop loses lock during a
reference switchover (see the Reference Switchover section),
holdover is triggered briefly until the next reference clock edge
at the PFD.
Rev. A | Page 33 of 76
YES
NO
DLD == HIGH
WAIT FOR DLD TO GO HIGH. THIS TAKES
5 TO 255 CYCLES (PROGRAMMING OF
THE DLD DELAY COUNTER) WITH THE
REFERENCE AND FEEDBACK CLOCKS
INSIDE THE LOCK WINDOW AT THE PFD.
THIS ENSURES THAT THE HOLDOVER
FUNCTION WAITS FOR THE PLL TO SETTLE
AND LOCK BEFORE THE HOLDOVER
FUNCTION CAN BE RETRIGGERED.
Figure 41. Flowchart of Automatic/Internal Holdover Mode
07972-069
When in holdover mode, the charge pump stays in a high
impedance state as long as there is no reference clock present.
As in the external holdover mode, the B counter (in the N divider)
is reset synchronously with the charge pump leaving the high
impedance state on the reference path PFD event. This helps to
align the edges out of the R and N dividers for faster settling of
the PLL and reduce frequency errors during settling. Because the
prescaler is not reset, this feature works best when the B and R
numbers are close because this results in a smaller phase difference
for the loop to settle out.
LOOP OUT OF LOCK. DIGITAL LOCK
DETECT SIGNAL GOES LOW WHEN THE
LOOP LEAVES LOCK AS DETERMINED
BY THE PHASE DIFFERENCE AT THE
INPUT OF THE PFD.
NO
AD9516-5
•
•
The following registers affect the internal/automatic holdover
function:
•
•
•
•
•
Register 0x018[6:5], lock detect counter. These bits change
how many PFD cycles with edges inside the lock detect
window are required for the DLD indicator to indicate lock.
This impacts the time required before the LD pin can begin
to charge, as well as the delay from the end of a holdover
event until the holdover function can be reengaged.
Register 0x018[3], disable digital lock detect. This bit must
be set to 0b to enable the DLD circuit. Internal/automatic
holdover does not operate correctly without the DLD function
enabled.
Register 0x01A[5:0], lock detect pin output select. Set this
to 000100b to put it in the current source lock detect mode
if using the LD pin comparator. Load the LD pin with a
capacitor of an appropriate value.
Register 0x01D[3], LD pin comparator enable. 1b = enable;
0b = disable. When disabled, the holdover function always
senses the LD pin as high.
Register 0x01D[1], external holdover control.
Register 0x01D[0] and Register 0x01D[2], holdover enable.
If holdover is disabled, both external and automatic/internal
holdover are disabled.
•
•
•
•
•
•
•
And, finally,
•
Frequency Status Monitors
The AD9516 contains three frequency status monitors that are
used to indicate if the PLL reference (or references, in the case
of single-ended mode) and the VCO have fallen below a threshold
frequency. Figure 42 is a diagram that shows their location in
the PLL.
For example, to use automatic holdover with the following:
•
•
The PLL reference frequency monitors have two threshold
frequencies: normal and extended (see Table 12). The reference
frequency monitor thresholds are selected in Register 0x01B[7:5].
The reference frequency monitor status can be found in
Register 0x01F[3:1].
Digital lock detect: five PFD cycles, high range window
Automatic holdover using the LD pin comparator
Set the following registers (in addition to the normal PLL registers):
Register 0x018[6:5] = 00b; lock detect counter = five cycles.
Register 0x018[4] = 0b; lock detect window = high range.
REF_SEL
VS
GND
RSET
REFMON
DISTRIBUTION
REFERENCE
REFERENCE
SWITCHOVER
LD
REF1
REF2
REFIN (REF1)
CPRSET VCP
LOCK
DETECT
STATUS
R
DIVIDER
STATUS
PROGRAMMABLE
R DELAY
REFIN (REF2)
N DIVIDER
P, P + 1
PRESCALER
A/B
COUNTERS
PROGRAMMABLE
N DELAY
PHASE
FREQUENCY
DETECTOR
HOLD
CHARGE
PUMP
CP
CLK FREQUENCY
STATUS
DIVIDE BY
2, 3, 4, 5, OR 6
CLK
0
STATUS
1
CLK
1
07972-070
•
•
Connect REFMON pin to REFSEL pin.
PLL
REFERENCE
•
Register 0x018[3] = 0b; DLD normal operation.
Register 0x01A[5:0] = 000100b; current source lock detect
mode.
Register 0x01B[7:0] = 0xF7; set REFMON pin to status of
REF1 (active low).
Register 0x01C[2:1] = 11b; enable REF1 and REF2 input
buffers.
Register 0x01D[3] = 1b; enable LD pin comparator.
Register 0x01D[2] = 1b; enable holdover function.
Register 0x01D[1] = 0b; use internal/automatic holdover
mode.
Register 0x01D[0] = 1b; enable holdover function
(complete VCO calibration before enabling this bit).
Register 0x232 = 0x01; update all registers.
0
Figure 42. Reference and CLK Status Monitors
Rev. A | Page 34 of 76
AD9516-5
CLK Direct to LVPECL Outputs
CLOCK DISTRIBUTION
A clock channel consists of a pair (or double pair, in the case of
CMOS) of outputs that share a common divider. A clock output
consists of the drivers that connect to the output pins. The clock
outputs have either LVPECL or LVDS/CMOS signal levels at
the pins.
The AD9516 has five clock channels: three channels are LVPECL
(six outputs); two channels are LVDS/CMOS (up to four LVDS
outputs, or up to eight CMOS outputs).
Each channel has its own programmable divider that divides the
clock frequency that is applied to its input. The LVPECL channel
dividers can divide by any integer from 2 to 32, or the divider
can be bypassed to achieve a divide-by-1. Each LVDS/CMOS
channel divider contains two of these divider blocks in a cascaded
configuration. The total division of the channel is the product
of the divide value of the cascaded dividers. This allows divide
values of (1 to 32) × (1 to 32), or up to 1024 (note that this is
not all values from 1 to 1024 but only the set of numbers that
are the product of the two dividers).
The VCO divider can be set to divide by 2, 3, 4, 5, or 6 and must
be used if the external clock signal connected to the CLK input
is greater than 1600 MHz.
The channel dividers allow for a selection of various duty cycles,
depending on the currently set division. That is, for any specific
division, D, the output of the divider can be set to high for N + 1
input clock cycles and low for M + 1 input clock cycles (where
D = N + M + 2). For example, a divide-by-5 can be high for one
divider input cycle and low for four cycles, or a divide-by-5 can
be high for three divider input cycles and low for two cycles.
Other combinations are also possible.
The channel dividers include a duty-cycle correction function
that can be disabled. In contrast to the selectable duty cycle
just described, this function can correct a non-50% duty cycle
caused by an odd division. However, this requires that the
division be set by M = N + 1.
In addition, the channel dividers allow a coarse phase offset or
delay to be set. Depending on the division selected, the output
can be delayed by up to 31 input clock cycles. The divider
outputs can also be set to start high or start low.
Operating Modes
There are two clock distribution operating modes. These operating
modes are shown in Table 25.
It is not necessary to use the VCO divider if the CLK frequency
is less than the maximum channel divider input frequency
(1600 MHz); otherwise, the VCO divider must be used to
reduce the frequency going to the channel dividers.
Table 25. Clock Distribution Operating Modes
Mode
2
1
0x1E1[0]
0
1
VCO Divider
Used
Not used
It is possible to connect the CLK directly to the LVPECL outputs,
OUT0 to OUT5. However, the LVPECL outputs may not be able
to provide full a voltage swing at the highest frequencies.
To connect the LVPECL outputs directly to the CLK input, the
VCO divider must be selected as the source to the distribution
section even if no channel uses it.
Table 26. Settings for Routing VCO Divider Input Directly
to LVPECL Outputs
Register Setting
0x1E1[0] = 0b
0x192[1] = 1b
0x195[1] = 1b
0x198[1] = 1b
Selection
VCO divider selected
Direct to OUT0, OUT1 outputs
Direct to OUT2, OUT3 outputs
Direct to OUT4, OUT5 outputs
Clock Frequency Division
The total frequency division is a combination of the VCO
divider (when used) and the channel divider. When the VCO
divider is used, the total division from the VCO or CLK to the
output is the product of the VCO divider (2, 3, 4, 5, and 6) and
the division of the channel divider. Table 27 and Table 28 indicate
how the frequency division for a channel is set. For the LVPECL
outputs, there is only one divider per channel. For the LVDS/
CMOS outputs, there are two dividers (X.1, X.2) cascaded
per channel.
Table 27. Frequency Division for Divider 0 to Divider 2
VCO
Divider
Setting
2 to 6
2 to 6
2 to 6
VCO Divider
Bypassed
VCO Divider
Bypassed
Channel
Divider
Setting
Don’t care
Bypass
2 to 32
Bypass
CLK Direct
to Output
Setting
Enable
Disable
Disable
No
Frequency
Division
1
(2 to 6) × (1)
(2 to 6) × (2 to 32)
1
2 to 32
No
2 to 32
Table 28. Frequency Division for Divider 3 and Divider 4
VCO Divider
Setting
2 to 6
2 to 6
2 to 6
Channel Divider Setting
X.1
X.2
Bypass
Bypass
2 to 32
Bypass
2 to 32
2 to 32
Bypass
Bypass
Bypass
1
2 to 32
2 to 32
1
1
2 to 32
Resulting Frequency
Division
(2 to 6) × (1) × (1)
(2 to 6) × (2 to 32) × (1)
(2 to 6) × (2 to 32) ×
(2 to 32)
1
(2 to 32) × (1)
2 to 32 × (2 to 32)
The channel dividers feeding the LVPECL output drivers contain
one 2-to-32 frequency divider. This divider provides for division
by 2 to 32. Division by 1 is accomplished by bypassing the divider.
The dividers also provide for a programmable duty cycle, with
optional duty-cycle correction when the divide ratio is odd.
Rev. A | Page 35 of 76
AD9516-5
A phase offset or delay in increments of the input clock cycle is
selectable. The channel dividers operate with a signal at their
inputs up to 1600 MHz. The features and settings of the dividers
are selected by programming the appropriate setup and control
registers (see Table 47 through Table 57).
VCO Divider
The VCO divider provides frequency division between the
external CLK input and the clock distribution channel dividers.
The VCO divider can be set to divide by 2, 3, 4, 5, or 6 (see
Table 55, Register 0x1E0[2:0]).
Channel Dividers—LVPECL Outputs
Each pair of LVPECL outputs is driven by a channel divider.
There are three channel dividers (0, 1, and 2) driving six
LVPECL outputs (OUT0 to OUT5). Table 29 lists the register
locations used for setting the division and other functions of
these dividers. The division is set by the values of M and N. The
divider can be bypassed (equivalent to divide-by-1, divider circuit
is powered down) by setting the bypass bit. The duty-cycle
correction can be enabled or disabled according to the setting
of the DCCOFF bits.
Table 29. Setting DX for Divider 0, Divider 1, and Divider 21
Divider
0
1
2
1
Low Cycles
M
0x190[7:4]
0x193[7:4]
0x196[7:4]
High Cycles
N
0x190[3:0]
0x193[3:0]
0x196[3:0]
Bypass
0x191[7]
0x194[7]
0x197[7]
DCCOFF
0x192[0]
0x195[0]
0x198[0]
Note that the value stored in the register = # of cycles minus 1. For example,
0x190[7:4] = 0001b equals two low cycles (M = 2) for Divider 0.
Channel Frequency Division (0, 1, and 2)
For each channel (where the channel number is x: 0, 1, or 2),
the frequency division, DX, is set by the values of M and N
(four bits each, representing Decimal 0 to Decimal 15), where
The DCC function is enabled, by default, for each channel divider.
However, the DCC function can be disabled individually for each
channel divider by setting the DCCOFF bit for that channel.
Certain M and N values for a channel divider result in a non-50%
duty cycle. A non-50% duty cycle can also result with an even
division, if M ≠ N. The duty-cycle correction function
automatically corrects non-50% duty cycles at the channel
divider output to 50% duty cycle. Duty-cycle correction
requires the following channel divider conditions:
•
•
An even division must be set as M = N
An odd division must be set as M = N + 1
When not bypassed or corrected by the DCC function, the duty
cycle of each channel divider output is the numerical value of
(N + 1)/(N + M + 2), expressed as a percentage (%).
Table 30 to Table 32 list the duty cycles at the output of the channel
dividers for various configurations.
Table 30. Duty Cycle with VCO Divider, Input Duty Cycle Is 50%
VCO
Divider
Even
Odd = 3
Odd = 5
Even,
Odd
Even,
Odd
DX
N+M+2
1 (divider
bypassed)
1 (divider
bypassed)
1 (divider
bypassed)
Even
Odd
Number of Low Cycles = M + 1
VCO
Divider
Even
Number of High Cycles = N + 1
Odd = 3
Odd = 5
When a divider is bypassed, DX = 1.
Even
Otherwise, DX = (N + 1) + (M + 1) = N + M + 2. This allows
each channel divider to divide by any integer from 2 to 32.
DX
N+M+2
1 (divider
bypassed)
1 (divider
bypassed)
1 (divider
bypassed)
Even
Odd
Duty Cycle and Duty-Cycle Correction (0, 1, and 2)
Odd = 3
Even
The duty cycle of the clock signal at the output of a channel is a
result of some or all of the following conditions:
Odd = 3
Odd
Odd = 5
Even
Odd = 5
Odd
What are the M and N values for the channel?
Is the DCC enabled?
Is the VCO divider used?
What is the CLK input duty cycle?
33.3%
50%
40%
50%
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
50%, requires M = N
50%, requires M = N + 1
Table 31. Duty Cycle with VCO Divider, Input Duty Cycle Is X%
The cycles are cycles of the clock signal currently routed to the
input of the channel dividers (VCO divider out or CLK).
•
•
•
•
Output Duty Cycle
DCCOFF = 1 DCCOFF = 0
50%
50%
Rev. A | Page 36 of 76
Output Duty Cycle
DCCOFF = 1 DCCOFF = 0
50%
50%
33.3%
(1 + X%)/3
40%
(2 + X%)/5
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
50%,
requires M = N
50%,
requires M = N + 1
50%,
requires M = N
(3N + 4 + X%)/(6N + 9),
requires M = N + 1
50%,
requires M = N
(5N + 7 + X%)/(10N + 15),
requires M = N + 1
AD9516-5
Case 1
Table 32. Channel Divider Output Duty Cycle When the
VCO Divider Is Not Used
50%
Odd
X%
Odd
Output Duty Cycle
DCCOFF = 1 DCCOFF = 0
1 (divider
Same as input
bypassed)
duty cycle
(N + 1)/
(M + N + 2)
(N + 1)/
(M + N + 2)
(N + 1)/
(M + N + 2)
Case 2
50%, requires M = N
50%, requires
M=N+1
(N + 1 + X%)/(2 × N + 3),
requires M = N + 1
For Φ ≥ 16:
Δt = (Φ − 16 + M + 1) × TX
Δc = Δt/TX
By giving each divider a different phase offset, output-to-output
delays can be set in increments of the channel divider input
clock cycle. Figure 43 shows the results of setting such a coarse
offset between outputs.
If the CLK input is routed directly to the output, the duty cycle of
the output is the same as the CLK input.
CHANNEL
DIVIDER INPUT
0
1
2
Tx
Phase Offset or Coarse Time Delay (0, 1, and 2)
Each channel divider allows for a phase offset, or a coarse time
delay, to be programmed by setting register bits (see Table 33).
These settings determine the number of cycles (successive
rising edges) of the channel divider input frequency by which to
offset, or delay, the rising edge of the output of the divider. This
delay is with respect to a nondelayed output (that is, with a
phase offset of zero). The amount of the delay is set by five bits
loaded into the phase offset (PO) register, plus the start high
(SH) bit for each channel divider. When the start high bit is set,
the delay is also affected by the number of low cycles (M) that
are programmed for the divider.
The sync function must be used to make phase offsets effective
(see the Synchronizing the Outputs—SYNC Function section).
Table 33. Setting Phase Offset and Division for Divider 0,
Divider 1, and Divider 21
Divider
0
1
2
1
Start
High (SH)
0x191[4]
0x194[4]
0x197[4]
Phase
Offset (PO)
0x191[3:0]
0x194[3:0]
0x197[3:0]
Low
Cycles (M)
0x190[7:4]
0x193[7:4]
0x196[7:4]
High
Cycles (N)
0x190[3:0]
0x193[3:0]
0x196[3:0]
Note that the value stored in the register = # of cycles minus 1. For example,
Register 0x190[7:4] = 0001b equals two low cycles (M = 2) for Divider 0.
Let
Δt = delay (in seconds).
Δc = delay (in cycles of clock signal at input to DX).
TX = period of the clock signal at the input of the divider, DX (in
seconds).
Φ=
16 × SH[4] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] + 1 × PO[0]
The channel divide-by is set as N = high cycles and M = low
cycles.
3
4
5
6
7
8
9
10 11 12 13 14 15
CHANNEL DIVIDER OUTPUTS
DIV = 4, DUTY = 50%
SH = 0
DIVIDER 0 PO = 0
DIVIDER 1
SH = 0
PO = 1
DIVIDER 2
SH = 0
PO = 2
07972-071
Any
DX
N+M+2
Channel
divider
bypassed
Even
Input Clock
Duty Cycle
Any
For Φ ≤ 15:
Δt = Φ × TX
Δc = Δt/TX = Φ
1 × Tx
2 × Tx
Figure 43. Effect of Coarse Phase Offset (or Delay)
Channel Dividers—LVDS/CMOS Outputs
Channel Divider 3 and Channel Divider 4 each drive a pair of
LVDS outputs, giving four LVDS outputs (OUT6 to OUT9).
Alternatively, each of these LVDS differential outputs can be
configured individually as a pair (A and B) of CMOS singleended outputs, providing for up to eight CMOS outputs. By default,
the B output of each pair is off but can be turned on as desired.
Channel Divider 3 and Channel Divider 4 each consist of two
cascaded, 2 to 32, frequency dividers. The channel frequency
division is DX.1 × DX.2, or up to 1024. Divide-by-1 is achieved by
bypassing one or both of these dividers. Both of the dividers also
have DCC enabled by default, but this function can be disabled,
if desired, by setting the DCCOFF bit of the channel. A coarse
phase offset or delay is also programmable (see the Phase Offset
or Coarse Time Delay (Divider 3 and Divider 4) section). The
channel dividers operate up to 1600 MHz. The features and
settings of the dividers are selected by programming the
appropriate setup and control registers (see Table 47 and Table 48
through Table 57).
Table 34. Setting Division (DX) for Divider 3 and Divider 41
Divider
3
3.1
3.2
4
4.1
4.2
1
M
0x199[7:4]
0x19B[7:4]
0x19E[7:4]
0x1A0[7:4]
N
0x199[3:0]
0x19B[3:0]
0x19E[3:0]
0x1A0[3:0]
Bypass
0x19C[4]
0x19C[5]
0x1A1[4]
0x1A1[5]
DCCOFF
0x19D[0]
0x19D[0]
0x1A2[0]
0x1A2[0]
Note that the value stored in the register = # of cycles minus 1. For example,
Register 0x199[7:4] = 0001b equals two low cycles (M = 2) for Divider 3.1.
Rev. A | Page 37 of 76
AD9516-5
Channel Frequency Division (Divider 3 and Divider 4)
The division for each channel divider is set by the bits in the
registers for the individual dividers (X.Y = 3.1, 3.2, 4.1, and 4.2).
Number of Low Cycles = MX.Y + 1
Number of High Cycles = NX.Y + 1
When both X.1 and X.2 are bypassed, DX = 1 × 1 = 1.
When only X.2 is bypassed, DX = (NX.1 + MX.1 + 2) × 1.
When both X.1 and X.2 are not bypassed, DX = (NX.1 + MX.1 + 2) ×
(NX.2 + MX.2 + 2).
By cascading the dividers, channel division up to 1024 can be
obtained. However, not all integer value divisions from 1 to
1024 are obtainable; only the values that are the product of the
separate divisions of the two dividers (DX.1 × DX.2) can be realized.
If only one divider is needed when using Divider 3 and Divider 4,
use the first one (X.1) and bypass the second one (X.2). Do not
bypass X.1 and use X.2.
Duty Cycle and Duty-Cycle Correction (Divider 3 and
Divider 4)
The same duty cycle and DCC considerations apply to Divider 3
and Divider 4 as to Divider 0, Divider 1, and Divider 2 (see the
Duty Cycle and Duty-Cycle Correction (0, 1, and 2) section);
however, with these channel dividers, the number of possible
configurations is more complex.
Duty-cycle correction on Divider 3 and Divider 4 requires the
following channel divider conditions:
•
•
•
•
An even DX.Y must be set as MX.Y = NX.Y (low cycles = high
cycles).
An odd DX.Y must be set as MX.Y = NX.Y + 1 (number of low
cycles must be one greater than the number of high cycles).
If only one divider is bypassed, it must be the second
divider, X.2.
If only one divider has an even divide-by, it must be the
second divider, X.2.
Table 36. Divider 3 and Divider 4 Duty Cycle; VCO Divider
Not Used; Duty Cycle Correction Off (DCCOFF = 1)
Input
Clock
Duty
Cycle
50%
X%
50%
NX.1 + MX.1 + 2
Bypassed
Bypassed
Even, odd
NX.2 + MX.2 + 2
Bypassed
Bypassed
Bypassed
X%
Even, odd
Bypassed
50%
Even, odd
Even, odd
X%
Even, odd
Even, odd
VCO
Divider
Even
Odd
Even
Odd
Even
Odd
Even
DX.1
DX.2
NX.1 + MX.1 + 2
Bypassed
Bypassed
Even (NX.1 = MX.1)
Even (NX.1 = MX.1)
Odd (MX.1 = NX.1 + 1)
Odd (MX.1 = NX.1 + 1)
Even (NX.1 = MX.1)
Odd
Even (NX.1 = MX.1)
Even
Odd (MX.1 = NX.1 + 1)
Odd
Odd (MX.1 = NX.1 + 1)
Even
Odd (MX.1 = NX.1 + 1)
Odd
Odd (MX.1 = NX.1 + 1)
NX.2 + MX.2 + 2
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Even
(NX.2 = MX.2)
Even
(NX.2 = MX.2)
Even
(NX.2 = MX.2)
Even
(NX.2 = MX.2)
Odd
(MX.2 = NX.2 + 1)
Odd
(MX.2 = NX.2 + 1)
Table 35. Divider 3 and Divider 4 Duty Cycle; VCO Divider
Used; Duty Cycle Correction Off (DCCOFF = 1)
DX.1
NX.1 + MX.1 + 2
Bypassed
Bypassed
Bypassed
Even, odd
DX.2
NX.2 + MX.2 + 2
Bypassed
Bypassed
Bypassed
Bypassed
Odd
Even, odd
Bypassed
Even
Even, odd
Even, odd
Odd
Even, odd
Even, odd
DX.2
Output
Duty Cycle
50%
X%
(NX.1 + 1)/
(NX.1 + MX.1 + 2)
(NX.1 + 1)/
(NX.1 + MX.1 + 2)
(NX.2 + 1)/
(NX.2 + MX.2 + 2)
(NX.2 + 1)/
(NX.2 + MX.2 + 2)
Table 37. Divider 3 and Divider 4 Duty Cycle; VCO Divider
Used; Duty Cycle Correction On (DCCOFF = 0); VCO Divider
Input Duty Cycle = 50%
The possibilities for the duty cycle of the output clock from
Divider 3 and Divider 4 are shown in Table 35 through Table 39.
VCO
Divider
Even
Odd = 3
Odd = 5
Even
DX.1
Output Duty Cycle
50%
33.3%
40%
(NX.1 + 1)/
(NX.1 + MX.1 + 2)
(NX.1 + 1)/
(NX.1 + MX.1 + 2)
(NX.2 + 1)/
(NX.2 + MX.2 + 2)
(NX.2 + 1)/
(NX.2 + MX.2 + 2)
Rev. A | Page 38 of 76
Output
Duty Cycle
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
AD9516-5
Table 38. Divider 3 and Divider 4 Duty Cycle; VCO Divider
Used; Duty Cycle Correction On (DCCOFF = 0); VCO
Divider Input Duty Cycle = X%
DX.1
VCO
Divider
Even
Odd = 3
Odd = 5
Even
Odd
Even
Odd = 3
Odd = 5
Even
Odd
Even
Odd
Even
Odd = 3
Odd = 5
NX.1 + MX.1 + 2
Bypassed
Bypassed
Bypassed
Even
(NX.1 = MX.1)
Even
(NX.1 = MX.1)
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.1 = NX.1 + 1)
Even
(NX.1 = MX.1)
Even
(NX.1 = MX.1)
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.1 = NX.1 + 1)
Table 39. Divider 3 and Divider 4 Duty Cycle; VCO Divider
Not Used; Duty Cycle Correction On (DCCOFF = 0)
Input
Clock
Duty
Cycle
50%
50%
DX.2
NX.2 + MX.2 +
2
Bypassed
Bypassed
Bypassed
Bypassed
Output
Duty Cycle
50%
(1 + X%)/3
(2 + X%)/5
50%
Bypassed
50%
50%
Bypassed
50%
X%
Bypassed
(3NX.1 + 4 + X%)/
(6NX.1 + 9)
(5NX.1 + 7 + X%)/
(10NX.1 + 15)
50%
50%
50%
50%
50%
X%
50%
50%
50%
X%
Bypassed
Even
(NX.2 = MX.2)
Even
(NX.2 = MX.2)
Even
(NX.2 = MX.2)
Even
(NX.2 = MX.2)
Odd
(MX.2 = NX.2 + 1)
Odd
(MX.2 = NX.2 + 1)
Odd
(MX.2 = NX.2 + 1)
X%
X%
(6NX.1NX.2 + 9NX.1 +
9NX.2 + 13 + X%)/
(3(2NX.1 + 3)
(2NX.2 + 3))
(10NX.1NX.2 + 15NX.1 +
15NX.2 + 22 + X%)/
(5(2 NX.1 + 3)
(2 NX.2 + 3))
X%
DX.1
DX.2
NX.1 + MX.1 + 2
Bypassed
Even
(NX.1 = MX.1)
Bypassed
Even
(NX.1 = MX.1)
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.1 = NX.1 + 1)
Even
(NX.1 = MX.1)
Even
(NX.1 = MX.1)
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.1 = NX.1 + 1)
NX.2 + MX.2 + 2
Bypassed
Bypassed
Output
Duty Cycle
50%
50%
Bypassed
Bypassed
X% (high)
50%
Bypassed
50%
Bypassed
(NX.1 + 1 + X%)/
(2NX.1 + 3)
(NX.1 + 1 + X%)/
(2NX.1 + 3)
50%
Bypassed
Even
(NX.2 = MX.2)
Even
(NX.2 = MX.2)
Even
(NX.2 = MX.2)
Even
(NX.2 = MX.2)
Odd
(MX.2 = NX.2 + 1)
Odd
(MX.2 = NX.2 + 1)
50%
50%
50%
50%
(2NX.1NX.2 + 3NX.1 +
3NX.2 + 4 + X%)/
((2NX.1 + 3)(2NX.2 + 3))
Phase Offset or Coarse Time Delay (Divider 3 and Divider 4)
Divider 3 and Divider 4 can be set to have a phase offset or
delay. The phase offset is set by a combination of the bits in the
phase offset and start high registers (see Table 40).
Table 40. Setting Phase Offset and Division for Divider 3 and
Divider 41
Divider
3 3.1
3.2
4 4.1
4.2
1
Start
High (SH)
0x19C[0]
0x19C[1]
0x1A1[0]
0x1A1[1]
Phase
Offset (PO)
0x19A[3:0]
0x19A[7:4]
0x19F[3:0]
0x19F[7:4]
Low
Cycles M
0x199[7:4]
0x19B[7:4]
0x19E[7:4]
0x1A0[7:4]
High
Cycles N
0x199[3:0]
0x19B[3:0]
0x19E[3:0]
0x1A0[3:0]
Note that the value stored in the register is equal to the number of cycles
minus 1. For example, Register 0x199[7:4] = 0001b equals two low cycles
(M = 2) for Divider 3.1.
Rev. A | Page 39 of 76
AD9516-5
Let
Δt = delay (in seconds).
Φx.y = 16 × SH[0] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] +
1 × PO[0].
TX.1 = period of the clock signal at the input to DX.1 (in seconds).
TX.2 = period of the clock signal at the input to DX.2 (in seconds).
Case 1
Calculating the Fine Delay
The following values and equations are used to calculate the
delay of the delay block.
IRAMP (μA) = 200 × (Ramp Current + 1)
Number of Capacitors = Number of Bits =
0 in Ramp Capacitors + 1
Example: 101 = 1 + 1 = 2; 110 = 1 + 1 = 2; 100 = 2 + 1 = 3;
001 = 2 + 1 = 3; 111 = 0 + 1 = 1.
When Φx.1 ≤ 15 and Φx.2 ≤ 15:
Δt = Φx.1 × TX.1 + ΦX.2 × Tx.2
Delay Range (ns) = 200 × ((No. of Caps + 3)/(IRAMP)) × 1.3286
Case 2
Case 3
No. of Caps 1
6
Offset ns 0.34 1600 I RAMP 10 4
I RAMP
Delay Full Scale (ns) = Delay Range + Offset
When ΦX.1 ≥ 16 and ΦX.2 ≤ 15:
Δt = (ΦX.1 − 16 + MX.1 + 1) × TX.1 + ΦX.2 × TX.2
Fine Delay (ns) =
Delay Range × Delay Fraction × (1/63) + Offset
When Φx.1 ≤ 15 and Φx.2 ≥ 16:
Δt = ΦX.1 × TX.1 + (ΦX.2 – 16 + MX.2 + 1) × TX.2
Note that only delay fraction values up to 47 decimal (101111b;
0x02F) are supported.
Case 4
When ΦX.1 ≥ 16 and ΦX.2 ≥ 16:
Δt =
(ΦX.1 − 16 + MX.1 + 1) × TX.1 + (ΦX.2 − 16 + MX.2 + 1) × TX.2
In no case can the fine delay exceed one-half of the output clock
period. If a delay longer than half of the clock period is attempted,
the output stops clocking.
Fine Delay Adjust (Divider 3 and Divider 4)
The delay function adds some jitter that is greater than that
specified for the nondelayed output. This means that the delay
function should be used primarily for clocking digital chips, such
as FPGA, ASIC, DUC, and DDC. An output with this delay
enabled may not be suitable for clocking data converters. The
jitter is higher for long full scales because the delay block uses a
ramp and trip points to create the variable delay. A slower ramp
time produces more time jitter.
Each AD9516 LVDS/CMOS output (OUT6 to OUT9) includes
an analog delay element that can be programmed to give variable
time delays (Δt) in the clock signal at that output.
BYPASS
VCO
CLK DIVIDER
DIVIDER
X.1
CMOS
∆t
LVDS
FINE DELAY
ADJUST
CMOS
OUTM
OUTM
OUTPUT
DRIVERS
DIVIDER
X.2
Synchronizing the Outputs—SYNC Function
BYPASS
LVDS
FINE DELAY
ADJUST
CMOS
OUTN
OUTN
07972-072
CMOS
∆t
Figure 44. Fine Delay (OUT6 to OUT9)
The amount of delay applied to the clock signal is determined
by programming four registers per output (see Table 41).
Table 41. Setting Analog Fine Delays
OUTPUT
(LVDS/CMOS)
OUT6
OUT7
OUT8
OUT9
Ramp
Capacitors
0x0A1[5:3]
0x0A4[5:3]
0x0A7[5:3]
0x0AA[5:3]
Ramp
Current
0x0A1[2:0]
0x0A4[2:0]
0x0A7[2:0]
0x0AA[2:0]
Delay
Fraction
0x0A2[5:0]
0x0A5[5:0]
0x0A8[5:0]
0x0AB[5:0]
Delay
Bypass
0x0A0[0]
0x0A3[0]
0x0A6[0]
0x0A9[0]
The AD9516 clock outputs can be synchronized to each other.
Outputs can be individually excluded from synchronization.
Synchronization consists of setting the nonexcluded outputs to
a preset set of static conditions and, subsequently, releasing
these outputs to continue clocking at the same instant with the
preset conditions applied. This allows for the alignment of the
edges of two or more outputs or for the spacing of edges
according to the coarse phase offset settings for two or more
outputs.
Synchronization of the outputs is executed in several ways:
Rev. A | Page 40 of 76
By forcing the SYNC pin and then releasing it (manual sync)
By setting and then resetting any one of the following three
bits: the soft SYNC bit (Register 0x230[0]), the soft reset bit
(Register 0x000[2] [mirrored]), or the power-down
distribution reference bit (Register 0x230[1])
By executing synchronization of the outputs as part of the
chip power-up sequence
By forcing the RESET pin low, then releasing it (chip reset)
By forcing the PD pin low, then releasing it (chip power-down)
AD9516-5
between 14 and 15 cycles of clock at the channel divider input,
plus either one cycle of the VCO divider input (see Figure 45),
or one cycle of the CLK input (see Figure 46), depending on
whether the VCO divider is used. Cycles are counted from the
rising edge of the signal.
The most common way to execute the SYNC function is to use
the SYNC pin to do a manual synchronization of the outputs.
This requires a low going signal on the SYNC pin, which is held
low and then released when synchronization is desired. The timing
of the SYNC operation is shown in Figure 45 (using VCO divider)
and Figure 46 (VCO divider not used). There is an uncertainty
of up to one cycle of the clock at the input to the channel divider
due to the asynchronous nature of the SYNC signal with respect
to the clock edges inside the AD9516. The delay from the SYNC
rising edge to the beginning of synchronized output clocking is
CHANNEL DIVIDER
OUTPUT CLOCKING
Another common way to execute the SYNC function is by setting
and resetting the soft SYNC bit at Register 0x230[0] (see Table 47
through Table 57 for details). Both the setting and resetting of
the soft SYNC bit require an update all registers operation
(Register 0x232[0] = 1) to take effect.
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER OUTPUT STATIC
INPUT TO VCO DIVIDER
1
1
INPUT TO CHANNEL DIVIDER
2
3
4
5
6
7
8
9
10
11
12
13
14
SYNC PIN
OUTPUT OF
CHANNEL DIVIDER
07972-073
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT
Figure 45. SYNC Timing When VCO Divider Is Used—CLK or VCO Is Input
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER OUTPUT STATIC
INPUT TO CLK
INPUT TO CHANNEL DIVIDER
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SYNC PIN
OUTPUT OF
CHANNEL DIVIDER
07972-074
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT
Figure 46. SYNC Timing When VCO Divider Is Not Used—CLK Input Only
Rev. A | Page 41 of 76
AD9516-5
The AD9516 outputs are in pairs, sharing a channel divider per
pair (two pairs of pairs, four outputs, in the case of CMOS). The
synchronization conditions apply to both outputs of a pair.
For this reason, the LVPECL outputs have several power-down
modes. This includes a safe power-down mode that continues
to protect the output devices while powered down, although it
consumes somewhat more power than a total power-down. If
the LVPECL output pins are terminated, it is best to select the
safe power-down mode. If the pins are not connected (unused),
it is acceptable to use the total power-down mode.
LVDS/CMOS Outputs—OUT6 to OUT9
OUT6 to OUT9 can be configured as either an LVDS differential
output or as a pair of CMOS single-ended outputs. The LVDS
outputs allow for selectable output current from ~1.75 mA to ~7 mA.
Each channel (a divider and its outputs) can be excluded from
any sync operation by setting the nosync bit of the channel.
Channels that are set to ignore SYNC (excluded channels) do
not set their outputs static during a sync operation, and their
outputs are not synchronized with those of the nonexcluded
channels.
3.5mA
Clock Outputs
3.5mA
The AD9516 offers three output level choices: LVPECL, LVDS,
and CMOS. OUT0 to OUT5 are LVPECL differential outputs;
and OUT6 to OUT9 are LVDS/CMOS outputs. These outputs
can be configured as either LVDS differential or as pairs of
single-ended CMOS outputs.
LVPECL Outputs—OUT0 to OUT5
The LVPECL differential voltage (VOD) is selectable from 400 mV
to 960 mV (see Register 0x0F0[3:2] to Register 0x0F5[3:2]). The
LVPECL outputs have dedicated pins for power supply
(VS_LVPECL), allowing a separate power supply to be used.
VS_LVPECL can range from 2.5 V to 3.3 V.
3.3V
OUT
OUT
OUT
Figure 48. LVDS Output, Simplified Equivalent Circuit with
3.5 mA Typical Current Source
The LVDS output polarity can be set as noninverting or inverting,
which allows for the adjustment of the relative polarity of outputs
within an application without requiring a board layout change. Each
LVDS output can be powered down, if not needed, to save power.
OUT6 to OUT9 can also be CMOS outputs. Each LVDS output can
be configured to be two CMOS outputs. This provides for up to
eight CMOS outputs: OUT6A, OUT6B, OUT7A, OUT7B,
OUT8A, OUT8B, OUT9A, and OUT9B. When an output is
configured as CMOS, the CMOS Output A is automatically turned
on. The CMOS Output B can be turned on or off independently.
The relative polarity of the CMOS outputs can also be selected for
any combination of inverting and noninverting. See Table 52:
Register 0x140[7:5], Register 0x141[7:5], Register 0x142[7:5], and
Register 0x143[7:5].
Each LVDS/CMOS output can be powered down, as needed, to
save power. The CMOS output power-down is controlled by the
same bit that controls the LVDS power-down for that output.
This power-down control affects both CMOS Output A and
CMOS Output B. However, when CMOS Output A is powered up,
CMOS Output B output can be powered on or off separately.
Figure 47. LVPECL Output, Simplified Equivalent Circuit
The LVPECL output polarity can be set as noninverting or
inverting, which allows for the adjustment of the relative
polarity of outputs within an application without requiring a
board layout change. Each LVPECL output can be powered
down or powered up as needed. Because of the architecture of
the LVPECL output stages, there is the possibility of electrical
overstress and breakdown under certain power-down conditions.
Rev. A | Page 42 of 76
VS
OUT1/
OUT1
07972-035
07972-033
GND
OUT
07972-034
A sync operation brings all outputs that have not been excluded (by
the nosync bit) to a preset condition before allowing the outputs to
begin clocking in synchronicity. The preset condition takes into
account the settings in each of the channel’s start high bit and its
phase offset. These settings govern both the static state of each
output when the sync operation is happening and the state and
relative phase of the outputs when they begin clocking again upon
completion of the sync operation. Between outputs and after
synchronization, this allows for the setting of phase offsets.
Figure 49. CMOS Equivalent Output Circuit
AD9516-5
RESET MODES
The AD9516 has several ways to force the chip into a reset
condition that restores all registers to their default values and
makes these settings active.
Power-On Reset—Start-Up Conditions When VS Is Applied
A power-on reset (POR) is issued when the VS power supply is
turned on. The POR pulse duration is <100 ms and initializes
the chip to the power-on conditions that are determined by the
default register settings. These are indicated in the Default Value
(Hex) column of Table 47. At power-on, the AD9516 also executes
a SYNC operation, which brings the outputs into phase alignment
according to the default settings. It is recommended that the
user not toggle SCLK during the reset pulse.
Asynchronous Reset via the RESET Pin
An asynchronous hard reset is executed by momentarily pulling
RESET low. A reset restores the chip registers to the default settings.
It is recommended that the user not toggle SCLK for 20 ns after
RESET goes high.
Soft Reset via Register 0x000[2]
A soft reset is executed by writing Register 0x000[2] and
Register 0x000[5] = 1b. This bit is not self-clearing; therefore,
it must be cleared by writing Register 0x000[2] and Register
0x000[2] = 0b to reset it and complete the soft reset operation.
A soft reset restores the default values to the internal registers.
The soft reset bit does not require an update registers command
(Register 0x232 = 0x01) to be issued.
POWER-DOWN MODES
Chip Power-Down via PD
The AD9516 can be put into a power-down condition by pulling
the PD pin low. Power-down turns off most of the functions and
currents inside the AD9516. The chip remains in this power-down
state until PD is brought back to logic high. When the AD9516
wakes up, it returns to the settings programmed into its registers
prior to the power-down, unless the registers are changed by
new programming while the PD pin is held low.
The PD power-down shuts down the currents on the chip, except
the bias current that is necessary to maintain the LVPECL outputs
in a safe shutdown mode. This is needed to protect the LVPECL
output circuitry from damage that can be caused by certain
termination and load configurations when tristated. Because this
is not a complete power-down, it can be called sleep mode.
When the AD9516 is in a PD power-down, the chip is in the
following state:
•
•
•
•
•
•
The PLL is off (asynchronous power-down).
The CLK input buffer is off.
All dividers are off.
All LVDS/CMOS outputs are off.
All LVPECL outputs are in safe off mode.
The serial port is active and responds to commands.
If the AD9516 clock outputs must be synchronized to each
other, a SYNC is required upon exiting power-down (see the
Synchronizing the Outputs—SYNC Function section).
PLL Power-Down
The PLL section of the AD9516 can be selectively powered
down. There are three PLL operating modes that are set by
Register 0x010[1:0], as shown in Table 49.
In asynchronous power-down mode, the device powers down as
soon as the registers are updated.
In synchronous power-down mode, the PLL power-down is
gated by the charge pump to prevent unwanted frequency jumps.
The device goes into power-down on the occurrence of the next
charge pump event after the registers are updated.
Distribution Power-Down
The distribution section can be powered down by writing to
Register 0x230[1] = 1b. This turns off the bias to the distribution
section. If the LVPECL power-down mode is normal operation
(00b), it is possible for a low impedance load on that LVPECL
output to draw significant current during this power-down. If the
LVPECL power-down mode is set to 11b, the LVPECL output is
not protected from reverse bias and can be damaged under
certain termination conditions.
Individual Clock Output Power-Down
Any of the clock distribution outputs can be powered down
individually by writing to the appropriate registers. The register
map details the individual power-down settings for each output.
The LVDS/CMOS outputs can be powered down, regardless of
their output load configuration.
The LVPECL outputs have multiple power-down modes
(see Table 53) that give some flexibility in dealing with the
various output termination conditions. When the mode is set to
10b, the LVPECL output is protected from reverse bias to
2 VBE + 1 V. If the mode is set to 11b, the LVPECL output is
not protected from reverse bias and can be damaged under
certain termination conditions. This setting also affects the
operation when the distribution block is powered down with
0x230[1] = 1b (see the Distribution Power-Down section).
Individual Circuit Block Power-Down
Other AD9516 circuit blocks (such as CLK, REF1, and REF2)
can be powered down individually. This gives flexibility in
configuring the part for power savings whenever certain chip
functions are not needed.
Rev. A | Page 43 of 76
AD9516-5
SERIAL CONTROL PORT
The AD9516 serial control port is a flexible, synchronous, serial
communications port that allows an easy interface with many
industry-standard microcontrollers and microprocessors. The
AD9516 serial control port is compatible with most synchronous
transfer formats, including both the Motorola SPI® and Intel®
SSR® protocols. The serial control port allows read/write access
to all registers that configure the AD9516. Single or multiple byte
transfers are supported, as well as MSB first or LSB first transfer
formats. The AD9516 serial control port can be configured for a
single bidirectional I/O pin (SDIO only) or for two unidirectional
I/O pins (SDIO/SDO). By default, the AD9516 is in bidirectional
mode, long instruction (long instruction is the only instruction
mode supported).
During this period, the serial control port state machine enters
a wait state until all data is sent. If the system controller decides
to abort the transfer before all of the data is sent, the state machine
must be reset, either by completing the remaining transfers or
by returning the CS low for at least one complete SCLK cycle
(but less than eight SCLK cycles). Raising the CS on a nonbyte
boundary terminates the serial transfer and flushes the buffer.
SERIAL CONTROL PORT PIN DESCRIPTIONS
Communication Cycle—Instruction Plus Data
SCLK (serial clock) is the serial shift clock. This pin is an input.
SCLK is used to synchronize serial control port reads and writes.
Write data bits are registered on the rising edge of this clock,
and read data bits are registered on the falling edge. This pin
is internally pulled down by a 30 kΩ resistor to ground.
SDIO (serial data input/output) is a dual-purpose pin that acts
as either an input only (unidirectional mode) or as both an input/
output (bidirectional mode). The AD9516 defaults to the
bidirectional I/O mode (Register 0x000[0] = 0b).
SDO (serial data output) is used only in the unidirectional I/O
mode (Register 0x000[0] = 1b) as a separate output pin for
reading back data.
CS (chip select bar) is an active low control that gates the read
and write cycles. When CS is high, SDO and SDIO are in a high
impedance state. This pin is internally pulled up by a 30 kΩ
resistor to VS.
16
CS
17
SDO
21
SDIO
22
AD9516-5
SERIAL
CONTROL
PORT
07972-036
SCLK
Figure 50. Serial Control Port
GENERAL OPERATION OF SERIAL CONTROL PORT
A write or a read operation to the AD9516 is initiated by pulling
CS low.
CS stall high is supported in modes where three or fewer bytes
of data (plus instruction data) are transferred (see Table 42).
In these modes, CS can temporarily return high on any byte
boundary, allowing time for the system controller to process the
next byte. CS can go high on byte boundaries only and during
either part (instruction or data) of the transfer.
In streaming mode (see Table 42), any number of data bytes can
be transferred in a continuous stream. The register address is
automatically incremented or decremented (see the MSB/LSB
First Transfers section). CS must be raised at the end of the last
byte to be transferred, thereby ending the stream mode.
There are two parts to a communication cycle with the AD9516.
The first part writes a 16-bit instruction word into the AD9516,
coincident with the first 16 SCLK rising edges. The instruction
word provides the AD9516 serial control port with information
regarding the data transfer, which is the second part of the
communication cycle. The instruction word defines whether
the upcoming data transfer is a read or a write, the number of
bytes in the data transfer, and the starting register address for
the first byte of the data transfer.
Write
If the instruction word is for a write operation, the second part
is the transfer of data into the serial control port buffer of the
AD9516. Data bits are registered on the rising edge of SCLK.
The length of the transfer (1, 2, or 3 bytes or streaming mode)
is indicated by two bits ([W1:W0]) in the instruction byte.
When the transfer is 1, 2, or 3 bytes, but not streaming, CS can
be raised after each sequence of eight bits to stall the bus (except
after the last byte, where it ends the cycle). When the bus is stalled,
the serial transfer resumes when CS is lowered. Raising CS on
a nonbyte boundary resets the serial control port. During a write,
streaming mode does not skip over reserved or unused registers;
therefore, the user must know the correct bit pattern to write to
the reserved registers to preserve proper operation of the part.
Refer to the register map (see Table 47) to determine if the default
value for reserved registers is nonzero. It does not matter what
data is written to blank or unused registers.
Because data is written into a serial control port buffer area, and
not directly into the actual control registers of the AD9516, an
additional operation is needed to transfer the serial control port
buffer contents to the actual control registers of the AD9516,
thereby causing them to become active. The update registers
operation consists of setting Register 0x232[0] = 1b (this bit is selfclearing). Any number of bytes of data can be changed before
executing an update registers. The update registers operation
simultaneously actuates all register changes that have been
written to the buffer since any previous update.
Rev. A | Page 44 of 76
AD9516-5
Read
If the instruction word is for a read operation, the next N × 8
SCLK cycles clock out the data from the address specified in the
instruction word, where N is 1 to 3, as determined by [W1:W0].
If N = 4, the read operation is in streaming mode, continuing
until CS is raised. Streaming mode does not skip over reserved
or blank registers. The readback data is valid on the falling
edge of SCLK.
The default mode of the AD9516 serial control port is the
bidirectional mode. In bidirectional mode, both the sent data
and the readback data appear on the SDIO pin. It is also possible to
set the AD9516 to unidirectional mode via the SDO active bit
(Register 0x000[0] = 1b). In unidirectional mode, the readback
data appears on the SDO pin.
A readback request reads the data that is in the serial control
port buffer area, or the data that is in the active registers (see
Figure 51). Readback of the buffer or active registers is controlled
by Register 0x004[0].
The AD9516 supports only the long instruction mode; therefore,
Register 0x000[4:3] must be set to 11b. (This register uses
mirrored bits). Long instruction mode is the default at powerup or reset.
SDO
CS
SERIAL
CONTROL
PORT
UPDATE
REGISTERS
WRITE REGISTER 0x232 = 0x01
TO UDATE REGISTERS
07972-037
SDIO
ACTIVE REGISTERS
SCLK
BUFFER REGISTERS
The AD9516 uses Register Address 0x000 to Register
Address 0x232.
Figure 51. Relationship Between Serial Control Port Buffer Registers and
Active Registers of the AD9516
INSTRUCTION WORD (16 BITS)
The MSB of the instruction word is R/W, which indicates
whether the instruction is a read or a write. The next two bits,
[W1:W0], indicate the length of the transfer in bytes. The final
13 bits are the address ([A12:A0]) at which to begin the read or
write operation.
For a write, the instruction word is followed by the number of
bytes of data indicated by Bits[W1:W0], see Table 42.
Table 42. Byte Transfer Count
W1
0
0
1
1
W0
0
1
0
1
Bytes to Transfer
1
2
3
Streaming mode
The 13 bits found in Bits[A12:A0] select the address within the
register map that is written to or read from during the data
transfer portion of the communications cycle. Only Bits[A9:A0]
are needed to cover the range of the 0x232 registers used by the
AD9516. Bits[A12:A10] must always be set to 0b. For multibyte
transfers, this address is the starting byte address. In MSB first
mode, subsequent bytes decrement the address.
MSB/LSB FIRST TRANSFERS
The AD9516 instruction word and byte data can be MSB first
or LSB first. Any data written to Register 0x000 must be mirrored;
the upper four bits (Bits[7:4]) must mirror the lower four bits
(Bits[3:0]). This makes it irrelevant whether LSB first or MSB first
is in effect. As an example of this mirroring, see the default
setting for this register: 0x000, which mirrors Bit 4 and Bit 3.
This sets the long instruction mode (which is the default and
the only mode that is supported).
The default for the AD9516 is MSB first.
When LSB first is set by Register 0x000[1] and Register 0x000[6],
it takes effect immediately, because it affects only the operation
of the serial control port and does not require that an update be
executed.
When MSB first mode is active, the instruction and data bytes
must be written from MSB to LSB. Multibyte data transfers in
MSB first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent data
bytes must follow, in order, from high address to low address. In
MSB first mode, the serial control port internal address generator
decrements for each data byte of the multibyte transfer cycle.
When LSB first is active, the instruction and data bytes must be
written from LSB to MSB. Multibyte data transfers in LSB first
format start with an instruction byte that includes the register
address of the least significant data byte followed by multiple
data bytes. The internal byte address generator of the serial control
port increments for each byte of the multibyte transfer cycle.
The AD9516 serial control port register address decrements from
the register address just written toward 0x000 for multibyte I/O
operations if the MSB first mode is active (default). If the LSB
first mode is active, the register address of the serial control port
increments from the address just written toward Register 0x232
for multibyte I/O operations.
Streaming mode always terminates when it hits Address 0x232.
Note that unused addresses are not skipped during multibyte
I/O operations.
Table 43. Streaming Mode (No Addresses Are Skipped)
Write Mode
LSB first
MSB first
Rev. A | Page 45 of 76
Address Direction
Increment
Decrement
Stop Sequence
0x230, 0x231, 0x232, stop
0x001, 0x000, 0x232, stop
AD9516-5
Table 44. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
LSB
I0
R/W
W1
W0
A12 = 0
A11 = 0
A10 = 0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CS
SCLK DON'T CARE
R/W W1 W0 A12 A11 A10 A9
A8
A7
A6 A5
A4 A3 A2
A1 A0
D7 D6 D5
16-BIT INSTRUCTION HEADER
D4 D3
D2 D1
D0
D7
D6 D5
REGISTER (N) DATA
D4 D3 D2
D1 D0
DON'T CARE
REGISTER (N – 1) DATA
07972-038
SDIO DON'T CARE
DON'T CARE
Figure 52. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes of Data
CS
SCLK
DON'T CARE
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
SDO DON'T CARE
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
16-BIT INSTRUCTION HEADER
REGISTER (N) DATA
REGISTER (N – 1) DATA
REGISTER (N – 2) DATA
REGISTER (N – 3) DATA DON'T
CARE
07972-039
SDIO
DON'T CARE
Figure 53. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes of Data
tHIGH
tDS
tS
DON'T CARE
SDIO
DON'T CARE
tLOW
DON'T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
A6
A5
D4
D3
D2
D1
D0
DON'T CARE
07972-040
SCLK
tC
tSCLK
tDH
CS
Figure 54. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements
CS
SCLK
DATA BIT N
07972-041
tDV
SDIO
SDO
DATA BIT N – 1
Figure 55. Timing Diagram for Serial Control Port Register Read
CS
SCLK DON'T CARE
A0 A1 A2 A3
A4
A5 A6 A7
A8
A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4
16-BIT INSTRUCTION HEADER
D5 D6
REGISTER (N) DATA
D7
D0
D1 D2
D6
REGISTER (N + 1) DATA
Figure 56. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes of Data
Rev. A | Page 46 of 76
D3 D4 D5
D7
DON'T CARE
07972-042
SDIO DON'T CARE
DON'T CARE
AD9516-5
tS
tC
CS
tSCLK
tHIGH
SCLK
tLOW
tDS
SDIO
BIT N
BIT N + 1
07972-043
tDH
Figure 57. Serial Control Port Timing—Write
Table 45. Serial Control Port Timing
Parameter
tDS
tDH
tCLK
tS
tC
tHIGH
tLOW
tDV
Description
Setup time between data and the rising edge of SCLK
Hold time between data and the rising edge of SCLK
Period of the clock
Setup time between the CS falling edge and the SCLK rising edge (start of communication cycle)
Setup time between the SCLK rising edge and the CS rising edge (end of communication cycle)
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
SCLK to valid SDIO and SDO (see Figure 55)
Rev. A | Page 47 of 76
AD9516-5
THERMAL PERFORMANCE
Table 46. Thermal Parameters for 64-Lead LFCSP
Symbol
θJA
θJMA
θJMA
ΨJB
θJC
ΨJT
Thermal Characteristic Using a JEDEC JESD51-7 Plus JEDEC JESD51-5 2S2P Test Board
Junction-to-ambient thermal resistance, natural convection per JEDEC JESD51-2 (still air)
Junction-to-ambient thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air)
Junction-to-ambient thermal resistance, 2.0 m/sec airflow per JEDEC JESD51-6 (moving air)
Junction-to-board characterization parameter, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air)
and JEDEC JESD51-8
Junction-to-case thermal resistance (die-to-heat sink) per MIL-Std 883, Method 1012.1
Junction-to-top-of-package characterization parameter, natural convection per JEDEC JESD51-2 (still air)
The AD9516 is specified for a case temperature (TCASE). To ensure
that TCASE is not exceeded, an airflow source can be used.
Use the following equation to determine the junction
temperature on the application PCB:
Value (°C/W)
22.0
19.2
17.2
11.6
1.3
0.1
Values of θJA are provided for package comparison and PCB
design considerations. θJA can be used for a first-order
approximation of TJ by the following equation:
TJ = TA + (θJA × PD)
TJ = TCASE + (ΨJT × PD)
where TA is the ambient temperature (°C).
where:
TJ is the junction temperature (°C).
TCASE is the case temperature (°C) measured by the user at the
top center of the package.
ΨJT is the value from Table 46.
PD is the power dissipation of the device (see Table 13.)
Values of θJC are provided for package comparison and PCB
design considerations when an external heat sink is required.
Values of ΨJB are provided for package comparison and PCB
design considerations.
Rev. A | Page 48 of 76
AD9516-5
REGISTER MAPS
REGISTER MAP OVERVIEW
Register addresses that are not listed in Table 47 (as well as ones marked unused) are not used and writing to those registers has no effect.
The user should write the default value only to the register addresses marked reserved.
Table 47. Register Map Overview
Ref.
Addr.
(Hex)
Parameter
Bit 7 (MSB)
Serial Port Configuration
0x000
Serial port
SDO active
configuration
0x001
0x002
0x003
0x004
PLL
0x010
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Default
Value
(Hex)
LSB first
Soft reset
Long
instruction
Long
instruction
Soft reset
LSB first
SDO active
0x18
Blank
Reserved
Part ID (read only)
Blank
Part ID
Readback
control
PFD and
charge pump
R Counter
0x011
0x012
0x013
0x014
0x015
0x016
A counter
B counter
0x017
0x018
PLL Control 2
PLL Control 3
0x019
PLL Control 4
0x01A
PFD
polarity
Charge pump current
Read back
active
registers
Charge pump mode
PLL power-down
0x01
0x00
0x7D
14-bit R divider, Bits[7:0] (LSB)
14-bit R divider, Bits[13:8] (MSB)
6-bit A counter
13-bit B counter, Bits[7:0] (LSB)
Blank
13-bit B counter, Bits[12:8] (MSB)
Reset R
Reset A and
Reset all
B counter
Prescaler P
Set CP pin
counter
B counters
counters
bypass
to VCP/2
STATUS pin control
Antibacklash pulse width
Reserved
Lock detect counter
Digital
Disable
Reserved
lock detect
digital
window
lock detect
R path delay
N path delay
R, A, B counters
SYNC pin reset
0x01
0x00
0x00
0x03
0x00
0x06
PLL Control 5
Reserved
0x00
0x01B
PLL Control 6
CLK
frequency
monitor
0x01C
PLL Control 7
Disable
switchover
deglitch
0x01D
PLL Control 8
0x01E
0x01F
PLL Control 9
PLL readback
(read-only)
0x020
to
0x04F
PLL Control 1
Blank
Blank
Reference
frequency
monitor
threshold
REF2
(REFIN)
frequency
monitor
Select
REF2
LD pin control
REF1 (REFIN)
frequency
monitor
Use
REF_SEL pin
Reserved
Reserved
REFMON pin control
Reserved
PLL status
register
disable
Holdover
active
LD pin
comparator
enable
Reserved
REF2
CLK
selected
frequency >
threshold
Blank
Rev. A | Page 49 of 76
0x00
0x06
0x00
0x00
REF2
power-on
REF1
power-on
Differential
reference
0x00
Holdover
enable
External
holdover
control
Holdover
enable
0x00
REF2
frequency >
threshold
REF1
frequency >
threshold
Digital
lock detect
0x00
N/A
AD9516-5
Ref.
Addr.
(Hex)
Parameter
Bit 7 (MSB) Bit 6
Fine Delay Adjust—OUT6 to OUT9
0x0A0 OUT6 delay
bypass
0x0A1 OUT6 delay
Blank
full-scale
0x0A2 OUT6 delay
Blank
fraction
0x0A3 OUT7 delay
bypass
0x0A4 OUT7 delay
Blank
full-scale
0x0A5 OUT7 delay
Blank
fraction
0x0A6 OUT8 delay
bypass
0x0A7 OUT8 delay
Blank
full-scale
0x0A8 OUT8 delay
Blank
fraction
0x0A9 OUT9 delay
bypass
0x0AA OUT9 delay
Blank
full-scale
0x0AB
OUT9 delay
fraction
OUT1
Blank
0x0F2
OUT2
Blank
0x0F3
OUT3
Blank
0x0F4
OUT4
Blank
0x0F5
OUT5
Blank
0x142
OUT8
0x143
OUT9
0x144
to
0x18F
Bit 2
Bit 1
Blank
Bit 0 (LSB)
OUT6 delay
bypass
OUT6 ramp current
OUT6 ramp capacitors
OUT6 delay fraction
Blank
OUT7 delay fraction
Blank
OUT8 delay fraction
Blank
0x00
0x01
0x00
0x00
OUT9 delay
bypass
OUT9 ramp current
OUT9 ramp capacitors
0x01
0x00
OUT8 delay
bypass
OUT8 ramp current
OUT8 ramp capacitors
0x00
0x00
OUT7 delay
bypass
OUT7 ramp current
OUT7 ramp capacitors
0x01
0x01
0x00
0x00
Blank
0x0F1
OUT7
Bit 3
OUT9 delay fraction
Blank
0x141
Bit 4
Blank
0x0AC
to
0x0EF
LVPECL Outputs
0x0F0
OUT0
0x0F6
to
0x13F
LVDS/CMOS Outputs
0x140
OUT6
Bit 5
Default
Value
(Hex)
OUT0
invert
OUT1
invert
OUT0 LVPECL
differential voltage
OUT1 LVPECL
differential voltage
OUT0 power-down
0x08
OUT1 power-down
0x0A
OUT2
invert
OUT3
invert
OUT2 LVPECL
differential voltage
OUT3 LVPECL
differential voltage
OUT2 power-down
0x08
OUT3 power-down
0x0A
OUT4
invert
OUT5
invert
OUT4 LVPECL
differential voltage
OUT5 LVPECL
differential voltage
OUT4 power-down
0x08
OUT5 power-down
0x0A
Blank
OUT6 CMOS
output polarity
OUT7 CMOS
output polarity
OUT8 CMOS
output polarity
OUT9 CMOS
output polarity
OUT6
CMOS B
OUT7
CMOS B
OUT8
CMOS B
OUT9
CMOS B
OUT6 select
LVDS/CMOS
OUT7 select
LVDS/CMOS
OUT8 select
LVDS/CMOS
OUT9 select
LVDS/CMOS
Blank
Rev. A | Page 50 of 76
OUT6 LVDS
output current
OUT7 LVDS
output current
OUT8 LVDS
output current
OUT9 LVDS
output current
OUT6
power-down
OUT7
power-down
OUT8
power-down
OUT9
power-down
0x42
0x43
0x42
0x43
AD9516-5
Ref.
Addr.
(Hex)
Parameter
Bit 7 (MSB)
LVPECL Channel Dividers
0x190
Divider 0
(PECL)
0x191
Divider 0
bypass
0x192
0x193
0x194
Divider 1
(PECL)
Divider 1
bypass
Bit 6
Bit 5
Bit 4
Divider 0 low cycles
Divider 0
Divider 0
nosync
force high
Divider 1 low cycles
Divider 1
Divider 1
nosync
force high
0x195
0x196
0x197
Divider 2
(PECL)
Divider 2
bypass
Divider 2 low cycles
Divider 2
Divider 2
nosync
force high
0x198
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Divider 0 high cycles
Divider 0 phase offset
Divider 0
start high
Blank
Divider 1
start high
Blank
Divider 2
start high
Blank
Default
Value
(Hex)
0x00
0x80
Divider 0
direct to
output
Divider 1 high cycles
Divider 1 phase offset
Divider 0
DCCOFF
Divider 1
direct to
output
Divider 2 high cycles
Divider 2 phase offset
Divider 1
DCCOFF
Divider 2
direct to
output
Divider 2
DCCOFF
0x00
0xBB
0x00
0x00
0x00
0x00
0x00
LVDS/CMOS Channel Dividers
0x199
0x19A
0x19B
0x19C
Divider 3
(LVDS/CMOS)
Low Cycles Divider 3.1
Phase Offset Divider 3.2
Low Cycles Divider 3.2
Reserved
Bypass
Divider 3.2
0x19D
0x19E
0x19F
0x1A0
0x1A1
Divider 4
(LVDS/CMOS)
Reserved
Low Cycles Divider 4.1
Phase Offset Divider 4.2
Low Cycles Divider 4.2
Bypass
Divider 4.2
0x1A2
0x1A3
0x1A4
to
0x1DF
VCO Divider and CLK Input
0x1E0
VCO divider
0x1E1
Input CLKs
0x1E2
to
0x22A
System
0x230
Power-down
and SYNC
0x231
Update All Registers
0x232
Update all
registers
Bypass
Divider 3.1
Blank
Bypass
Divider 4.1
Blank
Divider 3
nosync
Divider 4
nosync
High Cycles Divider 3.1
0x22
Phase Offset Divider 3.1
High Cycles Divider 3.2
Divider 3
Start High
force high
Divider 3.2
0x00
0x11
0x00
High Cycles Divider 4.1
Phase Offset Divider 4.1
High Cycles Divider 4.2
Divider 4
Start High
force high
Divider 4.2
Start High
Divider 3.1
Divider 3
DCCOFF
Start High
Divider 4.1
Divider 4
DCCOFF
0x00
0x22
0x00
0x11
0x00
0x00
Reserved (read-only)
Blank
Blank
Reserved
VCO divider
Powerdown
clock input
section
Blank
Reserved
Reserved
Powerdown
SYNC
Bypass
VCO divider
Powerdown
distribution
reference
Soft SYNC
Blank
Blank
Rev. A | Page 51 of 76
0x02
0x00
0x00
0x00
Update all
registers
(self-clearing)
0x00
AD9516-5
REGISTER MAP DESCRIPTIONS
Table 48 through Table 57 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal
address. A range of bits (for example, from Bit 5 through Bit 2) is indicated using a colon and brackets, as follows: [5:2].
Table 48. Serial Port Configuration
Reg.
Addr.
(Hex)
0x000
Bits
[7:4]
Name
Mirrored, Bits[3:0]
3
Long instruction
2
Soft reset
1
LSB first
0
SDO active
0x003
[7:0]
Part ID (read only)
0x004
0
Read back active registers
Description
Bits[7:4] should always mirror Bits[3:0], so that it does not matter whether the part is in
MSB or LSB first mode (see Bit 1, Register 0x000). The user should set the bits as follows:
Bit 7 = Bit 0.
Bit 6 = Bit 1.
Bit 5 = Bit 2.
Bit 4 = Bit 3.
Short/long instruction mode. This part uses long instruction mode only, so this bit should
always be set to 1b.
0: 8-bit instruction (short).
1: 16-bit instruction (long) (default).
Soft reset.
1: soft reset; restores default values to internal registers. Not self-clearing. Must be cleared
to 0b to complete reset operation.
MSB or LSB data orientation.
0: data-oriented MSB first; addressing decrements (default).
1: data-oriented LSB first; addressing increments.
Selects unidirectional or bidirectional data transfer mode.
0: SDIO pin used for write and read; SDO set to high impedance; bidirectional mode (default).
1: SDO used for read, SDIO used for write; unidirectional mode.
Uniquely identifies the dash version (-0 through -5) of the AD9516.
AD9516-0: 0x01.
AD9516-1: 0x41.
AD9516-2: 0x81.
AD9516-3: 0x43.
AD9516-4: 0xC3.
AD9516-5: 0xC1.
Selects register bank used for a readback.
0: reads back buffer registers (default).
1: reads back active registers.
Rev. A | Page 52 of 76
AD9516-5
Table 49. PLL
Reg.
Addr.
(Hex)
0x010
Bits
7
Name
PFD polarity
[6:4]
CP current
[3:2]
CP mode
[1:0]
PLL power-down
0x011
[7:0]
0x012
[5:0]
0x013
0x014
[5:0]
[7:0]
0x015
[4:0]
0x016
7
14-bit R divider,
Bits[7:0] (LSB)
14-bit R divider,
Bits[13:8] (MSB)
6-bit A counter
13-bit B counter,
Bits[7:0] (LSB)
13-bit B counter,
Bits[12:8] (MSB)
Set CP pin
to VCP/2
6
Reset R counter
5
Reset A and B
counters
4
Reset all counters
3
B counter bypass
Description
Sets the PFD polarity.
0: positive; higher control voltage produces higher frequency (default).
1: negative; higher control voltage produces lower frequency.
Charge pump current (with CPRSET = 5.1 kΩ).
6
5
4
ICP (mA)
0
0
0
0.6
0
0
1
1.2
0
1
0
1.8
0
1
1
2.4
1
0
0
3.0
1
0
1
3.6
1
1
0
4.2
1
1
1
4.8 (default)
Charge pump operating mode.
3
2
Charge Pump Mode
0
0
High impedance state
0
1
Force source current (pump up)
1
0
Force sink current (pump down)
1
1
Normal operation (default)
PLL operating mode.
1
0 Mode
0
0 Normal operation
0
1 Asynchronous power-down (default)
1
0 Normal operation
1
1 Synchronous power-down
R divider LSBs—lower eight bits (default = 0x01).
R divider MSBs—upper six bits (default = 0x00).
A counter (part of N divider) (default = 0x00).
B counter (part of N divider)—lower eight bits (default = 0x03).
B counter (part of N divider)—upper five bits (default = 0x00).
Sets the CP pin to one-half of the VCP supply voltage.
0: CP normal operation (default).
1: CP pin set to VCP/2.
Resets R counter (R divider). This bit is not self-clearing.
0: normal (default).
1: holds the R counter in reset.
Resets A and B counters (part of N divider).
0: normal (default). This bit is not self-clearing.
1: holds the A and B counters in reset.
Resets R, A, and B counters. This bit is not self-clearing.
0: normal (default).
1: holds the R, A, and B counters in reset.
B counter bypass. This is valid only when operating the prescaler in FD mode.
0: normal (default).
1: B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider.
Rev. A | Page 53 of 76
AD9516-5
Reg.
Addr.
(Hex)
0x017
Bits
[2:0]
[7:2]
Name
Prescaler P
STATUS pin
control
Description
Prescaler. DM = dual modulus, and FD = fixed divide.
2
1 0
Mode
Prescaler
0
0 0
FD
Divide-by-1
0
0 1
FD
Divide-by-2
0
1 0
DM
Divide-by-2 (2/3 mode)
0
1 1
DM
Divide-by-4 (4/5 mode)
1
0 0
DM
Divide-by-8 (8/9 mode)
1
0 1
DM
Divide-by-16 (16/17 mode)
1
1 0
DM
Divide-by-32 (22/23 mode) (default)
1
1 1
FD
Divide-by-3
Selects the STATUS pin signal.
Level or
Dynamic
Signal
7
6 5
4
3
2
Signal at STATUS Pin
0
0 0
0
0
0
LVL
Ground (dc) (default)
0
0 0
0
0
1
DYN
N divider output (after the delay)
0
0 0
0
1
0
DYN
R divider output (after the delay)
0
0 0
0
1
1
DYN
A divider output
0
0 0
1
0
0
DYN
Prescaler output
0
0 0
1
0
1
DYN
PFD up pulse
0
0 0
1
1
0
DYN
PFD down pulse
0
X X
X
X
X
LVL
Ground (dc); for all other cases of 0x0XXXX not specified
The selections that follow are the same as for REFMON:
1
0 0
0
0
0
LVL
Ground (dc)
1
0 0
0
0
1
DYN
REF1 clock (differential reference when in differential mode)
1
0 0
0
1
0
DYN
REF2 clock (not available in differential mode)
1
0 0
0
1
1
DYN
Selected reference to PLL (differential reference when in differential mode)
1
0 0
1
0
0
DYN
Unselected reference to PLL (not available in differential mode)
1
0 0
1
0
1
LVL
Status of selected reference (status of differential reference); active high
1
0 0
1
1
0
LVL
Status of unselected reference (not available in differential mode); active high
1
0 0
1
1
1
LVL
Status of REF1 frequency (active high)
1
0 1
0
0
0
LVL
Status of REF2 frequency (active high)
1
0 1
0
0
1
LVL
(Status of REF1 frequency) AND (status of REF2 frequency)
1
0 1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of CLK)
1
0 1
0
1
1
LVL
Status of CLK frequency (active high)
1
0 1
1
0
0
LVL
Selected reference (low = REF1, high = REF2)
1
0 1
1
0
1
LVL
Digital lock detect (DLD); active high
1
0 1
1
1
0
LVL
Holdover active (active high)
1
0 1
1
1
1
LVL
LD pin comparator output (active high)
1
1 0
0
0
0
LVL
VS (PLL supply)
1
1 0
0
0
1
DYN
REF1 clock (differential reference when in differential mode)
1
1 0
0
1
0
DYN
REF2 clock (not available in differential mode)
1
1
0
0
1
1
DYN
Selected reference to PLL (differential reference when in differential mode)
1
1
0
1
0
0
DYN
Unselected reference to PLL (not available when in differential mode)
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
LVL
LVL
LVL
LVL
LVL
Status of selected reference (status of differential reference); active low
Status of unselected reference (not available in differential mode); active low
Status of REF1 frequency (active low)
Status of REF2 frequency (active low)
(Status of REF1 frequency) AND (status of REF2 frequency)
1
1
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of CLK)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
LVL
LVL
LVL
LVL
LVL
Status of CLK Frequency (active low)
Selected reference (low = REF2, high = REF1)
Digital lock detect (DLD) (active low)
Holdover active (active low)
LD pin comparator output (active low)
Rev. A | Page 54 of 76
AD9516-5
Reg.
Addr.
(Hex)
0x018
0x019
Bits
[1:0]
Name
Antibacklash
pulse width
[6:5]
Lock detect
counter
4
Digital lock
detect window
3
Disable digital
lock detect
[7:6]
R, A, B counters
SYNC pin reset
[5:3]
[2:0]
R path delay
N path delay
Description
1
0 Antibacklash Pulse Width (ns)
0
0 2.9 (default)
0
1 1.3
1
0 6.0
1
1 2.9
Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked
condition.
6
5 PFD Cycles to Determine Lock
0
0
5 (default)
0
1
16
1
0
64
1
1
255
If the time difference of the rising edges at the inputs to the PFD is less than the lock detect window time, the digital
lock detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold.
0: high range (default).
1: low range.
Digital lock detect operation.
0: normal lock detect operation (default).
1: disables lock detect.
7
6 Action
0
0
Does nothing on SYNC (default)
0
1
Asynchronous reset
1
0
Synchronous reset
1
1
Does nothing on SYNC
R path delay (default = 0x0); see Table 2.
N path delay (default = 0x0); see Table 2.
Rev. A | Page 55 of 76
AD9516-5
Reg.
Addr.
(Hex)
0x01A
0x01B
Bits
6
Name
Reference
frequency
monitor
threshold
[5:0]
LD pin control
7
CLK frequency
monitor
6
REF2 (REFIN)
frequency
monitor
5
REF1 (REFIN)
frequency
monitor
Description
Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect the CLK
frequency monitor’s detection threshold (see Table 12: REF1, REF2, and CLK frequency status monitor parameter).
0: frequency valid if frequency is above the higher frequency threshold (default).
1: frequency valid if frequency is above the lower frequency threshold.
Selects the LD pin signal.
Level or
Dynamic
5
4 3 2 1 0 Signal
Signal at LD Pin
0
0
0 0 0 0
LVL
Digital lock detect (high = lock, low = unlock) (default)
0
0
0 0 0 1
DYN
P-channel, open-drain lock detect (analog lock detect)
0
0
0 0 1 0
DYN
N-channel, open-drain lock detect (analog lock detect)
0
0
0 0 1 1
HIZ
High-Z LD pin
0
0
0 1 0 0
CUR
Current source lock detect (110 μA when DLD is true)
0
X X X X X LVL
Ground (dc); for all other cases of 0x0XXXX not specified
The selections that follow are the same as for REFMON:
1
0
0 0 0 0
LVL
Ground (dc)
1
0
0 0 0 1
DYN
REF1 clock (differential reference when in differential mode)
1
0
0 0 1 0
DYN
REF2 clock (not available in differential mode)
1
0
0 0 1 1
DYN
Selected reference to PLL (differential reference when in differential mode)
1
0
0 1 0 0
DYN
Unselected reference to PLL (not available in differential mode)
1
0
0 1 0 1
LVL
Status of selected reference (status of differential reference); active high
1
0
0 1 1 0
LVL
Status of unselected reference (not available in differential mode); active high
1
0
0 1 1 1
LVL
Status of REF1 frequency (active high)
1
0
1 0 0 0
LVL
Status of REF2 frequency (active high)
1
0
1 0 0 1
LVL
(Status of REF1 frequency) AND (status of REF2 frequency)
1
0
1 0 1 0
LVL
(DLD) AND (status of selected reference) AND (status of CLK)
1
0
1 0 1 1
LVL
Status of CLK frequency (active high)
1
0
1 1 0 0
LVL
Selected reference (low = REF1, high = REF2)
1
0
1 1 0 1
LVL
Digital lock detect (DLD); active high
1
0
1 1 1 0
LVL
Holdover active (active high)
1
0
1 1 1 1
LVL
Not available; do not use
1
1
0 0 0 0
LVL
VS (PLL supply)
1
1
0 0 0 1
DYN
REF1 clock (differential reference when in differential mode)
1
1
0 0 1 0
DYN
REF2 clock (not available in differential mode)
1
1
0
0
1
1
DYN
1
1
0
1
0
0
DYN
Selected reference to PLL (differential reference when in differential mode)
Unselected reference to PLL (not available when in differential mode)
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
LVL
LVL
LVL
LVL
LVL
Status of selected reference (status of differential reference); active low
Status of unselected reference (not available in differential mode); active low
Status of REF1 frequency (active low)
Status of REF2 frequency (active low)
(Status of REF1 frequency) AND (status of REF2 frequency)
1
1
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of CLK)
1
1
1 0 1 1
LVL
Status of CLK frequency (active low)
1
1
1 1 0 0
LVL
Selected reference (low = REF2, high = REF1)
1
1
1 1 0 1
LVL
Digital lock detect (DLD); active low
1
1
1 1 1 0
LVL
Holdover active (active low)
1
1
1 1 1 1
LVL
Not available; do not use
Enables or disables CLK frequency monitor.
0: disables CLK frequency monitor (default).
1: enables CLK frequency monitor.
Enables or disables REF2 frequency monitor.
0: disables REF2 frequency monitor (default).
1: enables REF2 frequency monitor.
REF1 (REFIN) frequency monitor enable; this is for both REF1 (single-ended) and REFIN (differential) inputs (as selected
by differential reference mode).
0: disables REF1 (REFIN) frequency monitor (default).
1: enables REF1 (REFIN) frequency monitor.
Rev. A | Page 56 of 76
AD9516-5
Reg.
Addr.
(Hex)
0x01C
Bits
[4:0]
Name
REFMON pin
control
7
Disable
switchover
deglitch
6
Select REF2
5
Use REF_SEL pin
4
3
2
Reserved
Reserved
REF2
power-on
1
REF1
power-on
0
Differential
reference
Description
Selects the signal that is connected to the REFMON pin.
Level or
Dynamic
Signal
4
3
2
1
0
Signal at REFMON Pin
0
0
0
0
0
LVL
Ground (dc) (default)
0
0
0
0
1
DYN
REF1 clock (differential reference when in differential mode)
0
0
0
1
0
DYN
REF2 clock (not available in differential mode)
0
0
0
1
1
DYN
Selected reference to PLL (differential reference when in differential mode)
0
0
1
0
0
DYN
Unselected reference to PLL (not available in differential mode)
0
0
1
0
1
LVL
Status of selected reference (status of differential reference); active high
0
0
1
1
0
LVL
Status of unselected reference (not available in differential mode); active high
0
0
1
1
1
LVL
Status of REF1 frequency (active high)
0
1
0
0
0
LVL
Status of REF2 frequency (active high)
0
1
0
0
1
LVL
(Status of REF1 frequency) AND (status of REF2 frequency)
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of CLK)
0
1
0
1
1
LVL
Status of CLK frequency (active high)
0
1
1
0
0
LVL
Selected reference (low = REF1, high = REF2)
0
1
1
0
1
LVL
Digital lock detect (DLD); active low
0
1
1
1
0
LVL
Holdover active (active high)
0
1
1
1
1
LVL
LD pin comparator output (active high)
1
0
0
0
0
LVL
VS (PLL supply)
1
0
0
0
1
DYN
REF1 clock (differential reference when in differential mode)
1
0
0
1
0
DYN
REF2 clock (not available in differential mode)
1
0
0
1
1
DYN
Selected reference to PLL (differential reference when in differential mode)
1
0
1
0
0
DYN
Unselected reference to PLL (not available when in differential mode)
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
LVL
LVL
LVL
LVL
LVL
Status of selected reference (status of differential reference); active low
Status of unselected reference (not available in differential mode); active low
Status of REF1 frequency (active low)
Status of REF2 frequency (active low)
(Status of REF1 frequency) AND (status of REF2 frequency)
1
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of CLK)
1
1
0
1
1
LVL
Status of CLK frequency (active low)
1
1
1
0
0
LVL
Selected reference (low = REF2, high = REF1)
1
1
1
0
1
LVL
Digital lock detect (DLD); active low
1
1
1
1
0
LVL
Holdover active (active low)
1
1
1
1
1
LVL
LD pin comparator output (active low)
Disables or enables the switchover deglitch circuit.
0: enables switchover deglitch circuit (default).
1: disables switchover deglitch circuit.
If Register 0x01C[5] = 0, selects reference for PLL.
0: select REF1 (default).
1: select REF2.
If Register 0x01C[4] = 0 (manual), sets method of PLL reference selection.
0: uses Register 0x01C[6] (default).
1: uses REF_SEL pin.
0: default.
0: default.
This bit turns the REF2 power on.
0: REF2 power off (default).
1: REF2 power on.
This bit turns the REF1 power on.
0: REF1 power off (default).
1: REF1 power on.
Selects the PLL reference mode, differential or single-ended. Single-ended must be selected for the automatic
reference switchover or REF1 and REF2 to work.
0: single-ended reference mode (default).
1: differential reference mode.
Rev. A | Page 57 of 76
AD9516-5
Reg.
Addr.
(Hex)
0x01D
0x01F
Bits
4
Name
PLL status
register disable
3
LD pin
comparator
enable
2
Holdover enable
1
External
holdover control
0
Holdover enable
5
Holdover active
4
REF2 selected
3
CLK frequency >
threshold
2
REF2
frequency >
threshold
1
REF1
frequency >
threshold
0
Digital
lock detect
Description
Disables the PLL status register readback.
0: PLL status register enable (default).
1: PLL status register disable.
Enables the LD pin voltage comparator. This function is used with the LD pin current source lock detect mode. When in
the internal (automatic) holdover mode, this function enables the use of the voltage on the LD pin to determine if the
PLL was previously in a locked state (see Figure 41). Otherwise, this function can be used with the REFMON and STATUS
pins to monitor the voltage on the LD pin.
0: disables LD pin comparator; internal/automatic holdover controller treats this pin as true/high (default).
1: enables LD pin comparator.
Along with Register 0x01D[0], enables the holdover function.
0: holdover disabled (default).
1: holdover enabled.
Enables the external hold control through the SYNC pin. (This disables the internal holdover mode.)
0: automatic holdover mode—holdover controlled by automatic holdover circuit (default).
1: external holdover mode—holdover controlled by SYNC pin.
Along with Register 0x01D[2], enables the holdover function.
0: holdover disabled (default).
1: holdover enabled.
Read-only register. Indicates if the part is in the holdover state (see Figure 41). This is not the same as holdover enabled.
0: not in holdover.
1: holdover state active.
Read-only register. Indicates which PLL reference is selected as the input to the PLL.
0: REF1 selected (or differential reference if in differential mode).
1: REF2 selected.
Read-only register. Indicates if the CLK frequency is greater than the threshold (see Table 12: REF1, REF2, and CLK
frequency status monitor).
0: CLK frequency is less than the threshold.
1: CLK frequency is greater than the threshold.
Read-only register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by
Register 0x01A[6].
0: REF2 frequency is less than threshold frequency.
1: REF2 frequency is greater than threshold frequency.
Read-only register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by
Register 0x01A[6].
0: REF1 frequency is less than threshold frequency.
1: REF1 frequency is greater than threshold frequency.
Read-only register. Digital lock detect.
0: PLL is not locked.
1: PLL is locked.
Rev. A | Page 58 of 76
AD9516-5
Table 50. Fine Delay Adjust—OUT6 to OUT9
Reg.
Addr.
(Hex)
0x0A0
Bits
0
Name
OUT6 delay
bypass
0x0A1
[5:3]
OUT6 ramp
capacitors
[2:0]
OUT6 ramp
current
0x0A2
[5:0]
0x0A3
0
OUT6 delay
fraction
OUT7 delay
bypass
0x0A4
[5:3]
OUT7 ramp
capacitors
Description
Bypasses or uses the delay function.
0: uses the delay function.
1: bypasses the delay function (default).
Selects the number of ramp capacitors used by the delay function. The combination of the number of
capacitors and the ramp current sets the full-scale delay.
5 4 3 Number of Capacitors
0 0 0 4 (default)
0 0 1 3
0 1 0 3
0 1 1 2
1 0 0 3
1 0 1 2
1 1 0 2
1 1 1 1
Ramp current for the delay function. The combination of the number of capacitors and the ramp current
sets the full-scale delay.
2 1 0 Current (μA)
0 0 0 200 (default)
0 0 1 400
0 1 0 600
0 1 1 800
1 0 0 1000
1 0 1 1200
1 1 0 1400
1 1 1 1600
Selects the fraction of the full-scale delay desired (6-bit binary). A setting of 000000b gives zero delay.
Only delay values of up to 47 decimals (101111b; 0x02F) are supported (default: 0x00).
Bypasses or uses the delay function.
0: uses the delay function.
1: bypasses the delay function (default).
Selects the number of ramp capacitors used by the delay function. The combination of the number of the
capacitors and the ramp current sets the full-scale delay.
5 4 3 Number of Capacitors
0 0 0 4 (default)
0 0 1 3
0 1 0 3
0 1 1 2
1 0 0 3
1 0 1 2
1 1 0 2
1 1 1 1
Rev. A | Page 59 of 76
AD9516-5
Reg.
Addr.
(Hex)
0x0A4
Bits
[2:0]
Name
OUT7 ramp
current
0x0A5
[5:0]
0x0A6
0
OUT7 delay
fraction
OUT8 delay
bypass
0x0A7
[5:3]
OUT8 ramp
capacitors
[2:0]
OUT8 ramp
current
0x0A8
[5:0]
0x0A9
[0]
OUT8 delay
fraction
OUT9 delay
bypass
Description
Ramp current for the delay function. The combination of the number of capacitors and the ramp
current sets the full-scale delay.
2 1 0 Current (μA)
0 0 0 200 (default)
0 0 1 400
0 1 0 600
0 1 1 800
1 0 0 1000
1 0 1 1200
1 1 0 1400
1 1 1 1600
Selects the fraction of the full-scale delay desired (6-bit binary). A setting of 000000b gives zero delay.
Only delay values of up to 47 decimals (101111b; 0x02F) are supported (default: 0x00).
Bypasses or uses the delay function.
0: uses the delay function.
1: bypasses the delay function (default).
Selects the number of ramp capacitors used by the delay function. The combination of the number of
capacitors and the ramp current sets the full-scale delay.
5 4 3 Number of Capacitors
0 0 0 4 (default)
0 0 1 3
0 1 0 3
0 1 1 2
1 0 0 3
1 0 1 2
1 1 0 2
1 1 1 1
Ramp current for the delay function. The combination of the number of capacitors and the ramp
current sets the full-scale delay.
2 1 0 Current (μA)
0 0 0 200 (default)
0 0 1 400
0 1 0 600
0 1 1 800
1 0 0 1000
1 0 1 1200
1 1 0 1400
1 1 1 1600
Selects the fraction of the full-scale delay desired (6-bit binary). A setting of 000000b gives zero delay.
Only delay values of up to 47 decimals (101111b; 0x02F) are supported (default: 0x00).
Bypasses or uses the delay function.
0: uses the delay function.
1: bypasses the delay function (default).
Rev. A | Page 60 of 76
AD9516-5
Reg.
Addr.
(Hex)
0x0AA
0x0AB
Bits
[5:3]
Name
OUT9 ramp
capacitors
[2:0]
OUT9 ramp
current
[5:0]
OUT9 delay
fraction
Description
Selects the number of ramp capacitors used by the delay function. The combination of the number of
capacitors and the ramp current sets the full-scale delay.
5 4 3 Number of Capacitors
0 0 0 4 (default)
0 0 1 3
0 1 0 3
0 1 1 2
1 0 0 3
1 0 1 2
1 1 0 2
1 1 1 1
Ramp current for the delay function. The combination of the number of capacitors and the ramp
current sets the full-scale delay.
2 1 0 Current Value (μA)
0 0 0 200 (default)
0 0 1 400
0 1 0 600
0 1 1 800
1 0 0 1000
1 0 1 1200
1 1 0 1400
1 1 1 1600
Selects the fraction of the full-scale delay desired (6-bit binary). A setting of 000000b gives zero delay.
Only delay values of up to 47 decimals (101111b; 0x02F) are supported (default: 0x00).
Table 51. LVPECL Outputs
Reg.
Addr.
(Hex)
0x0F0
Bits
4
Name
OUT0 invert
[3:2]
OUT0 LVPECL
differential
voltage
[1:0]
OUT0
power-down
Description
Sets the output polarity.
0: noninverting (default).
1: inverting.
Sets the LVPECL output differential voltage (VOD).
3 2 VOD (mV)
0 0 400
0 1 600
1 0 780 (default)
1 1 960
LVPECL power-down modes.
1 0 Mode
0 0 Normal operation (default)
0 1 Partial power-down, reference on; use only if there are no external load resistors
1 0 Partial power-down, reference on; safe LVPECL power-down
1 1 Total power-down, reference off; use only if there are no external load resistors
Rev. A | Page 61 of 76
Output
On
Off
Off
Off
AD9516-5
Reg.
Addr.
(Hex)
0x0F1
0x0F2
0x0F3
Bits
4
Name
OUT1 invert
[3:2]
OUT1 LVPECL
differential
voltage
[1:0]
OUT1
power-down
4
OUT2 invert
[3:2]
OUT2 LVPECL
differential
voltage
[1:0]
OUT2
power-down
4
OUT3 invert
[3:2]
OUT3 LVPECL
differential
voltage
[1:0]
OUT3
power-down
Description
Sets the output polarity.
0: noninverting (default).
1: inverting.
Sets the LVPECL output differential voltage (VOD).
3 2 VOD (mV)
0 0 400
0 1 600
1 0 780 (default)
1 1 960
LVPECL power-down modes.
1 0 Mode
0 0 Normal operation
0 1 Partial power-down, reference on; use only if there are no external load resistors
1 0 Partial power-down, reference on; safe LVPECL power-down (default)
1 1 Total power-down, reference off; use only if there are no external load resistors
Sets the output polarity.
0: noninverting (default).
1: inverting.
Sets the LVPECL output differential voltage (VOD).
3 2 VOD (mV)
0 0 400
0 1 600
1 0 780 (default)
1 1 960
LVPECL power-down modes.
1 0 Mode
0 0 Normal operation (default)
0 1 Partial power-down, reference on; use only if there are no external load resistors
1 0 Partial power-down, reference on, safe LVPECL power-down
1 1 Total power-down, reference off; use only if there are no external load resistors
Sets the output polarity.
0: noninverting (default).
1: inverting.
Sets the LVPECL output differential voltage (VOD).
3 2 VOD (mV)
0 0 400
0 1 600
1 0 780 (default)
1 1 960
LVPECL power-down modes.
1 0 Mode
0 0 Normal operation
0 1 Partial power-down, reference on; use only if there are no external load resistors
1 0 Partial power-down, reference on, safe LVPECL power-down (default)
1 1 Total power-down, reference off; use only if there are no external load resistors
Rev. A | Page 62 of 76
Output
On
Off
Off
Off
Output
On
Off
Off
Off
Output
On
Off
Off
Off
AD9516-5
Reg.
Addr.
(Hex)
0x0F4
0x0F5
Bits
4
Name
OUT4 invert
[3:2]
OUT4 LVPECL
differential
voltage
[1:0]
OUT4
power-down
4
OUT5 invert
[3:2]
OUT5 LVPECL
differential
voltage
[1:0]
OUT5
power-down
Description
Sets the output polarity.
0: noninverting (default).
1: inverting.
Sets the LVPECL output differential voltage (VOD).
3 2 VOD (mV)
0 0 400
0 1 600
1 0 780 (default)
1 1 960
LVPECL power-down modes.
1 0 Mode
0 0 Normal operation
0 1 Partial power-down, reference on; use only if there are no external load resistors
1 0 Partial power-down, reference on, safe LVPECL power-down
1 1 Total power-down, reference off; use only if there are no external load resistors
Sets the output polarity.
0: noninverting (default).
1: inverting.
Sets the LVPECL output differential voltage (VOD).
3 2 VOD (mV)
0 0 400
0 1 600
1 0 780 (default)
1 1 960
LVPECL power-down modes.
1 0 Mode
0 0 Normal operation
0 1 Partial power-down, reference on; use only if there are no external load resistors
1 0 Partial power-down, reference on, safe LVPECL power-down (default)
1 1 Total power-down, reference off; use only if there are no external load resistors
Rev. A | Page 63 of 76
Output
On
Off
Off
Off
Output
On
Off
Off
Off
AD9516-5
Table 52. LVDS/CMOS Outputs
Reg.
Addr.
(Hex)
0x140
0x141
Bits
[7:5]
Name
OUT6 output polarity
4
OUT6 CMOS B
3
OUT6 select LVDS/CMOS
[2:1]
OUT6 LVDS output current
0
OUT6 power-down
[7:5]
OUT7 output polarity
4
OUT7 CMOS B
3
OUT7 select LVDS/CMOS
[2:1]
OUT7 LVDS output current
Description
In CMOS mode, Bits[7:5] select the output polarity of each CMOS output.
In LVDS mode, only Bit 5 determines LVDS polarity.
7 6 5
OUT6A (CMOS)
OUT6B (CMOS)
OUT6 (LVDS)
0
0
0
Noninverting
Inverting
Noninverting
0
1
0
Noninverting
Noninverting
Noninverting (default)
1
0
0
Inverting
Inverting
Noninverting
1
1
0
Inverting
Noninverting
Noninverting
0
0
1
Inverting
Noninverting
Inverting
0
1
1
Inverting
Inverting
Inverting
1
0
1
Noninverting
Noninverting
Inverting
1
1
1
Noninverting
Inverting
Inverting
In CMOS mode, turns on/off the CMOS B output. This has no effect in LVDS mode.
0: turns off the CMOS B output (default).
1: turns on the CMOS B output.
Selects LVDS or CMOS logic levels.
0: LVDS (default).
1: CMOS.
Sets output current level in LVDS mode. This has no effect in CMOS mode.
2
1 Current (mA)
Recommended Termination (Ω)
0
0
1.75
100
0
1
3.5
100 (default)
1
0
5.25
50
1
1
7
50
Power-down output (LVDS/CMOS).
0: powers on (default).
1: powers off.
In CMOS mode, Bits[7:5] select the output polarity of each CMOS output.
In LVDS mode, only Bit 5 determines LVDS polarity.
7 6 5
OUT7A (CMOS)
OUT7B (CMOS)
OUT7 (LVDS)
0
0
0
Noninverting
Inverting
Noninverting
0
1
0
Noninverting
Noninverting
Noninverting (default)
1
0
0
Inverting
Inverting
Noninverting
1
1
0
Inverting
Noninverting
Noninverting
0
0
1
Inverting
Noninverting
Inverting
0
1
1
Inverting
Inverting
Inverting
1
0
1
Noninverting
Noninverting
Inverting
1
1
1
Noninverting
Inverting
Inverting
In CMOS mode, turns on/off the CMOS B output. This has no effect in LVDS mode.
0: turns off the CMOS B output (default).
1: turns on the CMOS B output.
Selects LVDS or CMOS logic levels.
0: LVDS (default).
1: CMOS.
Sets output current level in LVDS mode. This has no effect in CMOS mode.
2
1 Current (mA)
Recommended Termination (Ω)
0
0
1.75
100
0
1
3.5
100 (default)
1
0
5.25
50
1
1
7
50
Rev. A | Page 64 of 76
AD9516-5
Reg.
Addr.
(Hex)
0x142
0x143
Bits
0
Name
OUT7 power-down
[7:5]
OUT8 output polarity
4
OUT8 CMOS B
3
OUT8 select LVDS/CMOS
[2:1]
OUT8 LVDS output current
0
OUT8 power-down
[7:5]
OUT9 output polarity
4
OUT9 CMOS B
3
OUT9 select LVDS/CMOS
Description
Power-down output (LVDS/CMOS).
0: powers on.
1: powers off (default).
In CMOS mode, Bits[7:5] select the output polarity of each CMOS output.
In LVDS mode, only Bit 5 determines LVDS polarity.
7 6
5
OUT8A (CMOS)
OUT8B (CMOS)
OUT8 (LVDS)
0
0
0
Noninverting
Inverting
Noninverting
0
1
0
Noninverting
Noninverting
Noninverting (default)
1
0
0
Inverting
Inverting
Noninverting
1
1
0
Inverting
Noninverting
Noninverting
0
0
1
Inverting
Noninverting
Inverting
0
1
1
Inverting
Inverting
Inverting
1
0
1
Noninverting
Noninverting
Inverting
1
1
1
Noninverting
Inverting
Inverting
In CMOS mode, turns on/off the CMOS B output. There is no effect in LVDS mode.
0: turns off the CMOS B output (default).
1: turns on the CMOS B output.
Selects LVDS or CMOS logic levels.
0: LVDS (default).
1: CMOS.
Sets output current level in LVDS mode. This has no effect in CMOS mode.
2
1
Current (mA)
Recommended Termination (Ω)
0
0
1.75
100
0
1
3.5
100 (default)
1
0
5.25
50
1
1
7
50
Power-down output (LVDS/CMOS).
0: powers on (default).
1: powers off.
In CMOS mode, Bits[7:5] select the output polarity of each CMOS output.
In LVDS mode, only Bit 5 determines LVDS polarity.
7 6
5
OUT9A (CMOS)
OUT9B (CMOS)
OUT9 (LVDS)
0
0
0
Noninverting
Inverting
Noninverting
0
1
0
Noninverting
Noninverting
Noninverting (default)
1
0
0
Inverting
Inverting
Noninverting
1
1
0
Inverting
Noninverting
Noninverting
0
0
1
Inverting
Noninverting
Inverting
0
1
1
Inverting
Inverting
Inverting
1
0
1
Noninverting
Noninverting
Inverting
1
1
1
Noninverting
Inverting
Inverting
In CMOS mode, turns on/off the CMOS B output. This has no effect in LVDS mode.
0: turns off the CMOS B output (default).
1: turns on the CMOS B output.
Selects LVDS or CMOS logic levels.
0: LVDS (default).
1: CMOS.
Rev. A | Page 65 of 76
AD9516-5
Reg.
Addr.
(Hex)
Bits
[2:1]
Name
OUT9 LVDS output current
[0]
OUT9 power-down
Description
Sets output current level in LVDS mode. This has no effect in CMOS mode.
2 1 Current (mA)
Recommended Termination (Ω)
0
0
1.75
100
0
1
3.5
100 (default)
1
0
5.25
50
1
1
7
50
Power-down output (LVDS/CMOS).
0: powers on.
1: powers off (default).
Table 53. LVPECL Channel Dividers
Reg.
Addr.
(Hex)
0x190
0x191
0x192
0x193
0x194
Bits
[7:4]
Name
Divider 0 low cycles
[3:0]
Divider 0 high cycles
7
Divider 0 bypass
6
Divider 0 nosync
5
Divider 0 force high
4
Divider 0 start high
[3:0]
1
Divider 0 phase offset
Divider 0 direct to output
0
Divider 0 DCCOFF
[7:4]
Divider 1 low cycles
[3:0]
Divider 1 high cycles
7
Divider 1 bypass
6
Divider 1 nosync
Description
Number of clock cycles (minus 1) of the Divider 0 input during which the Divider 0 output
stays low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0).
Number of clock cycles (minus 1) of the Divider 0 input during which the Divider 0 output
stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0).
Bypasses and powers down the divider; routes input to the divider output.
0: uses the divider.
1: bypasses the divider (default).
No sync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
Forces divider output to high. This operation requires that the Divider 0 nosync bit (Bit 6) also
be set. This bit has no effect if the Divider 0 bypass bit (Bit 7) is set.
0: normal operation (default).
1: divider output forced to the setting of the Divider 0 start high bit.
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
Phase offset (default: 0x0).
Connects OUT0 and OUT1 to Divider 0 or directly to CLK input.
0: OUT0 and OUT1 are connected to Divider 0 (default).
1: If Register 0x1E1[0] = 0b, the CLK is routed directly to OUT0 and OUT1.
If Register 0x1E1[0] = 1b, there is no effect.
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
Number of clock cycles (minus 1) of the Divider 1 input during which the Divider 1 output stays
low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0xB).
Number of clock cycles (minus 1) of the Divider 1 input during which the Divider 1 output stays
high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0xB).
Bypasses and powers down the divider; routes input to divider output.
0: uses divider (default).
1: bypasses divider.
No sync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
Rev. A | Page 66 of 76
AD9516-5
Reg.
Addr.
(Hex)
0x195
0x196
0x197
0x198
Bits
5
Name
Divider 1 force high
4
Divider 1 start high
[3:0]
1
Divider 1 phase offset
Divider 1 direct to output
0
Divider 1 DCCOFF
[7:4]
Divider 2 low cycles
[3:0]
Divider 2 high cycles
7
Divider 2 bypass
6
Divider 2 nosync
5
Divider 2 force high
4
Divider 2 start high
[3:0]
1
Divider 2 phase offset
Divider 2 direct to output
0
Divider 2 DCCOFF
Description
Forces divider output to high. This operation requires that the Divider 1 nosync bit (Bit 6) also
be set. This bit has no effect if the Divider 1 bypass bit (Bit 7) is set.
0: normal operation (default).
1: divider output forced to the setting of the Divider 1 start high bit.
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
Phase offset (default: 0x0).
Connects OUT2 and OUT3 to Divider 1 or directly to CLK input.
0: OUT2 and OUT3 are connected to Divider 1 (default).
1: If Register 0x1E1[0] = 0b, the CLK is routed directly to OUT2 and OUT3.
If Register 0x1E1[0] = 1b, this has no effect.
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
Number of clock cycles (minus 1) of the Divider 2 input during which the Divider 2 output stays
low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0).
Number of clock cycles (minus 1) of the Divider 2 input during which the Divider 2 output stays
high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0).
Bypasses and powers down the divider; route input to divider output.
0: uses divider (default).
1: bypasses divider.
No sync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
Forces divider output to high. This operation requires that the Divider 2 nosync bit (Bit 6) also
be set. This bit has no effect if the Divider 2 bypass bit (Bit 7) is set.
0: normal operation (default).
1: divider output forced to the setting of the Divider 2 start high bit.
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
Phase offset (default: 0x0).
Connects OUT4 and OUT5 to Divider 2 or directly to CLK input.
0: OUT4 and OUT5 are connected to Divider 2 (default).
1: if 0x1E1[0] = 0b, the CLK is routed directly to OUT4 and OUT5.
If 0x1E1[0] = 1b, there is no effect.
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
Rev. A | Page 67 of 76
AD9516-5
Table 54. LVDS/CMOS Channel Dividers
Reg.
Addr.
(Hex)
0x199
Bits
[7:4]
Name
Low Cycles Divider 3.1
[3:0]
High Cycles Divider 3.1
[7:4]
[3:0]
[7:4]
Phase Offset Divider 3.2
Phase Offset Divider 3.1
Low Cycles Divider 3.2
[3:0]
High Cycles Divider 3.2
5
Bypass Divider 3.2
4
Bypass Divider 3.1
3
Divider 3 nosync
2
Divider 3 force high
1
Start High Divider 3.2
0
Start High Divider 3.1
0x19D
0
Divider 3 DCCOFF
0x19E
[7:4]
Low Cycles Divider 4.1
[3:0]
High Cycles Divider 4.1
[7:4]
[3:0]
[7:4]
Phase Offset Divider 4.2
Phase Offset Divider 4.1
Low Cycles Divider 4.2
[3:0]
High Cycles Divider 4.2
5
Bypass Divider 4.2
4
Bypass Divider 4.1
3
Divider 4 nosync
0x19A
0x19B
0x19C
0x19F
0x1A0
0x1A1
Description
Number of clock cycles (minus 1) of the Divider 3.1 input during which the Divider 3.1 output
stays low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x2).
Number of clock cycles (minus 1) of the Divider 3.1 input during which the Divider 3.1 output
stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x2).
Refers to LVDS/CMOS channel divider function description (default: 0x0).
Refers to LVDS/CMOS channel divider function description (default: 0x0).
Number of clock cycles (minus 1) of the Divider 3.2 input during which the Divider 3.2 output
stays low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x1).
Number of clock cycles (minus 1) of the Divider 3.2 input during which the Divider 3.2 output
stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x1).
Bypasses (and powers down) 3.2 divider logic, routes clock to 3.2 output.
0: does not bypass (default).
1: bypasses.
Bypasses (and powers down) 3.1 divider logic, routes clock to 3.1 output.
0: does not bypass (default).
1: bypasses.
No sync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
Forces Divider 3 output high. Requires that the Divider 3 nosync bit (Bit 3) also be set.
0: forces low (default).
1: forces high.
Divider 3.2 starts high/low.
0: starts low (default).
1: starts high.
Divider 3.1 starts high/low.
0: starts low (default).
1: starts high.
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
Number of clock cycles (minus 1) of the Divider 4.1 input during which the Divider 4.1 output
stays low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x2).
Number of clock cycles (minus 1) of the Divider 4.1 input during which the Divider 4.1 output
stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x2).
Refers to LVDSCMOS channel divider function description (default: 0x0).
Refers to LVDSCMOS channel divider function description (default: 0x0).
Number of clock cycles (minus 1) of the Divider 4.2 input during which the Divider 4.2 output
stays low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x1).
Number of clock cycles (minus 1) of the Divider 4.2 input during which the Divider 4.2 output
stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x1).
Bypasses (and powers down) 4.2 divider logic, routes clock to 4.2 output.
0: does not bypass (default).
1: bypasses.
Bypasses (and powers down) 4.1 divider logic, routes clock to 4.1 output.
0: does not bypass (default).
1: bypasses.
No sync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
Rev. A | Page 68 of 76
AD9516-5
Reg.
Addr.
(Hex)
0x1A2
Bits
2
Name
Divider 4 force high
1
Start High Divider 4.2
0
Start High Divider 4.1
0
Divider 4 DCCOFF
Description
Forces Divider 4 output high. Requires that the Divider 4 nosync bit (Bit 3) also be set.
0: forces low (default).
1: forces high.
Divider 4.2 starts high/low.
0: starts low (default).
1: starts high.
Divider 4.1 starts high/low.
0: starts low (default).
1: starts high.
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
Table 55. VCO Divider and CLK Input
Reg.
Addr.
(Hex)
0x1E0
Bits
[2:0]
Name
VCO divider
0x1E1
4
Power-down clock input
section
0
Bypass VCO divider
Description
2
1
0
Divide
0
0
0
2
0
0
1
3
0
1
0
4 (default)
0
1
1
5
1
0
0
6
1
0
1
Output static
1
1
0
Output static
1
1
1
Output static
Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree).
0: normal operation (default).
1: powers down.
Bypasses or uses the VCO divider.
0: uses VCO divider (default).
1: bypasses VCO divider.
Table 56. System
Reg.
Addr.
(Hex)
230
Bits
2
Name
Power-down SYNC
1
Power-down distribution
reference
0
Soft SYNC
Description
Powers down the sync function.
0: normal operation of the sync function (default).
1: powers down the SYNC circuitry.
Powers down the reference for distribution section.
0: normal operation of the reference for the distribution section (default).
1: powers down the reference for the distribution section.
The soft SYNC bit works the same as the SYNC pin, except that the polarity of the bit is
reversed; that is, a high level forces selected channels into a predetermined static state, and a 1to-0 transition triggers a SYNC.
0: same as SYNC high (default).
1: same as SYNC low.
Rev. A | Page 69 of 76
AD9516-5
Table 57. Update All Registers
Reg.
Addr.
(Hex)
0x232
Bits
0
Name
Update all registers
Description
This bit must be set to 1 to transfer the contents of the buffer registers into the active registers,
which happens on the next SCLK rising edge. This bit is self-clearing; that is, it does not have to
be set back to 0.
1: updates all active registers to the contents of the buffer registers (self-clearing).
Rev. A | Page 70 of 76
AD9516-5
APPLICATIONS INFORMATION
Within the AD9516 family, lower VCO frequencies generally
result in slightly lower jitter. The difference in integrated jitter
(from 12 kHz to 20 MHz offset) for the same output frequency is
usually less than 150 fs over the entire VCO frequency range
(1.45 GHz to 2.95 GHz) of the AD9516 family. If the desired
frequency plan can be achieved with a version of the AD9516
that has a lower VCO frequency, choosing the lower frequency
part results in the lowest phase noise and the lowest jitter. However,
choosing a higher VCO frequency may result in more flexibility
in frequency planning.
Choosing a nominal charge pump current in the middle of the
allowable range as a starting point allows the designer to increase or
decrease the charge pump current and, thus, allows the designer
to fine-tune the PLL loop bandwidth in either direction.
ADIsimCLK is a powerful PLL modeling tool that can be
downloaded from www.analog.com. It is a very accurate tool for
determining the optimal loop filter for a given application.
USING THE AD9516 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Any high speed ADC is extremely sensitive to the quality of its
sampling clock. An ADC can be thought of as a sampling mixer,
and any noise, distortion, or timing jitter on the clock is combined
with the desired signal at the analog-to-digital output. Clock
integrity requirements scale with the analog input frequency
and resolution, with higher analog input frequency applications
at ≥14-bit resolution being the most stringent. The theoretical
SNR of an ADC is limited by the ADC resolution and the jitter
on the sampling clock.
⎞
⎟⎟
⎠
where:
fA is the highest analog frequency being digitized.
tJ is the rms jitter on the sampling clock.
Figure 58 shows the required sampling clock jitter as a function
of the analog frequency and effective number of bits (ENOB).
110
1
SNR = 20log 2πf t
A J
100
18
16
90
80
tJ =
100
fS
200
fS
14
S
12
400
f
70
1ps
60
2ps
10
10p
s
8
50
40
ENOB
The AD9516 has the following four frequency dividers: the
reference (or R) divider, the feedback (or N) divider, the VCO
divider, and the channel divider. When trying to achieve a
particularly difficult frequency divide ratio requiring a large
amount of frequency division, some of the frequency division
can be done by either the VCO divider or the channel divider,
thus allowing a higher phase detector frequency and more
flexibility in choosing the loop bandwidth.
⎛
1
SNR(dB) = 20 × log⎜⎜
⎝ 2π × f A × t J
6
30
10
100
fA (MHz)
1k
07972-044
The AD9516 is a highly flexible PLL. When choosing the PLL
settings and version of the AD9516, keep in mind the following
guidelines.
Considering an ideal ADC of infinite resolution, where the step
size and quantization error can be ignored, the available SNR
can be expressed approximately by
SNR (dB)
FREQUENCY PLANNING USING THE AD9516
Figure 58. SNR and ENOB vs. Analog Input Frequency
See the AN-756 Application Note, Sampled Systems and the Effects
of Clock Phase Noise and Jitter; and the AN-501 Application Note,
Aperture Uncertainty and ADC System Performance, at
www.analog.com.
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. (Distributing a single-ended clock on a noisy PCB
may result in coupled noise on the sample clock. Differential
distribution has inherent common-mode rejection that can
provide superior clock performance in a noisy environment.)
The AD9516 features both LVPECL and LVDS outputs that
provide differential clock outputs, which enable clock solutions that
maximize converter SNR performance. The input requirements of
the ADC (differential or single-ended, logic level, and termination)
should be considered when selecting the best clocking/converter
solution.
Rev. A | Page 71 of 76
AD9516-5
LVPECL CLOCK DISTRIBUTION
The LVPECL outputs of the AD9516 provide the lowest jitter clock
signals that are available from the AD9516. The LVPECL outputs
(because they are open emitter) require a dc termination to bias
the output transistors. The simplified equivalent circuit in
Figure 47 shows the LVPECL output stage.
In most applications, an LVPECL far-end Thevenin termination
(see Figure 59) or Y-termination (see Figure 60) is recommended.
In each case, the VS of the receiving buffer should match the
VS_LVPECL. If it does not match, ac coupling is recommended (see
Figure 61).
The resistor network is designed to match the transmission line
impedance (50 Ω) and the switching threshold (VS − 1.3 V).
VS_DRV
VS_LVPECL
LVPECL
50Ω
127Ω
127Ω
SINGLE-ENDED
(NOT COUPLED)
VS
LVPECL
07972-045
LVDS CLOCK DISTRIBUTION
The AD9516 provides four clock outputs (OUT6 to OUT9) that
are selectable as either CMOS or LVDS level outputs. LVDS is a
differential output option that uses a current mode output stage.
The nominal current is 3.5 mA, which yields a 350 mV output
swing across a 100 Ω resistor. An output current of 7 mA is also
available in cases where a larger output swing is required. The
LVDS output meets or exceeds all ANSI/TIA/EIA-644
specifications.
Figure 59. DC-Coupled 3.3 V LVPECL Far-End Thevenin Termination
VS = 3.3V
Z0 = 50Ω
50Ω
LVPECL
50Ω
50Ω
LVPECL
07972-147
VS_LVPECL
Z0 = 50Ω
Thevenin-equivalent termination uses a resistor network to provide
50 Ω termination to a dc voltage that is below VOL of the LVPECL
driver. In this case, VS_LVPECL on the AD9516 should equal VS of
the receiving buffer. Although the resistor combination shown
in Figure 60 results in a dc bias point of VS_LVPECL − 2 V, the actual
common-mode voltage is VS_LVPECL − 1.3 V because additional
current flows from the AD9516 LVPECL driver through the pulldown resistor.
The circuit is identical when VS_LVPECL = 2.5 V, except that the
pull-down resistor is 62.5 Ω and the pull-up resistor is 250 Ω.
50Ω
83Ω
LVPECL Y-termination is an elegant termination scheme that
uses the fewest components and offers both odd- and even-mode
impedance matching. Even-mode impedance matching is an
important consideration for closely coupled transmission lines
at high frequencies. Its main drawback is that it offers limited
flexibility for varying the drive strength of the emitter-follower
LVPECL driver. This can be an important consideration when
driving long trace lengths but is usually not an issue. In the case
shown in Figure 60, where VS_LVPECL = 2.5 V, the 50 Ω termination
resistor connected to ground should be changed to 19 Ω.
A recommended termination circuit for the LVDS outputs is
shown in Figure 62.
Figure 60. DC-Coupled 3.3 V LVPECL Y-Termination
VS
VS_LVPECL
0.1nF
100Ω DIFFERENTIAL
100Ω
(COUPLED)
0.1nF TRANSMISSION LINE
100Ω
100Ω
DIFFERENTIAL (COUPLED)
LVDS
07972-047
LVDS
LVPECL
VS
VS
LVPECL
200Ω
07972-046
Figure 62. LVDS Output Termination
200Ω
See the AN-586 Application Note, LVDS Data Outputs for HighSpeed Analog-to-Digital Converters for more information on LVDS.
Figure 61. AC-Coupled LVPECL with Parallel Transmission Line
Rev. A | Page 72 of 76
AD9516-5
Whenever single-ended CMOS clocking is used, some general
guidelines should be followed.
Point-to-point nets should be designed such that a driver has
only one receiver on the net, if possible. This allows for simple
termination schemes and minimizes ringing due to possible
mismatched impedances on the net. Series termination at the
source is generally required to provide transmission line matching
and/or to reduce current transients at the driver. The value of
the resistor is dependent on the board design and timing
requirements (typically 10 Ω to 100 Ω is used). CMOS outputs
are also limited in terms of the capacitive load or trace length
that they can drive. Typically, trace lengths less than 3 inches
are recommended to preserve signal rise/fall times and preserve
signal integrity.
10Ω
60.4Ω
(1.0 INCH)
CMOS
MICROSTRIP
Figure 63. Series Termination of CMOS Output
Termination at the far end of the PCB trace is a second option.
The CMOS outputs of the AD9516 do not supply enough current
to provide a full voltage swing with a low impedance resistive, farend termination, as shown in Figure 64. The far-end termination
network should match the PCB trace impedance and provide the
desired switching point. The reduced signal swing may still meet
receiver input requirements in some applications. This can be
useful when driving long trace lengths on less critical nets.
VS
CMOS
10Ω
50Ω
100Ω
CMOS
100Ω
07972-077
The AD9516 provides four clock outputs (OUT6 to OUT9)
that are selectable as either CMOS or LVDS level outputs. When
selected as CMOS, each output becomes a pair of CMOS outputs,
each of which can be individually turned on or off and set as
noninverting or inverting. These outputs are 3.3 V CMOS
compatible.
CMOS
07972-076
CMOS CLOCK DISTRIBUTION
Figure 64. CMOS Output with Far-End Termination
Because of the limitations of single-ended CMOS clocking,
consider using differential outputs when driving high speed
signals over long traces. The AD9516 offers both LVPECL and
LVDS outputs that are better suited for driving long traces where
the inherent noise immunity of differential signaling provides
superior performance for clocking converters.
Rev. A | Page 73 of 76
AD9516-5
OUTLINE DIMENSIONS
0.60 MAX
9.00
BSC SQ
0.60
MAX
48
64
49
1
PIN 1
INDICATOR
PIN 1
INDICATOR
0.50
BSC
0.50
0.40
0.30
1.00
0.85
0.80
SEATING
PLANE
33
32
16
17
0.05 MAX
0.02 NOM
0.30
0.23
0.18
0.25 MIN
7.50
REF
0.80 MAX
0.65 TYP
12° MAX
6.35
6.20 SQ
6.05
EXPOSED PAD
(BOTTOM VIEW)
0.20 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
091707-C
8.75
BSC SQ
TOP VIEW
Figure 65. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD9516-5BCPZ
AD9516-5BCPZ-REEL7
AD9516-5/PCBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Evaluation Board
Z = RoHS Compliant Part.
Rev. A | Page 74 of 76
Package Option
CP-64-4
CP-64-4
AD9516-5
NOTES
Rev. A | Page 75 of 76
AD9516-5
NOTES
©2009–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07972-0-8/11(A)
Rev. A | Page 76 of 76