ISSI IS45S32800J-6TLA1 Internal bank for hiding row access/precharge Datasheet

IS42S32800J
IS45S32800J
8M x 32
256Mb SYNCHRONOUS DRAM
PRELIMINARY INFORMATION
SEPTEMBER 2014
FEATURES
• Clock frequency:166, 143 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
OVERVIEW
ISSI's 256Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
The 256Mb SDRAM is organized in 2Meg x 32 bit x 4
Banks.
• Single Power supply: 3.3V + 0.3V
• LVTTL interface
KEY TIMING PARAMETERS
• Programmable burst length
– (1, 2, 4, 8, full page)
Parameter
• Programmable burst sequence:
Sequential/Interleave
• Auto Refresh (CBR)
Clk Frequency
• Self Refresh
-6
-7
-75E
Unit
CAS Latency = 3
6
7
—
ns
CAS Latency = 2
10
10
7.5
ns
CAS Latency = 3
166
143
—
Mhz
• 4096 refresh cycles every 16ms (A2 grade) or
64 ms (Commercial, Industrial, A1 grade)
CAS Latency = 2
100
100
133
Mhz
• Random column address every clock cycle
CAS Latency = 3
5.4
5.4
—
ns
• Programmable CAS latency (2, 3 clocks)
CAS Latency = 2
6.5
6.5
6
ns
• Burst read/write and burst read/single write
operations capability
Clk Cycle Time
Access Time from Clock
ADDRESS TABLE
• Burst termination by burst stop and precharge
command
Parameter
8M x 32
Configuration
2M x 32 x 4 banks
OPTIONS
Refresh Count
• Package: 90-ball TF-BGA, 86-pin TSOP2
• Operating Temperature Range:
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
Automotive Grade, A1 (-40oC to +85oC)
Automotive Grade, A2 (-40oC to +105oC)
Com./Ind.
4K / 64ms
A1
4K / 64ms
A2
4K / 16ms
Row Addresses
A0 – A11
Column
Addresses
A0 – A8
Bank Address
Pins
BA0, BA1
Autoprecharge
Pins
A10/AP
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
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Rev. 0A
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1
IS42S32800J, IS45S32800J
DEVICE OVERVIEW
The 256Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V Vdd
and 3.3V Vddq memory systems containing 268,435,456
bits. Internally configured as a quad-bank DRAM with a
synchronous interface. Each 67,108,864-bit bank is organized as 4,096 rows by 512 columns by 32 bits.
The 256Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible.
The 256Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE function
enabled. Precharge one bank while accessing one of the
other three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
SDRAM read and write accesses are burst oriented starting
at a selected location and continuing for a programmed
number of locations in a programmed sequence. The
registration of an ACTIVE command begins accesses,
followed by a READ or WRITE command. The ACTIVE
command in conjunction with address bits registered are
used to select the bank and row to be accessed (BA0,
BA1 select the bank; A0-A11 select the row). The READ
or WRITE commands in conjunction with address bits
registered are used to select the starting column location
for the burst access.
Programmable READ or WRITE burst lengths consist of
1, 2, 4 and 8 locations or full page, with a burst terminate
option.
FUNCTIONAL BLOCK DIAGRAM (For 2Mx32x4 Banks)
DQM0 - DQM3
DATA IN
BUFFER
COMMAND
DECODER
&
CLOCK
GENERATOR
32
REFRESH
CONTROLLER
MODE
REGISTER
12
DQ 0-31
SELF
REFRESH
A10
CONTROLLER
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
4
32
32
VDD/VDDQ
DATA OUT
BUFFER
Vss/VssQ
32
12
MULTIPLEXER
REFRESH
COUNTER
ROW
ADDRESS
LATCH
12
12
COLUMN
ADDRESS LATCH
ROW
ADDRESS
BUFFER
4096
4096
4096
4096
ROW DECODER
CLK
CKE
CS
RAS
CAS
WE
MEMORY CELL
ARRAY
BANK 0
SENSE AMP I/O GATE
512
(x 32)
BANK CONTROL LOGIC
9
BURST COUNTER
COLUMN
ADDRESS BUFFER
2
COLUMN DECODER
9
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IS42S32800J, IS45S32800J
PIN CONFIGURATIONS
86 pin TSOP - Type II for x32
VDD
1
86
VSS
DQ0
2
85
DQ15
VDDQ
3
84
VSSQ
DQ1
4
83
DQ14
DQ2
5
82
DQ13
VSSQ
6
81
VDDQ
DQ3
7
80
DQ12
DQ4
8
79
DQ11
VDDQ
9
78
VSSQ
DQ5
10
77
DQ10
DQ6
11
76
DQ9
VSSQ
12
75
VDDQ
DQ7
13
74
DQ8
NC
14
73
NC
VDD
15
72
VSS
DQM0
16
71
DQM1
WE
17
70
NC
CAS
18
69
NC
RAS
19
68
CLK
CS
20
67
CKE
A11
21
66
A9
BA0
22
65
A8
BA1
23
64
A7
A10
24
63
A6
A0
25
62
A5
A1
26
61
A4
A2
27
60
A3
DQM2
28
59
DQM3
VDD
29
58
VSS
NC
30
57
NC
DQ16
31
56
DQ31
VSSQ
32
55
VDDQ
DQ17
33
54
DQ30
DQ18
34
53
DQ29
VDDQ
35
52
VSSQ
DQ19
36
51
DQ28
DQ20
37
50
DQ27
VSSQ
38
49
VDDQ
DQ21
39
48
DQ26
DQ22
40
47
DQ25
VDDQ
41
46
VSSQ
DQ23
42
45
DQ24
VDD
43
44
VSS
PIN DESCRIPTIONS
A0-A11
A0-A8
BA0, BA1
DQ0 to DQ31
CLK
CKE
CS
RAS
CAS
3
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
DQM0-DQM3
Vdd
Vss
Vddq
Vssq
NC
Write Enable
x32 Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
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Rev. 0A
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IS42S32800J, IS45S32800J
PIN CONFIGURATION
package code: B 90 bALL Tf-bga (Top View) (8.00 mm x 13.00 mm Body, 0.8 mm Ball Pitch)
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
DQ26 DQ24
VSS
VDD DQ23 DQ21
DQ28 VDDQ VSSQ
VDDQ VSSQ DQ19
VSSQ DQ27 DQ25
DQ22 DQ20 VDDQ
VSSQ DQ29 DQ30
DQ17 DQ18 VDDQ
VDDQ DQ31
NC
NC
DQ16 VSSQ
VSS DQM3
A3
A2
DQM2 VDD
A4
A5
A6
A10
A0
A1
A7
A8
NC
NC
BA1
A11
CLK
CKE
A9
BA0
CS
RAS
DQM1
NC
NC
CAS
WE DQM0
VDDQ DQ8
VSS
VDD
DQ7 VSSQ
VSSQ DQ10 DQ9
DQ6
DQ5 VDDQ
VSSQ DQ12 DQ14
DQ1
DQ3 VDDQ
DQ11 VDDQ VSSQ
DQ13 DQ15
VSS
VDDQ VSSQ DQ4
VDD
DQ0
DQ2
PIN DESCRIPTIONS
A0-A11
A0-A8 BA0, BA1
DQ0 to DQ31
CLK
CKE
CS
RAS
CAS
4
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
DQM0-DQM3
Vdd
Vss
Vddq
Vssq
NC
Write Enable
x32 Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
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Rev. 0A
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IS42S32800J, IS45S32800J
PIN FUNCTIONS
Symbol Type
A0-A11
Input Pin
BA0, BA1
Input Pin
CAS
Input Pin
CKE
Input Pin
CLK
Input Pin
CS
Input Pin
DQM0-DQM3
Input Pin
DQ0-DQ31
Input/Output Pin
RAS
Input Pin
WE
Input Pin
Vddq
Vdd
Vssq
Vss
5
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Function (In Detail)
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE command (column address
A0-A8), with A10 defining auto precharge) to select one location out of the memory
array in the respective bank. A10 is sampled during a PRECHARGE command to
determine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE
or PRECHARGE command is being applied.
CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" for details on device commands.
The CKE input determines whether the CLK input is enabled. The next rising edge
of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE
is LOW, the device will be in either power-down mode, clock suspend mode, or self
refresh mode. CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH.
DQM0 - DQM3 control the four bytes of the I/O buffers (DQ0-DQ31). In read
mode, DQMn control the output buffer. When DQMn is LOW, the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the HIGH impedance state whenDQMn is HIGH. This function corresponds to OE in conventional
DRAMs. In write mode, DQMn control the input buffer. When DQMn is LOW, the
corresponding buffer byte is enabled, and data can be written to the device. When
DQMn is HIGH, input data is masked and cannot be written to the device.
Data on the Data Bus is latched on these pins during Write commands, and buffered after
Read commands.
RAS, in conjunction with CAS and WE, forms the device command. See the "Command Truth Table" item for details on device commands.
WE, in conjunction with RAS and CAS, forms the device command. See the "Command Truth Table" item for details on device commands.
Vddq is the output buffer power supply.
Vdd is the device internal power supply.
Vssq is the output buffer ground.
Vss is the device internal ground.
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Rev. 0A
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IS42S32800J, IS45S32800J
GENERAL DESCRIPTION
READ
The READ command selects the bank from BA0, BA1 inputs
and starts a burst read access to an active row. Inputs
A0-A8 provides the starting column location. When A10 is
HIGH, this command functions as an AUTO PRECHARGE
command. When the auto precharge is selected, the row
being accessed will be precharged at the end of the READ
burst. The row will remain open for subsequent accesses
when AUTO PRECHARGE is not selected. DQ’s read
data is subject to the logic level on the DQM inputs two
clocks earlier. When a given DQM signal was registered
HIGH, the corresponding DQ’s will be High-Z two clocks
later. DQ’s will provide valid data when the DQM signal
was registered LOW.
WRITE
A burst write access to an active row is initiated with the
WRITE command. BA0, BA1 inputs selects the bank,
and the starting column location is provided by inputs
A0-A8. Whether or not AUTO-PRECHARGE is used is
determined by A10.
The row being accessed will be precharged at the end of
the WRITE burst, if AUTO PRECHARGE is selected. If
AUTO PRECHARGE is not selected, the row will remain
open for subsequent accesses.
A memory array is written with corresponding input data
on DQ’s and DQM input logic level appearing at the same
time. Data will be written to memory when DQM signal is
LOW. When DQM is HIGH, the corresponding data inputs
will be ignored, and a WRITE will not be executed to that
byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
BA0, BA1 can be used to select which bank is precharged
or they are treated as “Don’t Care”. A10 determined
whether one or all banks are precharged. After executing this command, the next command for the selected
bank(s) is executed after passage of the period tRP, which
is the period required for bank precharging. Once a bank
has been precharged, it is in the idle state and must be
activated prior to any READ or WRITE commands being
issued to that bank.
AUTO PRECHARGE
The AUTO PRECHARGE function ensures that the precharge is initiated at the earliest valid stage within a burst.
This function allows for individual-bank precharge without
requiring an explicit command. A10 to enable the AUTO
6
PRECHARGE function in conjunction with a specific READ
or WRITE command. For each individual READ or WRITE
command, auto precharge is either enabled or disabled.
AUTO PRECHARGE does not apply except in full-page
burst mode. Upon completion of the READ or WRITE
burst, a precharge of the bank/row that is addressed is
automatically performed.
AUTO REFRESH COMMAND
This command executes the AUTO REFRESH operation. The row address and bank to be refreshed are automatically
generated during this operation. The stipulated period (trc) is
required for a single refresh operation, and no other commands can be executed during this period. This command
is executed at least 4096 times for every Tref. During an
AUTO REFRESH command, address bits are “Don’t Care”. This command corresponds to CBR Auto-refresh.
BURST TERMINATE
The BURST TERMINATE command forcibly terminates
the burst read and write operations by truncating either
fixed-length or full-page bursts and the most recently
registered READ or WRITE command prior to the BURST
TERMINATE.
COMMAND INHIBIT
COMMAND INHIBIT prevents new commands from being
executed. Operations in progress are not affected, apart
from whether the CLK signal is enabled
NO OPERATION
When CS is low, the NOP command prevents unwanted
commands from being registered during idle or wait
states.
LOAD MODE REGISTER
During the LOAD MODE REGISTER command the mode
register is loaded from A0-A11. This command can only
be issued when all banks are idle.
ACTIVE COMMAND
When the ACTIVE COMMAND is activated, BA0, BA1
inputs selects a bank to be accessed, and the address
inputs on A0-A11 selects the row. Until a PRECHARGE
command is issued to the bank, the row remains open
for accesses.
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Rev. 0A
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IS42S32800J, IS45S32800J
COMMAND TRUTH TABLE
CKE
Function
n–1
n
CS
RAS
CAS
WE
BA1
BA0
A10
Device deselect (DESL)
H
×
H
×
×
×
×
×
×
No operation (NOP)
H
×
L
H
H
H
×
×
×
Burst stop (BST)
H
×
L
H
H
L
×
×
×
Read
H
×
L
H
L
H
V
V
L
Read with auto precharge
H
×
L
H
L
H
V
V
H
Write
H
×
L
H
L
L
V
V
L
Write with auto precharge
H
×
L
H
L
L
V
V
H
Bank activate (ACT)
H
×
L
L
H
H
V
V
V
Precharge select bank (PRE) H
×
L
L
H
L
V
V
L
Precharge all banks (PALL) H
×
L
L
H
L
×
×
H
CBR Auto-Refresh (REF)
H
H
L
L
L
H
×
×
×
Self-Refresh (SELF)
H
L
L
L
L
H
×
×
×
Mode register set (MRS)
H
×
L
L
L
L
L
L
L
A11
A9 - A0
×
×
×
V
V
V
V
V
×
×
×
×
V
Note: H=Vih, L=Vil x= Vih or Vil, V = Valid Data.
DQM TRUTH TABLE
CKE
Function n-1
n
Data write / output enable H
×
Data mask / output disable H
×
Upper byte write enable / output enable H
×
Lower byte write enable / output enable H
×
Upper byte write inhibit / output disable H
×
Lower byte write inhibit / output disable H
×
DQM
U
L
H
L
×
H
×
L
L
H
×
L
×
H
Note: H=Vih, L=Vil x= Vih or Vil, V = Valid Data.
7
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IS42S32800J, IS45S32800J
CKE TRUTH TABLE
CKE
Current State /Function
n–1
Activating Clock suspend mode entry
H
Any Clock suspend mode
L
Clock suspend mode exit
L
Auto refresh command Idle (REF)
H
Self refresh entry Idle (SELF)
H
Power down entry Idle
H
Self refresh exit
L
L
Power down exit
L
n
L
L
H
H
L
L
H
H
H
CS
×
×
×
L
L
×
L
H
×
RAS
×
×
×
L
L
×
H
×
×
CAS
×
×
×
L
L
×
H
×
×
WE
×
×
×
H
H
×
H
×
×
Address
×
×
×
×
×
×
×
×
×
Note: H=Vih, L=Vil x= Vih or Vil, V = Valid Data.
8
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IS42S32800J, IS45S32800J
FUNCTIONAL TRUTH TABLE
Current State
CS
RAS CAS
WE
Address
Command Action
Idle
H
X
X
X
X
DESL
Nop or Power Down(2)
L
H
H
H
X
NOP
Nop or Power Down(2)
L
H
H
L
X
BST
Nop or Power Down
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL (3)
L
H
L
L
A, CA, A10
WRIT/ WRITA
ILLEGAL(3)
L
L
H
H
BA, RA
ACT
Row activating
L
L
H
L
BA, A10
PRE/PALL
Nop
L
L
L
H
X
REF/SELF
Auto refresh or Self-refresh(4)
L
L
L
L
OC, BA1=L
MRS
Mode register set
H
X
X
X
X
DESL
Nop
L
H
H
H
X
NOP
Nop
L
H
H
L
X
BST
Nop
L
H
L
H
BA, CA, A10
READ/READA
Begin read (5)
L
H
L
L
BA, CA, A10
WRIT/ WRITA
Begin write (5)
L
L
H
H
BA, RA
ACT
ILLEGAL (3)
L
L
H
L
BA, A10
PRE/PALL
Precharge
Precharge all banks(6)
Row Active
Read
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L
OC, BA
MRS
ILLEGAL
H
X
X
X
X
DESL
Continue burst to end to
Row active
L
H
H
H
X
NOP
Continue burst to end Row
Row active
L
H
H
L
X
BST
Burst stop, Row active
L
H
L
H
BA, CA, A10
READ/READA
Terminate burst,
begin new read (7)
L
H
L
L
BA, CA, A10
WRIT/WRITA
Terminate burst,
begin write (7,8)
L
L
H
H
BA, RA
ACT
ILLEGAL (3)
L
L
H
L
BA, A10
PRE/PALL
Terminate burst Precharging
Write
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L
OC, BA
MRS
ILLEGAL
H
X
X
X
X
DESL
Continue burst to end Write recovering
L
H
H
H
X
NOP
Continue burst to end Write recovering
L
H
H
L
X
BST
Burst stop, Row active
L
H
L
H
BA, CA, A10
READ/READA
Terminate burst, start read :
Determine AP (7,8)
L
H
L
L
BA, CA, A10
WRIT/WRITA
Terminate burst, new write :
Determine AP (7)
L
L
H
H
BA, RA
RA ACT
ILLEGAL (3)
L
L
H
L
BA, A10
PRE/PALL
Terminate burst Precharging (9)
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L
OC, BA
MRS
ILLEGAL
Note: H=Vih, L=Vil x= Vih or Vil, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code
9
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IS42S32800J, IS45S32800J
FUNCTIONAL TRUTH TABLE Continued:
Current State
CS
RAS CAS
WE
Address
Command
Action
Read with auto
Precharging
H
×
×
× ×
DESL
Continue burst to end, Precharge
L
H
H
H
x
NOP
Continue burst to end, Precharge
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL (11)
L
H
L
L
BA, CA, A10
WRIT/ WRITA
ILLEGAL (11)
L
L
H
H
BA, RA
ACT
ILLEGAL (3)
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL (11)
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
OC, BA
MRS
ILLEGAL
Write with Auto
H
×
×
×
×
DESL
Precharge
Continue burst to end, Write
recovering with auto precharge
L
H
H
H
×
NOP
Continue burst to end, Write
recovering with auto precharge
Precharging
Row Activating
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL(11)
L
H
L
L
BA, CA, A10
WRIT/ WRITA
ILLEGAL (11)
L
L
H
H
BA, RA
ACT
ILLEGAL (3,11)
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL (3,11)
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
OC, BA
MRS
ILLEGAL
H
×
×
×
×
DESL
Nop, Enter idle after tRP
L
H
H
H
×
NOP
Nop, Enter idle after tRP
L
H
H
L
×
BST
Nop, Enter idle after tRP
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL (3)
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL (3)
L
L
H
H
BA, RA
ACT
ILLEGAL(3)
L
L
H
L
BA, A10
PRE/PALL
Nop Enter idle after tRP
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
OC, BA
MRS
ILLEGAL
H
×
×
×
×
DESL
Nop, Enter bank active after tRCD
L
H
H
H
×
NOP
Nop, Enter bank active after tRCD
L
H
H
L
×
BST
Nop, Enter bank active after tRCD
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL (3)
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL (3)
L
L
H
H
BA, RA
ACT
ILLEGAL (3,9)
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL (3)
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
OC, BA
MRS
ILLEGAL
Note: H=Vih, L=Vil x= Vih or Vil, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code
10
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Rev. 0A
8/14/2014
IS42S32800J, IS45S32800J
FUNCTIONAL TRUTH TABLE Continued:
Current State
Write Recovering
CS
RAS CAS
WE
Address
Command
Action
H
×
×
×
×
DESL
Nop, Enter row active after tDPL
L
H
H
H
×
NOP
Nop, Enter row active after tDPL
L
H
H
L
×
BST
Nop, Enter row active after tDPL
L
H
L
H
BA, CA, A10
READ/READA
Begin read (8)
L
H
L
L
BA, CA, A10
WRIT/ WRITA
Begin new write
L
L
H
H
BA, RA
ACT
ILLEGAL (3)
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL (3)
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
OC, BA
MRS
ILLEGAL
Write Recovering
H
×
×
×
×
DESL
Nop, Enter precharge after tDPL
with Auto
L
H
H
H
×
NOP
Nop, Enter precharge after tDPL
Precharge
L
H
H
L
×
BST
Nop, Enter row active after tDPL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL(3,8,11)
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL (3,11)
L
L
H
H
BA, RA
ACT
ILLEGAL (3,11)
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL (3,11)
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
OC, BA
MRS
ILLEGAL
H
×
×
×
×
DESL Nop, Enter idle after tRC
L
H
H
×
×
NOP/BST
Nop, Enter idle after tRC
Refresh
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
OC, BA
MRS
ILLEGAL
Mode Register
H
×
×
×
×
DESL
Nop, Enter idle after 2 clocks
Accessing
L
H
H
H
×
NOP
Nop, Enter idle after 2 clocks
L
H
H
L
×
BST
ILLEGAL
L
H
L
× BA, CA, A10
READ/WRITE
ILLEGAL
L
L
× ×
BA, RA
ACT/PRE/PALL
REF/MRS
ILLEGAL
Note: H=Vih, L=Vil x= Vih or Vil, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code
Notes:
1. All entries assume that CKE is active (CKEn-1=CKEn=H).
2. If both banks are idle, and CKE is inactive (Low), the device will enter Power Down mode. All input buffers except CKE will be
disabled.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of
that bank.
4. If both banks are idle, and CKE is inactive (Low), the device will enter Self-Refresh mode. All input buffers except CKE will be
disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data which don’t satisfy tDPL.
10. Illegal if tRRD is not satisfied.
11. Illegal for single bank, but legal for other banks.
11
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Rev. 0A
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IS42S32800J, IS45S32800J
CKE RELATED COMMAND TRUTH TABLE(1)
Current State
Self-Refresh (S.R.)
Operation
INVALID, CLK (n - 1) would exit S.R.
Self-Refresh Recovery(2)
Self-Refresh Recovery(2)
Illegal
Illegal
Maintain S.R.
Self-Refresh Recovery Idle After trc
Idle After trc
Illegal
Illegal
Begin clock suspend next cycle(5)
Begin clock suspend next cycle(5)
Illegal
Illegal
Exit clock suspend next cycle(2)
Maintain clock suspend
Power-Down (P.D.)
INVALID, CLK (n - 1) would exit P.D.
EXIT P.D. --> Idle(2)
Maintain power down mode
Both Banks Idle
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Auto-Refresh
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Self-Refresh(3)
Refer to operations in Operative Command Table
Power-Down(3)
Any state
Refer to operations in Operative Command Table
other than
Begin clock suspend next cycle(4)
listed above
Exit clock suspend next cycle
Maintain clock suspend
CKE
n-1
H
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
L
L
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
n
X
H
H
H
H
L
H
H
H
H
L
L
L
L
H
L
X
H
L
H
H
H
H
H
L
L
L
L
L
X
H
L
H
L
CS
X
H
L
L
L
X
H
L
L
L
H
L
L
L
X
X
X
X
X
H
L
L
L
L
H
L
L
L
L
X
X
X
X
X
RAS
X
X
H
H
L
X
X
H
H
L
X
H
H
L
X
X
X
X
X
X
H
L
L
L
X
H
L
L
L
X
X
X
X
X
CAS
X
X
H
L
X
X
X
H
L
X
X
H
L
X
X
X
X
X
X
X
X
H
L
L
X
X
H
L
L
X
X
X
X
X
WE Address
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
—
X
X
X
X
X
—
X
—
X
—
H
X
L Op - Code
X
—
X
—
X
—
H
X
L Op - Code
X
X
X
X
X
X
X
X
X
X
Notes:
1. H : High level, L : low level, X : High or low level (Don’t care).
2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup
time must be satisfied
before any command other than EXIT.
3. Power down and Self refresh can be entered only from the both banks idle state.
4. Must be legal command as defined in Operative Command Table.
5. Illegal if txsr is not satisfied.
12
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Rev. 0A
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IS42S32800J, IS45S32800J
STATE DIAGRAM
Self
Refresh
SELF
SELF exit
Mode
Register
Set
MRS
CBR (Auto)
Refresh
REF
IDLE
CKE
CKE
ACT
Power
Down
CKE
Row
Active
BST
rge
th
ha
wi
ec
rite
Pr
W
to
Au
Read
CKE
POWER
ON
tio
CKE
READA
(P
rec
ha
CKE
READA
SUSPEND
PR
E
n)
tio
ina
erm
et
rge
arg
ch
ter
mi
Pre
na
E(
CKE
READ
SUSPEND
n)
RR
WRITEA
CKE
Write
CKE
CKE
Read
READ
WRITE
WRITEA
SUSPEND
BST
h
wit
ad arge
h
ec
Pr
CKE
to
WRITE
SUSPEND
Read
Re
Write
Au
Write
Active
Power
Down
CKE
Precharge
Precharge
Automatic sequence
Manual Input
13
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Rev. 0A
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IS42S32800J, IS45S32800J
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Parameters
Vdd max
Maximum Supply Voltage
Vddq max
Maximum Supply Voltage for Output Buffer
Vin
Input Voltage
Vout
Output Voltage
Pd max
Allowable Power Dissipation
IcsOutput Shorted Current
Topr
Operating Temperature
Com.
Ind.
A1
A2
Tstg
Storage Temperature
Rating
Unit
-0.5 to +4.6
V
-0.5 to +4.6
V
-0.5 to Vdd + 0.5
V
-1.0 to Vddq + 0.5
V
1
W
50
mA
0 to +70
°C
-40 to +85
-40 to +85
-40 to +105
-65 to +150
°C
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. All voltages are referenced to Vss.
DC RECOMMENDED OPERATING CONDITIONS
(Ta = 0oC to +70oC for Commercial grade. Ta = -40oC to +85oC for Industrial and A1 grade. Ta = -40oC to +105oC for A2 grade.)
Symbol
Parameter Min.
Typ.
Max.
Unit
Vdd
Supply Voltage
3.0
3.3
3.6
V
Vddq
I/O Supply Voltage
3.0
3.3
3.6
V
Vih(1)
Input High Voltage
2.0
—
Vddq + 0.3 V
Vil(2)
Input Low Voltage
-0.3
—
+0.8
V
Note:
1. Vih (max) = Vddq +1.2V (pulse width < 3ns).
2. Vil (min) = -1.2V (pulse width < 3ns).
3. All voltages are referenced to Vss.
CAPACITANCE CHARACTERISTICS (At Ta = 0 to +25°C, Vdd = Vddq = 3.3 ± 0.3V)
Symbol
Parameter
Min.
Max.
Input Capacitance: CLK
2.0
4.0
Cin1
Cin2
Input Capacitance:All other input pins
1.5
4.0
Ci/o
Data Input/Output Capacitance:DQ's
4.0
6.0
Unit
pF
pF
pF
THERMAL RESISTANCE
14
Package
Substrate
Theta-ja
(Airflow = 0m/s)
Theta-ja
(Airflow = 1m/s)
Theta-ja
(Airflow = 2m/s)
Theta-jc
Units
BGA(90)
4-layer
36.1
31.4
29.6
7.5
C/W
BOP2(86)
4-layer
73.2
66.1
62.2
12.5
C/W
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Rev. 0A
8/14/2014
IS42S32800J, IS45S32800J
DC ELECTRICAL CHARACTERISTICS 1 (3) (Recommended Operation Conditions unless otherwise noted.)
Symbol
Parameter
Test Condition
Idd1
Operating Current
One bank active, CL = 3, BL = 1, (1)
-6
-7
-75E
Unit
140
120
120
mA
tclk = tclk (min), trc = trc (min)
Idd2p
Precharge Standby Current
(In Power-Down Mode)
CKE ≤ Vil (max), tck = 15ns
4
4
4
mA
Idd2ps
Precharge Standby Current
(In Power-Down Mode)
CKE ≤ Vil (max), CLK ≤ Vil (max)
4
4
4
mA
Idd2n (2)
Precharge Standby Current
(In Non Power-Down Mode)
CS ≥ Vdd - 0.2V, CKE ≥ Vih (min)
tck = 15ns
30
30
30
mA
Idd2ns
Precharge Standby Current
(In Non Power-Down Mode)
CS ≥ Vdd - 0.2V, CKE ≥ Vih (min) or
CKE ≤ Vil (max), All inputs stable
20
20
20
mA
Idd3p
Active Standby Current
(Power-Down Mode)
CKE ≤ Vil (max), tck = 15ns
8
8
8
mA
Idd3ps
Active Standby Current
(Power-Down Mode)
CKE ≤ Vil (max), CLK ≤ Vil (max)
8
8
8
mA
Idd3n (2)
Active Standby Current
(In Non Power-Down Mode)
CS ≥ Vdd - 0.2V, CKE ≥ Vih (min)
tck = 15ns
35
35
35
mA
Idd3ns
Active Standby Current
(In Non Power-Down Mode)
CS ≥ Vdd - 0.2V, CKE ≥ Vih (min) or
CKE ≤ Vil (max), All inputs stable
20
20
20
mA
Idd4
Operating Current
All banks active, BL = 4, CL = 3,
tck = tck (min)
190
170
170
mA
Idd5
Auto-Refresh Current
trc = trc (min), tclk = tclk (min)
180
160
160
mA
Idd6
Self-Refresh Current
CKE ≤ 0.2V
5
5
5
mA
1. Idd (max) is specified at the output open condition.
2. Input signals are changed one time during 30ns.
3. All values applicable for operation for TA ≤ 85°C. For A2 temperature grade with TA > 85°C: IDD1 and IDD4 are derated to 5% above these
values; IDD3NS is derated to 30% above these values.
DC ELECTRICAL CHARACTERISTICS 2 (Recommended Operation Conditions unless otherwise noted.)
15
Symbol
Iil
Parameter
Input Leakage Current
Iol
Voh
Vol
Output Leakage Current
Output High Voltage Level
Output Low Voltage Level
Test Condition
0V ≤ Vin ≤ Vdd, with pins other than
the tested pin at 0V
Output is disabled, 0V ≤ Vout ≤ Vdd,
Ioh = -2mA Iol = 2mA Min
-10
Max
10
Unit
µA
-10
2.4
—
10
—
0.4
µA
V
V
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Rev. 0A
8/14/2014
IS42S32800J, IS45S32800J
AC ELECTRICAL CHARACTERISTICS (1,2,3,4)
-6
Symbol
Parameter
tck3
Clock Cycle Time
tck2
tac3
Access Time From CLK
tac2
tch
CLK HIGH Level Width
tcl
CLK LOW Level Width
toh3
Output Data Hold Time
toh2
tlz
Output LOW Impedance Time
thz3
Output HIGH Impedance Time
thz2
-7
Min.
Max.
CAS Latency = 3
6
—
7
CAS Latency = 2
10
—
CAS Latency = 3
—
5.4
CAS Latency = 2
—
-75E
Min. Max.
Min. Max.
Units
—
—
—
ns
10
—
7.5
—
ns
—
5.4
—
—
ns
6.5
—
6.5
—
6
ns
2.5
—
2.5
—
2.5
—
ns
2.5
—
2.5
—
2.5
—
ns
CAS Latency = 3
2.5
—
2.5
—
—
—
ns
CAS Latency = 2
2.5
—
2.5
—
2.5
—
ns
0
—
0
—
0
—
ns
CAS Latency = 3
2.5
5.4
2.5
5.4
—
—
ns
CAS Latency = 2
2.5
6.5
2.5
6.5
2.5
6
ns
tds
Input Data Setup Time(2)
1.5
—
1.5
—
1.5
—
ns
tdh
Input Data Hold Time
1.0
—
1.0
—
1.0
—
ns
tas
Address Setup Time
1.5
—
1.5
—
1.5
—
ns
tah
Address Hold Time
1.0
—
1.0
—
1.0
—
ns
tcks
CKE Setup Time
1.5
—
1.5
—
1.5
—
ns
tckh
CKE Hold Time(2)
1.0
—
1.0
—
1.0
—
ns
tcms
Command Setup Time (CS, RAS, CAS, WE, DQM)
1.5
—
1.5
—
1.5
—
ns
tcmh
Command Hold Time (CS, RAS, CAS, WE, DQM)
1.0
—
1.0
—
1.0
—
ns
—
ns
(2)
(2)
(2)
(2)
(2)
(2)
trc
Command Period (REF to REF / ACT to ACT)
60
—
70
tras
Command Period (ACT to PRE)
42
100K
49
100K
67.5
37
trp
Command Period (PRE to ACT)
18
—
20
—
15
—
ns
trcd
Active Command To Read / Write Command Delay Time
18
—
20
—
15
—
ns
trrd
Command Period (ACT [0] to ACT[1])
12
—
14
—
15
—
ns
tdpl
Input Data To Precharge
Command Delay time
12
—
14
—
15
—
ns
tdal
Input Data To Active / Refresh
Command Delay time (During Auto-Precharge)
30
—
35
—
30
—
ns
tmrd
Mode Register Program Time
12
14
—
15
—
ns
7
—
7.5
—
ns
70
—
75
—
ns
100K ns
—
tdde
Power Down Exit Setup Time
6
—
txsr
Self-Refresh Exit Time(5)
70
—
tt
Transition Time
0.3
1.2
0.3
1.2
0.3
1.2
ns
tref
Refresh Cycle Time (4096) Ta ≤ 70oC Com., Ind., A1, A2
—
64
—
64
—
64
ms
Ta ≤ 85 C Ind., A1, A2
—
64
—
64
—
64
ms
Ta > 85 C A2
—
16
—
16
—
16
ms
o
o
Notes:
1. The power-on sequence must be executed before starting memory operation.
2. Measured with tt = 1 ns. If clock rising time is longer than 1ns, (tt /2 - 0.5) ns should be added to the parameter.
3. The reference level is 1.4V when measuring input signal timing. Rise and fall times are measured between Vih(min.) and Vil (max).
4. Use recommended operation conditions.
5. Self-Refresh Mode is not supported for A2 grade with Ta > +85oC.
16
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IS42S32800J, IS45S32800J
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
Symbol Parameter
-6
-7
-75E
Units
—
Clock Cycle Time
6
7
7.5
ns
—
Operating Frequency
166
143
133
MHz
tcac
CAS Latency
3
3
2
cycle
trcd
Active Command To Read/Write Command Delay Time
3
3
2
cycle
6
—
6
—
—
4
cycle
trac
RAS Latency (trcd + tcac)
trc
Command Period (REF to REF / ACT to ACT)
10
10
9
cycle
tras
Command Period (ACT to PRE)
7
7
5
cycle
trp
Command Period (PRE to ACT)
3
3
2
cycle
trrd
Command Period (ACT[0] to ACT [1])
2
2
2
cycle
tccd
Column Command Delay Time
(READ, READA, WRIT, WRITA)
1
1
1
cycle
tdpl
Input Data To Precharge Command Delay Time
2
2
2
cycle
tdal
Input Data To Active/Refresh Command Delay Time
(During Auto-Precharge)
5
5
4
cycle
trbd
Burst Stop Command To Output in HIGH-Z Delay Time
3
—
3
—
—
2
cycle
0
0
0
cycle
3
—
3
—
—
2
cycle
0
0
0
cycle
tpql
Last Output To Auto-Precharge Start Time (Read) CAS Latency = 3
CAS Latency = 2
-2
—
-2
—
—
-1
cycle
tqmd
DQM To Output Delay Time (Read)
2
2
2
cycle
tdmd
DQM To Input Delay Time (Write)
0
0
0
cycle
tmrd
Mode Register Set To Command Delay Time
2
2
2
cycle
(Read)
twbd
trql
twdl
CAS Latency = 3
CAS Latency = 2
Burst Stop Command To Input in Invalid Delay Time
(Write)
Precharge Command To Output in HIGH-Z Delay Time
(Read)
17
CAS Latency = 3
CAS Latency = 2
CAS Latency = 3
CAS Latency = 2
Precharge Command To Input in Invalid Delay Time
(Write)
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Rev. 0A
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IS42S32800J, IS45S32800J
AC TEST CONDITIONS
Input Load
Output Load
tCK
tCH
tCL
3.0V
CLK 1.4V
0V
1.4V
tCMS
50Ω
Z = 50Ω
tCMH
Output
3.0V
50 pF
INPUT 1.4V
0V
tAC
tOH
OUTPUT
1.4V
1.4V
AC TEST CONDITIONS
Parameter
AC Input Levels
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Measurement Reference Level
18
Rating
0V to 3.0V
1 ns
1.4V
1.4V
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19
FUNCTIONAL DESCRIPTION
Initialization
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to
be accessed (BA0 and BA1 select the bank, A0-A11 select the
row). The address bits A0-A8 registered coincident with the
READ or WRITE command are used to select the starting
column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information
covering device initialization, register definition, command
descriptions and device operation.
SDRAMs must be powered up and initialized in a
predefined manner.
The 256M SDRAM is initialized after the power is applied
to Vdd and Vddq (simultaneously) and the clock is stable
with DQM High and CKE High.
A 100µs delay is required prior to issuing any command
other than a COMMAND INHIBIT or a NOP. The COMMAND
INHIBIT or NOP may be applied during the 100µs period and
should continue at least through the end of the period.
With at least one COMMAND INHIBIT or NOP command
having been applied, a PRECHARGE command should
be applied once the 100µs delay has been satisfied. All
banks must be precharged. This will leave all banks in an
idle state after which at least two AUTO REFRESH cycles
must be performed. After the AUTO REFRESH cycles are
complete, the SDRAM is then ready for mode register
programming.
The mode register should be loaded prior to applying
any operational command because it will power up in an
unknown state.
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Initialize and Load Mode Register(1)
T0
CLK
T1
tCK
Tn+1
tCH
To+1
tCL
Tp+1
Tp+2
Tp+3
tCKS tCKH
CKE
COMMAND
tCMS tCMH
tCMS tCMH
tCMS tCMH
NOP
PRECHARGE
AUTO
REFRESH
NOP
AUTO
REFRESH
NOP
Load MODE
REGISTER
NOP
ACTIVE
DQM0-DQM3
tAS tAH
A0-A9, A11
ALL BANKS
A10
SINGLE BANK
BA0, BA1
CODE
tAS tAH
ROW
CODE
ROW
tAS tAH
ALL BANKS
BANK
CODE
DQ
T
Power-up: VCC
and CLK stable
tRP
Precharge
all banks
tRC
AUTO REFRESH
tRC
AUTO REFRESH
T = 100µs Min.
tMRD
Program MODE REGISTER (2, 3, 4)
DON'T CARE
Notes:
1. If CS is High at clock High time, all commands applied are NOP.
2. The Mode register may be loaded prior to the Auto-Refresh cycles if desired.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after the command is issued.
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Auto-Refresh Cycle
T0
CLK
tCK
T1
tCL
T2
Tn+1
tCH
To+1
tCKS tCKH
CKE
tCMS tCMH
COMMAND
PRECHARGE
NOP
Auto
Refresh
NOP
Auto
Refresh
NOP
ACTIVE
DQM0 - DQM3
A0-A9, A11
ROW
ALL BANKS
A10
ROW
SINGLE BANK
BA0, BA1
DQ
BANK
BANK(s)
tAS tAH
High-Z
tRP
tRC
tRC
DON'T CARE
Notes:
1. CAS latency = 2, 3
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Self-Refresh Cycle
T0
T1
tCK
CLK
T2
tCH
tCKS tCKH
Tn+1
To+1
To+2
tCL
tCKS
≥ tRAS
CKE
tCKS
tCMS tCMH
COMMAND
PRECHARGE
NOP
Auto
Refresh
NOP
NOP
Auto
Refresh
DQM0 - DQM3
A0-A9, A11
ALL BANKS
A10
SINGLE BANK
tAS tAH
BA0, BA1
BANK
DQ High-Z
Precharge all
active banks
tRP
Enter self
refresh mode
tXSR
CLK stable prior to exiting
Exit self refresh mode
self refresh mode
(Restart refresh time base)
DON'T CARE
Note:
1. Self-Refresh Mode is not supported for A2 grade with Ta > +85oC.
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Register Definition
Mode Register
Mode register bits M0-M2 specify the burst length, M3
specifies the type of burst (sequential or interleaved), M4- M6
specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifies the WRITE burst mode, and M10 and
M11 are reserved for future use.
The mode register must be loaded when all banks are
idle, and the controller must wait the specified time before
initiating the subsequent operation.Violating either of these
requirements will result in unspecified operation.
The mode register is used to define the specific mode
of operation of the SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency,
an operating mode and a write burst mode, as shown in
MODE REGISTER DEFINITION.
The mode register is programmed via the LOAD MODE
REGISTER command and will retain the stored information
until it is programmed again or the device loses power.
MODE REGISTER DEFINITION
BA1 BA0 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
Mode Register (Mx)
Burst Length
(1)
Reserved
M2
M1 M0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
M3=0
M3=1
1
2
4
8
Reserved
Reserved
Reserved
Full Page
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Burst Type
M3
Type
0
1
Sequential
Interleaved
Latency Mode
M6 M5 M4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Operating Mode
M8 M7
M6-M0
Mode
0 0
— —
Defined
—
Standard Operation
All Other States Reserved
Write Burst Mode
M9
0
1
23
Mode
Programmed Burst Length
Single Location Access
1. To ensure compatibility with future devices,
should program BA1, BA0, A11, A10 = "0"
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Burst Length
Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown in
MODE REGISTER DEFINITION. The burst length determines the maximum number of column locations that can
be accessed for a given READ or WRITE command. Burst
lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a full-page
burst is available for the sequential type. The full-page
burst is used in conjunction with the BURST TERMINATE
command to generate arbitrary burst lengths.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, mean-
ing that the burst will wrap within the block if a boundary
is reached. The block is uniquely selected by A1-A8 (x32)
when the burst length is set to two; by A2-A8 (x32) when
the burst length is set to four; and by A3-A8 (x32) when the
burst length is set to eight. The remaining (least significant)
address bit(s) is (are) used to select the starting location
within the block. Full-page bursts wrap within the page if
the boundary is reached.
Burst Type
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in BURST DEFINITION table.
Burst Definition
BurstStarting Column
Order of Accesses Within a Burst
Length
Address
Type = Sequential
Type = Interleaved
A 0
2
0
0-1 0-1
1
1-0
1-0
A 1
A0
0
0
0-1-2-3
0-1-2-3
4
0
1 1-2-3-0 1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
A2
A1
A0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
8
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Full
n = A0-A8
Cn, Cn + 1, Cn + 2
Not Supported
Page
Cn + 3, Cn + 4...
(y)
(location 0-y)
…Cn - 1,
Cn…
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CAS Latency
Operating Mode
The CAS latency is the delay, in clock cycles, between
the registration of a READ command and the availability of
the first piece of output data. The latency can be set to two or
three clocks.
If a READ command is registered at clock edge n, and
the latency is m clocks, the data will be available by clock
edge n + m. The DQs will start driving as a result of the
clock edge one cycle earlier (n + m - 1), and provided that
the relevant access times are met, the data will be valid by
clock edge n + m. For example, assuming that the clock
cycle time is such that all relevant access times are met,
if a READ command is registered at T0 and the latency
is programmed to two clocks, the DQs will start driving
after T1 and the data will be valid by T2, as shown in CAS
Latency diagrams. The Allowable Operating Frequency
table indicates the operating frequencies at which each
CAS latency setting can be used.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
The normal operating mode is selected by setting M7 and M8
to zero; the other combinations of values for M7 and M8 are
reserved for future use and/or test modes. The programmed
burst length applies to both READ and WRITE bursts.
Test modes and reserved states should not be used because unknown operation or incompatibility with future
versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1,
the programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses.
CAS Latency
Allowable Operating Frequency (MHz)
Speed
CAS Latency = 2
CAS Latency = 3
-6
100
166
-7
100
143
-75E
133
—
CAS Latency
T0
T1
T2
T3
READ
NOP
NOP
CLK
COMMAND
tAC
DOUT
DQ
tOH
tLZ
CAS Latency - 2
T0
T1
T2
T3
T4
READ
NOP
NOP
NOP
CLK
COMMAND
tAC
DOUT
DQ
tLZ
tOH
CAS Latency - 3
DON'T CARE
UNDEFINED
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Activating Specific Row Within Specific Bank
CHIP Operation
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued
to a bank within the SDRAM, a row in that bank must be
“opened.” This is accomplished via the ACTIVE command,
which selects both the bank and the row to be activated
(see Activating Specific Row Within Specific Bank).
After opening a row (issuing an ACTIVE command), a READ
or WRITE command may be issued to that row, subject to
the trcd specification. Minimum trcd should be divided by
the clock period and rounded up to the next whole number
to determine the earliest clock edge after the ACTIVE
command on which a READ or WRITE command can be
entered. For example, a trcd specification of 18ns with a
125 MHz clock (8ns period) results in 2.25 clocks, rounded
to 3. This is reflected in the following example, which covers any case where 2 < [trcd (MIN)/tck] ≤ 3. (The same
procedure is used to convert other specification limits from
time units to clock cycles).
A subsequent ACTIVE command to a different row in the
same bank can only be issued after the previous active
row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the
same bank is defined by trc.
CLK
HIGH
CKE
CS
RAS
CAS
WE
A0-A11
ROW ADDRESS
BA0, BA1
BANK ADDRESS
A subsequent ACTIVE command to another bank can be
issued while the first bank is being accessed, which results
in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to
different banks is defined by trrd.
Example: Meeting trcd (MIN) when 2 < [trcd (min)/tck] ≤ 3
T0
T1
T2
ACTIVE
NOP
NOP
T3
T4
CLK
COMMAND
READ or
WRITE
tRCD
DON'T CARE
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READs
READ bursts are initiated with a READ command, as
shown in the READ COMMAND diagram.
The starting column and bank addresses are provided with
the READ command, and auto precharge is either enabled or
disabled for that burst access. If auto precharge is enabled,
the row being accessed is precharged at the completion of
the burst. For the generic READ commands used in the following illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from the
starting column address will be available following the
CAS latency after the READ command. Each subsequent
data-out element will be valid by the next positive clock
edge. The CAS Latency diagram shows general timing
for each possible CAS latency setting.
Upon completion of a burst, assuming no other commands
have been initiated, the DQs will go High-Z. A full-page burst
will continue until terminated. (At the end of the page, it will
wrap to column 0 and continue.)
Data from any READ burst may be truncated with a subsequent READ command, and data from a fixed-length
READ burst may be immediately followed by data from a
READ command. In either case, a continuous flow of data
can be maintained. The first data element from the new
burst follows either the last element of a completed burst
or the last desired data element of a longer burst which
is being truncated.
The new READ command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This
is shown in Consecutive READ Bursts for CAS latencies
of two and three; data element n + 3 is either the last of
a burst of four or the last desired of a longer burst. The SDRAM uses a pipelined architecture and therefore does
not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle
following a previous READ command. Full-speed random
read accesses can be performed to the same bank, as
shown in Random READ Accesses, or each subsequent
READ may be performed to a different bank.
Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length
READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations).
The WRITE burst may be initiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be
avoided. In a given system design, there may be a possibility that the device driving the input data will go Low-Z
before the SDRAM DQs go High-Z. In this case, at least
a single-cycle delay should occur between the last read
data and the WRITE command.
27
READ COMMAND
CLK
CKE
HIGH
CS
RAS
CAS
WE
A0-A8
COLUMN ADDRESS
A9, A11
AUTO PRECHARGE
A10
NO PRECHARGE
BA0, BA1
BANK ADDRESS
The DQM input is used to avoid I/O contention, as shown
in Figures RW1 and RW2. The DQM signal must be asserted (HIGH) at least three clocks prior to the WRITE
command (DQM latency is two clocks for output buffers)
to suppress data-out from the READ. Once the WRITE
command is registered, the DQs will go High-Z (or remain
High-Z), regardless of the state of the DQM signal, provided
the DQM was active on the clock just prior to the WRITE
command that truncated the READ command. If not, the
second WRITE will be an invalid WRITE. For example, if
DQM was LOW during T4 in Figure RW2, then the WRITEs
at T5 and T7 would be valid, while the WRITE at T6 would
be invalid.
The DQM signal must be de-asserted prior to the WRITE
command (DQM latency is zero clocks for input buffers)
to ensure that the written data is not masked.
A fixed-length READ burst may be followed by, or truncated
with, a PRECHARGE command to the same bank (provided
that auto precharge was not activated), and a full-page burst
may be truncated with a PRECHARGE command to the
same bank.The PRECHARGE command should be issued
x cycles before the clock edge at which the last desired
data element is valid, where x equals the CAS latency
minus one. This is shown in the READ to PRECHARGE
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diagram for each possible CAS latency; data element n +
3 is either the last of a burst of four or the last desired of
a longer burst. Following the PRECHARGE command, a
subsequent command to the same bank cannot be issued
until trp is met. Note that part of the row precharge time is
hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command
and address buses be available at the appropriate time to
issue the command; the advantage of the PRECHARGE
command is that it can be used to truncate fixed-length
or full-page bursts.
Full-page READ bursts can be truncated with the BURST
TERMINATE command, and fixed-length READ bursts
may be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated.The BURST
TERMINATE command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This is
shown in the READ Burst Termination diagram for each
possible CAS latency; data element n + 3 is the last desired
data element of a longer burst.
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RW1 - READ to WRITE
T0
T1
T2
T3
T4
T5
T6
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
WRITE
ADDRESS
BANK,
COL n
CLK
DQM
BANK,
COL b
tHZ
DOUT n
DQ
DOUT n+1
DIN b
DOUT n+2
CAS Latency - 2
tDS
DON'T CARE
RW2 - READ to WRITE
T0
T1
T2
T3
T4
T5
COMMAND
READ
NOP
NOP
NOP
NOP
WRITE
ADDRESS
BANK,
COL n
CLK
DQM
BANK,
COL b
tHZ
DQ
DOUT n
CAS Latency - 3
DIN b
tDS
DON'T CARE
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Consecutive READ Bursts
T0
T1
T2
T3
T4
T5
T6
COMMAND
READ
NOP
NOP
NOP
READ
NOP
NOP
ADDRESS
BANK,
COL n
DOUT n+3
DOUT b
CLK
BANK,
COL b
DQ
DOUT n
DOUT n+1
DOUT n+2
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
COMMAND
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
ADDRESS
BANK,
COL n
DOUT n+2
DOUT n+3
DOUT b
CLK
BANK,
COL b
DQ
DOUT n
DOUT n+1
CAS Latency - 3
DON'T CARE
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Random READ Accesses
T0
T1
T2
T3
T4
T5
COMMAND
READ
READ
READ
READ
NOP
NOP
ADDRESS
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
CLK
DQ
DOUT n
DOUT b
DOUT m
DOUT x
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
COMMAND
READ
READ
READ
READ
NOP
NOP
NOP
ADDRESS
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
CLK
DQ
DOUT n
DOUT b
DOUT m
DOUT x
CAS Latency - 3
DON'T CARE
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READ Burst Termination
T0
T1
T2
T3
T4
READ
NOP
NOP
NOP
T5
T6
NOP
NOP
CLK
COMMAND
BURST
TERMINATE
x = 1 cycle
BANK a,
COL n
ADDRESS
DQ
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
READ
NOP
NOP
NOP
T4
T5
T6
T7
NOP
NOP
NOP
CLK
COMMAND
BURST
TERMINATE
x = 2 cycles
ADDRESS
BANK,
COL n
DQ
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 3
DON'T CARE
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ALTERNATING BANK READ ACCESSES
T0
CLK
tCK
T1
tCL
T2
tCH
T3
T4
T5
T6
T7
T8
NOP
READ
NOP
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
ACTIVE
ACTIVE
tCMS tCMH
DQM0 - DQM3
tAS tAH
A0-A9, A11
ROW
tAS tAH
A10
ROW
tAS tAH
BA0, BA1
BANK 0
COLUMN m(2)
COLUMN b(2)
ROW
ENABLE AUTO PRECHARGE
ROW
ENABLE AUTO PRECHARGE
ROW
BANK 0
ROW
BANK 3
tLZ
BANK 3
tOH
tOH
DQ
DOUT m
tAC
tRCD - BANK 0
tRRD
tOH
DOUT m+1
tAC
BANK 0
tOH
DOUT m+2
tAC
tOH
DOUT m+3
tAC
tAC
tRP - BANK 0
CAS Latency - BANK 0
tRCD - BANK 3
DOUT b
tAC
tRCD - BANK 0
CAS Latency - BANK 3
tRAS - BANK 0
tRC - BANK 0
DON'T CARE
Notes:
1) Cas latency = 2, Burst Length = 4
2) x32: A9, A11 = "Don't Care"
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READ - FULL-PAGE BURST
T0
CLK
tCK
T1
tCL
T2
T3
tCH
T4
T5
T6
Tn+1
NOP
NOP
NOP
Tn+2
Tn+3
Tn+4
NOP
NOP
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
BURST TERM
tCMS tCMH
DQM0 - DQM3
tAS tAH
A0-A9, A11
ROW
tAS tAH
A10
ROW
tAS tAH
BA0, BA1
BANK
COLUMN m(2)
BANK
tAC
DQ
tLZ
tRCD
CAS Latency
tAC
DOUT m
tAC
DOUT m+1
tOH
tOH
each row (x4) has
1,024 locations
tAC
DOUT m+2
tOH
tAC
DOUT m-1
tAC
DOUT m
tHZ
DOUT m+1
tOH
tOH
tOH
DON'T CARE
Full page Full-page burst not self-terminating.
completion Use BURST TERMINATE command.
UNDEFINED
Notes:
1) Cas latency = 2, Burst Length = Full Page
2) x32: A9, A11 = "Don't Care"
34
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READ - DQM OPERATION
T0
CLK
tCK
T1
tCL
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
NOP
NOP
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
tCMS tCMH
DQM0 - DQM3
tAS tAH
A0-A9, A11
ROW
tAS tAH
A10
ROW
tAS tAH
DISABLE AUTO PRECHARGE
BANK
BANK
BA0, BA1
COLUMN m(2)
ENABLE AUTO PRECHARGE
tAC
DQ
tLZ
tRCD
CAS Latency
tOH
DOUT m
tHZ
tAC
tLZ
tOH
DOUT m+2
tAC
tOH
DOUT m+3
tHZ
DON'T CARE
UNDEFINED
Notes:
1) Cas latency = 2, Burst Length = 4
2) x32: A9, A11 = "Don't Care"
35
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READ to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
tRP
COMMAND
READ
ADDRESS
BANK a,
COL n
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
BANK
(a or all)
BANK a,
ROW
tRQL
DQ
DOUT n
DOUT n+1
DOUT n+2
NOP
High-Z
DOUT n+3
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
tRP
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
PRECHARGE
NOP
NOP
BANK,
COL b
BANK a,
ROW
tRQL
DQ
DOUT n
DOUT n+1
ACTIVE
DOUT n+2
High-Z
DOUT n+3
CAS Latency - 3
DON'T CARE
36
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WRITEs
WRITE bursts are initiated with a WRITE command, as
shown in WRITE Command diagram.
WRITE Command
CLK
CKE
HIGH
CS
RAS
CAS
WE
A0-A8
COLUMN ADDRESS
A9, A11
AUTO PRECHARGE
A10
NO PRECHARGE
BA0, BA1
BANK ADDRESS
The starting column and bank addresses are provided with
the WRITE command, and auto precharge is either enabled
or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of
the burst. For the generic WRITE commands used in the
following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be
registered coincident with the WRITE command. Subsequent
data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst,
assuming no other commands have been initiated, the
DQs will remain High-Z and any additional input data will
be ignored (see WRITE Burst). A full-page burst will continue until terminated. (At the end of the page, it will wrap
to column 0 and continue.)
Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE
burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on
any clock following the previous WRITE command, and the
data provided coincident with the new command applies to
the new command.
37
An example is shown in WRITE to WRITE diagram. Data n
+ 1 is either the last of a burst of two or the last desired of
a longer burst. The SDRAM uses a pipelined architecture
and therefore does not require the 2n rule associated with
a prefetch architecture. A WRITE command can be initiated
on any clock cycle following a previous WRITE command.
Full-speed random write accesses within a page can be
performed to the same bank, as shown in Random WRITE
Cycles, or each subsequent WRITE may be performed to
a different bank.
Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed-length WRITE
burst may be immediately followed by a subsequent READ
command. Once the READ com mand is registered, the
data inputs will be ignored, and WRITEs will not be executed. An example is shown in WRITE to READ. Data n
+ 1 is either the last of a burst of two or the last desired
of a longer burst.
Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command to the
same bank (provided that auto precharge was not activated), and a full-page WRITE burst may be truncated
with a PRECHARGE command to the same bank. The
PRECHARGE command should be issued tdpl after the
clock edge at which the last desired input data element
is registered. The auto precharge mode requires a tdpl of
at least one clock plus time, regardless of frequency. In
addition, when truncating a WRITE burst, the DQM signal
must be used to mask input data for the clock edge prior
to, and the clock edge coincident with, the PRECHARGE
command. An example is shown in the WRITE to PRECHARGE diagram. Data n+1 is either the last of a burst
of two or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to the
same bank cannot be issued until trp is met.
In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum
time (as described above) provides the same operation that
would result from the same fixed-length burst with auto
precharge.The disadvantage of the PRECHARGE command
is that it requires that the command and address buses be
available at the appropriate time to issue the command; the
advantage of the PRECHARGE command is that it can be
used to truncate fixed-length or full-page bursts.
Fixed-length or full-page WRITE bursts can be truncated
with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with
the BURST TERMINATE command will be ignored. The
last data written (provided that DQM is LOW at that time)
will be the input data applied one clock previous to the
BURST TERMINATE command. This is shown in WRITE
Burst Termination, where data n is the last desired data
element of a longer burst.
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WRITE Burst
T0
T1
T2
T3
COMMAND
WRITE
NOP
NOP
NOP
ADDRESS
BANK,
COL n
CLK
DQ
DIN n
DIN n+1
DON'T CARE
WRITE to WRITE
T0
T1
T2
COMMAND
WRITE
NOP
WRITE
ADDRESS
BANK,
COL n
CLK
DQ
BANK,
COL b
DIN n
DIN n+1
DIN b
DON'T CARE
Random WRITE Cycles
T0
T1
T2
T3
COMMAND
WRITE
WRITE
WRITE
WRITE
ADDRESS
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
DIN b
DIN m
DIN x
CLK
DQ
38
DIN n
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WRITE to READ
T0
T1
T2
T3
T4
T5
COMMAND
WRITE
NOP
READ
NOP
NOP
NOP
ADDRESS
BANK,
COL n
DOUT b
DOUT b+1
CLK
DQ
BANK,
COL b
DIN n
DIN n+1
CAS Latency - 2
DON'T CARE
WP1 - WRITE to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
tRP
COMMAND
WRITE
ADDRESS
BANK a,
COL n
NOP
NOP
PRECHARGE
BANK
(a or all)
NOP
ACTIVE
NOP
BANK a,
ROW
tDPL
DQ
DIN n
DIN n+1
DIN n+2
DON'T CARE
39
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WP2 - WRITE to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
tRP
COMMAND
WRITE
ADDRESS
BANK a,
COL n
NOP
NOP
PRECHARGE
NOP
NOP
BANK
(a or all)
ACTIVE
BANK a,
ROW
tDPL
DQ
DIN n
DIN n+1
DON'T CARE
WRITE Burst Termination
T0
T1
T2
COMMAND
WRITE
BURST
TERMINATE
NEXT
COMMAND
ADDRESS
BANK,
COL n
CLK
DQ
DIN n
(ADDRESS)
(DATA)
DON'T CARE
40
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IS42S32800J, IS45S32800J
write - full page burst
T0
T1
tCK
CLK
T2
T3
T4
T5
Tn+1
Tn+2
NOP
NOP
NOP
NOP
BURST TERM
tDS tDH
tDS tDH
tDS tDH
tDS
DIN m
DIN m+1
DIN m+2
DIN m+3
tCL
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
tCMS tCMH
DQM0 - DQM3
tAS tAH
A0-A9, A11
ROW
tAS tAH
A10
ROW
tAS tAH
BA0, BA1
BANK
COLUMN m(2)
BANK
DQ
tRCD
tDH
tDS
tDH
tDS
tDH
DIN m-1
Full page completed
DON'T CARE
Notes:
1) Burst Length = Full Page
2) x32: A9, A11 = "Don't Care"
41
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WRITE - DQM OPERATION
T0
T1
T2
tCK
CLK
tCL
T3
T4
T5
T6
T7
NOP
NOP
NOP
NOP
NOP
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQM0 - DQM3
tAS tAH
A0-A9, A11
A10
BA0, BA1
COLUMN m(2)
ROW
tAS tAH
ENABLE AUTO PRECHARGE
ROW
tAS tAH
DISABLE AUTO PRECHARGE
BANK
BANK
tDS
tDH
DIN m
DQ
tRCD
tDS tDH
tDS
tDH
DIN m+2
DIN m+3
DON'T CARE
Notes:
1) Burst Length = 4
2) x32: A9, A11 = "Don't Care"
42
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ALTERNATING BANK WRITE ACCESSES
T0
tCK
CLK
T1
T2
tCL
tCH
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
ACTIVE
NOP
WRITE
ACTIVE
tCMS tCMH
DQM0 - DQM3
tAS tAH
A0-A9, A11
ROW
tAS tAH
A10
ROW
tAS tAH
BA0, BA1
BANK 0
COLUMN m(2)
COLUMN b(2)
ROW
ENABLE AUTO PRECHARGE
ROW
ENABLE AUTO PRECHARGE
ROW
BANK 0
tDS
DQ
tDH
DIN m
tRCD - BANK 0
tRRD
tRAS - BANK 0
tRC - BANK 0
ROW
BANK 1
tDS tDH
DIN m+1
BANK 1
tDS
tDS tDH
DIN m+2
tDH
DIN m+3
tDS
tDH
DIN b
tDPL - BANK 0
tRCD - BANK 1
BANK 0
tDS
tDH
DIN b+1
tDS
tDH
DIN b+2
tRP - BANK 0
tDS
tDH
DIN b+3
tRCD - BANK 0
tDPL - BANK 1
DON'T CARE
Notes:
1) Burst Length = 4
2) x32: A9, A11 = "Don't Care"
43
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CLOCK SUSPEND
Clock suspend mode occurs when a column access/burst
is in progress and CKE is registered LOW. In the clock
suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled
LOW, the next internal positive clock edge is suspended.
Any command or data present on the input pins at the time
of a suspended internal clock edge is ignored; any data
present on the DQ pins remains driven; and burst counters
are not incremented, as long as the clock is suspended.
(See following examples.)
Clock suspend mode is exited by registering CKE HIGH;
the internal clock and related operation will resume on the
subsequent positive clock edge.
Clock Suspend During WRITE Burst
T0
T1
NOP
WRITE
T2
T3
T4
T5
NOP
NOP
DIN n+1
DIN n+2
CLK
CKE
INTERNAL
CLOCK
COMMAND
BANK a,
COL n
ADDRESS
DQ
DIN n
DON'T CARE
Clock Suspend During READ Burst
T0
T1
T2
COMMAND
READ
NOP
NOP
ADDRESS
BANK a,
COL n
T3
T4
T5
T6
NOP
NOP
NOP
CLK
CKE
INTERNAL
CLOCK
DQ
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
DON'T CARE
44
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Clock Suspend Mode
T0
CLK
tCK
T1
tCKS tCKH
tCL
T2
tCH
T3
T4
T5
T6
T7
NOP
NOP
NOP
T8
T9
tCKS tCKH
CKE
tCMS tCMH
COMMAND
READ
NOP
NOP
WRITE
NOP
tCMS tCMH
DQM0 - DQM3
tAS tAH
A0-A9, A11
COLUMN m(2)
tAS tAH
COLUMN n(2)
A10
tAS tAH
BA0, BA1
BANK
BANK
tAC
tAC
DOUT m
DQ
tLZ
tHZ
DOUT m+1
tDS
tDH
DIN e
DIN e+1
tOH
DON'T CARE
UNDEFINED
Notes:
1) Cas latency = 3, Burst Length = 2, Auto Precharge is disabled.
2) x32: A9, A11 = "Don't Care"
45
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PRECHARGE
PRECHARGE Command
The PRECHARGE command (see figure) is used to deactivate the open row in a particular bank or the open row in
all banks.The bank(s) will be available for a subsequent row
access some specified time (trp) after the PRECHARGE
command is issued. Input A10 determines whether one or
all banks are to be precharged, and in the case where only
one bank is to be precharged, inputs BA0, BA1 select the
bank. When all banks are to be precharged, inputs BA0,
BA1 are treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to
that bank.
CLK
CKE
HIGH
CS
RAS
CAS
WE
POWER-DOWN
Power-down occurs if CKE is registered LOW coincident
with a NOP or COMMAND INHIBIT when no accesses
are in progress. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down;
if power-down occurs when there is a row active in either
bank, this mode is referred to as active power-down.
Entering power-down deactivates the input and output
buffers, excluding CKE, for maximum power savings while
in standby. The device may not remain in the power-down
state longer than the refresh period (64ms) since no refresh
operations are performed in this mode.
The power-down state is exited by registering a NOP or
COMMAND INHIBIT and CKE HIGH at the desired clock
edge (meeting tcks). See figure below (Power-Down).
A0-A9, A11
ALL BANKS
A10
BANK SELECT
BA0, BA1
BANK ADDRESS
POWER-DOWN
CLK
≥ tCKS
tCKS
CKE
COMMAND
NOP
All banks idle
NOP
Input buffers gated off
Enter power-down mode
Exit power-down mode
less than TREF
46
ACTIVE
tRCD
tRAS
tRC
DON'T CARE
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Power-Down Mode Cycle
T0
T1
tCK
CLK
tCKS tCKH
T2
tCL
Tn+1
Tn+2
tCH
tCKS
tCKS
CKE
tCMS tCMH
COMMAND
PRECHARGE
NOP
NOP
NOP
ACTIVE
DQM0 - DQM3
ROW
A0-A9, A11
ALL BANKS
A10
ROW
SINGLE BANK
tAS tAH
BA0, BA1
BANK
BANK
DQ High-Z
Two clock cycles
Precharge all
active banks
All banks idle, enter
power-down mode
Input buffers gated
off while in
power-down mode
All banks idle
Exit power-down mode
DON'T CARE
Note:
x32: A9, A11 = "Don't Care"
47
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BURST READ/SINGLE WRITE
SDRAMs support CONCURRENT AUTO PRECHARGE.
Four cases where CONCURRENT AUTO PRECHARGE
occurs are defined below.
The burst read/single write mode is entered by programming
the write burst mode bit (M9) in the mode register to a logic
1. In this mode, all WRITE commands result in the access
of a single column location (burst of one), regardless of
the programmed burst length. READ commands access
columns according to the programmed burst length and
sequence, just as in the normal mode of operation (M9
= 0).
READ with Auto Precharge
1. Interrupted by a READ (with or without auto precharge):
A READ to bank m will interrupt a READ on bank n,
CAS latency later. The PRECHARGE to bank n will
begin when the READ to bank m is registered.
2. Interrupted by a WRITE (with or without auto precharge):
A WRITE to bank m will interrupt a READ on bank n
when registered. DQM should be used three clocks prior
to the WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to
bank m is registered.
CONCURRENT AUTO PRECHARGE
An access command (READ or WRITE) to another bank
while an access command with auto precharge enabled is
executing is not allowed by SDRAMs, unless the SDRAM
supports CONCURRENT AUTO PRECHARGE. ISSI
READ With Auto Precharge interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
NOP
NOP
NOP
NOP
CLK
NOP
COMMAND
BANK n
READ - AP
BANK n
Page Active
READ - AP
BANK m
NOP
READ with Burst of 4
Interrupt Burst, Precharge
Idle
tRP - BANK n
Internal States
BANK m
Page Active
READ with Burst of 4
BANK n,
COL a
ADDRESS
tRP - BANK m
Precharge
BANK n,
COL b
DQ
DOUT a
DOUT a+1
DOUT b
DOUT b+1
CAS Latency - 3 (BANK n)
DON'T CARE
CAS Latency - 3 (BANK m)
READ With Auto Precharge interrupted by a WRITE
T0
T1
T2
T3
NOP
NOP
NOP
T4
T5
T6
T7
NOP
NOP
NOP
CLK
COMMAND
READ - AP
BANK n
BANK n
READ with Burst of 4
Internal States
Interrupt Burst, Precharge
Page Active
BANK m
ADDRESS
WRITE - AP
BANK m
tRP - BANK n
Page Active
WRITE with Burst of 4
BANK n,
COL a
Idle
tDPL - BANK m
Write-Back
BANK m,
COL b
DQM
DOUT a
DQ
CAS Latency - 3 (BANK n)
48
DIN b
DIN b+1
DIN b+2
DIN b+3
DON'T CARE
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WRITE with Auto Precharge
4. Interrupted by a WRITE (with or without auto precharge):
AWRITE to bank m will interrupt a WRITE on bank n when
registered. The PRECHARGE to bank n will begin after
tdpl is met, where tdpl begins when the WRITE to bank
m is registered. The last valid data WRITE to bank n will
be data registered one clock prior to a WRITE to bank m.
3. Interrupted by a READ (with or without auto precharge):
A READ to bank m will interrupt a WRITE on bank n when
registered, with the data-out appearing (CAS latency)
later. The PRECHARGE to bank n will begin after tdpl
is met, where tdpl begins when the READ to bank m is
registered. The last valid WRITE to bank n will be datain registered one clock prior to the READ to bank m.
WRITE With Auto Precharge interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
NOP
NOP
NOP
NOP
CLK
NOP
COMMAND
BANK n
WRITE - AP
BANK n
Page Active
NOP
READ - AP
BANK m
WRITE with Burst of 4
Interrupt Burst, Write-Back
Precharge
tDPL - BANK n
tRP - BANK n
Internal States
BANK m
Page Active
READ with Burst of 4
BANK n,
COL a
ADDRESS
DQ
DIN a
tRP - BANK m
Precharge
BANK m,
COL b
DIN a+1
DOUT b
DOUT b+1
CAS Latency - 3 (BANK m)
DON'T CARE
WRITE With Auto Precharge interrupted by a WRITE
T0
T1
T2
T3
NOP
NOP
T4
T5
T6
T7
NOP
NOP
NOP
CLK
NOP
COMMAND
BANK n
WRITE - AP
BANK n
Page Active
WRITE with Burst of 4
WRITE - AP
BANK m
Interrupt Burst, Write-Back
tDPL - BANK n
Internal States
BANK m
ADDRESS
DQ
Page Active
WRITE with Burst of 4
BANK n,
COL a
DIN a
Precharge
tRP - BANK n
tDPL - BANK m
Write-Back
BANK m,
COL b
DIN a+1
DIN a+2
DIN b
DIN b+1
DIN b+2
DIN b+3
DON'T CARE
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READ WITH AUTO PRECHARGE
T0
CLK
tCK
T1
tCL
T2
T3
tCH
T4
T5
T6
NOP
NOP
T7
T8
NOP
ACTIVE
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
tCMS tCMH
DQM0 - DQM3
tAS tAH
A0-A9, A11
ROW
tAS tAH
A10
ROW
tAS tAH
BA0, BA1
BANK
COLUMN m(2)
ROW
ENABLE AUTO PRECHARGE
ROW
BANK
BANK
tAC
DQ
tRCD
tRAS
tRC
tLZ
CAS Latency
tAC
DOUT m
tAC
DOUT m+1
tAC
DOUT m+2
tHZ
DOUT m+3
tOH
tOH
tOH
tOH
tRP
DON'T CARE
UNDEFINED
Notes:
1) Cas latency = 2, Burst Length = 4
2) x32: A9, A11 = "Don't Care"
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READ WITHOUT AUTO PRECHARGE
T0
CLK
tCK
T1
tCL
T2
tCH
T3
T4
T5
T6
T7
T8
NOP
ACTIVE
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
PRECHARGE
tCMS tCMH
DQM0 - DQM3
tAS tAH
A0-A9, A11
ROW
tAS tAH
A10
ROW
tAS tAH
DISABLE AUTO PRECHARGE
SINGLE BANK
BANK
BANK
BANK
BA0, BA1
COLUMN m(2)
ROW
ALL BANKS
ROW
tAC
DQ
tRCD
tRAS
tRC
tLZ
CAS Latency
BANK
tAC
DOUT m
tAC
DOUT m+1
tAC
DOUT m+2
tHZ
DOUT m+3
tOH
tOH
tOH
tOH
DON'T CARE
tRP
UNDEFINED
Notes:
1) Cas latency = 2, Burst Length = 4
2) x32: A9, A11 = "Don't Care"
51
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 0A
8/14/2014
IS42S32800J, IS45S32800J
SINGLE READ WITH AUTO PRECHARGE
T0
tCK
CLK
T1
tCL
T2
tCH
T3
T4
T5
T6
T7
NOP
NOP
T8
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
NOP
NOP
READ
ACTIVE
NOP
tCMS tCMH
DQM0 - DQM3
tAS
tAH
A0-A9, A11
ROW
tAS tAH
A10
ROW
tAS tAH
BA0, BA1
BANK
COLUMN m(2)
ROW
ENABLE AUTO PRECHARGE
ROW
BANK
BANK
tOH
tAC
DOUT m
DQ
tRCD
tRAS
tRC
tHZ
CAS Latency
tRP
DON'T CARE
UNDEFINED
Notes:
1) Cas latency = 2, Burst Length = 1
2) x32: A9, A11 = "Don't Care"
52
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 0A
8/14/2014
IS42S32800J, IS45S32800J
SINGLE READ WITHOUT AUTO PRECHARGE
T0
CLK
tCK
T1
tCL
T2
tCH
T3
T4
T5
T6
T7
T8
NOP
NOP
PRECHARGE
NOP
ACTIVE
NOP
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
tCMS tCMH
DQM0 - DQM3
tAS tAH
A0-A9, A11
ROW
tAS tAH
A10
ROW
tAS tAH
DISABLE AUTO PRECHARGE
SINGLE BANK
BANK
BANK
BANK
BA0, BA1
COLUMN m(2)
ROW
ALL BANKS
ROW
tAC
BANK
tOH
DOUT m
DQ
tRCD
tRAS
tRC
tLZ
CAS Latency
tHZ
DON'T CARE
tRP
UNDEFINED
Notes:
1) Cas latency = 2, Burst Length = 1
2) x32: A9, A11 = "Don't Care"
53
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 0A
8/14/2014
IS42S32800J, IS45S32800J
WRITE - WITH AUTO PRECHARGE
T0
CLK
tCK
T1
tCL
T2
tCH
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQM0 - DQM3
tAS tAH
A0-A9, A11
ROW
tAS tAH
A10
ROW
tAS tAH
BA0, BA1
BANK
COLUMN m(2)
ROW
ENABLE AUTO PRECHARGE
ROW
BANK
tDS tDH
DQ
DIN m
tRCD
tRAS
tRC
BANK
tDS tDH
DIN m+1
tDS tDH
DIN m+2
tDS
tDH
DIN m+3
tDPL
tRP
DON'T CARE
Notes:
1) Burst Length = 4
2) x32: A9, A11 = "Don't Care"
54
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 0A
8/14/2014
IS42S32800J, IS45S32800J
WRITE - WITHOUT AUTO PRECHARGE
T0
CLK
tCK
T1
tCL
T2
tCH
T3
T4
T5
T6
NOP
NOP
NOP
T7
T8
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
PRECHARGE
NOP
ACTIVE
tCMS tCMH
DQM0 - DQM3
tAS tAH
A0-A9, A11
ROW
tAS tAH
A10
ROW
tAS tAH
BA0, BA1
COLUMN m(2)
ROW
ALL BANKS
ROW
SINGLE BANK
DISABLE AUTO PRECHARGE
BANK
BANK
tDS tDH
DQ
DIN m
tRCD
tRAS
tRC
BANK
tDS tDH
DIN m+1
tDS tDH
DIN m+2
tDS
BANK
tDH
DIN m+3
tDPL(3)
tRP
DON'T CARE
Notes:
1) Burst Length = 4
2) x32: A9, A11 = "Don't Care"
3) tras must not be violated.
55
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 0A
8/14/2014
IS42S32800J, IS45S32800J
SINGLE WRITE WITH AUTO PRECHARGE
T0
tCK
CLK
T1
tCL
T2
tCH
T3
T4
T5
T6
T7
NOP
NOP
NOP
T8
T9
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
NOP
NOP
WRITE
ACTIVE
NOP
tCMS tCMH
DQM0-DQM3
A0-A9, A11
A10
BA0, BA1
tAS tAH
COLUMN m(2)
ROW
tAS tAH
ROW
ENABLE AUTO PRECHARGE
ROW
tAS tAH
ROW
BANK
BANK
BANK
tDS tDH
DQ
DIN m
tRCD
tRAS
tRC
tDPL
tRP
DON'T CARE
Notes:
1) Burst Length = 1
2) x32: A9, A11 = "Don't Care"
56
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 0A
8/14/2014
IS42S32800J, IS45S32800J
SINGLE WRITE - WITHOUT AUTO PRECHARGE
T0
tCK
CLK
T1
tCL
T2
tCH
T3
T4
NOP
NOP
T5
T6
T7
T8
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
PRECHARGE
NOP
ACTIVE
NOP
tCMS tCMH
DQM0 - DQM3
tAS tAH
A0-A9, A11
ROW
tAS tAH
A10
ROW
tAS tAH
BA0, BA1
COLUMN m(2)
ROW
DISABLE AUTO PRECHARGE
ALL BANKS
ROW
SINGLE BANK
BANK
BANK
BANK
BANK
tDS tDH
DQ
DIN m
tRCD
tRAS
tRC
tDPL(3)
tRP
DON'T CARE
Notes:
1) Burst Length = 1
2) x32: A9, A11 = "Don't Care"
3) tras must not be violated.
57
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 0A
8/14/2014
IS42S32800J, IS45S32800J
ORDERING INFORMATION - VDD = 3.3V
Commercial Range: 0°C to +70°C
Frequency
Speed (ns)
Order Part No.
Package
166 MHz
6
IS42S32800J-6TL
86-Pin, TSOP-ll, Lead-free
166 MHz
6
IS42S32800J-6BL
90-Ball TF-BGA, Lead-free
143 MHz
7
IS42S32800J-7TL
86-Pin, TSOP-ll, Lead-free
143 MHz
7
IS42S32800J-7BL
90-Ball TF-BGA, Lead-free
Industrial Range: -40°C to +85°C
Frequency
Speed (ns)
Order Part No.
Package
166 MHz
6
IS42S32800J-6TLI
86-Pin, TSOP-ll, Lead-free
166 MHz
6
IS42S32800J-6BI
90-Ball TF-BGA
166 MHz
6
IS42S32800J-6BLI
90-Ball TF-BGA, Lead-free
143 MHz
7
IS42S32800J-7TLI
86-Pin, TSOP-ll, Lead-free
143 MHz
7
IS42S32800J-7BI
90-Ball TF-BGA
143 MHz
7
IS42S32800J-7BLI
90-Ball TF-BGA, Lead-free
133 MHz
7.5
IS42S32800J-75ETLI
86-Pin, TSOP-ll, Lead-free
133 MHz
7.5
IS42S32800J-75EBLI
90-Ball TF-BGA, Lead-free Automotive Range: -40°C to +85°C
Frequency
Speed (ns)
Order Part No.
Package
166 MHz
6
IS45S32800J-6TLA1
86-Pin, TSOP-ll, Lead-free
166 MHz
6
IS45S32800J-6BLA1
90-Ball TF-BGA, Lead-free 143 MHz
7
IS45S32800J-7TLA1
86-Pin, TSOP-ll, Lead-free
143 MHz
7
IS45S32800J-7BLA1
90-Ball TF-BGA, Lead-free
Automotive Range: -40°C to +105°C
Frequency
Speed (ns)
Order Part No.
Package
143 MHz
7
IS45S32800J-7TLA2
86-Pin, TSOP-ll, Lead-free
143 MHz
7
IS45S32800J-7BLA2
90-Ball TF-BGA, Lead-free
*Contact ISSI for leaded part support.
58
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 0A
8/14/2014
59
0.80
Package Outline
0.45
08/14/2008
1. CONTROLLING DIMENSION : MM .
2. Reference document : JEDEC MO-207
NOTE :
IS42S32800J, IS45S32800J
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 0A
8/14/2014
D1
60
Θ
Package Outline
09/26/2006
4. Formed leads shall be planar with respect to one another within 0.1mm
at the seating plane after final test.
3. Dimension b does not include dambar protrusion/intrusion.
2. Dimension D and E1 do not include mold protrusion .
1. Controlling dimension : mm
NOTE :
Θ
IS42S32800J, IS45S32800J
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 0A
8/14/2014