FSEZ1317 (EZ-PSR for 2-Chip Product) Primary-Side-Regulation PWM with POWER MOSFET Integrated Features Description Low Standby Power Under 30mW Green-Mode: Linearly Decreasing PWM Frequency This third-generation Primary Side Regulation (PSR) and highly integrated PWM controller provides several features to enhance the performance of low-power flyback converters. The proprietary topology, TRUECURRENT™, of FSEZ1317 enables precise CC regulation and simplified circuit design for batterycharger applications. A low-cost, smaller, and lighter charger results, as compared to a conventional design or a linear transformer. Cable Compensation in CV Mode Available in the 7-Lead SOP and DIP Packages High-Voltage Startup Fewest External Component Counts Constant-Voltage (CV) and Constant-Current (CC) Control without Secondary-Feedback Circuitry Fixed PWM Frequency at 50kHz with Frequency Hopping to Solve EMI Problem Peak-Current-Mode Control in CV Mode Cycle-by-Cycle Current Limiting VDD Over-Voltage Protection with Auto Restart VDD Under-Voltage Lockout (UVLO) Gate Output Maximum Voltage Clamped at 15V To minimize standby power consumption, the proprietary green mode provides off-time modulation to linearly decrease PWM frequency under light-load conditions. Green mode assists the power supply in meeting power conservation requirements. By using the FSEZ1317, a charger can be implemented with few external components and minimized cost. A typical output CV/CC characteristic envelope is shown in Figure 1. Fixed Over-Temperature Protection with Auto Restart Applications Battery chargers for cellular phones, cordless phones, PDA, digital cameras, power tools, etc. Replaces linear transformers and RCC SMPS Figure 1. Typical Output V-I Characteristic Ordering Information Part Number Operating Temperature Range Package Packing Method FSEZ1317MY -40°C to +105°C 7-Lead, Small Outline Package (SOP-7) Tape & Reel FSEZ1317NY -40°C to +105°C 7-Lead, Dual Inline Package (DIP-7) Tube © 2009 Fairchild Semiconductor Corporation FSEZ1317 • Rev. 1.0.4 www.fairchildsemi.com FSEZ1317 — Primary-Side-Regulation PWM with POWER MOSFET Integrated May 2010 Rsn L1 T1 Rsn2 D1 DF Csn D4 CO1 RF Rsn1 AC Input C1 D2 Csn2 D3 CO2 Rd DC Output Dsn C2 CVDD DFa R1 CVS 7 HV DRAIN 8 1 CS 3 GND R2 VS 5 2 VDD COMR 4 RSENSE CCR Figure 2. Typical Application Internal Block Diagram Figure 3. Functional Block Diagram © 2009 Fairchild Semiconductor Corporation FSEZ1317 • Rev. 1.0.4 www.fairchildsemi.com 2 FSEZ1317 — Primary-Side-Regulation PWM with POWER MOSFET Integrated Application Diagram F: Fairchild Logo Z: Plant Code X: 1-Digit Year Code Y: 1-Digit Week Code TT: 2-Digit Die Run Code T: Package Type (M=SOP, N=DIP) P: Y=Green Package M: Manufacture Flow Code Figure 4. Top Mark Pin Configuration Figure 5. SOP and Dip Pin Configuration Pin Definitions Pin # Name Description 1 CS Current Sense. This pin connects a current-sense resistor, to detect the MOSFET current for peak-current-mode control in CV mode, and provides the output-current regulation in CC mode. 2 VDD Power Supply. IC operating current and MOSFET driving current are supplied using this pin. This pin is connected to an external VDD capacitor of typically 10µF. The threshold voltages for startup and turn-off are 16V and 5V, respectively. The operating current is lower than 5mA. 3 GND Ground 4 COMR Cable Compensation. This pin connects a 1µF capacitor between the COMR and GND pins for compensation voltage drop due to output cable loss in CV mode. 5 VS Voltage Sense. This pin detects the output voltage information and discharge time based on voltage of auxiliary winding. 7 HV High Voltage. This pin connects to bulk capacitor for high-voltage startup. 8 DRAIN Driver Output. Power MOSFET drain. This pin is the high-voltage power MOSFET drain. © 2009 Fairchild Semiconductor Corporation FSEZ1317 • Rev. 1.0.4 www.fairchildsemi.com 3 FSEZ1317 — Primary-Side-Regulation PWM with POWER MOSFET Integrated Marking Information Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VHV Parameter HV Pin Input Voltage (1,2) VVDD DC Supply Voltage VVS VS Pin Input Voltage VCS Min. -0.3 Max. Units 500 V 30 V 7.0 V CS Pin Input Voltage -0.3 7.0 V VCOMV Voltage Error Amplifier Output Voltage -0.3 7.0 V VCOMI Current Error Amplifier Output Voltage -0.3 7.0 V VDS Drain-Source Voltage 700 V TA=25°C 1 A TA=100°C 0.6 A ID Continuous Drain Current IDM Pulsed Drain Current 4 A EAS Single Pulse Avalanche Energy 50 mJ IAR Avalanche Current 1 A PD Power Dissipation (TA＜50°C) 660 mW θJA Thermal Resistance (Junction-to-Air) 150 °C/W DIP 95 °C/W SOP 39 °C/W DIP 25 °C/W +150 °C ΨJT TJ TSTG TL ESD SOP Thermal Resistance (Junction-to-Case) Operating Junction Temperature -40 Storage Temperature Range -55 Lead Temperature (Reflow, 3 Cycles) Electrostatic Discharge Capability (Except HV Pin) +150 °C +260 °C Human Body Model, JEDEC-JESD22_A114 3500 Charged Device Model, JEDEC-JESD22_C101 1250 V Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltage values, except differential voltages, are given with respect to the GND pin. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol TA Parameter Operating Ambient Temperature © 2009 Fairchild Semiconductor Corporation FSEZ1317 • Rev. 1.0.4 Min. Max. Units -40 +105 °C www.fairchildsemi.com 4 FSEZ1317 — Primary-Side-Regulation PWM with POWER MOSFET Integrated Absolute Maximum Ratings Unless otherwise specified, VDD=15V and TA=25℃. Symbol Parameter Conditions Min. Typ. Max. Units VDD Section VOP Continuously Operating Voltage 23 V VDD-ON Turn-On Threshold Voltage 15 16 17 V VDD-OFF Turn-Off Threshold Voltage 4.5 5.0 5.5 V Operating Current 2.5 5.0 mA IDD-GREEN Green-Mode Operating Supply Current 0.95 1.20 mA VDD-OVP VDD Over-Voltage-Protection Level (OVP) IDD-OP VDD-OVP-HYS tD-VDDOVP 24 V Hysteresis Voltage for VDD OVP 1.5 2.0 2.5 V VDD Over-Voltage-Protection Debounce Time 50 200 300 µs HV Startup Current Source Section VHV-MIN Minimum Startup Voltage on HV Pin 50 V IHV Supply Current Drawn from HV Pin VDC=100V 1.5 3.0 mA Leakage Current after Startup HV=500V, VDD= VDDOFF+1V 0.96 3.00 µA IHV-LC Oscillator Section fOSC fOSC-N-MIN fOSC-CM-MIN Frequency Center Frequency Frequency Hopping Range 47 50 53 ±1.5 ±2.0 ±2.5 Minimum Frequency at No-Load 370 Minimum Frequency at CCM Hz 13 fDV Frequency Variation vs. VDD Deviation VDD=10~25V, fDT Frequency Variation vs. Temperature Deviation TA=-40°C to 105°C 1 kHz kHz 2 % 15 % Voltage-Sense Section Itc VBIAS-COMV IC Bias Current Adaptive Bias Voltage Dominated by VCOMV RVS=20kΩ 10 µA 1.4 V Current-Sense Section tPD tMIN-N VTH Propagation Delay to GATE Output Minimum On Time at No-Load 700 Threshold Voltage for Current Limit 90 200 ns 850 1050 ns 0.8 V Voltage-Error-Amplifier Section VVR Reference Voltage VN Green-Mode Starting Voltage on EA_V fOSC-2kHz 2.475 2.500 2.5 2.525 V V VG Green-Mode Ending Voltage on EA_V fOSC=1kHz 0.4 V Current-Error-Amplifier Section VIR Reference Voltage 2.475 2.500 2.525 V Cable Compensation Section VCOMR COMR Pin for Cable Compensation 0.75 V Continued on the following page… © 2009 Fairchild Semiconductor Corporation FSEZ1317 • Rev. 1.0.4 www.fairchildsemi.com 5 FSEZ1317 — Primary-Side-Regulation PWM with POWER MOSFET Integrated Electrical Characteristics Unless otherwise specified, VDD=15V and TA=25℃. Symbol Parameter Conditions Min. Typ. Max. Units 70 75 80 % (3) Internal MOSFET Section DCYMAX BVDSS ∆BVDSS/∆TJ RDS(ON) IS IDSS Maximum Duty Cycle Drain-Source Breakdown Voltage ID=250μA, VGS=0V Breakdown Voltage Temperature Coefficient ID=250μA, Referenced to TA=25°C Static Drain-Source On-Resistance ID=0.5A, VGS=10V 700 V 0.53 13 16 Ω 1 A VDS=700V, TA=25°C 10 µA VDS=560V, TA=100°C 100 µA 10 30 ns 20 50 ns 175 200 pF 23 25 pF Maximum Continuous Drain-Source Diode Forward Current Drain-Source Leakage Current tD-ON Turn-On Delay Time tD-OFF Turn-Off Delay Time CISS Input Capacitance COSS Output Capacitance V/°C VDS=350V, ID=1A, (4) RG=25Ω VGS=0V, VDS=25V, fS=1MHz Over-Temperature-Protection Section TOTP Threshold Temperature for OTP (5) +140 °C Notes: 3. These parameters, although guaranteed, are not 100% tested in production. 4. Pulse test: pulsewidth ≦ 300µs, duty cycle ≦ 2%. 5. When the Over-temperature protection is activated, the power system enter latch mode and output is disabled. © 2009 Fairchild Semiconductor Corporation FSEZ1317 • Rev. 1.0.4 www.fairchildsemi.com 6 FSEZ1317 — Primary-Side-Regulation PWM with POWER MOSFET Integrated Electrical Characteristics (Continued) 5.5 16.6 5.3 VDD_OFF (V) VDD_ON (V) 17 16.2 15.8 15.4 5.1 4.9 4.7 15 4.5 -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 0 Temperature (ºC) Turn-On Threshold Voltage (VDD-ON) vs. Temperature Figure 7. 5 54 4.2 52 Fosc (KHz) IDD_OP (mA) Figure 6. 3.4 2.6 1.8 50 75 85 100 125 Turn-Off Threshold Voltage (VDD-OFF) vs. Temperature 50 48 46 1 44 -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 Temperature (ºC) Figure 8. 0 25 50 75 85 100 125 Temperature (ºC) Operating Current (IDD-OP) vs. Temperature Figure 9. 2.525 1.2 2.515 1.12 IDD_Green (mA) VVR (V) 25 Temperature (ºC) 2.505 2.495 2.485 Center Frequency (fOSC) vs. Temperature 1.04 0.96 0.88 2.475 0.8 -40 -30 -15 0 25 50 75 85 100 125 -40 Temperature (ºC) -15 0 25 50 75 85 100 125 Temperature (ºC) Figure 10. Reference Voltage (VVR) vs. Temperature © 2009 Fairchild Semiconductor Corporation FSEZ1317 • Rev. 1.0.4 -30 Figure 11. Green Mode Operating Supply Current (IDD-GREEN) vs. Temperature www.fairchildsemi.com 7 FSEZ1317 — Primary-Side-Regulation PWM with POWER MOSFET Integrated Typical Performance Characteristics 15 420 14.2 Fosc_CM_MIN (KHz) Fosc_Green (Hz) 450 390 360 330 13.4 12.6 11.8 300 11 -40 -30 -15 0 25 50 75 85 100 -40 125 -30 -15 0 Temperature (ºC) 50 75 85 100 125 Figure 13. Minimum Frequency at CCM (fOSC-CM-MIN) vs. Temperature 3 1050 2.4 980 T MIN_N (ns) IHV (mA) Figure 12. Minimum Frequency at No Load (fOSC-N-MIN) vs. Temperature 1.8 1.2 910 840 770 0.6 700 0 -40 -30 -15 0 25 50 75 85 100 -40 125 -30 -15 0 25 50 75 85 100 125 Temperature (ºC) Temperature (ºC) Figure 14. Supply Current Drawn from HV Pin (IHV) vs. Temperature Figure 15. Minimum On Time at No Load (tMIN-N) vs. Temperature 2.55 0.65 2.52 0.56 2.49 0.47 V g (V) V n (V) 25 Temperature (ºC) 2.46 2.43 0.38 0.29 2.4 0.2 -40 -30 -15 0 25 50 75 85 100 125 -40 Temperature (ºC) Figure 16. Green Mode Starting Voltage on EA_V (VN) vs. Temperature © 2009 Fairchild Semiconductor Corporation FSEZ1317 • Rev. 1.0.4 -30 -15 0 25 50 75 85 100 125 Temperature (ºC) Figure 17. Green Mode Ending Voltage on EA_V (VG) vs. Temperature www.fairchildsemi.com 8 FSEZ1317 — Primary-Side-Regulation PWM with POWER MOSFET Integrated Typical Performance Characteristics (Continued) 11 1.5 10.5 VBIAS_COMV (V) 1.42 ITC (uA) 10 9.5 9 1.34 1.26 1.18 8.5 8 1.1 -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 0 Temperature (ºC) 50 75 85 100 125 Figure 19. Adaptive Bias Voltage Dominated by VCOMV (VBIAS-COMV) vs. Temperature 0.82 3 0.815 2.5 0.81 2 IHV_LC (uA) V TH (V) Figure 18. IC Bias Current (Itc) vs. Temperature 0.805 0.8 0.795 1.5 1 0.5 0.79 0 -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 0 Temperature (ºC) 25 50 75 85 100 125 Temperature (ºC) Figure 20. Threshold Voltage for Current Limit (VTH) vs. Temperature Figure 21. Leakage Current after Startup (IHV-LC) vs. Temperature 80 0.82 0.8 78 0.78 DCYMax (%) VCOMR (V) 25 Temperature (ºC) 0.76 0.74 76 74 72 0.72 70 0.7 -40 -30 -15 0 25 50 75 85 100 125 -40 Temperature (ºC) -15 0 25 50 75 85 100 125 Temperature (ºC) Figure 22. Variation Test Voltage on COMR Pin for Cable Compensation (VCOMR) vs. Temperature © 2009 Fairchild Semiconductor Corporation FSEZ1317 • Rev. 1.0.4 -30 Figure 23. Maximum Duty Cycle (DCYMAX) vs. Temperature www.fairchildsemi.com 9 FSEZ1317 — Primary-Side-Regulation PWM with POWER MOSFET Integrated Typical Performance Characteristics (Continued) Figure 24 shows the basic circuit diagram of primaryside regulated flyback converter, with typical waveforms shown in Figure 25. Generally, discontinuous conduction mode (DCM) operation is preferred for primary-side regulation because it allows better output regulation. The operation principles of DCM flyback converter are as follows: constant current regulation mode, VCOMI determines the duty cycle while VCOMV is saturated to HIGH. ID Np:Ns IO D During the MOSFET on time (tON), input voltage (VDL) is applied across the primary-side inductor (Lm). Then MOSFET current (Ids) increases linearly from zero to the peak value (Ipk). During this time, the energy is drawn from the input and stored in the inductor. + V DL VAC Lm + + VF - VO - L O A D - Ids When the MOSFET is turned off, the energy stored in the inductor forces the rectifier diode (D) to be turned on. While the diode is conducting, the output voltage (Vo), together with diode forward-voltage drop (VF), is 2 applied across the secondary-side inductor (Lm×Ns / 2 Np ) and the diode current (ID) decreases linearly from the peak value (Ipk×Np/Ns) to zero. At the end of inductor current discharge time (tDIS), all the energy stored in the inductor has been delivered to the output. EA_I V COMI IO Estimator CS RCS Ref t DIS Detector PWM Control V COMV VS EA_V RS1 Ref RS2 Primary-Side Regulation Controller When the diode current reaches zero, the transformer auxiliary winding voltage (Vw) begins to oscillate by the resonance between the primary-side inductor (Lm) and the effective capacitor loaded across the MOSFET. NA VDD VO Estimator + Vw - Figure 24. Simplified PSR Flyback Converter Circuit During the inductor current discharge time, the sum of output voltage and diode forward-voltage drop is reflected to the auxiliary winding side as (Vo+VF) × Na/Ns. Since the diode forward-voltage drop decreases as current decreases, the auxiliary winding voltage reflects the output voltage best at the end of diode conduction time where the diode current diminishes to zero. Thus, by sampling the winding voltage at the end of the diode conduction time, the output voltage information can be obtained. The internal error amplifier for output voltage regulation (EA_V) compares the sampled voltage with internal precise reference to generate error voltage (VCOMV), which determines the duty cycle of the MOSFET in CV mode. I pk I pk ⋅ NP NS I D .avg = I o Meanwhile, the output current can be estimated using the peak drain current and inductor current discharge time because output current is same as the average of the diode current in steady state. VF ⋅ The output current estimator picks up the peak value of the drain current with a peak detection circuit and calculates the output current using the inductor discharge time (tDIS) and switching period (ts). This output information is compared with internal precise reference to generate error voltage (VCOMI), which determines the duty cycle of the MOSFET in CC mode. With Fairchild’s innovative technique TRUECURRENT™, constant current (CC) output can be precisely controlled. NA NS VO ⋅ NA NS Figure 25. Key Waveforms of DCM Flyback Converter Among the two error voltages, VCOMV and VCOMI, the smaller one determines the duty cycle. Therefore, during constant voltage regulation mode, VCOMV determines the duty cycle while VCOMI is saturated to HIGH. During © 2009 Fairchild Semiconductor Corporation FSEZ1317 • Rev. 1.0.4 www.fairchildsemi.com 10 FSEZ1317 — Primary-Side-Regulation PWM with POWER MOSFET Integrated Functional Description In cellular phone charger applications, the battery is located at the end of cable, which typically causes several percentage of voltage drop on the battery voltage. FSEZ1317 has a built-in cable voltage drop compensation that provides a constant output voltage at the end of the cable over the entire load range in CV mode. As load increases, the voltage drop across the cable is compensated by increasing the reference voltage of the voltage regulation error amplifier. Operating Current The FSEZ1317 operating current is as small as 2.5mA, which results in higher efficiency and reduces the VDD hold-up capacitance requirement. Once FSEZ1317 enters “deep” green mode, the operating current is reduced to 0.95mA, assisting the power supply in meeting power conservation requirements. Green-Mode Operation The FSEZ1317 uses voltage regulation error amplifier output (VCOMV) as an indicator of the output load and modulates the PWM frequency as shown in Figure 26. The switching frequency decreases as the load decreases. In heavy load conditions, the switching frequency is fixed at 50kHz. Once VCOMV decreases below 2.5V, the PWM frequency linearly decreases from 50kHz. When FSEZ1317 enters deep green mode, the PWM frequency is reduced to a minimum frequency of 370Hz, thus gaining power saving to meet international power conservation requirements. Figure 27. Frequency Hopping High-Voltage Startup Figure 28 shows the HV-startup circuit for FSEZ1317 applications. The HV pin is connected to the line input or bulk capacitor through a resistor, RSTART (100kΩ recommended). During startup status, the internal startup circuit is enabled. Meanwhile, line input supplies the current, ISTARTUP, to charge the hold-up capacitor, CDD, through RSTART. When the VDD voltage reaches VDD-ON, the internal startup circuit is disabled, blocking ISTARTUP from flowing into the HV pin. Once the IC turns on, CDD is the only energy source to supply the IC consumption current before the PWM starts to switch. Thus, CDD must be large enough to prevent VDD from dropping down to VDD-OFF before the power can be delivered from the auxiliary winding. Figure 26. Switching Frequency in Green Mode Frequency Hopping 1 8 EMI reduction is accomplished by frequency hopping, which spreads the energy over a wider frequency range than the bandwidth measured by the EMI test equipment. FSEZ1317 has an internal frequency hopping circuit that changes the switching frequency between 47kHz and 53kHz over the period shown in Figure 27. 2 7 3 4 5 Figure 28. HV Startup Circuit © 2009 Fairchild Semiconductor Corporation FSEZ1317 • Rev. 1.0.4 www.fairchildsemi.com 11 FSEZ1317 — Primary-Side-Regulation PWM with POWER MOSFET Integrated Cable Voltage Drop Compensation The turn-on and turn-off thresholds are fixed internally at 16V and 5V, respectively. During startup, the hold-up capacitor must be charged to 16V through the startup resistor to enable the FSEZ1317. The hold-up capacitor continues to supply VDD until power can be delivered from the auxiliary winding of the main transformer. VDD is not allowed to drop below 5V during this startup process. This UVLO hysteresis window ensures that hold-up capacitor properly supplies VDD during startup. Pulse-by-pulse Current Limit When the sensing voltage across the current-sense resistor exceeds the internal threshold of 0.8V, the MOSFET is turned off for the remainder of switching cycle. In normal operation, the pulse-by-pulse current limit is not triggered since the peak current is limited by the control loop. Leading-Edge Blanking (LEB) Each time the power MOSFET switches on, a turn-on spike occurs at the sense resistor. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period, the current-limit comparator is disabled and cannot switch off the gate driver. As a result conventional RC filtering can be omitted. Protections The FSEZ1317 has several self-protection functions, such as Over-Voltage Protection (OVP), OverTemperature Protection (OTP), and pulse-by-pulse current limit. All the protections are implemented as auto-restart mode. Once the abnormal condition occurs, the switching is terminated and the MOSFET remains off, causing VDD to drop. When VDD drops to the VDD turn-off voltage of 5V, internal startup circuit is enabled again and the supply current drawn from the HV pin charges the hold-up capacitor. When VDD reaches the turn-on voltage of 16V, normal operation resumes. In this manner, the auto-restart alternately enables and disables the switching of the MOSFET until the abnormal condition is eliminated (see Figure 29). Gate Output The FSEZ1317 output stage is a fast totem-pole gate driver. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 15V Zener diode to protect the power MOSFET transistors against undesired over-voltage gate signals. Built-In Slope Compensation The sensed voltage across the current-sense resistor is used for current mode control and pulse-by-pulse current limiting. Built-in slope compensation improves stability and prevents sub-harmonic oscillations due to peak-current mode control. The FSEZ1317 has a synchronized, positive-slope ramp built-in at each switching cycle. Noise Immunity Noise from the current sense or the control signal can cause significant pulsewidth jitter, particularly in continuous-conduction mode. While slope compensation helps alleviate these problems, further precautions should still be taken. Good placement and layout practices should be followed. Avoiding long PCB traces and component leads, locating compensation and filter components near the FSEZ1317, and increasing the power MOS gate resistance are advised. Figure 29. Auto-Restart Operation VDD Over-Voltage Protection (OVP) VDD over-voltage protection prevents damage from overvoltage conditions. If the VDD voltage exceeds 24V at open-loop feedback condition, OVP is triggered and the PWM switching is disabled. The OVP has a debounce time (typically 200µs) to prevent false triggering due to switching noises. © 2009 Fairchild Semiconductor Corporation FSEZ1317 • Rev. 1.0.4 www.fairchildsemi.com 12 FSEZ1317 — Primary-Side-Regulation PWM with POWER MOSFET Integrated Over-Temperature Protection (OTP) The built-in temperature-sensing circuit shuts down PWM output if the junction temperature exceeds 140°C. Under-Voltage Lockout (UVLO) Application Fairchild Devices Input Voltage Range Output Output DC cable Cell Phone Charger FSEZ1317 (SOP-7) 90~265VAC 5V/0.7A (3.5W) AWG26, 1.8 Meter Features High efficiency (>65.5% at full load) meeting EPS 2.0 regulation with enough margin Low standby (Pin<30mW at no-load condition) Figure 30. Measured Efficiency Figure 31. Standby Power Figure 32. Schematic of Typical Application Circuit © 2009 Fairchild Semiconductor Corporation FSEZ1317 • Rev. 1.0.4 www.fairchildsemi.com 13 FSEZ1317 —Primary-Side-Regulation PWM with POWER MOSFET Integrated Typical Application Circuit (Primary-Side Regulated Flyback Charger) Transformer Specification Core: EE16 Bobbin: EE16 Figure 33. Transformer Specification Notes: 6. When W4R’s winding is reversed winding, it must wind one layer. 7. When W2 is winding, it must wind three layers and put one layer of tape after winding the first layer. No. Terminal Insulation Wire ts 15 2 41 1 39 0 37 2 S F W1 4 5 2UEW 0.23*2 W2 3 1 2UEW 0.17*1 ts W3 1 - COPPER SHIELD 1.2 3 W4 7 9 TEX-E 0.55*1 9 3 CORE ROUNDING TAPE Barrier Tape Primary Seconds 3 Pin Specification Remark Primary-Side Inductance 1－3 2.25mH ± 7% 100kHz, 1V Primary-Side Effective Leakage 1－3 80μH ± 5% Short One of the Secondary Windings © 2009 Fairchild Semiconductor Corporation FSEZ1317 • Rev. 1.0.4 www.fairchildsemi.com 14 FSEZ1317 — Primary-Side-Regulation PWM with POWER MOSFET Integrated Typical Application Circuit (Continued) FSEZ1317 — Primary-Side-Regulation PWM with POWER MOSFET Integrated Physical Dimensions Figure 34. 7-Lead, Small Outline Package (SOP-7) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2009 Fairchild Semiconductor Corporation FSEZ1317 • Rev. 1.0.4 www.fairchildsemi.com 15 FSEZ1317 — Primary-Side-Regulation PWM with POWER MOSFET Integrated Physical Dimensions 9.40 9.00 7 5 6.60 6.20 1 4 (0.56) 3.60 3.20 5.08 MAX 7.62 0.33 3.60 3.00 2.54 0.56 0.36 0.35 0.20 1.62 1.42 9.91 7.62 7.62 NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE COMPLIES TO JEDEC MS-001, VARIATION BA, EXCEPT FOR TERMINAL COUNT (7 RATHER THAN 8) B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994 E) DRAWING FILENAME AND REVISION: MKT-NA07BREV2 Figure 35. 7-Lead, Dual inline Package (DIP-7) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2009 Fairchild Semiconductor Corporation FSEZ1317 • Rev. 1.0.4 www.fairchildsemi.com 16 FSEZ1317 — Primary-Side-Regulation PWM with POWER MOSFET Integrated © 2009 Fairchild Semiconductor Corporation FSEZ1317 • Rev. 1.0.4 www.fairchildsemi.com 17