Cypress CY7C43683AV-7AC 3.3v 1k/4k/16k x36 unidirectional synchronous fifo with bus matching Datasheet

CY7C43663AV
CY7C43643AV
CY7C43683AV
3.3V 1K/4K/16K x36 Unidirectional Synchronous
FIFO with Bus Matching
Features
— ICC = 60 mA
— ISB = 10 mA
• Fully asynchronous and simultaneous Read and Write
operation permitted
• Mailbox bypass register for each FIFO
• Parallel and serial programmable Almost Full and
Almost Empty flags
• Retransmit function
• Standard or FWFT user selectable mode
• Partial reset
• Big or Little Endian format for word or byte bus sizes
• 128-pin TQFP packaging
• Easily expandable in width and depth
• High-speed, low-power, unidirectional, First-In
First-Out (FIFO) memories with bus-matching capabilities
• 1K × 36 (CY7C43643AV)
• 4K × 36 (CY7C43663AV)
• 16K × 36 (CY7C43683AV)
• 0.25-micron CMOS for optimum speed/power
• High-speed 133-MHz operation (7.5-ns Read/Write
cycle times)
• Low power
Logic Block Diagram
MBF1
CLKA
MBA
RT
MRS1
MRS2
PRS
FIFO,
Mail1
Mail2
Reset
Logic
Port B
Control
Logic
EF/OR
AE
Status
Flag Logic
AF
36
Programmable
Flag Offset
Registers
36
CLKB
CSB
W/RB
ENB
MBB
BM
SIZE
Read
Pointer
Write
Pointer
FF/IR
SPM
FS0/SD
FS1/SEN
A0–35
1K/4K/16K
× 36
Dual Ported
Memory
Input
Register
ENA
Output
Register
Port A
Control
Logic
W/RA
Bus Matching
Mail1
Register
CSA
Timing
Mode
B0–35
BE/FWFT
Mail2
Register
MBF2
Cypress Semiconductor Corporation
Document #: 38-06024 Rev. *C
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 26, 2002
CY7C43663AV
CY7C43643AV
CY7C43683AV
Pin Configuration[1]
EF/OR
NC
GND
CSB
W/RB
ENB
MBF1
VCC
AE
NC
VCC
AF
NC
MBF2
MBA
MRS1
FS0/SD
NC
GND
FS1/SEN
MRS2
MBB
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
CSA
FF/IR
NC
PRS
TQFP
Top View
W/RA
ENA
CLKA
GND
A35
A34
A33
A32
VCC
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
BE/FWFT
GND
A22
VCC
A21
A20
A19
A18
CY7C43643AV
CY7C43663AV
CY7C43683AV
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
CLKB
NC
VCC
B35
B34
B33
B32
GND
NC
B31
B30
B29
B28
B27
B26
RT
B25
B24
BM
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
SIZE
VCC
B15
B14
B13
B12
GND
B11
B10
GND
B6
VCC
B7
B8
B9
B2
B3
B4
B5
GND
A5
A4
A3
SPM
VCC
A2
A1
A0
GND
B0
B1
A9
A8
A7
A6
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
GND
A17
A16
A15
A14
A13
NC
A12
GND
A11
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Note:
1. Pin-compatible to IDT723623/33/43 family.
Document #: 38-06024 Rev. *C
Page 2 of 28
CY7C43663AV
CY7C43643AV
CY7C43683AV
Functional Description
The CY7C436X3AV is a monolithic, high-speed, low-power,
CMOS Unidirectional Synchronous FIFO memory which
supports clock frequencies up to 133 MHz and has Read
access times as fast as 6 ns.
The CY7C436X3AV is a synchronous (clocked) FIFO,
meaning each port employs a synchronous interface. All data
transfers through a port are gated to the LOW-to-HIGH
transition of a port clock by enable signals. The clocks for each
port are independent of one another and can be asynchronous
or coincident. The enables for each port are arranged to
provide a simple unidirectional interface between microprocessors and/or buses with synchronous control.
Communication between each port may bypass the FIFOs via
two mailbox registers. The mailbox registers’ width matches
the selected Port B bus width. Each mailbox register has a flag
(MBF1 and MBF2) to signal when new mail has been stored.
Two kinds of reset are available on the CY7C436X3AV: Master
Reset and Partial Reset. Master Reset initializes the Read and
Write pointers to the first location of the memory array,
configures the FIFO for Big or Little Endian byte arrangement,
and selects serial flag programming, parallel flag
programming, or one of the three possible default flag offset
settings, 8, 16, or 64. The FIFO also has two Master Reset
pins, MRS1 and MRS2.
Partial Reset also sets the Read and Write pointers to the first
location of the memory. Unlike Master Reset, any settings
existing prior to Partial Reset (i.e., programming method and
partial flag default offsets) are retained. Partial Reset is useful
since it permits flushing of the FIFO memory without changing
any configuration settings. The FIFO has its own independent
Partial Reset pin, PRS.
The CY7C436X3AV have two modes of operation: In the CY
Standard mode, the first word written to an empty FIFO is
deposited into the memory array. A Read operation is required
to access that word (along with all other words residing in
memory). In the First-Word Fall-Through Mode (FWFT), the
first long-word (36-bit-wide) written to an empty FIFO appears
automatically on the outputs, no Read operation required
(nevertheless, accessing subsequent words does necessitate
a formal Read request). The state of the FWFT/STAN pin
during FIFO operation determines the mode in use.
The FIFO has a combined Empty/Output Ready flag (EF/OR)
and a combined Full/Input Ready flag (FF/IR). The EF and FF
functions are selected in the CY Standard mode. EF indicates
whether the memory is empty or not. FF indicates whether the
memory is full. The IR and OR functions are selected in the
First-Word Fall-Through Mode. IR indicates whether or not the
FIFO has available memory locations. OR shows whether the
FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.
The FIFO has a programmable Almost Empty flag (AE) and a
programmable Almost Full flag (AF). AE indicates when a
selected number of words written to FIFO memory achieve a
predetermined “almost empty state.” AF indicates when a
selected number of words written to the memory achieve a
predetermined “almost full state.”[2]
FF/IR and AF are synchronized to the port clock that writes
data into its array. EF/OR and AE are synchronized to the port
clock that reads data from its array. Programmable offset for
AE and AF are loaded in parallel using Port A or in serial via
the SD input. Three default offset settings are also provided.
The AE threshold can be set at 8, 16, or 64 locations from the
empty boundary and AF threshold can be set at 8, 16, or 64
locations from the full boundary. All these choices are made
using the FS0 and FS1 inputs during Master Reset.
Two or more devices may be used in parallel to create wider
data paths.
The CY7C436X3AV are characterized for operation from
0°C – 70°C commercial and from –40°C – 85°C industrial.
Input ESD protection is greater than 2001V, and latch-up is
prevented by the use of guard rings.
Selection Guide
CY7C43643/63/83AV CY7C43643/63/83AV CY7C43643/63/83AV
–7
–10
–15
Maximum Frequency
133
100
66.7
MHz
6
8
10
ns
Maximum Access Time
Minimum Cycle Time
Unit
7.5
10
15
ns
Minimum Data or Enable Set-Up
3
4
5
ns
Minimum Data or Enable Hold
0
0
0
ns
Maximum Flag Delay
6
8
10
ns
60
60
60
mA
Active Power Supply
Current (ICC1)
Commercial
Industrial
60
CY7C43643AV
CY7C43663AV
CY7C43683AV
Density
1K × 36
4K × 36
16K × 36
Package
128 TQFP
128 TQFP
128 TQFP
Note:
2. When FIFO is operated at the almost empty/full boundary, there may be an uncertainty of up to two clock cycles for flag deassertion, but the flag will always
be asserted exactly when the FIFO content reaches the programmed value. Use the assertion edge for trigger if flag accuracy is required. Refer to Cypress’s
application note entitled “Designing with CY7C436xx Synchronous FIFOs” for more details on flag uncertainties.
Document #: 38-06024 Rev. *C
Page 3 of 28
CY7C43663AV
CY7C43643AV
CY7C43683AV
Pin Definitions
Signal Name
Description
I/O
Function
A0–35
Port A Data
I
36-bit unidirectional data port for side A.
AE
Almost Empty
Flag (Port B)
O
Programmable Almost Empty flag synchronized to CLKB. It is LOW when the
number of words in the FIFO is less than or equal to the value in the Almost Empty offset
register, X.[2]
AF
Almost Full Flag
O
Programmable Almost Full flag synchronized to CLKA. It is LOW when the number
of empty locations in the FIFO is less than or equal to the value in the Almost Full offset
register, Y.[2]
B0–35
Port B Data
O
36-bit unidirectional data port for side B.
BE/FWFT
Big
Endian/First-Wor
d Fall-Through
Select
I
This is a dual-purpose pin. During Master Reset, a HIGH on BE will select Big Endian
operation. In this case, depending on the bus size, the most significant byte or word on
Port A is transferred to Port B first. A LOW on BE will select Little Endian operation. In
this case, the least significant byte or word on Port A is transferred to Port B first. After
Master Reset, this pin selects the timing mode. A HIGH on FWFT selects CY Standard
mode, a LOW selects First-Word Fall-Through Mode. Once the timing mode has been
selected, the level on FWFT must be static throughout device operation.
BM
Bus Match
Select (Port B)
I
A HIGH on this pin enables either byte or word bus width on Port B, depending on
the state of SIZE. A LOW selects long-word operation. BM works with SIZE and BE to
select the bus size and endian arrangement for Port B. The level of BM must be static
throughout device operation.
CLKA
Port A Clock
I
CLKA is a continuous clock that synchronizes all data transfers through Port A
and can be asynchronous or coincident to CLKB. FF/IR and AF are all synchronized to
the LOW-to-HIGH transition of CLKA.
CLKB
Port B Clock
I
CLKB is a continuous clock that synchronizes all data transfers through Port B
and can be asynchronous or coincident to CLKA. EF/OR and AE are synchronized to
the LOW-to-HIGH transition of CLKB.
CSA
Port A Chip
Select
I
CSA must be LOW to enable a LOW-to HIGH transition of CLKA to read (from Mail2
register) or write on Port A. The A0–35 outputs are in the high-impedance state when
CSA is HIGH.
CSB
Port B Chip
Select
I
CSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write
(into Mail2 register) on Port B. The B0–35 outputs are in the high-impedance state when
CSB is HIGH.
EF/OR
Empty/Output
Ready Flag (Port
B)
O
This is a dual-function pin. In the CY Standard mode, the EF function is selected. EF
indicates whether or not the FIFO memory is empty. In the FWFT mode, the OR function
is selected. OR indicates the presence of valid data on B0–35 outputs, available for
reading. EF/OR is synchronized to the LOW-to-HIGH transition of CLKB.
ENA
Port A Enable
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read (from Mail2
register) or write data on Port A.
ENB
Port B Enable
I
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write (to
Mail2 register) data on Port B.
FF/IR
Port B Full/Input
Ready Flag
O
This is a dual-function pin. In the CY Standard mode, the FF function is selected. FF
indicates whether or not the FIFO memory is full. In the FWFT mode, the IR function is
selected. IR indicates whether or not there is space available for writing to the FIFO
memory. FF/IR is synchronized to the LOW-to-HIGH transition of CLKA.
FS1/SEN
Flag Offset
Select 1/Serial
Enable
I
FS0/SD
Flag Offset
Select 0/Serial
Data
I
FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register
programming. During Master Reset, FS1/SEN and FS0/SD, together with SPM, select
the flag offset programming method. Three offset register programming methods are
available: automatically load one of three preset values (8, 16, or 64), parallel load from
Port A, and serial load. When serial load is selected for flag offset register programming,
FS1/SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA.
When FS1/SEN is LOW, a rising edge on CLKA loads the bit present on FS0/SD into
the X and Y registers. The number of bit writes required to program the offset registers
is 20 for the CY7C43643AV, 24 for the CY7C43663AV, and 28 for the CY7C43683AV.
The first bit Write stores the Y-register MSB and the last bit Write stores the X-register
LSB.
Document #: 38-06024 Rev. *C
Page 4 of 28
CY7C43663AV
CY7C43643AV
CY7C43683AV
Pin Definitions (continued)
Signal Name
Description
I/O
Function
MBA
Port A Mailbox
Select
I
A HIGH level on MBA chooses a mailbox register for a Port A Read or Write
operation. When a Write operation is performed on Port A, a HIGH on MBA will write
the data into Mail1 register, a low on MBA will write the data into the FIFO memory.
MBB
Port B Mailbox
Select
I
A HIGH level on MBB chooses a mailbox register for a Port B Read or Write
operation. When a Read operation is performed on Port B, a HIGH level on MBB selects
data from the Mail1 register for output and a LOW level selects FIFO output register
data for output. Data can only be written into Mail2 register through Port B (MBB HIGH)
and not into the FIFO memory.
MBF1
Mail1 Register
Flag
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the Mail1
register. Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH
by a LOW-to-HIGH transition of CLKB when a Port B Read is selected and MBB is HIGH.
MBF1 is set HIGH following either a Master or Partial Reset.
MBF2
Mail2 Register
Flag
O
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the Mail2
register. Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH
by a LOW-to-HIGH transition of CLKA when a Port A Read is selected and MBA is HIGH.
MBF2 is set HIGH following either a Master or Partial Reset.
MRS1
Master Reset
I
A LOW on this pin initializes the FIFO Read and Write pointers to the first location
of memory and sets the Port B output register to all zeroes. A LOW pulse on MRS1
selects the programming method (serial or parallel) and one of three programmable flag
default offsets. It also configures Port B for bus size and endian arrangement. Four
LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must
occur while MRS1 is LOW.
MRS2
Master Reset
I
A LOW on this pin initializes the Mail2 Register.
PRS
Partial Reset
I
A LOW on this pin initializes the FIFO Read and Write pointers to the first location
of memory and sets the Port B output register to all zeroes. During Partial Reset, the
currently selected bus size, endian arrangement, programming method (serial or
parallel), and programmable flag settings are all retained.
RT
Retransmit
I
A LOW strobe on this pin will retransmit the data in the FIFO. This is achieved by
bringing the Read pointer back to location zero. The user will still need to preform Read
operations to retransmit the data. Retransmit function applies to CY standard mode only.
SIZE
Bus Size Select
I
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW
on this pin when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and
BE to select the bus size and endian arrangement for Port B. The level of SIZE must be
static throughout device operation.
SPM
Serial
Programming
I
A LOW on this pin selects serial programming of partial flag offsets. A HIGH on
this pin selects parallel programming or default offsets (8, 16, or 64).
W/RA
Port A
Write/Read
Select
I
A HIGH selects a Write operation and a LOW selects a Read operation on Port A
for a LOW-to-HIGH transition of CLKA. The A0–35 outputs are in the high-impedance
state when W/RA is HIGH.
W/RB
Port B
Write/Read
Select
I
A LOW selects a Write operation and a HIGH selects a Read operation on Port B
for a LOW-to-HIGH transition of CLKB. The B0–35 outputs are in the high-impedance
state when W/RB is LOW.
Document #: 38-06024 Rev. *C
Page 5 of 28
CY7C43663AV
CY7C43643AV
CY7C43683AV
Signal Description
Master Reset (MRS1, MRS2)
The FIFO memory of the CY7C436X3AV undergoes a
complete reset by taking its associated Master Reset (MRS1,
MRS2) input LOW for at least four Port A clock (CLKA) and
four Port B clock (CLKB) LOW-to-HIGH transitions. The
Master Reset input can switch asynchronously to the clocks.
A Master Reset initializes the internal Read and Write pointers
and forces the Full/Input Ready flag (FF/IR) LOW, the
Empty/Output Ready flag (EF/OR) LOW, the Almost Empty
flag (AE) LOW, and the Almost Full flag (AF) HIGH. A Master
Reset also forces the Mailbox flag (MBF1, MBF2) of the
parallel mailbox register HIGH. After a Master Reset, the
FIFO’s Full/Input Ready flag is set HIGH after two clock cycles
to begin normal operation. A Master Reset must be performed
on the FIFO after power up, before data is written to its
memory.
A LOW-to-HIGH transition on a FIFO Master Reset (MRS1,
MRS2) input latches the value of the Big Endian (BE) input,
determining the order by which bytes are transferred through
Port B.
A LOW-to-HIGH transition on a FIFO reset (MRS1, MRS2)
input latches the values of the Flag Select (FS0, FS1) and
Serial Programming Mode (SPM) inputs for choosing the
Almost Full and Almost Empty offset programming method
(see Almost Empty and Almost Full flag offset programming
below).
Partial Reset (PRS)
The FIFO memory of the CY7C436X3AV undergoes a limited
reset by taking its associated Partial Reset (PRS) input LOW
for at least four Port A clock (CLKA) and four Port B clock
(CLKB) LOW-to-HIGH transitions. The Partial Reset inputs
can switch asynchronously to the clocks. A Partial Reset
initializes the internal Read and Write pointers and forces the
Full/Input Ready flag (FF/IR) LOW, the Empty/Output Ready
flag (EF/OR) LOW, the Almost Empty flag (AE) LOW, and the
Almost Full flag (AF) HIGH. A Partial Reset also forces the
Mailbox flag (MBF1, MBF2) of the parallel mailbox register
HIGH. After a Partial Reset, the FIFO’s Full/Input Ready flag
is set HIGH after two clock cycles to begin normal operation.
Whatever flag offsets, programming method (parallel or
serial), and timing mode (FWFT or CY Standard mode) are
currently selected at the time a Partial Reset is initiated, those
settings will remain unchanged upon completion of the reset
operation. A Partial Reset may be useful in the case where
reprogramming a FIFO following a Master Reset would be
inconvenient.
Big Endian/First-Word Fall-Through (BE/FWFT)
This is a dual-purpose pin. At the time of Master Reset, the BE
select function is active, permitting a choice of Big or Little
Endian byte arrangement for data written to or Read from
Port B. This selection determines the order by which bytes (or
words) of data are transferred through this port. For the
following illustrations, assume that a byte (or word) bus size
has been selected for Port B.
A HIGH on the BE/FWFT input when the Master Reset (MRS1,
MRS2) inputs go from LOW to HIGH will select a Big Endian
arrangement. When data is moving in the direction from Port
A to Port B, the most significant byte (word) of the long-word
Document #: 38-06024 Rev. *C
written to Port A will be transferred to Port B first; the least
significant byte (word) of the long-word written to Port A will be
transferred to Port B last.
A LOW on the BE/FWFT input when the Master Reset (MRS1,
MRS2) inputs go from LOW to HIGH will select a Little Endian
arrangement. When data is moving in the direction from Port
A to Port B, the least significant byte (word) of the long-word
written to Port A will be transferred to Port B first; the most
significant byte (word) of the long-word written to Port A will be
transferred to Port B last.
After Master Reset, the FWFT select function is active,
permitting a choice between two possible timing modes: CY
Standard mode or First-Word Fall-Through (FWFT) Mode.
Once the Master Reset (MRS1, MRS2) input is HIGH, a HIGH
on the BE/FWFT input at the second LOW-to-HIGH transition
of CLKA will select CY Standard mode. This mode uses the
Empty Flag function (EF) to indicate whether or not there are
any words present in the FIFO memory. It uses the Full Flag
function (FF) to indicate whether or not the FIFO memory has
any free space for writing. In CY Standard mode, every word
read from the FIFO, including the first, must be requested
using a formal Read operation.
Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW
on the BE/FWFT input of the second LOW-to-HIGH transition
of CLKA will select FWFT Mode. This mode uses the Output
Ready function (OR) to indicate whether or not there is valid
data at the data outputs (B0–35). It also uses the Input Ready
(IR) function to indicate whether or not the FIFO memory has
any free space for writing. In the FWFT mode, the first word
written to an empty FIFO goes directly to data outputs, no
Read request necessary. Subsequent words must be
accessed by performing a formal Read operation.
Following Master Reset, the level applied to the BE/FWFT
input to choose the desired timing mode must remain static
throughout the FIFO operation.
Programming the Almost Empty and Almost Full Flags
Two registers in the CY7C436X3AV are used to hold the offset
values for the Almost Empty and Almost Full flags. The Port B
Almost Empty flag (AE) offset register is labeled X. The Port A
Almost Full flag (AF) offset register is labeled Y. The index of
each register name corresponds with preset values during the
reset of a FIFO, programmed in parallel using the FIFO’s Port
A data inputs, or programmed in serial using the Serial Data
(SD) input (see Table 1).
To load a FIFO’s Almost Empty flag and Almost Full flag offset
registers with one of the three preset values listed in Table 1,
the Serial Program Mode (SPM) and at least one of the
flag-select inputs must be HIGH during the LOW-to-HIGH
transition of its Master Reset input (MRS1, MRS2). For
example, to load the preset value of 64 into X and Y, SPM, FS0
and FS1 must be HIGH when the FIFO reset (MRS1, MRS2)
returns HIGH. When using one of the preset values for the flag
offsets, the FIFO can be reset simultaneously or at different
times.
To program the X and Y registers from Port A, perform a
Master Reset on both FIFOs simultaneously with SPM HIGH
and FS0 and FS1 LOW during the LOW-to-HIGH transition of
MRS1, MRS2. After this reset is complete, the first two writes
to the FIFO do not store data in RAM but load the offset
registers in the order Y and X. The Port A data inputs used by
the offset registers are (A0–9), (A0–11), or (A0–13), for the
Page 6 of 28
CY7C43663AV
CY7C43643AV
CY7C43683AV
CY7C436X3AV, respectively. The highest numbered input is
used as the most significant bit of the binary number in each
case. Valid programming values for the registers range from
0 – 1023 for the CY7C43643AV, 0 – 4095 for the
CY7C43663AV, and 0 – 16383 for the CY7C43683AV.[2]
Before programming the offset registers, FF/IR is set HIGH.
FIFOs begin normal operation after programming is complete.
When operating the FIFO in FWFT Mode with the Output
Ready flag LOW, the next word written is automatically sent to
the FIFO’s output register by the LOW-to-HIGH transition of
the port clock that sets the Output Ready flag HIGH, data
residing in the FIFO’s memory array is clocked to the output
register only when a Read is selected using the port’s Chip
Select, Write/Read Select, Enable, and Mailbox Select.
To program the X and Y registers serially, initiate a Master
Reset with SPM LOW, FS0/SD LOW, and FS1/SEN HIGH
during the LOW-to-HIGH transition of MRS1, MRS2. After this
reset is complete, the X and Y register values are loaded
bit-wise through the FS0/SD input on each LOW-to-HIGH
transition of CLKA that the FS1/SEN input is LOW. Twenty,
twenty- four, or twenty-eight bit writes are needed to complete
the programming for the CY7C436X3AV, respectively. The two
registers are written in the order Y then finally X. The first-bit
Write stores the most significant bit of the Y register and the
last-bit Write stores the least significant bit of the X register.
Each register value can be programmed from 0 – 1023
(CY7C43643AV), 0 – 4095 (CY7C43663AV), and 0 – 16383
(CY7C43683AV).
When operating the FIFO in CY Standard mode, regardless of
whether the Empty Flag is LOW or HIGH, data residing in the
FIFO’s memory array is clocked to the output register only
when a Read is selected using the port’s Chip Select,
Write/Read Select, Enable, and Mailbox Select.
When the option to program the offset registers serially is
chosen, the Port A Full/Input Ready (FF/IR) flag remains LOW
until all register bits are written. FF/IR is set HIGH by the
LOW-to-HIGH transition of CLKA after the last bit is loaded to
allow normal FIFO operation.
SPM, FS0/SD, and FS1/SEN function the same way in both
CY Standard and FWFT modes.
FIFO Write/Read Operation
The state of the Port A data (A0–35) lines is controlled by Port
A Chip Select (CSA) and Port A Write/Read Select (W/RA).
The A0–35 lines are in the high-impedance state when either
CSA or W/RA is HIGH. The A0–35 lines are active mail2
register outputs when both CSA and W/RA are LOW.
Data is loaded into the FIFO from the A0–35 inputs on a
LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is
HIGH, ENA is HIGH, MBA is LOW, and FF/IR is HIGH (see
Table 2). FIFO writes on Port A are independent of any
concurrent Port B operation.
The Port B control signals are identical to those of Port A with
the exception that the Port B Write/Read select (W/RB) is the
inverse of the Port A Write/Read select (W/RA). The state of
the Port B data (B0–35) lines is controlled by the Port B Chip
Select (CSB) and Port B Write/Read select (W/RB). The B0–35
lines are in the high-impedance state when either CSB is HIGH
or W/RB is LOW. The B0–35 lines are active outputs when CSB
is LOW and W/RB is HIGH.
Data is read from the FIFO to the B0–35 outputs by a
LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is
HIGH, ENB is HIGH, MBB is LOW, and EF/OR is HIGH (see
Table 3). FIFO reads and writes on Port B are independent of
any concurrent Port A operation.
The set-up and hold time constraints to the port clocks for the
port Chip Selects and Write/Read Selects are only for enabling
Write and Read operations and are not related to
high-impedance control of the data outputs. If a port enable is
LOW during a clock cycle, the port’s Chip Select and
Write/Read Select may change states during the set-up and
hold time window of the cycle.
Document #: 38-06024 Rev. *C
Synchronized FIFO Flags
Each FIFO is synchronized to its port clock through at least two
flip-flop stages. This is done to improve flag-signal reliability by
reducing the probability of the metastable events when CLKA
and CLKB operate asynchronously to one another. EF/OR and
AE are synchronized to CLKB. FF/IR and AF are synchronized
to CLKA. Table 4 shows the relationship of each port flag to
the FIFO.
Empty/Output Ready Flags (EF/OR)
These are dual-purpose flags. In the FWFT Mode, the Output
Ready (OR) function is selected. When the Output Ready flag
is HIGH, new data is present in the FIFO output register. When
the Output Ready flag is LOW, the previous data word remains
in the FIFO output register and any FIFO reads are ignored.
In the CY Standard mode, the Empty Flag (EF) function is
selected. When the Empty Flag is HIGH, data is available in
the FIFO’s RAM memory for reading to the output register.
When Empty Flag is LOW, the previous data word remains in
the FIFO output register and any FIFO reads are ignored.
The Empty/Output Ready flag of a FIFO is synchronized to
CLKB. For both the FWFT and CY Standard modes, the FIFO
Read pointer is incremented each time a new word is clocked
to its output register. The state machine that controls an Output
Ready flag monitors a Write pointer and Read pointer
comparator that indicates when the FIFO SRAM status is
empty, empty + 1, or empty + 2.
In FWFT Mode, from the time a word is written to a FIFO, it
can be shifted to the FIFO output register in a minimum of
three cycles of the Output Ready flag synchronizing clock.
Therefore, an Output Ready flag is LOW if a word in memory
is the next data to be sent to the FIFO output register and three
cycles have not elapsed since the time the word was written.
The Output Ready flag of the FIFO remains LOW until the third
LOW-to-HIGH transition of the synchronizing clock occurs,
simultaneously forcing the Output Ready flag HIGH and
shifting the word to the FIFO output register.
In the CY Standard mode, from the time a word is written to a
FIFO, the Empty flag will indicate the presence of data
available for reading in a minimum of two cycles of the Empty
flag synchronizing clock. Therefore, an Empty flag is LOW if a
word in memory is the next data to be sent to the FIFO output
register and two cycles have not elapsed since the time the
word was written. The Empty flag of the FIFO remains LOW
until the second LOW-to-HIGH transition of the synchronizing
clock occurs, forcing the Empty flag HIGH; only then can data
be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag
synchronizing clock begins the first synchronization cycle of a
Page 7 of 28
CY7C43663AV
CY7C43643AV
CY7C43683AV
Write if the clock transition occurs at time tSKEW1 or greater
after the Write. Otherwise, the subsequent clock cycle will be
the first synchronization cycle.
Full/Input Ready Flags (FF/IR)
This is a dual-purpose flag. In FWFT Mode, the Input Ready
(IR) function is selected. In CY Standard mode, the Full Flag
(FF) function is selected. For both timing modes, when the
Full/Input Ready flag is HIGH, a memory location is free in the
SRAM to receive new data. No memory locations are free
when the Full/Input Ready flag is LOW and any writes to the
FIFO are ignored.
The Full/Input Ready flag of a FIFO is synchronized to CLKA.
For both FWFT and CY Standard modes, each time a word is
written to a FIFO, its Write pointer is incremented. The state
machine that controls a Full/Input Ready flag monitors a Write
pointer and Read pointer comparator that indicates when the
FIFO SRAM status is full, full – 1, or full – 2. From the time a
word is read from a FIFO, its previous memory location is
ready to be written to in a minimum of two cycles of the
Full/Input Ready flag synchronizing clock. Therefore, a
Full/Input Ready flag is LOW if less than two cycles of the
Full/Input Ready flag synchronizing clock have elapsed since
the next memory Write location has been read. The second
LOW-to-HIGH transition on the Full/Input Ready flag synchronizing clock after the Read sets the Full/Input Ready flag
HIGH.
A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock begins the first synchronization cycle of a Read if
the clock transition occurs at time tSKEW1 or greater after the
Read. Otherwise, the subsequent clock cycle can be the first
synchronization cycle.
Almost Empty Flags (AE)
The Almost Empty flag of the FIFO is synchronized to port B
clock. The state machine that controls an Almost Empty flag
monitors a Write pointer and Read pointer comparator that
indicates when the FIFO SRAM status is almost empty, almost
empty + 1, or almost empty + 2. The Almost Empty state is
defined by the contents of register X for AE. These registers
are loaded with preset values during a FIFO reset,
programmed from Port A, or programmed serially (see Almost
Empty flag and Almost Full flag offset programming above). An
Almost Empty flag is LOW when its FIFO contains X or less
words and is HIGH when its FIFO contains (X + 2) or more
words.[2]
The Almost Empty flag is set HIGH by the first CLKB rising
edge after two FIFO writes that fills memory to the (X + 2) level.
A LOW-to-HIGH transition of CLKB begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the Write
that fills the FIFO to (X + 2) words. Otherwise, the subsequent
synchronizing clock cycle will be the first synchronization
cycle.
Almost Full Flags (AF)
The Almost Full flag of the FIFO is synchronized to port A
clock. The state machine that controls an Almost Full flag
monitors a Write pointer and Read pointer comparator that
indicates when the FIFO SRAM status is almost full, almost
full – 1, or almost full – 2. The Almost Full state is defined by
the contents of register Y for AF. These registers are loaded
with preset values during a FIFO reset, programmed from Port
Document #: 38-06024 Rev. *C
A, or programmed serially (see Almost Empty flag and Almost
Full flag offset programming above). An Almost Full flag is
LOW when the number of words in its FIFO is greater than or
equal to (1024 – Y), (4096 – Y), or (16384 – Y), for the
CY7C436X3AV respectively. An Almost Full flag is HIGH when
the number of words in its FIFO is less than or equal to
[1024 – (Y + 2)], [4096 – (Y + 2)], or [16384 – (Y + 2)], for the
CY7C436X3AV respectively.
The Almost Full flag is set HIGH by the first CLKA rising edge
after two FIFO reads that reduces the number of words in
memory to [1024/4096/16384 – (Y + 2)]. A LOW-to-HIGH
transition of CLKA begins the first synchronization cycle if it
occurs at time tSKEW2 or greater after the Read that reduces
the number of words in memory to [1024/4096/16384 –
(Y + 2)]. Otherwise, the subsequent synchronizing clock cycle
will be the first synchronization cycle.
Mailbox Registers
Each FIFO has a 36-bit bypass register to pass command and
control information between Port A and Port B without putting
it in queue. The Mailbox Select (MBA, MBB) inputs choose
between a mail register and a FIFO for a port data transfer
operation. The usable width of both the Mail1 and Mail2
registers matches the selected bus size of Port B.
A LOW-to-HIGH transition on CLKA writes A0-35 data to the
Mail1 Register when a Port A Write is selected by CSA, W/RA,
and ENA with MBA HIGH. If the selected Port A bus size is
also 36 bits, then the usable width of the Mail1 Register
employs data lines A0-35. If the selected Port A bus size is 18
bits, then the usable width of the Mail1 Register employs data
lines A0-17. (In this case, A18-35 are don’t care inputs.) If the
selected Port A bus size is 9 bits, then the usable width of the
Mail1 Register employs data lines A0–8. (In this case, A9-35 are
“Don’t Care” inputs.)
A LOW-to-HIGH transition on CLKB writes B0-35 data to the
Mail2 Register when a Port B Write is selected by CSB, W/RB,
and ENB with MBB HIGH. If the selected Port B bus size is
also 36 bits, then the usable width of the Mail2 Register
employs data lines B0–35. If the selected Port B bus size is 18
bits, then the usable width of the Mail2 Register employs data
lines B0–17. (In this case, B18–35 are don’t care inputs.) If the
selected Port B bus size is 9 bits, then the usable width of the
Mail2 Register employs data lines B0-8. (In this case, B9-35 are
“Don’t Care” inputs.)
Writing data to a mail register sets its corresponding flag
(MBF1 or MBF2) LOW. Attempted writes to a mail register are
ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus
comes from the FIFO output register if the port Mailbox Select
input is LOW and from the mail register if the port Mailbox
Select input is HIGH.
The Mail1 Register flag (MBF1) is set HIGH by a
LOW-to-HIGH transition on CLKB when a Port B Read is
selected by CSB, W/RB, and ENB with MBB HIGH.
The Mail2 Register flag (MBF2) is set HIGH by a
LOW-to-HIGH transition on CLKA when a Port A Read is
selected by CSA, W/RA, and ENA with MBA HIGH.
The data in a mail register remains intact after it is read and
changes only when new data is written to the register. The
Endian Select feature has no effect on the mailbox data.
Page 8 of 28
CY7C43663AV
CY7C43643AV
CY7C43683AV
Bus Sizing
Bus-Matching FIFO Reads
The Port B bus can be configured in a 36-bit long-word, 18-bit
word, or 9-bit byte format for data read from FIFO. The levels
applied to the Port B Bus Size Select (SIZE) and the Bus
Match Select (BM) determine the Port B bus size. These levels
should be static throughout FIFO operation. Both bus size
selections are implemented at the completion of Master Reset,
by the time the Full/Input Ready flag is set HIGH.
Data is read from the FIFO RAM in 36-bit long-word increments. If a long-word bus size is implemented, the entire longword immediately shifts to the FIFO output register. If byte or
word size is implemented on Port B, only the first one or two
bytes appear on the selected portion of the FIFO output
register, with the rest of the long-word stored in auxiliary
registers. In this case, subsequent FIFO reads output the rest
of the long-word to the FIFO output register.
Two different methods for sequencing data transfer are
available for Port B when the bus-size selection is either byte
or word size. They are referred to as Big Endian (most significant byte first) and Little Endian (least significant byte first).
The level applied to the Big Endian Select (BE) input during
the LOW-to-HIGH transition of MRS1/MRS2 selects the
endian method that will be active during FIFO operation. BE is
a don’t care input when the bus size selected for Port B is
long-word. The endian method is implemented at the
completion of Master Reset, by the time the Full/Input Ready
flag is set HIGH.
Only 36-bit long-word data is written to the FIFO memory on
the CY7C436X3AV. Bus-matching operations are done after
data is read from the FIFO. These bus-matching operations
are not available when transferring data via mailbox registers.
Furthermore, both the word- and byte-size bus selections limit
the width of the data bus that can be used for mail register
operations. In this case, only those byte lanes belonging to the
selected word- or byte-size bus can carry mailbox data. The
remaining data outputs will be indeterminate. The remaining
data inputs will be don’t care inputs. For example, when a
word-size bus is selected, then mailbox data can be transmitted only between A0–17 and B0–17. When a byte-size bus is
selected, then mailbox data can be transmitted only between
A0–8 and B0–8.
Document #: 38-06024 Rev. *C
When reading data from the FIFO in the byte or word format,
the unused B9–35 or B18–35 outputs are indeterminate.
Retransmit (RT)
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary. Retransmit
function applies to CY standard mode only.
The number of 36-/18-/9-bit words written into the FIFO should
be less than full depth minus 2/4/8 words between the reset of
the FIFO (master or partial) and Retransmit setup. A LOW
pulse on RT resets the internal Read pointer to the first physical location of the FIFO. CLKA and CLKB may be free running
but ENB must be disabled during and tRTR after the retransmit
pulse. With every valid Read cycle after retransmit, previously
accessed data is read and the Read pointer is incremented
until it is equal to the Write pointer. Flags are governed by the
relative locations of the Read and Write pointers and are updated during a retransmit cycle. Data written to the FIFO after
activation of RT are transmitted also. The full depth of the FIFO
can be repeatedly retransmitted.
Page 9 of 28
CY7C43663AV
CY7C43643AV
CY7C43683AV
BYTE ORDER ON PORT A:
BE
BM
SIZE
X
L
X
A27–35
A18–26
A
B
B27–35
B18–26
A
B
BM
SIZE
H
H
L
A0–8
D
C
B9–17
Write to FIFO
B0–8
D
C
Read from FIFO
(a) LONG WORD SIZE
B27–35
BE
A9–17
B27–35
B18–26
B18–26
B9–17
B0–8
A
B
B9–17
1st: Read from FIFO
B0–8
D
C
2nd: Read from FIFO
(b) WORD SIZE – BIG ENDIAN
B27–35
BE
BM
SIZE
L
H
L
B27–35
B18–26
B18–26
B9–17
B0–8
C
D
B9–17
B0–8
A
B
1st: Read from FIFO
2nd: Read from FIFO
(c) WORD SIZE – LITTLE ENDIAN
B27–35
BE
BM
SIZE
H
H
H
B18–26
B9–17
B0–8
A
B27–35
B18–26
B9–17
B0–8
B
B27–35
B18–26
B9–17
B18–26
B9–17
2nd: Read from FIFO
B0–8
C
B27–35
1st: Read from FIFO
3rd: Read from FIFO
B0–8
D
4th: Read from FIFO
(d) BYTE SIZE – BIG ENDIAN
B27–35
BE
BM
SIZE
L
H
H
B18–26
B9–17
B0–8
D
B27–35
B18–26
B9–17
B0–8
C
B27–35
B18–26
B9–17
B18–26
B9–17
2nd: Read from FIFO
B0–8
B
B27–35
1st: Read from FIFO
3rd: Read from FIFO
B0–8
A
4th: Read from FIFO
(e) BYTE SIZE – LITTLE ENDIAN
Document #: 38-06024 Rev. *C
Page 10 of 28
CY7C43663AV
CY7C43643AV
CY7C43683AV
Table 1. Flag Programming
FS1/SEN
FS0/SD
MRS1/MRS2
X and Y Registers[3]
H
H
H
↑
64
H
H
L
↑
16
H
L
H
↑
8
H
L
L
↑
Parallel programming via Port A
L
H
L
↑
Serial programming via SD
L
H
H
↑
Reserved
L
L
H
↑
Reserved
L
↑
Reserved
SPM
L
L
Table 2. Port A Enable Function
CSA
W/RA
ENA
MBA
CLKA
A0–35
Port Function
H
X
X
X
X
In high-impedance state
None
L
H
L
X
X
In high-impedance state
None
L
H
H
L
↑
In high-impedance state
FIFO Write
L
H
H
H
↑
In high-impedance state
Mail1 Write
L
L
L
L
X
Active, Mail2 register
None
L
L
H
L
↑
Active, Mail2 register
None
L
L
L
H
X
Active, Mail2 register
None
L
L
H
H
↑
Active, Mail2 register
Mail2 Read (set MBF2 HIGH)
Table 3. Port B Enable Function
CSB
W/RB
ENB
MBB
CLKB
B0–35
Port Function
H
X
X
X
X
In high-impedance state
None
L
L
L
X
X
In high-impedance state
None
L
L
H
L
↑
In high-impedance state
None
L
L
H
H
↑
In high-impedance state
Mail2 Write
L
H
L
L
X
Active, FIFO output register
None
L
H
H
L
↑
Active, FIFO output register
FIFO Read
L
H
L
H
X
Active, Mail1 register
None
L
H
H
H
↑
Active, Mail1 register
Mail1 Read (set MBF1 HIGH)
Note:
3. X register holds the offset for AE; Y register holds the offset for AF.
Document #: 38-06024 Rev. *C
Page 11 of 28
CY7C43663AV
CY7C43643AV
CY7C43683AV
Table 4. FIFO Flag Operation (CY Standard and FWFT Modes)
Number of Words in FIFO Memory[2, 4, 5, 6, 7]
CY7C43643AV
CY7C43663AV
0
AE
AF
FF/IR
0
L
L
H
H
1–X
H
L
H
H
H
H
H
H
H
H
L
H
H
H
L
L
1–X
(X + 1) to [1024 –
(Y + 1)]
Synchronized to CLKA
EF/OR
0
1–X
Synchronized to CLKB
CY7C43683AV
(X + 1) to [4096 – (X + 1) to [16384 –
(Y + 1)]
(Y + 1)]
(1024 – Y) to 1023 (4096 – Y) to 4095
(16384 – Y) to
16383
1024
4096
16384
Table 5. Data Size for FIFO Long-Word Reads
Size Mode[8]
Data Written to FIFO
Data Read From FIFO
BM
SIZE
BE
A27–35
A18–26
A9–17
A0–8
B27–35
B18–26
B9–17
B0–8
L
X
X
A
B
C
D
A
B
C
D
Table 6. Data Size for Word Reads
Size Mode[8]
Data Written to FIFO
Read No.
BM
SIZE
BE
A27–35
A18–26
A9–17
A0–8
H
L
H
A
B
C
D
H
L
L
A
B
C
Data Read From FIFO
B9–17
D
B0–8
1
A
B
2
C
D
1
C
D
2
A
B
Table 7. Data Size for Byte Reads from FIFO
Size Mode[8]
Data Written to FIFO
Read No.
BM
SIZE
BE
A27–35
A18–26
A9–17
A0–8
H
H
H
A
B
C
D
H
H
L
A
B
C
D
Data Read From
FIFO
B0–8
1
A
2
B
3
C
4
D
1
D
2
C
3
B
4
A
Notes:
4. X is the Almost Empty offset for FIFO used by AE. Y is the Almost Full offset for FIFO used by AF. Both X and Y are selected during a FIFO reset or Port A
programming.
5. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
6. Data in the output register does not count as a “word in FIFO memory”. Since in FWFT Mode, the first word written to an empty FIFO goes unrequested to
the output register (no Read operation necessary), it is not included in the FIFO memory count.
7. The OR and IR functions are active during FWFT mode; the EF and FF functions are active in CY Standard mode.
8. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.
Document #: 38-06024 Rev. *C
Page 12 of 28
CY7C43663AV
CY7C43643AV
CY7C43683AV
Maximum Ratings[9,11]
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ...................................–65°C to +150°C
Ambient Temperature with
Power Applied...............................................–55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[10] .....................................–0.5V to VCC+0.5V
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... > 200 mA
Operating Range
Range
Ambient Temperature
VCC[12]
Commercial
0°C to +70°C
3.3V ± 10%
–40°C to +85°C
3.3V ± 10%
Industrial
DC Input Voltage[10] .................................–0.5V to VCC+0.5V
Electrical Characteristics Over the Operating Range
CY7C43643/63/83AV
Parameter
Description
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
VCC = 3.0V, IOH = –2.0 mA
2.4
V
VOL
Output LOW Voltage
VCC = 3.0V, IOL = 8.0 mA
0.5
V
VIH
Input HIGH Voltage
2.0
VCC
V
VIL
Input LOW Voltage
–0.5
0.8
V
IIX
Input Leakage Current
VCC = Max.
–10
+10
µA
IOZL
IOZH
Output OFF, High Z
Current
VSS < VO< VCC
–10
+10
µA
ICC1[13]
Active Power Supply
Current
Commercial
60
mA
Industrial
60
mA
ISB[14]
Average Standby Current
Commercial
10
mA
Industrial
10
mA
Capacitance[15]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
Unit
TA = 25°C, f = 1 MHz, VCC = 3.3V
4
pF
8
pF
Notes:
9. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
10. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
11. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
12. Operating VCC Range for –7 speed is 3.3V ± 5%.
13. Input signals switch from 0V – 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs
are unloaded.
14. All inputs = VCC – 0.2V, except CLKA and CLKB (which are at frequency = 0 MHz). All outputs are unloaded.
15. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06024 Rev. *C
Page 13 of 28
CY7C43663AV
CY7C43643AV
CY7C43683AV
AC Test Loads and Waveforms (–10, –15)
R1 = 330Ω
ALL INPUT PULSES
3.3V
OUTPUT
3.0V
[16]
CL = 30 pF
R2 = 680Ω
90%
10%
90%
10%
GND
≤ 3 ns
INCLUDING
JIG AND
SCOPE
≤ 3 ns
AC Test Loads and Waveforms (–7)
VCC/2
50Ω
ALL INPUT PULSES
3.0V
GND
I/O
90%
10%
90%
10%
≤ 3 ns
Z0 = 50Ω
≤ 3 ns
Switching Characteristics Over the Operating Range
CY7C43643/63/
83AV
–7
Parameter
Description
Min.
Max.
CY7C43643/
63/83AV
–10
CY7C43643/
63/83AV
–15
Min.
Min.
133
Max.
100
Max.
Unit
67
MHz
fS
Clock Frequency, CLKA or CLKB
tCLK
Clock Cycle Time, CLKA or CLKB
7.5
10
15
ns
tCLKH
Pulse Duration, CLKA or CLKB HIGH
3.5
4
6
ns
tCLKL
Pulse Duration, CLKA or CLKB LOW
3.5
4
6
ns
tDS
Set-Up Time, A0–35 before CLKA↑ and B0–35 before
CLKB↑
3
4
5
ns
tENS
Set-Up Time, CSA, W/RA, ENA, and MBA before
CLKA↑; CSB, W/RB, ENB, and MBB before CLKB↑
3
4
5
ns
tRSTS
Set-Up Time, MRS1/MRS2, PRS, RT LOW before
CLKA↑ or CLKB↑[17]
2.5
4
5
ns
tFSS
Set-Up Time, FS0 and FS1 before MRS1/MRS2
HIGH
5
7
7.5
ns
tBES
Set-Up Time, BE/FWFT before MRS1/MRS2 HIGH
5
7
7.5
ns
tSPMS
Set-Up Time, SPM before MRS1/MRS2 HIGH
5
7
7.5
ns
tSDS
Set-Up Time, FS0/SD before CLKA↑
3
4
5
ns
tSENS
Set-Up Time, FS1/SEN before CLKA↑
3
4
5
ns
tFWS
Set-Up Time, FWFT before CLKA↑
0
0
0
ns
tDH
Hold Time, A0–35 after CLKA↑ and B0–35 after
CLKB↑
0
0
0
ns
tENH
Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑;
CSB, W/RB, ENB, and MBB after CLKB↑
0
0
0
ns
Note:
16. CL = 5 pF for tDIS.
17. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
Document #: 38-06024 Rev. *C
Page 14 of 28
CY7C43663AV
CY7C43643AV
CY7C43683AV
Switching Characteristics Over the Operating Range (continued)
CY7C43643/63/
83AV
–7
Parameter
Description
Min.
Max.
CY7C43643/
63/83AV
–10
CY7C43643/
63/83AV
–15
Min.
Min.
Max.
Max.
Unit
tRSTH
Hold Time, MRS1/MRS2, PRS, RT LOW after
CLKA↑ or CLKB↑[17]
1
2
2
ns
tFSH
Hold Time, FS0 and FS1 after MRS1/MRS2 HIGH
1
1
2
ns
tBEH
Hold Time, BE/FWFT after MRS1/MRS2 HIGH
1
1
2
ns
tSPMH
Hold Time, SPM after MRS1/MRS2 HIGH
1
1
2
ns
tSDH
Hold Time, FS0/SD after CLKA↑
0
0
0
ns
tSENH
Hold Time, FS1/SEN after CLKA↑
0
0
0
ns
tSPH
Hold Time, FS1/SEN HIGH after MRS1/MRS2 HIGH
1
1
2
ns
[18]
Skew Time between CLKA↑ and CLKB↑ for EF/OR
and FF/IR
5
5
7.5
ns
tSKEW2[18]
Skew Time between CLKA↑ and CLKB↑ for AE and
AF
7
8
12
ns
tA
Access Time, CLKA↑ to A0–35 and CLKB↑ to B0–35
1
6
1
8
3
10
ns
tWFF
Propagation Delay Time, CLKA↑ to FF/IR
1
6
1
8
2
10
ns
tREF
Propagation Delay Time, CLKB↑ to EF/OR
1
6
1
8
2
10
ns
tPAE
Propagation Delay Time, CLKB↑ to AE
1
6
1
8
1
10
ns
tPAF
Propagation Delay Time, CLKA↑ to AF
1
6
1
8
1
10
ns
tPMF
Propagation Delay Time, CLKA↑ to MBF1 LOW or
MBF2 HIGH and CLKB↑ to MBF2 LOW or MBF1
HIGH
0
6
0
8
0
12
ns
tPMR
Propagation Delay Time, CLKA↑ to B0–35[19] and
CLKB↑ to A0–35[20]
1
7
2
11
3
12
ns
tMDV
Propagation Delay Time, MBA to A0–35 Valid and
MBB to B0–35 Valid
1
6
2
9
3
11
ns
tRSF
Propagation Delay Time, MRS1/MRS2 or PRS LOW
to AE LOW, AF HIGH,FF/ IR LOW, EF/ OR LOW and
MBF1/MBF2 HIGH
1
6
1
10
1
15
ns
tEN
Enable Time, CSA or W/RA LOW to A0–35 Active and
CSB LOW and W/RB HIGH to B0–35 Active
1
6
2
8
2
10
ns
tDIS
Disable Time, CSA or W/RA HIGH to A0–35 at High
Impedance and CSB HIGH or W/RB LOW to B0–35
at High Impedance
1
5
1
6
1
8
ns
tRTR
Retransmit Recovery Time
90
tSKEW1
90
90
ns
Notes:
18. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB
cycle.
19. Writing data to the Mail1 register when the B0–35 outputs are active and MBB is HIGH.
20. Writing data to the Mail2 register when the A0–35 outputs are active and MBA is HIGH.
Document #: 38-06024 Rev. *C
Page 15 of 28
CY7C43663AV
CY7C43643AV
CY7C43683AV
Switching Waveforms
Master Reset Loading X and Y with a Preset Value of Eight [21]
CLKA
CLKB
MRS1,
MRS2
tRSTH
tRSTS
tBES
tBEH
tFWS
BE/FWFT
tSPMS
tSPMH
SPM
tFSS
FS1/SEN,
FS0/SD
tRSF
tFSH
tWFF
FF/IR
tRSF
EF/OR
tRSF
AE
tRSF
AF
tRSF
MBF1
Note:
21. PRS must be HIGH during Master Reset.
Document #: 38-06024 Rev. *C
Page 16 of 28
CY7C43663AV
CY7C43643AV
CY7C43683AV
Switching Waveforms (continued)
Partial Reset (CY Standard and FWFT Modes) [22]
CLKA
CLKB
tRSTS
tRSTH
PRS
tWFF
tRSF
FF/IR
tRSF
EF/OR
tRSF
AE
tRSF
AF
tRSF
MBF1
Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
(CY Standard and FWFT Modes) [23]
CLKA
MRS1,
MRS2
tFSS
tFSH
tFSS
tFSH
SPM
FS1/SEN,
FS0/SD
tWFF
FF/IR
tENS
tENH
tSKEW1[24]
ENA
tDS
tDH
A0−35
AF Offset (Y)
AE Offset (X)
First Word to FIFO
Notes:
22. MRS1/MRS2 must be HIGH during Partial Reset.
23. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles. FIFO can only be programmed in
parallel when FF/IR is HIGH.
24. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB for FF/IR to transition HIGH in the next cycle. If the time between the rising
edge of CLKA and rising edge of CLKB is less than tSKEW1, then FF/IR may transition HIGH one cycle later than shown.
Document #: 38-06024 Rev. *C
Page 17 of 28
CY7C43663AV
CY7C43643AV
CY7C43683AV
Switching Waveforms (continued)
Serial Programming of the Almost-Full Flag and Almost-Empty Flag
Offset Values (CY Standard and FWFT Modes) [25, 26]
CLKA
MRS1,
MRS2
tFSS tFSH
SPM
tWFF
FF/IR
tFSS
tSENS
tSPH
tSENH
tSENS tSENH
FS1/SEN
tFSS tFSH
tSDS
tSDH
FS0/SD [26]
AF Offset (Y) MSB
tSDS
tSDH
AE Offset (X) LSB
Port B Long-Word Read Cycle Timing for FIFO (CY Standard and FWFT Modes)
tCLK
tCLKL
tCLKH
CLKB
EF/OR
HIGH
CSB
[28]
W/RB
MBB
tENS tENH
tENS
tENH
tENS
tENH
ENB
B0–35
(Standard Mode)
OR
B0–35
(FWFT Mode)
tEN
tEN
tMDV
tMDV
tA
tA
Previous Data
tA
W1[27]
W1[27]
No Operation
W2[27]
tDIS
tA
W2[27]
tDIS
W3[27]
Notes:
25. It is not necessary to program offset register bits on consecutive clock cycles. FIFO Write attempts into the memory are ignored until FF/IR is set HIGH.
26. Programmable offsets are written serially to the SD input in the order AF offset (Y) then AE offset (X).
27. Read From FIFO.
28. If W/RB switches from Read to Write before the assertion of CSB, tENS = tDIS + tENS.
Document #: 38-06024 Rev. *C
Page 18 of 28
CY7C43663AV
CY7C43643AV
CY7C43683AV
Switching Waveforms (continued)
Port B Word Read Cycle Timing for FIFO (CY Standard and FWFT Modes)[29]
CLKB
EF/OR
HIGH
CSB
[28]
W/RB
MBB
tENS tENH
ENB
B0–17
(Standard Mode)
tEN
tMDV
tA
tA
Read 1
Previous
OR
tMDV
tEN
B0–17
(FWFT Mode)
tDIS
No Operation
Read 2
tA
tA
tDIS
Read 2
Read 1
Read 3
Port B Byte Read Cycle Timing for FIFO (CY Standard and FWFT Modes) [30]
CLKB
EF/OR
HIGH
CSB
[28]
W/RB
MBB
tENS tENH
ENB
B0–8
(Standard Mode)
OR
B0–8
(FWFT Mode)
tEN
tMDV
tA
tA
tA
tA
tEN
tMDV
Previous
tA
Read 1
tA
Read 2
tA
Read 3
tA
Read 1
Read 2
Read 3
Read 4
No Operation
tDIS
Read 4
tDIS
Read 5
Notes:
29. Unused bytes B18–35 contains all zeroes for word-size reads.
30. Unused bytes B9–17, B18–26, and B27–35 contain all zeroes for byte-size reads.
Document #: 38-06024 Rev. *C
Page 19 of 28
CY7C43663AV
CY7C43643AV
CY7C43683AV
Switching Waveforms (continued)
OR Flag Timing and First Data Word Fall Through when FIFO is Empty (FWFT Mode) [31]
tCLK
tCLKH
tCLKL
CLKA
CSA
LOW
W/RA
HIGH
tENS tENH
MBA
tENS tENH
ENA
FF/IR
HIGH
tDS tDH
A0–35
W1
tSKEW1[32]
CLKB
tCLKH
tCLKL
tCLK
EF/OR
CSB
W/RB
MBB
tREF
tREF
FIFO Empty
LOW
HIGH
LOW
tENS tENH
ENB
tA
B0–35
Old Data in FIFO Output Register
W1
Notes:
31. If Port B size is word or byte, EF is set LOW by the last word or byte Read from the FIFO, respectively.
32. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition HIGH and to clock the next word to the FIFO output
register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of OR HIGH and load
of the first word to the output register may occur one CLKB cycle later than shown.
Document #: 38-06024 Rev. *C
Page 20 of 28
CY7C43663AV
CY7C43643AV
CY7C43683AV
Switching Waveforms (continued)
EF Flag Timing and First Data Read Fall Through when FIFO is Empty (CY Standard Mode) [31]
tCLK
tCLKH
tCLKL
CLKA
CSA
W/RA
LOW
HIGH
tENStENH
MBA
tENStENH
ENA
FF/IR
HIGH
tDS tDH
A0–35
W1
tSKEW1[33]
tCLKH
tCLKL
CLKB
tCLK
EF/OR
CSB
W/RB
MBB
tREF
tREF
FIFO Empty
LOW
HIGH
LOW
tENS tENH
ENB
tA
B0–35
W1
Note:
33. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKB cycle later than shown.
Document #: 38-06024 Rev. *C
Page 21 of 28
CY7C43663AV
CY7C43643AV
CY7C43683AV
Switching Waveforms (continued)
IR Flag Timing and First Available Write when FIFO is Full (FWFT Mode) [34]
tCLK
tCLKH tCLKL
CLKB
CSB
LOW
W/RB
HIGH
MBB
LOW
tENS tENH
ENB
EF/OR
HIGH
tA
B0–35
CLKA
Next Word From FIFO
Previous Word in FIFO
Output Register
[35] tCLKH tCLKL
tSKEW1
tCLK
FF/IR
FIFO Full
CSA
LOW
W/RA
HIGH
tWFF
tWFF
tENS tENH
MBA
tENS tENH
ENA
tDS tDH
A0–35
To FIFO
Notes:
34. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte Write of the long-word, respectively.
35. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown.
Document #: 38-06024 Rev. *C
Page 22 of 28
CY7C43663AV
CY7C43643AV
CY7C43683AV
Switching Waveforms (continued)
FF Flag Timing and First Available Write when FIFO is Full (CY Standard Mode) [34]
tCLK
tCLKH tCLKL
CLKB
CSB
LOW
W/RB
HIGH
MBB
LOW
tENS tENH
ENB
EF/OR
HIGH
tA
B0–35
Next Word From FIFO
Previous Word in FIFO
Output Register
tSKEW1[36] tCLKH tCLKL
CLKA
tCLK
FF/IR
FIFO Full
CSA
LOW
W/RA
HIGH
tWFF
tWFF
tENS t
ENH
MBA
tENS tENH
ENA
tDS tDH
A0−35
Note:
36. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of FF HIGH may occur one CLKA cycle later than shown.
Document #: 38-06024 Rev. *C
Page 23 of 28
CY7C43663AV
CY7C43643AV
CY7C43683AV
Switching Waveforms (continued)
Timing for AF when FIFO is Almost Full (CY Standard and FWFT Modes) [2, 37, 38, 39]
tSKEW2[40]
CLKA
tENS
tENH
ENA
tPAF
AF
tPAF
[D – (Y + 1)] Words in FIFO
(D – Y) Words in FIFO
CLKB
tENS
[D – (Y + 2)] Words in
FIFO
tENH
tENS
tENH
ENB
Timing for AE when FIFO is Almost Empty (CY Standard and FWFT Modes)
[ 2, 41, 42]
CLKA
tENS
tENH
tENS
tENH
ENA
tSKEW2[43]
CLKB
X Words in FIFO
tPAE
tPAE
AE
X Word in FIFO
(X + 1) Words in FIFO (X + 2) Words in FIFO
tENS
(X+2)Words in FIFO
tENH tENS
tENH
ENB
Notes:
37. Port A Write (CSA = LOW, W/RA = HIGH, MBA = LOW), Port B Read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been
read from the FIFO.
38. D = Maximum FIFO Depth = 1K for the CY7C43643AV, 4K for the 43663AV, and 16K for the CY7C43683AV.
39. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
40. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW2, then AF may transition HIGH one CLKB cycle later than shown.
41. Port A Write (CSA = LOW, W/RA = HIGH, MBA = LOW), Port B Read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been
read from the FIFO.
42. If Port B size is word or byte, AE is set LOW by the last word or byte Read from FIFO, respectively.
43. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown.
Document #: 38-06024 Rev. *C
Page 24 of 28
CY7C43663AV
CY7C43643AV
CY7C43683AV
Switching Waveforms (continued)
Timing for Mail1 Register and MBF1 Flag (CY Standard and FWFT Modes)
[44]
CLKA
tENS
tENH
CSA
tENS
tENH
tENS
tENH
tENS
tENH
tDS
tDH
[45]
W/RA
MBA
ENA
A0–35
W1
CLKB
tPMF
tPMF
MBF1
CSB
[28]
W/RB
MBB
tENS
tENH
ENB
tEN
B0−35
tMDV
FIFO Output
Register
tDIS
tPMR
W1 (Remains valid in Mail1 Register after Read)
Notes:
44. If Port B is configured for word size, data can be written to the Mail1 register using A0–17 (A18–35 are “Don’t Care” inputs). In this first case B0–17 will have
valid data (B18–35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0–8 (A9–35 are “Don’t Care”
inputs). In this second case, B0–8 will have valid data (B9–35 will be indeterminate).
45. If W/RA switches from Read to Write before the assertion of CSA, tENS = tDIS + tENS.
Document #: 38-06024 Rev. *C
Page 25 of 28
CY7C43663AV
CY7C43643AV
CY7C43683AV
Switching Waveforms (continued)
Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes) [46]
CLKB
tENS
tENH
tENS
tENH
tENS
tENH
tENS
tENH
tDS
tDH
CSB
[28]
W/RB
MBB
ENB
B0–35
W1
CLKA
tPMF
tPMF
MBF2
CSA
[45]
W/RA
MBA
tENS
ENA
tMDV
tEN
A0−35
FIFO Retransmit Timing
FIFO2 Output
Register
tENH
tPMR
tDIS
W1 (Remains valid in Mail2 Register after Read)
[46, 47, 48, 49, 50]
CLKA
CLKB
tRSTS
tRSTH
RT
t RTR
ENB
EFB/FFA
Notes:
46. If Port B is configured for word size, data can be written to the Mail2 register using B0–17 (B18–35 are don’t care inputs). In this first case A0–17 will have valid
data (A18–35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0–8 (B9–35 are “Don’t Care” inputs).
In this second case, A0–8 will have valid data (A9–35 will be indeterminate).
47. Clocks are free-running in this case. CY standard mode only. Write operation should be prohibited one Write clock cycle before the falling edge of RT, and
during the retransmit operation, i.e, when RT is LOW and tRTR after the RT rising edge.
48. The Empty and Full flags may change state during Retransmit as a result of the offset of the Read and Write pointers, but the Empty and Full flags will be
valid at tRTR.
49. For the AE and AF flags, two clock cycles are necessary after tRTR to update these flags.
50. The number of 36-/18-/9-bit words written into the FIFO should be less than full depth minus 2/4/8 words between the reset of the FIFO (master or partial)
and the Retransmit setup.
Document #: 38-06024 Rev. *C
Page 26 of 28
CY7C43663AV
CY7C43643AV
CY7C43683AV
3.3V 1K × 36 Unidirectional Synchronous FIFO with Bus Matching
Speed (ns)
Ordering Code
Package Name
Package Type
Operating Range
7
CY7C43643AV-7AC
A128
128-lead Thin Quad Flat Package
Commercial
10
CY7C43643AV-10AC
A128
128-lead Thin Quad Flat Package
Commercial
15
CY7C43643AV-15AC
A128
128-lead Thin Quad Flat Package
Commercial
3.3V 4K × 36 Unidirectional Synchronous FIFO with Bus Matching
Speed (ns)
Ordering Code
Package Name
Package Type
Operating Range
7
CY7C43663AV-7AC
A128
128-lead Thin Quad Flat Package
Commercial
10
CY7C43663AV-10AC
A128
128-lead Thin Quad Flat Package
Commercial
15
CY7C43663AV-15AC
A128
128-lead Thin Quad Flat Package
Commercial
3.3V 16K × 36 Unidirectional Synchronous FIFO with Bus Matching
Speed (ns)
Ordering Code
Package Name
PackageType
OperatingRange
7
CY7C43683AV-7AC
A128
128-lead Thin Quad Flat Package
Commercial
10
CY7C43683AV-10AC
A128
128-lead Thin Quad Flat Package
Commercial
15
CY7C43683AV-15AC
A128
128-lead Thin Quad Flat Package
Commercial
10
CY7C43683AV-10AI
A128
128-lead Thin Quad Flat Package
Industrial
Package Diagram
128-lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128
51-85101-B
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-06024 Rev. *C
Page 27 of 28
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C43663AV
CY7C43643AV
CY7C43683AV
Document Title: CY7C43643AV/CY7C43663AV/CY7C43683AV 3.3V 1K/4K/16K x36 Unidirectional Synchronous FIFO
with Bus Matching
Document Number: 38-06024
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
107253
05/23/01
SZV
Change from Spec 38-00776 to 38-06024
*A
109944
01/10/02
FSG
Preliminary to final
*B
117210
08/26/02
OOR
Added footnote to retransmit timing
Added note to retransmit section
*C
122276
12/26/02
RBI
Document #: 38-06024 Rev. *C
Power up requirements added to Maximum Ratings Information
Page 28 of 28