Anpec APW7035CKC-TUL Advanced pwm and linear power control Datasheet

APW7035
Advanced PWM and Linear Power Control
Features
General Description
•
The APW7035 integrates PWM controller and linear
controller , as well as the monitoring and protection
functions into a single package , which provides two
controlled power outputs with over-voltage and overcurrent protections. The PWM controller regulates
the DDR reference voltage (1.25V) or GPU Voltage
(2.05V) with a synchronous-rectified buck converter.
The linear controller regulates power for Memory
Voltage.
2 Regulated Voltage are provided
− Switching Power for Fixed Voltage (1.25V /
2.05V) or Adjustable Voltage
− Linear Regulator for FBVDDQ(2.5V)
•
Simple Single-Loop Control Design
− Voltage-Mode PWM Control
•
Excellent Output Voltage Regulation
The precision reference and voltage-mode PWM
control provide ±1% static regulation. The linear controller drives an external N-channel MOSFET to provide adjustable voltage.
− PWM Output : ±1%
− Linear Output : ±3%
•
Fast Transient Response
− High-Bandwidth Error Amplifier
− Full 0% to 100% Duty Ratio
•
•
•
The APW7035 monitors all the output voltages , and
a single Power Good signal is issued when the PWM
Voltage is within ±10% of the DAC setting and the
Linear regulator output levels are above their undervoltage thresholds. Additional built-in over-voltage protection for the PWM output uses the lower MOSFET
to prevent output voltages above 115% of the DAC
setting. The PWM over-current function monitors the
output current by using the voltage drop across the
upper MOSFET’s RDS(ON) , eliminating the need for a
current sensing resistor.
Power-Good Output Voltage Monitor
Over-Voltage and Over-Current Fault Monitors
Small Converter Size
− Constant Frequency Operation(200kHz)
− Reduce External Component Count
Applications
•
•
•
•
The APW7035A/B/C/D support a TTL 3-input Digital
to Analog converter that adjusts the synchronousrectified buck converter output from 1.00V to 3.20V
, reference to Table1.
Motherboard Power Regulation for Computers
Low-Voltage Distributed Power Supplies
VGA Card Power Regulation
Termination Voltage
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jul., 2001
1
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APW7035
Pin Description
VCC
1
20
UGATE
VCC
1
20
UGATE
DRIVE
2
19
PHASE
DRIVE
2
19
PHASE
NC
3
18
LGATE
VID2
3
18
LGATE
NC
4
17
PGND
VID1
4
17
PGND
PGOOD
5
16
OCSET
VID0
5
16
OCSET
SD
6
15
VSEN1
SD
6
15
VSEN1
VSEN2
7
14
FB
VSEN2
7
14
FB
SS
8
13
COMP
SS
8
13
COMP
NC
9
12
NC
NC
9
12
NC
VAUX
10
11
GND
VAUX
10
11
GND
APW7035-12/19
APW7035A/B/C/D
Ordering Information
V o ltag e C o de
12 : 1.2 5V
2 0 : 2.05 V
A : 1 .0 0V ~1 .35 V
B : 1 .40 V ~ 1.75 V C : 1 .8 0V ~2 .40 V D : 2 .5 0V ~3 .20 V
P a c ka ge C od e
K : S O P -2 0
T e m p . R an ge
C : 0 to 70 ° C
H a nd ling C od e
T U : T u be
T R : T ap e & R ee l
L ea d F re e C o de
L : L ea d F re e D evice
B lan k : O rigina l D evice
A P W 703 5
L ea d F re e C o de
H a nd ling C od e
T e m p . R an ge
P a c ka ge C od e
V o ltag e C o de
Block Diagram
VSEN1
VSEN2
VCC
OCSET
VAUX
Power-on
Reset (POR)
´1.10
-
-
+
DRIVE
+
+
VAUX
2 0 0m A
´0.75
´0.90
PGOOD
+
-
+
1.5V
-
´1.15
+
-
VCC
INHIBIT
SD
SOFT
START &
FAULT
LOGIC
OV
UGATE
OC1
+
-
V CC
PHASE
INHIBIT
+
ERROR
AMP1
2 8m A
SS
-
DAC
4.5V
DAC
VID0 VID1 VID2
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jul., 2001
PWM
COMP1
SYNCH
DRIVE
+
V CC
PWM1
LGATE
PGND
-
+
-
GATE
CONTROL
+
-
OSCILLATOR
V DAC
FB
2
GND
COMP
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APW7035
Absolute Maximum Ratings
Symbol
VCC
Parameter
Rating
Unit
15
V
GND -0.3 V to VCC +0.3
V
Supply Voltage
VI , VO
Input , Output or I/O Voltage
TA
Operating Ambient Temperature Range
0 to 70
°C
TJ
Junction Temperature Range
0 to 125
°C
TSTG
Storage Temperature Range
-65 to +150
°C
300 ,10 seconds
°C
Value
Unit
75
65
°C/W
TS
Soldering Temperature
Thermal Characteristics
Symbol
R θJA
Parameter
Thermal Resistance in Free Air
SOIC
SOIC (with 3in2 of Copper)
Electrical Characteristics
(Recommended operating conditions , Unless otherwise noted) Refer to Block and Simplified Power System
Diagrams , and Typical Application Schematic.
Symbol
Parameter
Test Conditions
APW7035
Min. Typ. Max.
Unit
9
mA
VCC Supply Current
ICC
Nominal Supply Current
UGATE, LGATE, DRIVE
open
Power-on Reset
Rising VCC Threshold
Vocset=4.5V
Falling VCC Threshold
Vocset=4.5V
Rising VAUX Threshold
Vocset=4.5V
VAUX Threshold Hysteresis
Vocset=4.5V
10.7
8.2
V
2.5
Rising VOCSET Threshold
V
V
0.5
V
1.26
V
Oscillator
FOCS
∆VOSC
Free Running Frequency
RT= Open
Ramp Amplitude
RT= Open
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jul., 2001
3
185
200
1.9
215
kHz
VP-P
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APW7035
Electrical Characteristics Cont.
(Recommended operating conditions , Unless otherwise noted) Refer to Block and Simplified Power System
Diagrams , and Typical Application Schematic.
Symbol
Parameter
Test Conditions
DAC and Bandgap Reference
VDAC DACOUT Voltage accuracy
VBG
Bandgap Reference Voltage
Bandgap Reference Tolerance
Linear Regulators
Regulation
Output Drive Current
VAUX-VDRIVE >0.6V
Synchronous PWM Controller Error Amplifier
DC Gain
GBWP Gain-Bandwidth Product
SR
Slew Rate
COMP=10pF
PWM Controller Gate Driver
IUGATE UGATE Source
VCC=12V, VUGATE =6V
RUGATE UGATE Sink
VUGATE1-PHASE =1V
ILGATE LGATE Source
VCC=12V, VLGATE =1V
RLGATE LGATE Sink
VLGATE= 1V
Protection
VSEN1 Over-Voltage
VSEN1 Rising
Protection
IOCSET OCSET Current Source
VOCSET= 4.5VDC
ISS
Soft Start Current
Power Good
VSEN1 Upper Threshold
VSEN1 Rising
VSEN1 Under Voltage
VSEN1 Rising
VSEN1 Hysteresis
Upper /Lower Threshold
VPGOOD PGOOD Voltage Low
IPGOOD= -4mA
APW7035
Min. Typ. Max.
-1.0
+1.0
1.265
-2.5
20
+2.5
%
V
%
3
40
%
mA
88
15
6
dB
MHz
V/µs
1
A
3
Ω
A
Ω
115
120
%
200
28
230
µA
µA
3.5
1
170
Unit
109
93
2
0.8
%
%
%
V
Functional Pin Description
VCC (Pin 1)
DRIVE (Pin 2)
Provide a 12V bias supply for the IC to this pin. This
pin also provides the gate bias charge for all the
MOSFETs controlled by the IC. The voltage at this
pin is monitored for Power-On Reset (POR) purposes.
Connect this pin to the gate of an external MOSFET.
This pin provides the drive for the FBVDDQ
regulator’s pass transistor.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jul., 2001
4
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APW7035
Functional Pin Description cont.
NC (Pin 3, Pin 4 and Pin 5)
No Connect. (APW7035-12,19)
(instead of N-channel MOSFETs) are employed as
pass elements. The voltage at this pin is monitored
for power-on reset purposes.
PGOOD (Pin 5)
GND (Pin 11)
PGOOD is an open drain output used to indicate the
status of the output voltages. This pin is pulled low
when the synchronous regulator output is not within
±10% of the DAC reference voltage or Linear regulator outputs are below under-voltage thresholds.
(APW7035-A,B,C,D)
Signal ground for the IC. All voltage levels are measured with respect to this pin.
FB and COMP (Pin 13, and 14)
COMP and FB are the available external pins of the
PWM converter error amplifier. The FB pin is the
inverting input of the error amplifier. Similarly , the
COMP pin is the error amplifier output. These pins
are used to compensate the voltage-mode control
feedback loop of the synchronous PWM converter.
VID2 , VID1 , VID0 (Pin 3,4 and 5)
VID0-2 are the TTL-compatible input pins to the 3-bit
DAC. The logic states of these three pins program
the internal voltage reference (DAC). The level of DAC
sets the microprocessor core converter output voltage , as well as the corresponding PGOOD and OVP
thresholds. (APW7035-A,B,C,D)
VSEN1 (Pin 15)
This pin is connected to the PWM converter’s output
voltage. The PGOOD and OVP comparator circuits
use this signal to report output voltage status and for
over- voltage protection.
SD (Pin 6)
The pin shuts down all the outputs. A TLL-compatible
, logic lebel high signal applied at this pin immediately discharges the soft-start capacitor , disbling all
the output.
OCSET (Pin 16)
Connect a resistor from this pin to the drain of the
respective upper MOSFET. This resistor , an internal 200µA current source , and the upper MOSFET’s
on-resistance set the converter over-current trip point.
An over-current trip cycles the soft-start function. The
voltage at this pin is monitored for power-on reset
(POR) purposes and pulling this pin low with an open
drain device will shutdown the IC.
VSEN2 (Pin 7)
Connect this pin to a resistor divider to set the linear
regulator (FBVDDQ) output voltage.
SS (Pin 8)
Connect a capacitor from this pin to ground. This
capacitor , along with an internal 28µA current source
, sets the soft-start interval of the converter.
PGND (Pin 17)
NC (Pin 9 and Pin12)
This is the power ground connection. Tie the synchronous PWM converter’s lower MOSFET source
to this pin.
No Connection.
LGATE (Pin 18)
VAUX (Pin 10)
Connect LGATE to the PWM converter’s lower
MOSFET gate. This pin provides the gate drive for
the lower MOSFET.
This pin provides boost current for the linear regulator’s
output drives in the event bipolar NPN transistors
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jul., 2001
5
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APW7035
Functional Pin Description cont.
PHASE (Pin 19)
UGATE (Pin 20)
Connect the PHASE pin to the PWM converter’s upper MOSFET source. This pin represents the gate
drive return current path and is used to monitor the
voltage drop across the upper MOSFET for over-current protection.
Connect UGATE pin to the PWM converter’s upper
MOSFET gate. This pin provides the gate drive for
the upper MOSFET.
Table1 Output Voltage Program
VID2
0
0
0
0
1
1
1
1
VID2
0
0
0
0
1
1
1
1
VID1
0
0
1
1
0
0
1
1
VID1
0
0
1
1
0
0
1
1
VID0
0
1
0
1
0
1
0
1
VID0
0
1
0
1
0
1
0
1
VID2
0
0
0
0
1
1
1
1
VID2
0
0
0
0
1
1
1
1
APW7035-A
1.35V
1.30V
1.25V
1.20V
1.15V
1.10V
1.05V
1.00V
APW7035-C
2.40V
2.30V
2.20V
2.10V
2.00V
1.90V
1.80V
0
VID1
0
0
1
1
0
0
1
1
VID1
0
0
1
1
0
0
1
1
VID0
0
1
0
1
0
1
0
1
VID0
0
1
0
1
0
1
0
1
APW7035-B
1.75V
1.70V
1.65V
1.60V
1.55V
1.50V
1.45V
1.40V
APW7035-D
3.20V
3.10V
3.00V
2.90V
2.80V
2.70V
2.60V
2.50V
Simplified Power System Diagram
5.0V IN
3.3 V IN
Q1
Q3
V OUT2
Linear Controller
V OUT1
PWM1
Controller
Q2
APW7035
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jul., 2001
6
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APW7035
Typical Application Circuit
C2
220pF
R1
10
12V
5.0V
L1
1
C1
1uF
VCC
OCSET
6
SD
PGOOD
UGATE
20
10
LGATE
VAUX
2
R2
66.7
2.5V
C11
330uF
R3
100
PGND
8
Q2B
APM7313
FB
VENS1
SS
COMP
15
14
C7
10pF
R9
3K
13
R8
100
11
C8
2700pF
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jul., 2001
C6
330uF
R7
64
17
GND
C9
0.1uF
C5
330uF
18
DRIVE
VENS1
7
2.05V
L2
19
R6
5.1
Q1
APM3055L
C10
330uF
Q2A
APM7313
R5
5.1
PHASE
C4
10uF
R4
1.2K
5
APW7035-12
3.3V
C3
330uF
16
7
R10
150K
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APW7035
Package Information
SO – 300mil ( Reference JEDEC Registration MS-013)
D
h*45
C
H
GAUGE
PLANE
E
1
2
3
A
Dim
Millimeters
L
A1
B
e
Variations
Dim
Inches
1
Variations
Min.
Max.
Variations
Min.
Max.
Min.
Max.
Variations
Min.
Max.
2.65
SO-20
12.60
13.0
A
0.093
0.1043
SO-20
0.496
0.512
A1
2.35
0.10
0.30
SO-24
15.20
15.60
A1
0.004
0.0120
SO-24
0.599
0.614
B
0.33
0.51
SO-28
17.70
18.11
B
0.013
0.020
SO-28
0.697
0.713
0.23
0.32
A
C
D
E
e
H
C
0.0091 0.0125
See variations
7.40
7.60
D
See variations
E
0.2914 0.2992
1.27BSC
10
10.65
e
0.050BSC
H
0.394
0.419
h
0.25
0.75
h
0.010
0.029
L
0.40
1.27
L
0.016
0.050
φ1
0°
8°
φ1
0°
8°
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jul., 2001
8
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APW7035
Physical Specifications
Terminal Material
Lead Solderability
Packaging
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb)
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
1000 devices per reel
Reflow Condition
(IR/Convection or VPR Reflow)
tp
TP
C ritical Zone
T L to T P
T e m p e ra tu re
R am p-up
TL
tL
T sm ax
T sm in
R am p-down
ts
Preheat
25
t 25 °C to Peak
T im e
Classificatin Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Large Body
Small Body
Average ramp-up rate
3°C/second max.
(TL to TP)
Preheat
- Temperature Min (Tsmin)
100°C
- Temperature Mix (Tsmax)
150°C
- Time (min to max)(ts)
60-120 seconds
Tsmax to TL
- Ramp-up Rate
Tsmax to TL
- Temperature(TL)
183°C
- Time (tL)
60-150 seconds
Peak Temperature(Tp)
225 +0/-5°C
240 +0/-5°C
Time within 5°C of actual Peak
10-30 seconds
10-30 seconds
Temperature(tp)
Ramp-down Rate
6°C/second max.
6 minutes max.
Time 25°C to Peak Temperature
Pb-Free Assembly
Large Body
Small Body
3°C/second max.
150°C
200°C
60-180 seconds
3°C/second max
217°C
60-150 seconds
245 +0/-5°C
250 +0/-5°C
10-30 seconds
20-40 seconds
6°C/second max.
8 minutes max.
Note: All temperatures refer to topside of the package. Measured on the body surface.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jul., 2001
9
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APW7035
Reliability test program
Test item
Method
Description
SOLDERABILITY
MIL-STD-883D-2003
245°C , 5 SEC
HOLT
MIL-STD-883D-1005.7
1000 Hrs Bias @ 125 °C
PCT
JESD-22-B, A102
168 Hrs, 100 % RH , 121°C
TST
MIL-STD-883D-1011.9
-65°C ~ 150°C, 200 Cycles
ESD
MIL-STD-883D-3015.7
VHBM > 2KV, VMM > 200V
Latch-Up
JESD 78
10ms , Itr > 100mA
Tape & Reel Dimensions
t
D
P
Po
E
P1
Bo
F
W
Ko
Ao
D1
T2
J
C
A
B
T1
SOP-20
330±1
62 ± 1.5
Application
F
D
C
12.75
±0.15
D1
SOP-20
11.5 ± 0.1
1.5+0.1
1.5+0.25
Application
A
B
J
T1
T2
W
2 + 0.6
24.4 +0.2
2± 0.2
Po
P1
Ao
24 + 0.3
- 0.1
Bo
4.0 ± 0.1
2.0 ± 0.1
8.2 ± 0.1
13± 0.1
P
E
12± 0.1
1.75± 0.1
Ko
t
2.5± 0.1 0.35±0.013
(mm)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jul., 2001
10
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APW7035
Cover Tape Dimensions
Application
SOP- 20
Carrier Width
24
Cover Tape Width
21.3
Devices Per Reel
1000
Customer Service
Anpec Electronics Corp.
Head Office :
5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jul., 2001
11
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