BSI BS62LV256SIP70 Very low power cmos sram 32k x 8 bit Datasheet

Very Low Power CMOS SRAM
32K X 8 bit
BS62LV256
Pb-Free and Green package materials are compliant to RoHS
n FEATURES
n DESCRIPTION
Ÿ Wide VCC operation voltage : 2.4V ~ 5.5V
Ÿ Very low power consumption :
VCC = 3.0V Operation current : 25mA (Max.) at 70ns
1mA (Max.) at 1MHz
Standby current : 0.01uA(Typ.) at 25OC
VCC = 5.0V Operation current : 40mA (Max.) at 55ns
2mA (Max.) at 1MHz
Standby current : 0.4uA (Typ.) at 25OC
Ÿ High speed access time :
-55
55ns(Max.) at VCC : 4.5~5.5V
-70
70ns(Max.) at VCC : 3.0~5.5V
Ÿ Automatic power down when chip is deselected
Ÿ Easy expansion with CE and OE options
Ÿ Three state outputs and TTL compatible
Ÿ Fully static operation
Ÿ Data retention supply voltage as low as 1.5V
The BS62LV256 is a high performance, very low power CMOS Static
Random Access Memory organized as 32,768 by 8 bits and
operates form a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical CMOS standby
current of 0.01uA and maximum access time of 70ns in 3.0V
operation.
Easy memory expansion is provided by an active LOW chip enable
(CE), and active LOW output enable (OE) and three-state output
drivers.
The BS62LV256 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV256 is available in DICE form, JEDEC standard 28 pin
330mil Plastic SOP, 600mil Plastic DIP, 8mmx13.4mm TSOP
(normal type).
n POWER CONSUMPTION
POWER DISSIPATION
PRODUCT
FAMILY
OPERATING
TEMPERATURE
STANDBY
Operating
(ICCSB1, Max)
VCC=5.0V
VCC=3.0V
PKG TYPE
(ICC, Max)
1MHz
VCC=5.0V
10MHz
fMax.
1MHz
VCC=3.0V
10MHz
fMax.
BS62LV256DC
BS62LV256PC
BS62LV256SC
DICE
Commercial
+0OC to +70OC
4.0uA
0.4uA
1.5mA
18mA
35mA
0.8mA
12mA
20mA
BS62LV256TC
SOP-28
TSOP-28
BS62LV256PI
PDIP-28
Industrial
-40OC to +85OC
BS62LV256SI
5.0uA
0.7uA
2mA
20mA
40mA
1mA
15mA
25mA
BS62LV256TI
SOP-28
TSOP-28
n PIN CONFIGURATIONS
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
PDIP-28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
•
BS62LV256PC
BS62LV256PI
BS62LV256SC
BS62LV256SI
BS62LV256TC
BS62LV256TI
n BLOCK DIAGRAM
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A5
A6
A7
A12
A14
A13
A8
A9
A11
Address
9
Input
512
Row
Decoder
Memory Array
512X512
Buffer
512
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
8
8
Data
Input
Buffer
Data
Output
Buffer
8
Column I/O
Write Driver
Sense Amp
8
64
Column Decoder
6
CE
WE
Control
Address Input Buffer
OE
VCC
GND
A4 A3 A2 A1 A0 A10
Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.
R0201-BS62LV256
1
Revision 2.6
Sep.
2006
BS62LV256
n PIN DESCRIPTIONS
Name
Function
A0-A14 Address Input
These 15 address inputs select one of the 32,768 x 8-bit in the RAM
CE Chip Enable Input
CE is active LOW. Chip enable must be active when data read form or write to the
device. If chip enable is not active, the device is deselected and is in standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
DQ0-DQ7 Data Input/Output
Ports
VCC
There 8 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
GND
Ground
n TRUTH TABLE
MODE
CE
WE
OE
I/O OPERATION
VCC CURRENT
Not selected
(Power Down)
H
X
X
High Z
ICCSB, ICCSB1
Output Disabled
L
H
H
High Z
ICC
Read
L
H
L
DOUT
ICC
Write
L
L
X
DIN
ICC
NOTES: H means VIH; L means VIL; X means don’t care (Must be VIH or VIL state)
n ABSOLUTE MAXIMUM RATINGS
TBIAS
TSTG
n OPERATING RANGE
RATING
UNITS
RANG
AMBIENT
TEMPERATURE
VCC
Terminal Voltage with
Respect to GND
Temperature Under
Bias
-0.5(2) to 7.0
V
Commercial
0OC to + 70OC
2.4V ~ 5.5V
-40 to +125
O
C
Industrial
-40OC to + 85OC
2.4V ~ 5.5V
Storage Temperature
-60 to +150
O
C
SYMBOL
VTERM
(1)
PARAMETER
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
20
mA
n CAPACITANCE
O
(TA = 25 C, f = 1.0MHz)
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. –2.0V in case of AC pulse width less than 30 ns.
R0201-BS62LV256
(1)
CIN
CIO
Input
Capacitance
Input/Output
Capacitance
VIN = 0V
6
pF
VI/O = 0V
8
pF
1. This parameter is guaranteed and not 100% tested.
2
Revision 2.6
Sep.
2006
BS62LV256
O
O
n DC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C)
PARAMETER
NAME
PARAMETER
TEST CONDITIONS
MIN.
TYP.(1)
MAX.
UNITS
2.4
--
5.5
V
VCC
Power Supply
VIL
Input Low Voltage
-0.5(2)
--
0.8
V
VIH
Input High Voltage
2.2
--
VCC+0.3(3)
V
IIL
Input Leakage Current
--
--
1
uA
ILO
Output Leakage Current
--
--
1
uA
VOL
Output Low Voltage
V CC = Max, IOL = 0.5mA
--
--
0.4
V
VOH
Output High Voltage
V CC = Min, IOH = -0.5mA
2.4
--
--
V
ICC(5)
Operating Power Supply
Current
CE = VIL,
VCC=3.0V
--
--
25
VCC=5.0V
--
--
40
Operating Power Supply
Current
CE = VIL,
VCC=3.0V
--
--
1
IDQ = 0mA, f = 1MHz
VCC=5.0V
--
--
2
CE = VIH,
VCC=3.0V
--
--
1.0
IDQ = 0mA
VCC=5.0V
--
--
2.0
CE≧VCC-0.2V,
VCC=3.0V
--
0.01
0.7
VIN≧V CC-0.2V or VIN≦0.2V
VCC=5.0V
--
0.4
5.0
ICC1
ICCSB
ICCSB1(6)
VIN = 0V to VCC
CE= VIH, or OE = VIH,
VI/O = 0V to V CC
Standby Current – TTL
Standby Current – CMOS
IDQ = 0mA, f =
FMAX(4)
1. Typical characteristics are at TA=25OC and not 100% tested.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns.
mA
mA
mA
uA
4. FMAX=1/tRC.
5. ICC (MAX.) is 20mA/35mA at VCC=3.0V/5.0V and TA=70OC.
6. ICCSB1(MAX.) is 0.4uA/4.0uA at VCC=3.0V/5.0V and TA=70OC.
O
O
n DATA RETENTION CHARACTERISTICS (TA = -40 C to +85 C)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP. (1)
MAX.
UNITS
VDR
VCC for Data Retention
CE≧VCC-0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
1.5
--
--
V
ICCDR(3)
Data Retention Current
CE≧VCC-0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
--
0.01
0.7
uA
tCDR
Chip Deselect to Data
Retention Time
0
--
--
ns
tRC (2)
--
--
ns
tR
See Retention Waveform
Operation Recovery Time
1. VCC=1.5V, TA=25OC and not 100% tested.
2. tRC = Read Cycle Time.
3. ICCDR(Max.) is 0.4uA at TA=70OC.
n LOW VCC DATA RETENTION WAVEFORM (CE Controlled)
Data Retention Mode
VCC
VCC
VDR≧1.5V
tCDR
CE
R0201-BS62LV256
VIH
VCC
tR
CE≧VCC - 0.2V
3
VIH
Revision 2.6
Sep.
2006
BS62LV256
n AC TEST CONDITIONS
n KEY TO SWITCHING WAVEFORMS
(Test Load and Input/Output Reference)
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
1V/ns
Input and Output Timing
Reference Level
0.5Vcc
tCLZ, tOLZ, tCHZ, tOHZ, tWHZ
Output Load
WAVEFORM
CL = 5pF+1TTL
CL
=
100pF+1TTL
Others
ALL INPUT PULSES
VCC
1 TTL
Output
90%
10%
GND
CL(1)
90%
10%
→ ←
Rise Time :
1V/ns
→ ←
Fall Time :
1V/ns
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM “H” TO “L”
WILL BE CHANGE
FROM “H” TO “L”
MAY CHANGE
FROM “L” TO “H”
WILL BE CHANGE
FROM “L” TO “H”
DON’T CARE
ANY CHANGE
PERMITTED
CHANGE :
STATE UNKNOW
DOES NOT
APPLY
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
1. Including jig and scope capacitance.
O
O
n AC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C)
READ CYCLE
CYCLE TIME : 55ns
(VCC = 4.5~5.5V)
MIN. TYP. MAX.
CYCLE TIME : 70ns
(VCC = 3.0~5.5V)
MIN. TYP. MAX.
JEDEC
PARAMETER
NAME
PARANETER
NAME
tAVAX
tRC
Read Cycle Time
55
--
--
70
--
--
ns
tAVQX
tAA
Address Access Time
--
--
55
--
--
70
ns
tE1LQV
tACS
Chip Select Access Time
--
--
55
--
--
70
ns
tGLQV
tOE
Output Enable to Output Valid
--
--
25
--
--
35
ns
tE1LQX
tCLZ
Chip Select to Output Low Z
10
--
--
10
--
--
ns
tGLQX
tOLZ
Output Enable to Output Low Z
10
--
--
10
--
--
ns
tE1HQZ
tCHZ
Chip Select to Output High Z
--
--
30
--
--
35
ns
tGHQZ
tOHZ
Output Enable to Output High Z
--
--
25
--
--
30
ns
tAVQX
tOH
Data Hold from Address Change
10
--
--
10
--
--
ns
R0201-BS62LV256
DESCRIPTION
4
UNITS
Revision 2.6
Sep.
2006
BS62LV256
n SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1
(1,2,4)
tRC
ADDRESS
tAA
tOH
tOH
DOUT
READ CYCLE 2
(1,3,4)
CE
tACS
tCLZ
tCHZ
(5)
(5)
DOUT
READ CYCLE 3
(1, 4)
tRC
ADDRESS
tAA
OE
tOH
tOE
tOLZ
CE
tACS
tCLZ
(5)
tOHZ
tCHZ
(5)
(1,5)
DOUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL.
5. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
R0201-BS62LV256
5
Revision 2.6
Sep.
2006
BS62LV256
O
O
n AC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C)
WRITE CYCLE
CYCLE TIME : 55ns
(VCC = 4.5~5.5V)
CYCLE TIME : 70ns
(VCC = 3.0~5.5V)
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
Write Cycle Time
55
--
--
70
--
--
ns
tAW
Address Valid to End of Write
55
--
--
70
--
--
ns
tE1LWH
tCW
Chip Select to End of Write
55
--
--
70
--
--
ns
tWLWH
tWP
Write Pulse Width
35
--
--
40
--
--
ns
tAVWL
tAS
Address Set up Time
0
--
--
0
--
--
ns
tWHAX
tWR
Write Recovery Time
0
--
--
0
--
--
ns
tWLQZ
tWHZ
Write to Output High Z
--
--
25
--
--
30
ns
tDVWH
tDW
Data to Write Time Overlap
35
--
--
40
--
--
ns
tWHDX
tDH
Data Hold from Write Time
0
--
--
0
--
--
ns
tGHQZ
tOHZ
Output Disable to Output in High Z
--
--
25
--
--
30
ns
tWHQX
tOW
End of Write to Output Active
5
--
--
5
--
--
ns
JEDEC
PARAMETER
NAME
PARANETER
NAME
tAVAX
tWC
tAVWH
DESCRIPTION
(CE, WE)
UNITS
n SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE 1
(1)
tWC
ADDRESS
tWR
(3)
OE
tCW
(11)
(5)
CE
tAW
WE
tWP
tAS
tOHZ
(2)
(4,10)
DOUT
tDH
tDW
DIN
R0201-BS62LV256
6
Revision 2.6
Sep.
2006
BS62LV256
WRITE CYCLE 2
(1,6)
tWC
ADDRESS
tCW
(5)
CE
(11)
tAW
tWP
WE
tAS
tWHZ
(2)
(4,10)
tOW
(7)
(8)
DOUT
tDW
tDH
(8,9)
DIN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive. The
data input setup and hold timing should be referenced to the second transition edge of the
signal that terminates the write.
3. tWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to
the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
11. tCW is measured from the later of CE going low to the end of write.
R0201-BS62LV256
7
Revision 2.6
Sep.
2006
BS62LV256
n ORDERING INFORMATION
BS62LV256
X
X
Z
YY
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green, RoHS Compliant
P: Pb free, RoHS Compliant
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
D: DICE
S: SOP
T: TSOP (8mm x 13.4mm)
P: PDIP
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does
not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result
in significant injury or death, including life-support systems and critical medical instruments.
n PACKAGE DIMENSIONS
0.020 ± 0.005X45°
θ
b
WITH PLATING
c c1
b1
BASE METAL
SOP - 28
R0201-BS62LV256
8
Revision 2.6
Sep.
2006
BS62LV256
n PACKAGE DIMENSIONS (continued)
12°(2x)
UNIT
SYMBOL
12°(2x)
e
HD
cL
1
MM
0.0433±0.004
1.10±0.10
A1
0.0045±0.0026
0.115±0.065
A2
0.039±0.002
1.00±0.05
b
0.009±0.002
0.22±0.05
b1
0.008±0.001
0.20±0.03
c
0.004 ~ 0.008
0.10 ~ 0.21
c1
0.004 ~ 0.006
0.10 ~ 0.16
D
0.465±0.004
11.80±0.10
E
0.315±0.004
8.00±0.10
e
0.022±0.004
0.55±0.10
HD
0.528±0.008
13.40±0.20
E
28
b
y
Seating Plane
14
INCH
A
12°(2x)
°
15
"A"
D
GAUGE
A
PLANE
A2
A
L
0.0197 +0.008
- 0.004
0.50 +0.20
- 0.10
L1
0.0315±0.004
0.80±0.10
y
0.004 Max.
0.1 Max.
0
0°~
0°~
8°
8°
0.254
0
A1
14
15
A
SEATING PLANE
12°(2x)
L
L1
"A" DATAIL VIEW
WITH PLATING
1
28
b
c c1
BASE METAL
b1
SECTION A-A
TSOP - 28
PDIP - 28
R0201-BS62LV256
9
Revision 2.6
Sep.
2006
BS62LV256
n Revision History
Revision No.
History
Draft Date
2.4
Add Icc1 characteristic parameter
Jan. 13, 2006
2.5
Change I-grade operation temperature range
- from –25OC to –40OC
May. 25, 2006
2.6
Revised ICCSB1 sepc.
- from 1.0uA to 4.0uA for 5V C-grade
- from 2.0uA to 5.0uA for 5V I-grade
- from 0.2uA to 0.4uA for 3V C-grade
- from 0.4uA to 0.7uA for 3V I-grade
Sep. 05, 2006
Remark
Revised ICCDR sepc.
- from 0.2uA to 0.4uA for C-grade
- from 0.4uA to 0.7uA for I-grade
R0201-BS62LV256
10
Revision 2.6
Sep.
2006
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