Dual Input Network Clock
Generator/Synchronizer
AD9549
FEATURES
APPLICATIONS
Flexible reference inputs
Input frequencies: 8 kHz to 750 MHz
Two reference inputs
Loss of reference indicators
Auto and manual holdover modes
Auto and manual switchover modes
Smooth A-to-B phase transition on outputs
Excellent stability in holdover mode
Programmable 16 + 1-bit input divider, R
Differential HSTL clock output
Output frequencies to 750 MHz
Low jitter clock doubler for frequencies of >400 MHz
Single-ended CMOS output for frequencies of <150 MHz
Programmable digital loop filter (<1 Hz to ~100 kHz)
High speed digitally controlled oscillator (DCO) core
Direct digital synthesizer (DDS) with integrated 14-bit DAC
Excellent dynamic performance
Programmable 16 + 1-bit feedback divider, S
Software controlled power-down
Available 64-lead LFCSP package
Network synchronization
Reference clock jitter cleanup
SONET/SDH clocks up to OC-192, including FEC
Stratum 3/3E reference clocks
Wireless base station, controllers
Cable infrastructure
Data communications
GENERAL DESCRIPTION
The AD9549 provides synchronization for many systems,
including synchronous optical networks (SONET/SDH). The
AD9549 generates an output clock, synchronized to one of two
external input references. The external references may contain
significant time jitter, also specified as phase noise. Using a
digitally controlled loop and holdover circuitry, the AD9549
continues to generate a clean (low jitter), valid output clock during
a loss of reference condition, even when both references have failed.
The AD9549 operates over an industrial temperature range of
−40°C to +85°C.
BASIC BLOCK DIAGRAM
AD9549
S1 TO S4
FDBK_IN
DAC_OUT
REFB_IN
REFERENCE
MONITORS
AND
SWITCHING
R
SERIAL PORT,
I/O LOGIC
DIGITAL PLL
R, S DIVIDERS
HOLDOVER
CLOCK
OUTPUT
DRIVERS
OUT
OUT_CMOS
SYSTEM CLOCK
MULTIPLIER
06744-001
REFA_IN
FILTER
DIGITAL INTERFACE
Figure 1.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700
Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.
AD9549
TABLE OF CONTENTS
Features .............................................................................................. 1
Power-Up ......................................................................................... 42
Applications ....................................................................................... 1
Power-On Reset .......................................................................... 42
General Description ......................................................................... 1
Programming Sequence ............................................................ 42
Basic Block Diagram ........................................................................ 1
Power Supply Partitioning............................................................. 43
Revision History ............................................................................... 3
3.3 V Supplies.............................................................................. 43
Specifications..................................................................................... 4
1.8 V Supplies.............................................................................. 43
DC Specifications ......................................................................... 4
Serial Control Port ......................................................................... 44
AC Specifications.......................................................................... 6
Serial Control Port Pin Descriptions ....................................... 44
Absolute Maximum Ratings ............................................................ 9
Operation of Serial Control Port .............................................. 44
Thermal Resistance ...................................................................... 9
The Instruction Word (16 Bits) ................................................ 45
ESD Caution .................................................................................. 9
MSB/LSB First Transfers ........................................................... 45
Pin Configuration and Function Descriptions ........................... 10
I/O Register Map ............................................................................ 48
Typical Performance Characteristics ........................................... 13
I/O Register Descriptions .............................................................. 53
Input/Output Termination Recommendations .......................... 16
Serial Port Configuration (Register 0x0000 to Register
0x0005) ........................................................................................ 53
Theory of Operation ...................................................................... 17
Overview...................................................................................... 17
Digital PLL Core (DPLLC)........................................................ 17
Phase Detector ............................................................................ 21
Digital Loop Filter Coefficients ................................................ 22
Closed-Loop Phase Offset ......................................................... 24
Lock Detection ............................................................................ 24
Reference Monitors .................................................................... 26
Reference Switchover ................................................................. 27
Holdover ...................................................................................... 29
Output Frequency Range Control ............................................ 32
Reconstruction Filter ................................................................. 32
FDBK_IN Inputs ........................................................................ 33
Reference Inputs ......................................................................... 33
Power-Down and Reset (Register 0x0010 to Register 0x0013)
....................................................................................................... 53
System Clock (Register 0x0020 to Register 0x0023) ............. 54
Digital PLL Control and Dividers (Register 0x0100 to
Register 0x0130) ......................................................................... 55
Free-Run (Single-Tone) Mode (Register 0x01A0 to Register
0x01AD) ...................................................................................... 61
Reference Selector/Holdover (Register 0x01C0 to Register
0x01C3)........................................................................................ 62
Doubler and Output Drivers (Register 0x0200 to Register
0x0201) ........................................................................................ 63
Monitor (Register 0x0300 to Register 0x0335)....................... 64
Calibration (User-Accessible Trim) (Register 0x0400 to
Register 0x0410) ......................................................................... 70
SYSCLK Inputs ........................................................................... 33
Harmonic Spur Reduction (Register 0x0500 to Register
0x0509) ........................................................................................ 71
Harmonic Spur Reduction ........................................................ 35
Applications Information .............................................................. 73
Output Clock Drivers and 2× Frequency Multiplier ............. 36
Sample Applications Circuit ..................................................... 73
Frequency Slew Limiter ............................................................. 37
Outline Dimensions ....................................................................... 74
Frequency Estimator .................................................................. 37
Ordering Guide .......................................................................... 74
Status and Warnings ................................................................... 39
Thermal Performance .................................................................... 41
Rev. D | Page 2 of 76
AD9549
REVISION HISTORY
12/10—Rev. C to Rev. D
Changes to IAVDD (Pin 19, Pin 23 to Pin 26, Pin 29, Pin 30,
Pin44, Pin 45) Parameter ................................................................. 4
Changes to Total Power Dissipation Parameter and Added
Endnote 4 ........................................................................................... 5
Changes to Pin 59 Description ......................................................11
Changes to Direct Digital Synthesizer (DDS) Section ...............20
Changes to Power-Up Section .......................................................42
Changes to Address 0x0002 Default Value (in Table 13) ...........48
Changes to Address 0x0400 and Address 0x40E Default Values
(in Table 13) .....................................................................................52
5/10—Rev. B to Rev. C
Deleted 64-Lead LFCSP (CP-64-1) .................................. Universal
Changes to SYSCLK PLL Enabled/Minimum Differential Input
Level Parameter, Table 2 ................................................................... 6
Updated Outline Dimensions ........................................................74
Changes to Ordering Guide ...........................................................74
1/10—Rev. A to Rev. B
Changes to I/O Register Map Section, Introduction and
Table 13 .............................................................................................48
Changes to Register 0x0405 to Register 0x0408—Reserved
Section ..............................................................................................70
Added Register 0x0406—Part Version Section ...........................71
12/09—Rev. 0 to Rev. A
Added 64-Lead LFCSP (CP-64-7) ................................... Universal
Changes to Total Power Dissipation Parameter ............................ 5
Changes to Serial Port Timing Specifications and
Propagation Delay Parameters ........................................................ 8
Added Exposed Paddle Notation to Figure 2; Changes to
Table 4 ............................................................................................... 10
Corrected DDS Phase Offset Resolution from 16 Bits to
14 Bits Throughout; Change to Figure 25 .................................... 20
Changes to Phase Lock Detection Section .................................. 24
Change to Figure 30 ........................................................................ 25
Changes to Loss of Reference and Reference Frequency
Monitor Sections ............................................................................. 26
Change to Output Frequency Range Control Section ............... 32
Change to Figure 46 ........................................................................ 36
Changes to Frequency Estimator Section .................................... 37
Changes to Programming Sequence Section .............................. 42
Changes to Power Supply Partitioning Section........................... 43
Change to Serial Control Port Section ......................................... 44
Changes to Figure 54 ...................................................................... 46
Added Exposed Paddle Notation to Outline Dimensions and
Changes to Ordering Guide ........................................................... 74
8/07—Revision 0: Initial Version
Rev. D | Page 3 of 76
AD9549
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V ± 5%, AVDD3 = 3.3 V ± 5%, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%. AVSS = 0 V, DVSS = 0 V, unless otherwise noted.
Table 1.
Parameter
SUPPLY VOLTAGE
DVDD_I/O (Pin 1)
DVDD (Pin 3, Pin 5, Pin 7)
AVDD3 (Pin 14, Pin 46, Pin 47, Pin 49)
AVDD3 (Pin 37)
AVDD (Pin 11, Pin 19, Pin 23 to Pin 26, Pin 29,
Pin 30, Pin 36, Pin 42, Pin 44, Pin 45, Pin 53)
SUPPLY CURRENT
IAVDD3 (Pin 14)
IAVDD3 (Pin 37)
IAVDD3 (Pin 46, Pin 47, Pin 49)
IAVDD (Pin 36, Pin 42)
IAVDD (Pin 11)
IAVDD (Pin 19, Pin 23 to Pin 26, Pin 29,
Pin 30, Pin 44, Pin 45)
IAVDD (Pin 53)
IDVDD (Pin 3, Pin 5, Pin 7)
IDVDD_I/O (Pin 1)
LOGIC INPUTS (Except Pin 32)
Input High Voltage (VIH)
Input Low Voltage (VIL)
Input Current (IINH, IINL)
Maximum Input Capacitance (CIN)
CLKMODESEL (Pin 32) LOGIC INPUT
Input High Voltage (VIH)
Input Low Voltage (VIL)
Input Current (IINH, IINL)
Maximum Input Capacitance (CIN)
LOGIC OUTPUTS
Output High Voltage (VOH)
Output Low Voltage (VOL)
REFERENCE INPUTS
Input Capacitance
Input Resistance
Differential Operation
Common Mode Input Voltage 1
(Applicable When DC-Coupled)
Differential Input Voltage Swing1
Single-Ended Operation
Input Voltage High (VIH)
Input Voltage Low (VIL)
Threshold Voltage
Input Current
FDBK_IN INPUT
Input Capacitance
Input Resistance
Differential Input Voltage Swing2
Min
Typ
Max
Unit
3.135
1.71
3.135
1.71
1.71
3.30
1.80
3.30
3.30
1.80
3.465
1.89
3.465
3.465
1.89
V
V
V
V
V
4.7
3.8
26
21
5.6
4.5
29
26
mA
mA
mA
mA
12
215
15
281
mA
mA
41
254
4
49
265
6
mA
mA
mA
DVDD_I/O
0.8
±200
V
V
µA
pF
AVDD
0.4
−50
V
V
µA
pF
2.0
DVSS
±60
3
Test Conditions/Comments
Pin 37 is typically 3.3 V, but can be set to 1.8 V
REFA, REFB buffers
CMOS output clock driver at 3.3 V
DAC output current source, fS = 1 GSPS
FDBK_IN input, HSTL output clock driver
(output doubler turned on)
REFA and REFB input buffer 1.8 V supply
Aggregate analog supply, including system
clock PLL
DAC power supply
Digital core
Digital I/O (varies dynamically)
Pin 9, Pin 10, Pin 54 to Pin 61, Pin 63, Pin 64
At VIN = 0 V and VIN = DVDD_I/O
Pin 32 only
1.4
AVSS
−18
3
2.7
DVSS
8.5
3
11.5
1.5
DVDD_I/O
0.4
V
V
14.5
pF
kΩ
AVDD3 −
0.2
500
2.0
AVSS
AVDD3 −
0.66
18
225
V
mV p-p
AVDD3 −
0.82
3
22
AVDD3
0.8
AVDD3 −
0.98
1
26
Rev. D | Page 4 of 76
V
V
V
mA
pF
kΩ
mV p-p
At VIN = 0 V and VIN = AVDD
Pin 62 and the following bidirectional pins:
Pin 9, Pin 10, Pin 54, Pin 55, Pin 63
IOH = 1 mA
IOL = 1 mA
Pin 12, Pin 13, Pin 15, Pin 16
Differential at Register 0x040F[1:0] = 00
Differential operation; note that LVDS signals
must be ac-coupled
Differential operation
Register 0x040F[1:0] = 10
Register 0x040F[1:0] = 10 (other settings
possible)
Single-ended operation
Pin 40, Pin 41
Differential
−12 dBm into 50 Ω; must be ac-coupled
AD9549
Parameter
SYSTEM CLOCK INPUT
SYSCLK PLL Bypassed
Input Capacitance
Input Resistance
Internally Generated DC Bias Voltage2
Differential Input Voltage Swing3
SYSCLK PLL Enabled
Input Capacitance
Input Resistance
Internally Generated DC Bias Voltage2
Differential Input Voltage Swing3
Crystal Resonator with SYSCLK PLL Enabled
Motional Resistance
CLOCK OUTPUT DRIVERS
HSTL Output Driver
Differential Output Voltage Swing
Common-Mode Output Voltage2
CMOS Output Driver
Output Voltage High (VOH)
Output Voltage Low (VOL)
Output Voltage High (VOH)
Output Voltage Low (VOL)
TOTAL POWER DISSIPATION
All Blocks Running4
Power-Down Mode
Min
2.4
0.93
632
2.4
0.93
632
Typ
Max
Unit
Test Conditions/Comments
System clock inputs should always be accoupled (both single-ended and differential)
1.5
2.6
1.17
2.8
1.38
pF
kΩ
V
mV p-p
Single-ended, each pin
Differential
3
2.6
1.17
2.8
1.38
0 dBm into 50 Ω
pF
kΩ
V
mV p-p
Single-ended, each pin
Differential
0 dBm into 50 Ω
9
100
Ω
25 MHz, 3.2 mm × 2.5 mm AT cut
1080
1280
1480
mV
Output driver static; see Figure 12 for output
swing vs. frequency
0.7
0.88
1.06
V
Output driver static; see Figure 13 and
Figure 14 for output swing vs. frequency
2.7
0.4
V
V
V
V
IOH = 1 mA, (Pin 37) = 3.3 V
IOL = 1 mA, (Pin 37) = 3.3 V
IOH = 1 mA, (Pin 37) = 1.8 V
IOL = 1 mA, (Pin 37) = 1.8 V
1060
24
1310
70
mW
mW
Worst case over supply, temperature, process
Using either the power-down and enable
register (Register 0x0010) or the PWRDOWN pin
Digital Power-Down Mode
Default with SYSCLK PLL Enabled
565
955
713
mW
mW
Default with SYSCLK PLL Disabled
945
1115
mW
1105
1095
1107
mW
mW
mW
0.4
1.4
With REFA or REFB Power-Down
With HSTL Clock Driver Power-Down
With CMOS Clock Driver Power-Down
Must be ≤0 V relative to AVDD3 (Pin 14) and ≥0 V relative to AVSS (Pin 33, Pin 43).
Relative to AVSS (Pin 33, Pin 43).
3
Must be ≤0 V relative to AVDD (Pin 36) and ≥0 V relative to AVSS (Pin 33, Pin 43).
4
Typical measurement done with only REFA and HSTL output doubler turned off.
1
2
Rev. D | Page 5 of 76
After reset or power-up with fS = 1 GHz,
S4 = 0, S1 to S3 = 1, fSYSCLK = 25 MHz
After reset or power-up with fS = 1 GHz,
S1 to S4 = 1
One reference still powered up
AD9549
AC SPECIFICATIONS
fS = 1 GHz, DAC RSET = 10 kΩ, power supply pins within the range specified in the DC Specifications section, unless otherwise noted.
Table 2.
Parameter
REFERENCE INPUTS
Frequency Range (Sine Wave)
Frequency Range (CMOS)
Frequency Range (LVPECL)
Frequency Range (LVDS)
Minimum Slew Rate
Minimum Pulse Width High
Minimum Pulse Width Low
FDBK_IN INPUT
Input Frequency Range
Minimum Differential Input Level
Minimum Slew Rate
SYSTEM CLOCK INPUT
SYSCLK PLL Bypassed
Input Frequency Range
Duty Cycle
Minimum Differential Input Level
SYSCLK PLL Enabled
VCO Frequency Range, Low Band
VCO Frequency Range, Auto Band
VCO Frequency Range, High Band
Maximum Input Rate of System Clock PFD
Without SYSCLK PLL Doubler
Input Frequency Range
Multiplication Range
Minimum Differential Input Level
With SYSCLK PLL Doubler
Input Frequency Range
Multiplication Range
Input Duty Cycle
Minimum Differential Input Level
Crystal Resonator with SYSCLK PLL Enabled
Crystal Resonator Frequency Range
Maximum Crystal Motional Resistance
CLOCK DRIVERS
HSTL Output Driver
Frequency Range
Duty Cycle
Rise Time/Fall Time (20-80%)
Jitter (12 kHz to 20 MHz)
HSTL Output Driver with 2× Multiplier
Frequency Range
Duty Cycle
Rise Time/Fall Time (20% to 80%)
Subharmonic Spur Level
Jitter (12 kHz to 20 MHz)
Min
Typ
10
0.008
0.008
0.008
Max
Unit
750
50
725
725
MHz
MHz
MHz
MHz
0.04
620
620
Test Conditions/Comments
Pin 12, Pin 13, Pin 15, and Pin 16
Minimum recommended slew rate: 40 V/μs
LVDS must be ac-coupled; lower frequency bound may
be higher, depending on the size of the decoupling
capacitor
V/ns
ps
ps
Pin 40, Pin 41
10
225
40
400
MHz
mV p-p
V/μs
−12 dBm into 50 Ω; must be ac-coupled
Pin 27, Pin 28
250
45
632
1000
55
700
810
900
810
900
1000
200
MHz
MHz
MHz
MHz
11
4
200
66
MHz
632
MHz
%
mV p-p
mV p-p
6
8
100
132
50
0 dBm into 50 Ω
When in the range, use the low VCO band exclusively
When in the range, use the VCO Auto band select
When in the range, use the high VCO band exclusively
Integer multiples of 2, maximum PFD rate and system
clock frequency must be met
0 dBm into 50 Ω
MHz
mV p-p
Integer multiples of 8
Deviating from 50% duty cycle may adversely affect
spurious performance.
0 dBm into 50 Ω
%
632
Maximum fOUT is 0.4 × fSYSCLK
10
50
100
MHz
Ω
AT cut, fundamental mode resonator
See the SYSCLK Inputs section for recommendations
20
48
725
52
165
MHz
%
ps
ps
See Figure 12 for maximum toggle rate
725
55
165
MHz
%
ps
dBc
ps
115
1.0
400
45
115
−35
1.1
Rev. D | Page 6 of 76
100 Ω termination across OUT/OUTB, 2 pF load
fIN = 19.44 MHz, fOUT = 155.52 MHz. 50 MHz system
clock input (see Figure 3 to Figure 11 for test conditions)
100 Ω termination across OUT/OUTB, 2 pF load
Without correction
fIN = 19.44 MHz, fOUT = 622.08 MHz, 50 MHz system
clock input (see Figure 3 to Figure 11 for test conditions)
AD9549
Parameter
CMOS Output Driver
(AVDD3/Pin 37) @ 3.3 V
Frequency Range
Duty Cycle
Rise Time/Fall Time (20-80%)
CMOS Output Driver
(AVDD3/Pin 37) @ 1.8 V
Frequency Range
Duty Cycle
Rise Time/Fall Time (20% to 80%)
HOLDOVER
Frequency Accuracy
OUTPUT FREQUENCY SLEW LIMITER
Slew Rate Resolution
Slew Rate Range
REFERENCE MONITORS
Loss of Reference Monitor
Operating Frequency Range
Minimum Frequency Error for
Continuous REF Present Indication
Minimum Frequency Error for
Continuous REF Present Indication
Maximum Frequency Error for
Continuous REF Lost Indication
Maximum Frequency Error for
Continuous REF Lost Indication
Reference Quality Monitor
Operating Frequency Range
Frequency Resolution (Normalized)
Frequency Resolution (Normalized)
Validation Timer
Timing Range
Timing Range
DAC OUTPUT CHARACTERISTICS
DCO Frequency Range (1st Nyquist Zone)
Output Resistance
Output Capacitance
Full-Scale Output Current
Gain Error
Output Offset
Voltage Compliance Range
Min
0.008
45
0.008
45
Typ
Max
Unit
Test Conditions/Comments
55
3
150
65
4.6
MHz
%
ns
See Figure 14 for maximum toggle rate
With 20 pF load and up to 150 MHz
With 20 pF load
55
5
40
65
6.8
MHz
%
ns
See Figure 13 for maximum toggle rate
With 20 pF load and up to 40 MHz
With 20 pF load
See the Holdover section
0.54
0
111
3 × 1016
Hz/sec
Hz/sec
P = 216 for minimum; P = 25 for maximum
P = 216 for minimum; P = 25 for maximum
7.63 × 103
167 × 106
−16
Hz
ppm
fREF = 8 kHz
−19
%
fREF = 155 MHz
−32
ppm
fREF = 8 kHz
−35
%
fREF = 155 MHz
0.008
0.2
150
408
ppm
32 × 10−9
65 × 10−6
10
50
5
20
−10
AVSS −
0.50
MHz
ppm
+0.5
137
2.8 × 105
sec
sec
450
MHz
Ω
pF
mA
% FS
μA
31.7
+10
0.6
AVSS +
0.50
0.1
Hz
Maximum Open-Loop Bandwidth
100
kHz
10
Degrees
0
Maximum Phase Margin
PFD Input Frequency Range
Feedforward Divider Ratio
Feedback Divider Ratio
85
~0.008
1
1
DPLL loop bandwidth sets lower limit
Single-ended (each pin internally terminated to AVSS)
Range depends on DAC RSET resistor
Outputs not dc-shorted to VSS
DIGITAL PLL
Minimum Open-Loop Bandwidth
Minimum Phase Margin
fREF = 8 kHz; OOL divider = 65,535 for minimum; OOL
divider = 1 for max (see the Reference Frequency
Monitor section)
fREF = 155 MHz; OOL divider = 65,535 for minimum;
OOL divider = 1 for maximum
See the Reference Validation Timers section
PIO = 5
PIO = 16
90
Degrees
~24.5
131,070
131,070
MHz
Rev. D | Page 7 of 76
Dependent on the frequency of REFA/REFB, the DAC
sample rate, and the P-, R-, and S-divider values
Dependent on the frequency of REFA/REFB, the DAC
sample rate, and the P-, R-, and S-divider values
Dependent on the frequency of REFA/REFB, the DAC
sample rate, and the P-, R-, and S-divider values
Dependent on the frequency of REFA/REFB, the DAC
sample rate, and the P-, R-, and S-divider values
1, 2, …, 65,535 or 2, 4, …, 131,070
1, 2, …, 65,535 or 2, 4, …, 131,070
AD9549
Parameter
LOCK DETECTION
Phase Lock Detector
Time Threshold Programming Range
Time Threshold Resolution
Lock Time Programming Range
Unlock Time Programming Range
Frequency Lock Detector
Normalized Frequency Threshold
Programming Range
Normalized Frequency Threshold
Programming Resolution
Lock Time Programming Range
Unlock Time Programming Range
Min
0
Max
Unit
Test Conditions/Comments
2097
μs
ps
sec
sec
FPFD_gain = 200
FPFD_gain = 200
In power-of-2 steps
In power-of-2 steps
sec
sec
FPFD_gain = 200; normalized to (fREF/R)2; see the
Frequency Lock Detection section for details
FPFD_gain = 200; normalized to (fREF/R)2; see the
Frequency Lock Detection section for details
In power-of-2 steps
In power-of-2 steps
0.488
32 × 10−9
192 ×
10−9
275
67 × 10−3
0
0.0021
5×
10−13
32 × 10−9
192 ×
10−9
DIGITAL TIMING SPECIFICATIONS
Time Required to Enter Power-Down
Time Required to Leave Power-Down
Reset Assert to High-Z Time
for S1 to S4 Configuration Pins
Reset Deassert to Low-Z Time
for S1 to S4 Configuration Pins
SERIAL PORT TIMING SPECIFICATIONS
SCLK Clock Rate (1/tCLK )
SCLK Pulse Width High, tHIGH
SCLK Pulse Width Low, tLOW
SDO/SDIO to SCLK Setup Time, tDS
SDO/SDIO to SCLK Hold Time, tDH
SCLK Falling Edge to Valid Data on
SDIO/SDO, tDV
CSB to SCLK Setup Time, tS
CSB to SCLK Hold Time, tH
CSB Minimum Pulse Width High, tPWH
IO_UPDATE Pin Setup Time
from SCLK Rising Edge of the Final Bit
IO_UPDATE Pin Hold Time
PROPAGATION DELAY
FDBK_IN to HSTL Output Driver
FDBK_IN to HSTL Output Driver with 2×
Frequency Multiplier Enabled
FDBK_IN to CMOS Output Driver
FDBK_IN Through S-Divider to CMOS
Output Driver
Frequency Tuning Word Update,
IO_UPDATE Pin Rising Edge to DAC
Output
Typ
275
67 × 10−3
15
18
60
µs
µs
ns
30
ns
25
Time from rising edge of RESET to high-Z on the S1,
S2, S3, and S4 configuration pins
Time from falling edge of RESET to low-Z on the S1, S2,
S3, and S4 configuration pins
50
MHz
11
ns
ns
ns
ns
ns
Refer to Figure 56
1.34
−0.4
3
tCLK
ns
ns
ns
sec
tCLK = period of SCLK in Hz
tCLK
sec
tCLK = period of SCLK in Hz
8
8
1.93
1.9
2.8
7.3
ns
ns
8.0
8.6
ns
ns
60/fs
ns
Rev. D | Page 8 of 76
Refer to Figure 58 for all write-related serial port
parameters, maximum SCLK rate for readback is
governed by tDV
fs = system clock frequency in GHz
AD9549
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Analog Supply Voltage (AVDD)
Digital Supply Voltage (DVDD)
Digital I/O Supply Voltage
(DVDD_I/O)
DAC Supply Voltage (AVDD3 Pins)
Maximum Digital Input Voltage
Storage Temperature
Operating Temperature Range
Lead Temperature
(Soldering, 10 sec)
Junction Temperature
THERMAL RESISTANCE
Rating
2V
2V
3.6 V
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
3.6 V
−0.5 V to DVDD_I/O + 0.5 V
−65°C to +150°C
−40°C to +85°C
300°C
Package Type
64-Lead LFCSP
θJB
13.9
θJC
1.7
Unit
°C/W typical
Note that the exposed pad on the bottom of the package must
be soldered to ground to achieve the specified thermal performance. See the Thermal Performance section for more
information.
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
θJA
25.2
ESD CAUTION
Rev. D | Page 9 of 76
AD9549
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
SCLK
SDIO
SDO
CSB
IO_UPDATE
RESET
PWRDOWN
HOLDOVER
REFSELECT
S4
S3
AVDD
AVSS
DAC_OUTB
DAC_OUT
AVDD3
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN 1
INDICATOR
AD9549
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DAC_RSET
AVDD3
AVDD3
AVDD
AVDD
AVSS
AVDD
FDBK_IN
FDBK_INB
AVSS
OUT_CMOS
AVDD3
AVDD
OUT
OUTB
AVSS
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED THERMAL DIE ON THE BOTTOM OF THE PACKAGE PROVIDES
THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
06744-002
NC
NC
AVDD
PFD_VRB
PFD_VRT
PFD_RSET
AVDD
AVDD
AVDD
AVDD
SYSCLK
SYSCLKB
AVDD
AVDD
LOOP_FILTER
CLKMODESEL
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DVDD_I/O
DVSS
DVDD
DVSS
DVDD
DVSS
DVDD
DVSS
S1
S2
AVDD
REFA_IN
REFA_INB
AVDD3
REFB_IN
REFB_INB
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Input/
Output
I
I
I
I/O
Pin Type
Power
Power
Power
3.3 V CMOS
Mnemonic
DVDD_I/O
DVSS
DVDD
S1, S2, S3, S4
11, 19, 23 to
26, 29, 30, 36,
42, 44, 45, 53
12
I
Power
AVDD
I
Differential
input
REFA_IN
13
I
Differential
input
REFA_INB
14, 46, 47, 49
15
I
I
Power
Differential
input
AVDD3
REFB_IN
16
I
Differential
input
REFB_INB
Pin No.
1
2, 4, 6, 8
3, 5, 7
9, 10, 54, 55
17, 18
NC
Description
I/O Digital Supply.
Digital Ground. Connect to ground.
Digital Supply.
Configurable I/O Pins. These pins are configured under program control (see
the Status and Warnings section) and do not have internal pull-up/pull-down
resistors.
Analog Supply. Connect to a nominal 1.8 V supply.
Frequency/Phase Reference A Input. This internally biased input is typically
ac-coupled and, when configured as such, can accept any differential signal
with single-ended swing between 0.4 V and 3.3 V. If dc-coupled, LVPECL or
CMOS input is preferred.
Complementary Frequency/Phase Reference A Input. Complementary signal
to the input provided on Pin 12. If using a single-ended, dc-coupled CMOS
signal into REFA_IN, bypass this pin to ground with a 0.01 μF capacitor.
Analog Supply. Connect to a nominal 3.3 V supply.
Frequency/Phase Reference B Input. This internally biased input is typically
ac-coupled and, when configured as such, can accept any differential signal
with single-ended swing between 0.4 V and 3.3 V. If dc-coupled, LVPECL or
CMOS input is preferred.
Complementary Frequency/Phase Reference B Input. Complementary signal
to the input provided on Pin 15. If using a single-ended, dc-coupled CMOS
signal into REFB_IN, bypass this pin to ground with a 0.01 μF capacitor.
No Connect. These are excess, unused pins that can be left floating.
Rev. D | Page 10 of 76
AD9549
Pin No.
20, 21
Input/
Output
O
22
O
27
I
28
I
31
O
32
I
1.8 V CMOS
CLKMODESEL
33, 39, 43, 52
34
O
O
GND
1.8 V HSTL
AVSS
OUTB
35
O
1.8 V HSTL
OUT
37
I
Power
AVDD3
38
O
3.3 V CMOS
OUT_CMOS
40
I
Differential
input
FDBK_INB
41
I
FDBK_IN
48
O
50
O
51
O
56
I/O
Differential
input
Current set
resistor
Differential
output
Differential
output
3.3 V CMOS
57
I/O
3.3 V CMOS
HOLDOVER
58
I
3.3 V CMOS
PWRDOWN
59
I
3.3 V CMOS
RESET
Pin Type
Current set
resistor
Differential
input
Differential
input
Mnemonic
PFD_VRB,
PFD_VRT
PFD_RSET
SYSCLK
SYSCLKB
LOOP_FILTER
DAC_RSET
DAC_OUT
DAC_OUTB
REFSELECT
Description
These pins must be capacitively decoupled. See the Phase Detector Pin
Connections section for details.
Connect a 5 kΩ resistor from this pin to ground (see the Phase Detector Pin
Connections section).
System Clock Input. The system clock input has internal dc biasing and should
always be ac-coupled, except when using a crystal. Single-ended 1.8 V CMOS
can also be used, but it may introduce a spur caused by an input duty cycle
that is not 50%. When using a crystal, tie the CLKMODESEL pin to AVSS, and
connect crystal directly to this pin and Pin 28.
Complementary System Clock. Complementary signal to the input provided
on Pin 27. Use a 0.01 μF capacitor to ground on this pin if the signal provided
on Pin 27 is single-ended.
System Clock Multiplier Loop Filter. When using the frequency multiplier to
drive the system clock, an external loop filter must be constructed and attached to
this pin. This pin should be pulled down to ground with a 1 kΩ resistor when
the system clock PLL is bypassed. See Figure 44 for a diagram of the system
clock PLL loop filter.
Clock Mode Select. Set to GND when connecting a crystal to the system clock
input (Pin 27 and Pin 28). Pull up to 1.8 V when using either an oscillator or an
external clock source. This pin can be left floating when the system clock PLL is
bypassed. (See the SYSCLK Inputs section for details on the use of this pin.)
Analog Ground. Connect to ground.
Complementary HSTL Output. See the Specifications and Primary 1.8 V
Differential HSTL Driver sections for details.
HSTL Output. See the Specifications and Primary 1.8 V Differential HSTL Driver
sections for details.
Analog Supply for CMOS Output Driver. This pin is normally 3.3 V but can be
1.8 V. This pin should be powered even if the CMOS driver is not used. See the
Power Supply Partitioning section for power supply partitioning.
CMOS Output. See the Specifications and the Output Clock Drivers and 2×
Frequency Multiplier sections. This pin is 1.8 V CMOS if Pin 37 is set to 1.8 V.
Complementary Feedback Input. In standard operating mode, this pin is
connected to the filtered DAC_OUTB output. This internally biased input is
typically ac-coupled, and when configured as such, can accept any differential
signal whose single-ended swing is at least 400 mV.
Feedback Input. In standard operating mode, this pin is connected to the
filtered DAC_OUT output.
DAC Output Current Setting Resistor. Connect a resistor (usually 10 kΩ) from
this pin to GND. See the DAC Output section.
DAC Output. This signal should be filtered and sent back on chip through
FDBK_IN input. This pin has an internal 50 Ω pull-down resistor.
Complementary DAC Output. This signal should be filtered and sent back on
chip through FDBK_INB input. This pin has an internal 50 Ω pull-down resistor.
Reference Select Input. In manual mode, the REFSELECT pin operates as a high
impedance input pin; and in automatic mode, it operates as a low impedance
output pin. Logic 0 (low) indicates/selects REFA. Logic 1 (high) indicates/selects
REFB. There is no internal pull-up/pull-down resistor on this pin.
Holdover (Active High). In manual holdover mode, this pin is used to force the
AD9549 into holdover mode. In automatic holdover mode, it indicates
holdover status. There is no internal pull-up/pull-down resistor on this pin.
Power-Down. When this active high pin is asserted, the device becomes
inactive and enters the full power-down state. This pin has an internal 50 kΩ
pull-down resistor.
Chip Reset. When this active high pin is asserted, the chip goes into reset. Note
that on power-up, it is recommended that the user assert a high to low edge
after the power supplies reach a threshold and stabilize. This pin has an
internal 50 kΩ pull-down resistor.
Rev. D | Page 11 of 76
AD9549
Pin No.
60
Input/
Output
I
Pin Type
3.3 V CMOS
Mnemonic
IO_UPDATE
61
I
3.3 V CMOS
CSB
62
O
3.3 V CMOS
SDO
63
I/O
3.3 V CMOS
SDIO
64
I
3.3 V CMOS
SCLK
Exposed
Die Pad
O
GND
EPAD
Description
I/O Update. A logic transition from 0 to 1 on this pin transfers data from the I/O
port registers to the control registers (see the Write section). This pin has an
internal 50 kΩ pull-down resistor.
Chip Select. Active low. When programming a device, this pin must be held
low. In systems where more than one AD9549 is present, this pin enables
individual programming of each AD9549. This pin has an internal 100 kΩ pullup resistor.
Serial Data Output. When the device is in 3-wire mode, data is read on this pin.
There is no internal pull-up/pull-down resistor on this pin.
Serial Data Input/Output. When the device is in 3-wire mode, data is written
via this pin. In 2-wire mode, data reads and writes both occur on this pin. There
is no internal pull-up/pull-down resistor on this pin.
Serial Programming Clock. Data clock for serial programming. This pin has an
internal 50 kΩ pull-down resistor.
Analog Ground. The exposed thermal pad on the bottom of the package provides the analog ground for the part. This exposed pad must be connected to
ground for proper operation.
Rev. D | Page 12 of 76
AD9549
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, AVDD, AVDD3, and DVDD are at nominal supply voltage; fS = 1 GHz, DAC RSET = 10 kΩ.
–70
RMS JITTER (12kHz TO 20MHz): 0.18ps
RMS JITTER (50kHz TO 80MHz): 0.24ps
PHASE NOISE (dBc/Hz)
–90
–100
–110
–120
–110
–120
–140
–140
100
1k
10k
100k
1M
FREQUENCY OFFSET (Hz)
10M
100M
–150
10
10M
100M
–110
–120
–90
–100
–110
–120
–130
–140
–140
1k
10k
100k
1M
FREQUENCY OFFSET (Hz)
10M
100M
06744-004
–130
Figure 4. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
(SYSCLK PLL Bypassed), fREF = 19.44 MHz, fOUT = 622.08 MHz,
DPLL Loop BW = 1 kHz, HSTL Output Doubler Enabled
–150
10
100
1k
10k
100k
1M
FREQUENCY OFFSET (Hz)
10M
100M
06744-007
PHASE NOISE (dBc/Hz)
–100
100
RMS JITTER (12kHz TO 20MHz): 1.0ps
RMS JITTER (50kHz TO 80MHz): 1.2ps
–80
–90
Figure 7. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
(SYSCLK PLL Enabled and Driven by R&S SMA100 at 50 MHz), fREF = 19.44 MHz,
fOUT = 155.52 MHz, SYSCLK Doubler Enabled, DPLL Loop BW =1 kHz
–70
RMS JITTER (12kHz TO 20MHz): 1.01ps
RMS JITTER (50kHz TO 80MHz): 1.04ps
–80
PHASE NOISE (dBc/Hz)
–90
–100
–110
–120
–90
–100
–110
–120
–130
–140
–140
1k
10k
100k
1M
FREQUENCY OFFSET (Hz)
10M
100M
06744-005
–130
100
RMS JITTER (12kHz TO 20MHz): 1.07ps
RMS JITTER (50kHz TO 80MHz): 1.16ps
–80
Figure 5. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
(SYSCLK PLL Enabled Driven by R&S SMA100 Signal Generator at 50 MHz),
fREF = 19.44 MHz, fOUT = 311.04 MHz, DPLL Loop BW = 1 kHz
–150
10
100
1k
10k
100k
1M
FREQUENCY OFFSET (Hz)
10M
100M
06744-008
–70
–150
10
1k
10k
100k
1M
FREQUENCY OFFSET (Hz)
–70
RMS JITTER (12kHz TO 20MHz): 0.36ps
RMS JITTER (50kHz TO 80MHz): 0.42ps
–80
–150
10
100
Figure 6. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
(SYSCLK PLL Enabled and Driven by R&S SMA100 Signal Generator at
50 MHz), fREF = 19.44 MHz, fOUT = 622.08 MHz, DPLL Loop BW = 1 kHz,
System Clock Doubler Enabled, HSTL Doubler Enabled
–70
PHASE NOISE (dBc/Hz)
–100
–130
Figure 3. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
(SYSCLK PLL Bypassed), fREF = 19.44 MHz,
fOUT = 311.04 MHz, DPLL Loop BW = 1 kHz
PHASE NOISE (dBc/Hz)
–90
–130
–150
10
RMS JITTER (12kHz TO 20MHz): 1.09ps
RMS JITTER (50kHz TO 80MHz): 1.14ps
–80
06744-003
PHASE NOISE (dBc/Hz)
–80
06744-006
–70
Figure 8. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
(SYSCLK PLL Enabled and Driven by R&S SMA100 Signal Generator at
50 MHz), fREF = 8 kHz, fOUT = 155.52 MHz, DPLL Loop BW = 10 Hz
Rev. D | Page 13 of 76
AD9549
–70
RMS JITTER (12kHz TO 20MHz): 4.2ps
–80
1.5
PHASE NOISE (dBc/Hz)
12kHz TO 20MHz RMS JITTER (ps)
2.0
1.0
0.5
–90
–100
–110
–120
–130
30
50
70
SYSTEM CLOCK PLL INPUT FREQUENCY (MHz)
90
–150
10
Figure 9. 12 kHz to 20 MHz RMS Jitter vs. System Clock PLL Input Frequency,
SYSCLK = 1 GHz, fREF = 19.44 MHz, fOUT = 155.52 MHz
RMS JITTER (12kHz TO 20MHz): 1.26ps
RMS JITTER (50kHz TO 80MHz): 1.30ps
PHASE NOISE (dBc/Hz)
–90
–100
–110
–120
–130
100
1k
10k
100k
1M
FREQUENCY OFFSET (Hz)
10M
100M
06744-010
–140
–150
10
1k
10k
100k
FREQUENCY OFFSET (Hz)
1M
10M
Figure 11. Additive Phase Noise at HSTL Output Driver, SYSCLK = 500 MHz
(SYSCLK PLL Disabled), fREF = 10.24 MHz, fOUT = 20.48 MHz,
DPLL Loop BW = 1 kHz
–70
–80
100
06744-011
0
10
06744-009
–140
Figure 10. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
(SYSCLK PLL Enabled and Driven by a 25 MHz Fox Crystal Oscillator),
fREF = 19.44 MHz, fOUT = 155.52 MHz, DPLL Loop BW = 1 kHz
Rev. D | Page 14 of 76
AD9549
650
0.6
0.4
550
0.2
0
FREQUENCY= 600MHz
TRISE (20→80%) = 104ps
TFALL (80→20%) = 107ps
V p-p = 1.17V DIFF.
DUTY CYCLE = 50%
–0.2
500
NOM SKEW 25°C, 1.8V SUPPLY
SLOW SKEW 90°C, 1.7V SUPPLY
–0.4
0
200
400
FREQUENCY (MHz)
600
800
–0.6
06744-012
450
0
0.5
1.0
1.5
TIME (ns)
2.0
2.5
06744-015
AMPLITUDE (V)
AMPLITUDE (mV)
600
Figure 15. Typical HSTL Output Waveform, Nominal Conditions,
DC-Coupled, Differential Probe Across 100 Ω load
Figure 12. HSTL Output Driver Single-Ended Peak-to-Peak Amplitude vs.
Toggle Rate (100 Ω Across Differential Pair)
2.5
1.8
1.6
2.0
1.4
AMPLITUDE (V)
AMPLITUDE (V)
1.2
1.5
1.0
NOM SKEW 25°C, 1.8V SUPPLY (20pF)
SLOW SKEW 90°C, 1.7V SUPPLY (20pF)
1.0
0.8
0.6
FREQUENCY= 20MHz
TRISE (20→80%) = 5.5ns
TFALL (80→20%) = 5.9ns
V p-p = 1.8V
DUTY CYCLE = 53%
0.4
0.5
0.2
0
10
20
FREQUENCY (MHz)
30
40
–0.2
0
20
40
60
80
100
TIME (ns)
06744-016
0
06744-013
0
Figure 16. Typical CMOS Output Driver Waveform (@ 1.8 V),
Nominal Conditions, Estimated Capacitance: 5 pF
Figure 13. CMOS Output Driver Peak-to-Peak Amplitude vs. Toggle Rate
(AVDD3 = 1.8 V) with 20 pF Load
3.5
3.3
3.0
2.8
AMPLITUDE (V)
NOM SKEW 25°C, 3.3V SUPPLY (20pF)
SLOW SKEW 90°C, 3.0V SUPPLY (20pF)
2.0
1.5
1.0
2.3
1.8
FREQUENCY= 40MHz
TRISE (20→80%) = 2.25ns
TFALL (80→20%) = 2.6ns
V p-p = 3.3V
DUTY CYCLE = 52%
1.3
0.8
0.5
0
0
50
100
FREQUENCY (MHz)
150
Figure 14. CMOS Output Driver Peak-to-Peak Amplitude vs. Toggle Rate
(AVDD3 = 3.3 V) with 20 pF Load
06744-014
0.3
–0.2
0
10
20
30
40
50
TIME (ns)
Figure 17. CMOS Output Driver Waveform (@ 3.3 V), Nominal Conditions,
Estimated Capacitance: 5 pF, fOUT = 20 MHz
Rev. D | Page 15 of 76
06744-017
AMPLITUDE (V)
2.5
AD9549
INPUT/OUTPUT TERMINATION RECOMMENDATIONS
0.01µF
0.01µF
AD9549
1.8V
HSTL
OUTPUT
100Ω
DOWNSTREAM
DEVICE
(HIGH-Z)
100Ω
(OPTIONAL)
AD9549
SELF-BIASING
REF INPUT
0.01µF
06744-018
06744-020
0.01µF
Figure 18. AC-Coupled HSTL Output Driver
Figure 20. Reference Input
0.1µF
50Ω
AD9549
1.8V
HSTL
OUTPUT
AVDD/2
DOWNSTREAM
DEVICE
(HIGH-Z)
100Ω
(OPTIONAL)
AD9549
SELF-BIASING
FDBK INPUT
0.1µF
06744-021
06744-019
50Ω
Figure 19. DC-Coupled HSTL Output Driver
Figure 21. FDBK_IN Input
Rev. D | Page 16 of 76
AD9549
THEORY OF OPERATION
OUT_CMOS
OUT
2×
DIGITAL PLL CORE
÷S
FDBK_IN
FREQ
EST.
REFSELECT
REFA_IN
PFD
÷R
PROG.
DIGITAL
LOOP
FILTER
FREQUENCY
TUNING
WORD
SLEW
LIMIT
DDS/DAC
DAC_OUT
REFB_IN
EXTERNAL
ANALOG
LOW-PASS
FILTER
LOCK DETECT
INPUT
REF
MONITOR
HOLDOVER
REF_CNTRL
LOW NOISE
CLOCK
MULTIPLIER
OOL AND LOR
S1 TO S4
IRQ AND
STATUS
LOGIC
CONTROL
LOGIC
AMP
DIGITAL
INTERFACE
HOLDOVER
SYSCLK
06744-022
SYSCLK PORT
Figure 22. Detailed Block Diagram
OVERVIEW
The AD9549 provides a clocking output that is directly related
in phase and frequency to the selected (active) reference (REFA
or REFB) but has a phase noise spectrum primarily governed
by the system clock. A wide band of reference frequencies is
supported. Jitter existing on the active reference is greatly reduced
by a programmable digital filter in the digital phase-locked loop
(PLL), which is the core of this product. The AD9549 supports
both manual and automatic holdover. While in holdover, the
AD9549 continues to provide an output as long as the system
clock is maintained. The frequency of the output during holdover is an average of the steady state output frequency prior to
holdover.
Also offered are manual and automatic switchover modes for
changing between the two references, should one become suspect
or lost. A digitally controlled oscillator (DCO) is implemented
using a direct digital synthesizer (DDS) with an integrated output
digital-to-analog converter (DAC), clocked by the system clock.
A bypassable PLL-based frequency multiplier is present, enabling
use of an inexpensive, low frequency source for the system clock.
For best jitter performance, the system clock PLL should be
bypassed; and a low noise, high frequency system clock should be
provided directly. Sampling theory sets an upper bound for the
DDS output frequency at 50%
of fS (where fS is the DAC sample rate), but a practical limitation
of 40% of fS is generally recommended to allow for the selectivity
of the required off-chip reconstruction filter. The output signal
from the reconstruction filter is fed back to the AD9549, both
to complete the PLL and to be processed through the output
circuitry. The output circuitry includes HSTL and CMOS output
buffers, as well as a frequency doubler for designs that must
provide frequencies above the Nyquist level of the DDS.
The individual functional blocks are described in the following
sections.
DIGITAL PLL CORE (DPLLC)
The digital phase-locked loop core (DPLLC) includes the
frequency estimation block and the digital phase lock control
block driving the DDS.
The start of the DPLLC signal chain is the reference signal, fR,
which appears on REFA or REFB inputs. The frequency of this
signal can be divided by an integer factor of R via the feedforward
divider. The output of the feedforward divider is routed to the
phase/frequency detector (PFD). Therefore, the frequency at
the input to the PFD is given by
Rev. D | Page 17 of 76
f PFD =
fR
R
AD9549
The PFD outputs a time series of digital words that are routed
to the digital loop filter. The digital filter implementation offers
many advantages: The filter response is determined by numeric
coefficients rather than by discrete component values; there is
no aging of components and, therefore, no drift of component
value over time; there is no thermal noise in the loop filter; and
there is no control node leakage current (which causes reference
feedthrough in a traditional analog PLL).
The output of the loop filter is a time series of digital words.
These words are applied to the frequency tuning input of a DDS
to steer the DCO frequency. The DDS provides an analog output
signal via an integrated DAC, effectively mimicking the operation
of an analog voltage-controlled oscillator (VCO).
The DPLLC can be programmed to operate in conjunction with
an internal frequency estimator to help decrease the time required
to achieve lock. When the frequency estimator is employed,
frequency acquisition is accomplished in the following twostep process:
1.
2.
An estimate is made of the frequency of fPFD. The phase
lock control loop is essentially inoperative during the
frequency estimation process. When a frequency estimate
is made, it is delivered to the DDS so that its output frequency
is approximately equal to fPFD multiplied by S (the modulus
of the feedback divider).
The phase lock control loop becomes active and acts as
a servo to acquire and hold phase lock with the reference
signal.
As mentioned in Step 1, the DPLLC includes a feedback divider
that allows the DCO to operate at an integer multiple (S) of fPFD.
This establishes a nominal DCO frequency (fDDS), given by
S
f DDS = f R
R
SYSCLK
÷R
÷PFD
DIV
PHASE
CLK DETECTOR
(TIME-TODIGITAL
CONVERTER)
÷P
LOOP
FILTER
α
β
SAMPLES
DELIVERED AT
SYSCLK RATE
DAC_OUT
PINS
CCI
DDS
ץ
FDBK_IN
PINS
÷S
EXTERNAL DAC
RECONSTRUCTION
FILTER
There is a lower bound on the value of R that is imposed by the
phase frequency detector within the DPLLC, which has a maximum operating frequency of fPFD[MAX], as explained in the Fine
Phase Detector section. The R-divider/2 bit must be set when
REFA or REFB is greater than 400 MHz. The user must also
ensure that R is chosen so that it satisfies the inequality.
fR
R ≥ ceil
f
PFD
[
MAX
]
The upper bound is
f
R ≤ floor R
8 kHz
where the ceil(x) function yields the nearest integer ≥ x.
For example, if fR = 155 MHz and fPFD[MAX] = 24.5 MHz, then
ceil (155/24.5) = 7, so R must be ≥7.
Feedback Divider (Divide-by-S)
The feedback divider is an integer divider allowing frequency
multiplication of the REF signal that appears at the input of the
phase detector. It is capable of handling frequencies well above
the Nyquist limit of the DDS. The divider depth is 16 bits, cascaded with an additional divide-by-2. Therefore, the divider is
capable of integer division from 1 to 65,535 (index of 1) or from
2 to 131,070 (index of 2). The divider is programmed via the I/O
register map to trigger on either the rising (default) or falling
edge of the feedback signal. Note that the value stored in the
S-divider register is one less than the actual R-divider, so setting
the S-divider register to 0 results in an S-divider equal to 1.
The feedback divider must be programmed within certain
boundaries. The S-divider/2 bit must be set when FDBK_IN is
greater than 400 MHz. The upper boundary on the feedback
divider is the lesser of the maximum programmable value of
S and the maximum practical output frequency of the DDS
(~40% fS). Two equations are given: SMAX1 for a feedback divider
index of 1 and SMAX2 for an index of 2.
40% f S R
S MAX1 = min
, 65,535
f
R
06744-023
REF
INPUT
SAMPLES
DELIVERED AT
THE CLK RATE
cascaded with an additional divide-by-2. Therefore, the divider
is capable of integer division from 1 to 65,535 (index of 1) or from
2 to 131,070 (index of 2). The divider is programmed via the I/O
register map to trigger on either the rising (default) or falling edge
of the REF source input signal. Note that the value stored in the
R-divider register is one less than the actual R-divider, so setting the
R-divider register to 0 results in an R-divider that is equal to 1.
Figure 23. Digital PLL Block Diagram
Feedforward Divider (Divide-by-R)
or
The feedforward divider is an integer divider that allows
frequency prescaling of the REF source input signal while
maintaining the desired low jitter performance of the AD9549.
40% f S R
, 131,070
S MAX 2 = min
f
R
The feedforward divider is a programmable modulus divider with
very low jitter injection. The divider is capable of handling input
frequencies as high as 750 MHz. The divider depth is 16 bits,
where R is the modulus of the feedforward divider, fS is the DAC
sample rate, and fR is the input reference frequency.
Rev. D | Page 18 of 76
AD9549
The DCO has a minimum frequency, fDCO[MIN] (see the DAC
Output Characteristics section of the AC Specifications table).
This minimum frequency imposes a lower bound, SMIN, on the
feedback divider value, as well.
error samples from the time-to-digital converter replaces the loop
filter. A DDS replaces the VCO, which produces a frequency that
is linearly related to the digital value provided by the loop filter.
This is shown in Figure 25 with some additional detail.
The samples provided by the time-to-digital converter are delivered
to the loop filter at a sample rate equal to the CLK frequency (that
is, fR/R). The loop filter is intended to oversample the time-todigital converter output at a rate determined by the P-divider.
The value of P is programmable via the I/O register map. It is
stored as a 5-bit number, PIO. The value of PIO is related to P by
the equation
f DCO[ MIN ]
, 1
S MIN = max R
fR
Note that reduced DCO frequencies result in worse jitter
performance (a consequence of the reduced slew rate of the
sinusoid generated by the DDS).
Forward and Reverse FEC Clock Scaling
The feedforward divider (divide-by-R) and feedback divider
(divide-by-S) enable FEC clock scaling. For instance, to multiply
the incoming signal by 255/237, set the S-divider to 255 and the
R-divider to 237. Be careful to abide by the limitations on the Rand S-dividers, and make sure the phase detector input frequency
is within specified limits.
Phase Detector
The phase detector is composed of two detectors: a coarse phase
detector and a fine phase detector. The two detectors operate in
parallel. Both detectors measure the duration (Δt) of the pulses
generated by a conventional three-state phase/frequency detector.
Together, the fine and coarse phase detectors produce a digital
word that is a time-to-digital conversion of the separation
between the edge transitions of the prescaled reference signal
and the feedback signal.
If the fine phase detector is able to produce a valid result, this
result alone serves as the phase error measurement. If the fine
phase detector is in either an overflow or underflow condition,
the phase error measurement uses the coarse phase detector
instead.
P = 2PIO
where 5 ≤ PIO ≤ 16.
Hence, the P-divider can provide divide ratios between 32 and
65,536 in power-of-2 steps. With a DAC sample rate of 1 GHz,
the loop filter sample rate can range from as low as 15.26 kHz to
a maximum of 31.25 MHz. Coupled to the loop filter is a cascaded
comb integrator (CCI) filter that provides a sample rate translation
between the loop filter sample rate (fS/P) and the DDS sample
rate, fS.
The choice of P is important because it controls both the
response of the CCI filter and the sample rate of the loop filter.
To understand the method for determining a useful value for P,
it is first necessary to examine the transfer function of the CCI
filter.
1 − e jωP
H (ω)CCI =
− jω
P (1 − e
or
ω=0
1,
H CCI (ω) = 1 1 − cos(ωP ) ,
ω>0
p2 1 − cos(ω)
Digital Loop Filter
The digital loop filter integrates and low-pass filters the digital
phase error values delivered by the phase detector. The loop
filter response mimics that of a second-order RC network used
to filter the output of a typical phase detector and charge pump
combination, as shown in Figure 24.
CLK
VCO
R2
C2
06744-024
C1
To evaluate the response in terms of absolute frequency, make
the substitution
ω=
2πf
fS
where fS is the DAC sample rate, and f is the frequency at which
HCCI is to be evaluated.
LOOP FILTER
PHASE/
CHANGE
FREQUENCY
PUMP
DETECTOR
2
Figure 24. Typical Analog PLL Block Diagram
The building blocks implemented on the AD9549, however, are
digital. A time-to-digital converter that produces digital values
proportional to the edge timing error between the CLK and
feedback signals replaces the phase-frequency detector and
charge pump. A digital filter that processes the edge timing
Analysis of this function reveals that the CCI magnitude response
follows a low-pass characteristic that consists of a series of P lobes.
The lobes are bounded by null points occurring at frequency multiples of fS/P. The peak of each successive lobe is lower than its
predecessor over the frequency range between dc and one-half fS.
For frequencies greater than one-half fS, the response is a reflection
about the vertical at one-half fS. Furthermore, the first lobe (which
appears between dc and fS/P) exhibits a monotonically decreasing
response. That is, the magnitude is unity at dc, and it steadily
decreases with frequency until it vanishes at the first null point
(fS/P).
Rev. D | Page 19 of 76
AD9549
PHASE
OFFSET
14
48
FREQUENCY
TUNING WORD
(FTW)
48
48
D Q
19
19
I-SET
ANGLE TO
14
AMPLITUDE
CONVERSION
DAC+
DAC
(14-BIT)
DAC–
06744-025
48-BIT ACCUMULATOR
fS
Figure 25. DDS Block Diagram
The null points imply the existence of transmission zeros placed
at finite frequencies. While transmission zeros placed at infinity
yield minimal phase delay, zeros placed closer to dc result in
increased phase delay. Hence, the position of the first null point
has a significant impact on the phase delay introduced by the CCI
filter. This is an important consideration because excessive phase
delay negatively impacts the overall closed-loop response. As
a rule of thumb, choose a value for P so that the frequency of
the first null point (fS/P) is the greater of 80× the desired loop
bandwidth or 1.5× the frequency of CLK (fR/R).
The value of P thus calculated (PMAX) is the largest usable value
in practice. Because P is programmed as PIO, it is necessary to
define PMAX in terms of PIO so that PIOMAX can be determined.
The condition PIO ≤ PIOMAX ensures that the impact of the phase
delay of the CCI filter on the phase margin of the loop does not
exceed 5°. PIOMAX can be expressed as
PIOMAX =
f S
2 f S
, floor log 2
max 5, min16, floor log 2
3f
REF
80 f LOOP
With a properly chosen value for P, the closed-loop response of
the digital PLL is primarily determined by the response of the
digital loop filter. Flexibility in controlling the loop filter response
translates directly into flexibility in the range of applications
satisfied by the architecture of the AD9549.
The AD9549 evaluation software automatically sets the value of
the P-divider based on the user’s input criteria. Therefore, the
formulas are provided here mainly to assist in understanding
how the part works.
Direct Digital Synthesizer (DDS)
One of the primary building blocks of the digital PLL is a direct
digital synthesizer (DDS). The DDS behaves like a sinusoidal
signal generator. The frequency of the sinusoid generated by the
DDS is determined by a frequency tuning word (FTW), which
is a digital (that is, numeric) value. Unlike an analog sinusoidal
generator, a DDS uses digital building blocks and operates as a
sampled system. Thus, it requires a sampling clock (fS) that serves
as the fundamental timing source of the DDS. The accumulator
behaves as a modulo-248 counter with a programmable step size
that is determined by the FTW. A block diagram of the DDS is
shown in Figure 25.
For example, given FTW = 5, the accumulator counts in
increments of 5 sec, incrementing on each fS cycle. Over time,
the accumulator reaches the upper end of its capacity (248 in this
case), at which point, it rolls over, retaining the excess. The average
rate at which the accumulator rolls over establishes the frequency of
the output sinusoid. The average rollover rate of the accumulator
is given by the following equation and establishes the output
frequency (fDDS) of the DDS:
FTW
f DDS = 48 f S
2
Solving this equation for FTW yields
f
FTW = round 2 48 DDS
f S
For example, given that fS = 1 GHz and fDDS = 19.44 MHz, then
FTW = 5,471,873,547,255 (0x04FA05143BF7).
The relative phase of the sinusoid can be controlled numerically,
as well. This is accomplished using the phase offset input to the
DDS (a programmable 14-bit value (Δphase); see the I/O Register
Map section). The resulting phase offset, ΔΦ (radians), is given by
∆phase
∆Φ = 2π
14
2
The DDS can be operated in either open-loop or closed-loop
mode, via the close loop bit in the PLL control register
(Register 0x0100, Bit 0).
There are two open-loop modes: single tone and holdover. In
single-tone mode, the DDS behaves like a frequency synthesizer
and uses the value stored in the FTW0 register to determine its
output frequency. Alternatively, the FTW and Δphase values can be
determined by the device itself using the frequency estimator.
Because single-tone mode ignores the reference inputs, it is very
useful for generating test signals to aid in debugging. Single tone
mode must be activated manually via register programming.
Note that due to the internal architecture of the AD9549, the
LSB of the 48-bit tuning word becomes a don’t care when
operating the DDS in single-tone mode. This results in an
effective frequency resolution of 7 µHz with the DAC system
clock equal to 1 GHz.
The input to the DDS is a 48-bit FTW that provides the
accumulator with a seed value. On each cycle of fS, the accumulator
adds the value of the FTW to the running total of its output.
Rev. D | Page 20 of 76
AD9549
In holdover mode, the AD9549 uses past tuning words when
the loop is closed to determine its output frequency. Therefore,
the loop must be successfully closed for holdover mode to work.
Switching in and out of holdover mode can be either automatic
or manual, depending on register settings.
Typically, the AD9549 operates in closed-loop mode. In closedloop mode, the FTW values come from the output of the digital
loop filter and vary with time. The DDS frequency is steered in
a manner similar to a conventional VCO-based PLL.
Using the recommended value of RDAC_REF, the full-scale DAC
output current can be set with 10-bit granularity over a range of
approximately 8.6 mA to 31.7 mA. The default value is 20 mA.
PHASE DETECTOR
Coarse Phase Detector
DAC Output
The coarse phase detector uses the DAC sample rate (fS) to
determine the edge timing deviation between the REF signal
and the feedback signal generated by the DDS. Hence, fS sets
the timing resolution of the coarse phase detector. At the
recommended rate of fS = 1 GHz, the coarse phase detector
spans a range of over 131 μs (sufficient to accommodate REF
signal frequencies as low as 8 kHz).
The output of the digital core of the DDS is a time series of
numbers representing a sinusoidal waveform. This series is
translated to an analog signal by means of a digital-to-analog
converter (DAC).
The phase gain of the coarse phase detector is controlled via the
I/O registers by means of two numeric entries. The first is a
3-bit, power-of-2 scale factor, PDS. The second is a 6-bit linear
scale factor, PDG.
Note that in closed-loop mode, the DDS phase offset capability
is inoperative.
The DAC outputs its signal to two pins driven by a balanced
current source architecture (see the DAC output diagram in
Figure 26). The peak output current derives from the combination of two factors. The first is a reference current (IDAC_REF)
established at the DAC_RSET pin, and the second is a scale
factor programmed into the I/O register map.
AVDD3
49
IFS
IFS/2
CURRENT
SWITCH
ARRAY
IFS/2 – ICODE
IOUTB 50
AVSS
f PFD[ MAX ] =
06744-026
52
fS
4(PFD _ Div)
fS
8(PFD _ Div)
Therefore, fPFD[MAX] is 25 MHz in the preceding example.
Figure 26. DAC Output Pins
The value of IDAC_REF is set by connecting a resistor (RDAC_REF)
between the DAC_RSET pin and ground. The DAC_RSET pin
is internally connected to a virtual voltage reference of 1.2 V
nominal, so the reference current can be calculated by
I DAC _ REF =
The fine phase detector operates on a divided down version
of fS as its sampling time base. The sample rate of the fine phase
detector is set using a 4-bit word (PFD_Div) in the I/O register
map (Register 0x0023) and is given by
The default value of PFD_Div is 5, so for fS = 1 GHz, the default
sample rate of the fine phase detector is 50 MHz. The upper
bound on the maximum allowable input frequency to the phase
detector (fPFD[MAX]) is 49% of the sample rate, or
CODE
50Ω
)
Fine Phase Detector
Fine Phase Detector Sample Rate =
CURRENT
SWITCH
ARRAY
IFS/2 + ICODE
50Ω
(
IFS/2
SWITCH
CONTROL
51 IOUT
f
PhaseGainCPD = R S 2 PDS + 6 PDG
f
R
1. 2
R DAC _ REF
The fine phase detector uses a proprietary technique to
determine the phase deviation between the REF signal and
feedback signal.
The phase gain of the fine phase detector is controlled by
an 8-bit scale factor (FPFD_Gain) in the I/O register map
(Register 0x0404). The nominal (default) value of FPFD_Gain
is 200 and establishes the phase gain as
Note that the recommended value of IDAC_REF is 120 μA, which
leads to a recommended value for RDAC_REF of 10 kΩ.
The scale factor consists of a 10-bit binary number (FSC)
programmed into the DAC full-scale current register (Address
0x040B and Address 0x040C) in the I/O register map. The fullscale DAC output current (IDAC_FS) is given by
192FSC
I DAC _ FS = I DAC _ REF 72 +
1024
Rev. D | Page 21 of 76
PhaseGain FP D =
R(210 × 10 7 )(FPFD _ Gain)
fR
AD9549
Phase Detector Gain Matching
DIGITAL LOOP FILTER COEFFICIENTS
Although the fine and coarse phase detectors use different means
to make a timing measurement, it is essential that both have
equivalent phase gain. Without proper gain matching, the
closed-loop dynamics of the system cannot be properly
controlled. Hence, the goal is to make PhaseGainCPD =
PhaseGainFPD.
To provide the desired flexibility, the loop filter has been
designed with three programmable coefficients (α, β, and γ).
The coefficients, along with P (where P = 2PIO), completely
define the response of the filter, which is given by
e jω + ( β − γ − 1)
H (ω) LoopFilter = α j 2ω
jω
e
+ (−γ − 2)e + (γ + 1)
This leads to
To evaluate the response in terms of absolute frequency, substitute
( f S 2 PDS + 6 )PDG = (210 × 10 7 )FPFD _ Gain
which simplifies to
2
PDS
PDG =
ω=
(16 × 10 7 )FPFD _ Gain
fS
Typically, FPFD_Gain is established first, and then PDG and
PDS are calculated. The proper choice for PDS is given by
10 7 × FPFD _ Gain
PDS = round log 2
2 fS
The loop filter coefficients are determined by the AD9549
evaluation software according to three parameters:
β = −4 πPf C tan(Φ)
The final value of PDG must satisfy 0 ≤ PDG ≤ 63. For example,
let fS = 700 MHz and FPFD_Gain = 200; then PDS = 1 and
PDG = 23.
Note that the AD9549 evaluation software calculates register
values that have the phase detector gains already matched.
Phase Detector Pin Connections
There are three pins associated with the phase detector that
must be connected to external components. Figure 27 shows the
recommended component values and their connections.
AD9549
21
PFD_VRB
γ=
PFD_RSET
F (Φ)β
2 38 π
f DDS f C F (Φ)β
α = − 7
10 FPFD _ Gain
where:
F (Φ) = 1 +
fC =
1
sin(Φ)
f LOOP
fS
Note that the range of loop filter coefficients is limited as follows:
0.1µF
0 < α < 223 (~8.39 × 106)
−0.125 < β < 0
−0.125 < γ < 0
10µF
0.1µF
Figure 27. Phase Detector Pin Connections
06744-027
4.99kΩ
0.1µF
1
2
FPFD_Gain is the value of the gain scale factor for the fine
phase detector as programmed into the I/O register map.
22
PFD_VRT
Φ is the desired closed-loop phase margin (0 < Φ< π/2 rad).
fLOOP is the desired open-loop bandwidth (Hz).
fDDS is the desired output frequency of the DDS (Hz).
Note that fDDS can also be expressed as fDDS = fR(S/R).
The three coefficients are calculated according to parameters
via the following equations:
10 7 FPFD _ Gain
PDG = round
PDS − 4
2
f
S
20
fS
where P is the divide ratio of the P-divider, fS is the DAC sample
rate, and f is the frequency at which the function is to be evaluated.
•
•
•
The final value of PDS must satisfy 0 ≤ PDS ≤ 7. The proper
choice for PDG is calculated using the following equation:
2πPf
The preceding constraints on β and γ constrain the closed-loop
phase margin such that both β and γ assume negative values.
Even though β and γ are limited to negative quantities, the values as
programmed are positive. The negative sign is assumed internally.
Note that the closed-loop phase margin is limited to the range
of 0° < Φ < 90° because β and γ are negative.
Rev. D | Page 22 of 76
AD9549
The min(), max(), floor(), ceil() and round() functions are
defined as follows:
The three coefficients are implemented as digital elements,
necessitating quantized values. Determination of the
programmed coefficient values in this context follows.
•
The quantized α coefficient is composed of three factors, where
α0, α1, and α2 are the programmed values for the α coefficient.
α
α QUANTIZED = 0 (2 α1 )(2 −α 2 )
2048
•
The boundary values for each are 0 ≤ α0 ≤ 4095, 0 ≤ α1 ≤ 22,
and 0 ≤ α2 ≤ 7. The optimal values of α0, α1, and α2 are
•
•
2048α
α 1 = max 0, min22, ceil log 2
4095
4095
α 2 = max 0, min7, floor log 2
+ α 1 − 11
α
[
]
α 0 = max 0, min{4095, round (α × 2 α 2 − α1 + 11 )}
The magnitude of the quantized β coefficient is composed of
two factors
(
βQUANTIZED = (β0 ) 2 −( β1 + 15)
)
where β0 and β1 are the programmed values for the β coefficient.
The boundary values for each are 0 ≤ β0 ≤ 4095 and 0 ≤ β1 ≤ 7.
The optimal values of β0 and β1 are
4095
− 15
β1 = max 0, min7, floor log 2
β
[
{
(
β0 = max 0, min 4095, round β × 2 β1 + 15
)}]
The magnitude of the quantized γ coefficient is composed of
two factors.
(
γ QUANTIZED = (γ 0 ) 2 −(γ1 + 15)
•
)
To demonstrate the wide programmable range of the loop filter
bandwidth, consider the following design example. The system
clock frequency (fS) is 1 GHz, the input reference frequency (fR)
is 19.44 MHz, the DDS output frequency (fDDS) is 155.52 MHz,
and the required phase margin (Φ) is 45°. fR is within the nominal
bandwidth of the phase detector (25 MHz), and fDDS/fR is an integer
(8), so the prescaler is not required. Therefore, R = 1 and S = 8 can
be used for the feedforward and feedback dividers, respectively.
Note that if fDDS/fR is a noninteger, then R and S must be chosen
such that S/R = fDDS/fR with S and R both constrained to integer
values. For example, if fR = 10 MHz and fDDS = 155.52 MHz,
then the optimal choice for S and R is 1944 and 125, respectively.
The open-loop bandwidth range under the defined conditions
spans 9.5 Hz to 257.5 kHz. The wide dynamic range of the loop
filter coefficients allows for programming of any open-loop
bandwidth within this range under these conditions. The
resulting closed-loop bandwidth range under the same
conditions is approximately 12 Hz to 359 kHz.
The resulting loop filter coefficients for the upper loop bandwidth,
along with the necessary programming values, are shown as
follows:
where γ0 and γ1 are the programmed values for the γ coefficient.
The boundary values for each are 0 ≤ γ0 ≤ 4095 and 0 ≤ γ1 ≤ 7.
The optimal values of γ0 and γ1 are
4095
− 15
γ 1 = max 0, min7, floor log 2
γ
[
The function min(x1, x2, … xn) chooses the smallest value
in the list of arguments.
The function max(x1, x2, … xn) chooses the largest value in
the list of arguments.
The function ceil(x) increases x to the next higher integer
if x is not an integer; otherwise, x is unchanged.
The function floor(x) reduces x to the next lower integer
if x is not an integer; otherwise, x is unchanged.
The function round(x) rounds x to the nearest integer.
]
γ 0 = max 0, min{4095, round ( γ × 2 γ 1 +15 )}
Rev. D | Page 23 of 76
α = 4322509.4784981
α0 = 2111 (0x83F)
α1 = 22 (0x16)
α2 = 0 (0x00)
β = −0.10354689386232
β0 = 3393 (0xD41)
β1 = 0 (0x00)
γ0 = 4095 (0xFFF)
γ = −0.12499215775201
γ1 = 0 (0x00)
AD9549
LOCK DETECTION
The resulting loop filter coefficients for the lower loop
bandwidth, along with the necessary programming values,
are shown as follows:
Phase Lock Detection
During the phase locking process, the output of the phase
detector tends toward a value of 0, which indicates perfect
alignment of the phase detector input signals. As the control
loop works to maintain the alignment of the phase detector
input signals, the output of the phase detector wanders around 0.
α = 0.005883404361345
α0 = 1542 (0x606)
α1 = 0 (0x00)
α2 = 7 (0x07)
β = −0.000003820176667
β0 = 16 (0x10)
β1 = 7 (0x07)
γ = −0.00000461136116
γ0 = 19 (0x13)
γ1 = 7 (0x07)
The AD9549 evaluation software generates these coefficients
automatically based on the user’s desired loop characteristics.
CLOSED-LOOP PHASE OFFSET
The AD9549 provides for limited control over the phase offset
between the reference input signal and the output signal by adding
a constant phase offset value to the output of the phase detector.
An adder is included at the output of the phase detector to support
this, as shown in Figure 28. The value of the constant (PLLOFFSET)
is set via the DPLL phase offset bits.
PHASE
OFFSET
VALUE
The phase lock detector tracks the absolute value of the digital
samples generated by the phase detector. These samples are
compared to the phase lock detect threshold value (PLDT)
programmed in the I/O register map. A false state at the output
of the comparator indicates that the absolute value of a sample
exceeds the value in the threshold bits. A true state at the output
of the comparator indicates alignment of the phase detector
input signals to the degree specified by the lock detection
threshold.
RESET
PHASE
DETECTOR
SAMPLES
ABSOLUTE
VALUE
CONTROL LOGIC
DIGITAL
COMPARATOR
UNLOCK
TIMER
P-DIVIDER
CLOCK
FEEDBACK
LOOP
FILTER
TO CCI
FILTER
Figure 28. Input Phase Offset Adder
For example, suppose that FPFD_Gain = 200, fCLK = 3 MHz, and
1° of phase offset is desired. First, the value of ΔtOFFSET must be
determined, as follows:
360
t CLK =
CLOSE
LOOP
PLDT = round (∆t × 210 × 10 7 × FPFD _ Gain)
FPFD_Gain is described in the Fine Phase Detector section.
deg
X
Figure 29. Phase Lock Detector Block Diagram
7
PLLOFFSET = ΔtOFFSET(2 × 10 × FPFD_Gain
∆t OFFSET =
5
Y
The phase lock detect threshold value is a 32-bit number stored
in the I/O register map.
PLLOFFSET is a function of the phase detector gain and the
desired amount of timing offset (ΔtOFFSET). It is given by
10
I/O PHASE LOCK DETECT
REGISTERS
THRESHOLD
06744-029
PHASE
DETECTOR
06744-028
3
CLK
PHASE
LOCK
DETECT
LOCK
TIMER
1 1
= 925.9 ps
360 3 MHz
where Δt is the maximum allowable timing error between the
signals at the input to the phase detector and the value of
FPFD_Gain is as described in the Fine Phase Detector section.
For example, suppose that fR/R = 3 MHz, FPFD_Gain = 200, and
the maximum timing deviation is given as 1°. This yields a Δt
value of
∆t =
Having determined ΔtOFFSET,
1°
360°
(R × TR ) =
R
360 f R
=
1
360(3 × 10 6 )
The resulting phase lock detect threshold is
PLLOFFSET = 925.9 ps(210 × 10 7 × 200) = 1896
2 10 × 10 7 × 200
= 1896
PLDT = round
6
360(3 × 10 )
The result has been rounded because PLLOFFSET is restricted to
integer values.
Note that the PLLOFFSET value is programmed as a 14-bit, twos
complement number. However, the user must ensure that the
magnitude is constrained to 12 bits, such that:
Hence, 1896 (0x00000768) is the value that must be stored in
the phase lock detect threshold bits.
−211 ≤ PLLOFFSET < +211
The preceding constraint yields a timing adjustment range of
±1 ns. This ensures that the phase offset remains within the
bounds of the fine phase detector.
Rev. D | Page 24 of 76
AD9549
The phase lock detect signal is generated once the control logic
observes that the output of the comparator has been in the true
state for 2x periods of the P-divider clock (see the Digital Loop
Filter section for a description of the P-divider). When the phase
lock detect signal is asserted, it remains asserted until cleared
by an unlock event or by a device reset.
Figure 31 shows the basic timing relationship between the
reference signal at the input to the phase detector, the phase
error magnitude, the output of the comparator, and the output
of the phase lock detector. The example shown here assumes
that X = 3 and Y = 1.
Note that the phase and frequency lock detectors may erroneously
indicate phase/frequency lock while in holdover. Therefore, the
user should use the phase and frequency lock signals in conjunction with either the reference input valid or the holdover active
signals to indicate phase/frequency lock.
The duration of the lock detection process is programmable via
the phase lock watchdog timer bits. The interval is controlled by a
5-bit number, X (0 ≤ X ≤ 20). The absolute duration of the
phase lock detect interval is
t LOCK =
Frequency Lock Detection
2X P
Frequency lock detection is similar to phase lock detection, with
the exception that the difference between successive phase
samples is the source of information. A running difference of
the phase samples serves as a digital approximation to the timederivative of the phase samples, which is analogous to frequency.
fS
Hysteresis in the phase lock detection process is controlled by
specifying the minimum duration that qualifies as an unlock
event. An unlock event is declared when the control logic
observes that the output of the comparator has been in the false
state for 2Y + 1 periods of the P-divider clock (provided that the
phase lock detect signal has been asserted). Detection of an
unlock event clears the phase lock detect signal, and the phase
lock detection process is automatically restarted.
The formula for the frequency lock detect threshold value
(FLDT) is
2
R
FLDT = round ∆f × 210 × 10 7 × FPFD _ Gain
f
R
The time required to declare an unlock event is programmable
via the phase unlock watchdog timer bits. The interval is
controlled by a 3-bit number, Y (0 ≤ Y ≤ 7). The absolute
duration of the unlock detection interval is
t UNLOCK =
where fR is the frequency of the active reference, R is the value of
the reference prescaler, and Δf is the maximum frequency
deviation of fR that is considered to indicate a frequency-locked
condition (Δf ≥ 0).
2 Y +1 P
fS
RESET
PHASE
DETECTOR
SAMPLES
DIFFERENCER
ABSOLUTE
VALUE
CONTROL LOGIC
DIGITAL
COMPARATOR
UNLOCK
TIMER
FREQUENCY
LOCK
DETECT
LOCK
TIMER
P-DIVIDER
CLOCK
Y
5
X
CLOSE
LOOP
06744-031
3
I/O FREQUENCY LOCK DETECT
REGISTERS
THRESHOLD
Figure 30. Frequency Lock Detection
fR/R
PHASE ERROR
MAGNITUDE
SAMPLES
THRESHOLD
0
fS/P
THRESHOLD
COMPARATOR
8
8
LOCKED
4
UNLOCK
TIMER
(Y = 1)
Figure 31. Lock/Unlock Detection Timing
Rev. D | Page 25 of 76
06744-030
LOCK
TIMER
(X = 3)
AD9549
For example, if fR = 3 MHz, R = 5, FPFD_Gain = 200, and a frequency lock threshold of 1% is specified, the frequency lock
detect threshold value is
The values of the two frequency bounds are
f PRESENT =
FLDT =
2
5
= 170,667
round (1% × 3 × 10 6 ) × 2 10 × 10 7 × 200 ×
6
3 × 10
Hence, 170,667 (0x00029AAB) is the value that should be stored
in the frequency lock detect threshold bits.
The duration of the frequency lock/unlock detection process is
controlled in exactly the same way as the phase lock/unlock
detection process in the previous section. However, different
control registers are used: namely, the frequency lock/unlock
watchdog timer bits.
f LOST =
+1,
the LOR circuit is capable of indicating an LOR condition in
little more than a single input reference period. For example,
if fS = 1 GHz and fR = 2.048 MHz, then the smallest usable N
value is
10 9
+ 1 = 245
N MIN = floor
6
2(2.048 × 10 )
This yields the following values for fPRESENT and fLOST:
The LOR circuits are internal watchdog timers that have a
programmable period. The period of the timer is set via the
I/O register map so that its period is longer than that of the
monitored reference signal. The rising edge of the reference
signal continuously resets the watchdog timer. If the timer
reaches a full count, this indicates that the reference was either
lost or its period was longer than the timer period. LOR does not
differentiate between these.
The period for each of the LOR timers is controlled by a 16-bit
word in the I/O register map. The period of the timer clock (tCLK)
is 2/fS. Therefore, the period of the watchdog timer (tWD) is
tWD = (2/fS)N
where N is the value of the 16-bit word stored in the I/O register
map for the appropriate LOR circuit.
Choose the value of N so that the watchdog period is greater
than the input reference period, expressed mathematically as
fPRESENT = 2,049,180
fLOST = 2,040,816
Note that N should be chosen sufficiently large to account for
any acceptable deviation in the period of the input reference
signal.
Notice that the value of N is inversely proportional to the
reference frequency, meaning that as the reference frequency
goes up, the precision for adjusting the threshold goes down.
Proper operation of the LOR circuit requires that N be no less
than 3. Therefore, the highest reference frequency for which the
LOR circuit functions properly is given by
f LOR[MAX] =
fS
6
Reference Frequency Monitor
The AD9549 can set an alert whenever one or both of the
reference inputs drift in frequency beyond user-specified limits.
Each of the two references has a dedicated out of limits (OOL)
circuit enabled/disabled via the I/O register map. Detection of
an OOL condition sets the appropriate OOL bit in both a status
register and an IRQ status register in the I/O register map. The
user can also assign a status pin (S1 to S4) to each of the OOL
flags by setting the appropriate bit in the I/O register map. This
provides a means to control external hardware based on the
state of the OOL flags directly.
Each reference monitor contains three main building blocks: a
programmable reference divider, a 32-bit counter, and a 32-bit
digital comparator.
fR
where fR is the frequency of the input reference.
The value of N results in establishing two frequencies: one for
which the LOR signal is never triggered (fPRESENT), and one for
which the LOR signal is always active (fLOST). Using these frequencies, the LOR signal intermittently toggles between states.
Rev. D | Page 26 of 76
16-BIT
GATE
OOL
DIVIDER
32-BIT
COUNTER
DIGITAL
COMPARATOR
CLK
fS
÷4
LOWER UPPER
LIMIT
LIMIT
Figure 32. Reference Monitor
OOL
06744-032
The AD9549 can set an alert when one or both of the reference
signals are not present. Each of the two reference inputs (REFA,
REFB) has a dedicated LOR (loss of reference) circuit enabled
via the I/O register map. Detection of an LOR condition sets the
appropriate LOR bit in both a status register and an IRQ status
register in the I/O register map. The LOR state is also internally
available to the multipurpose status pins (S1 to S4) of the AD9549.
By setting the appropriate bit in the I/O register map, the user
can assign a status pin to each of the LOR flags. This provides
a means to control external hardware based on the state of the
LOR flags directly.
f
N > floor S
2f
R
fS
2N
f
Note that when N is chosen to be floor S
2 fR
REFERENCE MONITORS
Loss of Reference
fS
2(N − 1)
AD9549
The following four values are needed to calculate the correct
values of the reference monitor:
System clock frequency, fS (usually 1 GHz)
Reference input frequency, fR (in Hz)
Error bound, E (1% = 0.01)
Monitor window size (W)
The monitor window size is the difference between the maximum
and minimum number of counts accumulated between adjacent
edges of the reference input. If this window is too small, random
variations cause the OOL detector to indicate incorrectly that
a reference is out of limits. However, the time required to
determine if the reference frequency is valid increases with window
size. A window size of at least 20 is a good starting point.
The four input values mentioned previously are used to calculate
the OOL divider (D) and OOL nominal value (N), which, in
turn, are used to calculate the OOL upper limit (U) and OOL
lower limit (L), according to the following formulas:
The AD9549 supports dual input reference clocks. Reference
switchover can be accomplished either automatically or manually
by appropriately programming the automatic selector bit in the
I/O register map (Register 0x01C0, Bit 2).
Transition to a newly selected reference depends on a number
of factors:
•
•
•
•
State of the REFSELECT pin
State of the REF_AB bit (Register 0x01C1[2])
State of the enable ref input override bit (Register 0x01C1[3])
Holdover status
A functional diagram of the reference switchover and holdover
logic is shown in Figure 33.
ACTIVE REFSEL STATE
REFSELECT
REF_AB
1
0
1 f
W
D = max 1, min 65,535, ceil × R ×
5 f S E
N=
0
DERIVED
REFSEL STATE
1
TO
REFERENCE
SWITCHING
CONTROL
LOGIC
OVERRIDE REFPIN
STATE
MACHINE
fS D
×
fR 4
AUTOREFSEL
AUTOHOLD
OVERRIDE HLDPIN
DERIVED
HOLDOVER
STATE
1
0
0
1
L = floor(N ) − floor(W )
U = ceil(N ) + floor(W )
The timing accuracy is dependent on two factors. The first is
the inherent accuracy of fS because it serves as the time base for
the reference monitor. As such, the accuracy of the reference
monitor can be no better than the accuracy of fS. The second
factor is the value of W, which must be sufficiently large (≥20)
so that the timer resolves the deviation between a nominal value
of fR and a value that is out of limits.
As an example, let fR = 10 MHz, Ε = 0.05%, fS = 1 GHz, and
W = 20. The limits are then
D = 79
Lower Limit = 1980
Upper Limit = 2020
Next, let Ε = 0.0005%. Then the limits are
D = 7999
Lower Limit = 199980
Upper Limit = 200020
Note that the number of counts (and time) required to make
this measurement has increased by 100×. In addition, it is
recommended that D be an odd number.
HOLDOVER
TO
HOLDOVER
CONTROL
LOGIC
HLDOVR
ACTIVE HOLDOVER STATE
06744-033
•
•
•
•
REFERENCE SWITCHOVER
Figure 33. Reference Switchover and Holdover Logic
In manual mode, the active reference is determined by an externally applied logic level to the REFSELECT pin. In automatic
mode, an internal state machine determines which reference is
active, and the REFSELECT pin becomes an output indicating
which reference the state machine is using.
The user can override the active reference chosen by the internal
state machine via the enable ref input override bit. The REF_AB
bit is then used to select the desired reference. When in override,
it is important to note that the REFSELECT pin does not
indicate the physical reference selected by the REF_AB bit.
Instead, it indicates the reference that the internal state machine
would select if the device were not in the override mode. This
allows the user to force a reference switchover by means of the
programming registers while monitoring the response of the
state machine via the REFSELECT pin.
The same type of operation (manual/automatic and override)
also applies to the holdover function, as shown in the reference
switchover logic diagram (see Figure 33). The dashed arrows in
the diagram indicate that the state machine output is available
to the REFSELECT and HOLDOVER pins when in override mode.
Rev. D | Page 27 of 76
AD9549
Use of Line Card Mode to Eliminate Runt Pulses
Effect of Reference Input Switchover on Output Clock
When two references are not in exact phase alignment and
a transition is made from one to the other, it is possible that an
extra pulse may be generated. This depends on the relative edge
placement of the two references and the point in time that a switchover is initiated. To eliminate the extra pulse problem, an enable
line card mode bit is provided (Register 0x01C1, Bit 4). The line
card mode logic is shown in Figure 34. When the enable line card
bit is set to 0, reference switchover occurs on command without
consideration of the relative edge placement of the references.
This means that there is the possibility of an extra pulse. However,
when this bit is set to 1, the timing of the reference switchover is
executed conditionally, as shown in Figure 35.
This section covers the transient behavior of the AD9549
during a clock switchover event. This is also applicable when
the AD9549 leaves holdover and reverts to being locked to
a reference input. There is no phase disturbance entering
holdover mode.
SELECTED
REFERENCE
0
REFB_IN
REFERENCE SWITCHING:
10ns DELTA @ 0.2Hz BANDWIDTH, 70° PHASE MARGIN
31
REF IN
1
29
FROM
REFERENCE
SELECTION
LOGIC
0
1
PHASE (µs)
ENABLE
LINE CARD
MODE
Q D
06744-034
1
21
Figure 34. Reference Switchover Control Logic
19
0
Note that when the line card mode is enabled, the rising edges
of the alternate reference are used to clock a latch. The latch
holds off the actual transition until the next rising edge of the
alternate reference.
1
3
2
3
1
2
REF IN
1
2
3
4
3
5
DISABLED
4
ENABLED
REF SELECTION STALLED UNTIL
NEXT RISING EDGE OF REFB
Figure 35. Reference Switchover Timing
2.5
3.0
3.5
4.0
∆y
∆x
=
4.75 divs
1s
=
105°
1s
= 0.292 Hz
The maximum frequency error for this transient is
4
MaxFrequencyError =
LINE CARD
MODE
REF IN
1.5
2.0
TIME (s)
The frequency disturbance is the slope of the shift in Figure 36.
The maximum slope is 4.75 divisions in one second of time,
which gives the following transient frequency error, assuming
that the output is also 30.72 MHz:
m=
SELECT REFB
SELECT
REFA
1.0
Figure 36 shows the output phase as a function of time for a
reference switchover event. In this example, Reference A and
Reference B are both 30.72 MHz and have a 10 ns (102°) phase
offset. The digital PLL loop bandwidth is 0.2 Hz.
4
06744-035
REFB IN
FROM REFERENCE
SELECTION LOGIC
2
0.5
Figure 36. Output Phase vs. Time for a Reference Switchover
Figure 35 shows a timing diagram that demonstrates the difference
between reference switchover with the line card mode enabled
and disabled. If enabled, when the reference switchover logic is
given the command to switch to the alternate reference, an actual
transition does not occur until the next rising edge of the alternate reference. This action eliminates the spurious pulse that can
occur when the line card mode is disabled.
1
25
23
0
REFA IN
27
06744-036
REFA_IN
Switching reference inputs with different phases causes a transient
frequency disturbance at the output of the PLL. The magnitude
of this disturbance depends on the frequency of the reference
inputs, the magnitude of the phase offset between the two
references, and the digital PLL loop bandwidth.
0.292 Hz
30.72 MHz
= 0.0095 ppm
To apply this to a general case, the designer should calculate the
maximum time difference between two reference edges that are
180° apart. The preceding calculation of the slope, m, becomes
0.5 Hz, not 0.292 Hz, for a phase shift of 180°. Next, the frequency
error must be scaled for the loop bandwidth used. The frequency
error for 1 kHz is 5000× greater than for 0.2 Hz, so the peak
frequency error for the preceding example of 102° is 47.4 ppm,
and 81.3 ppm for a 180° phase error between the reference inputs.
Rev. D | Page 28 of 76
AD9549
When calculating frequency error for a hitless switchover
environment such as Stratum 3, as defined in Telcordia
GR-1244-CORE, the designer must consider the frequency
error budget for the entire system. The frequency disturbance
caused by a reference clock switchover in the AD9549
contributes to this budget.
It is also critical that the designer differentiate between applications that require the output clock to track the input clock,
as opposed to applications that require the PLL to smooth out
transient disturbances on the input.
Based on all of the preceding considerations, the AD9549
digital PLL architecture allows the designer to choose a loop
bandwidth tailored to meet the requirements for a given
application. The loop bandwidth can range from 0.1 Hz up
to 100 kHz, provided that the loop bandwidth is never more
than 1/10th of the phase detector frequency.
HOLDOVER
Holdover Control and Frequency Accuracy
Holdover functionality provides the user with a means of
maintaining the output clock signal even in the absence of a
reference signal at the REFA or REFB input. In holdover mode,
the output clock is generated from the SYSCLK input (via the
DDS) by directly applying a frequency tuning word to the DDS.
The frequency accuracy of the AD9549 is exactly the frequency
accuracy of the system clock input.
Transfer from normal operation to holdover mode can be
accomplished either manually or automatically by appropriately
programming the automatic holdover bit (Register 0x01C0, Bit 0,
0 = manual, 1 = auto). The actual transfer to holdover operation,
however, depends on the state of the HOLDOVER pin and the
state of the enable holdover override and holdover on/off
control register bits (Register 0x01C1, Bits 1:0).
Manual holdover is established when the automatic holdover bit is
a Logic 0 (default). In manual mode, holdover is determined by
the state of the HOLDOVER pin (0 = normal, 1 = holdover). The
HOLDOVER pin is configured as a high impedance (>100 kΩ)
input pin to accommodate manual holdover operation.
Automatic holdover is invoked when the automatic holdover bit
is a Logic 1. In automatic mode, the HOLDOVER pin is configured
as a low impedance output with its logic state indicating the
holdover state as determined by the internal state machine
(0 = normal, 1 = holdover).
In automatic holdover operation, the user can override the internal
state machine by programming the enable holdover override bit
to a Logic 1 and the holdover mode bit (Register 0x001C0[4])
to the desired state (0 = normal, 1 = holdover). However, the
HOLDOVER pin does not indicate the forced holdover state in
the override condition but continues to indicate the holdover
state as chosen by the internal state machine (even though the
state machine choice is overridden). This allows the user to
force a holdover state by means of the programming registers
while monitoring the response of the state machine via the
HOLDOVER pin. A diagram of the reference switchover and
holdover logic is shown in Figure 33.
Note that the default state for the reference switchover bits is as
follows: automatic holdover = 0, enable holdover override = 0,
and holdover mode = 0.
Rev. D | Page 29 of 76
AD9549
RESET
FAILA & VALIDB & AUTOREFSEL & OVRDREFPIN
REFA
&
HOLDOVER
1
REFB
&
HOLDOVER
2
REFA
&
HOLDOVER
FA
IL
AU B &
TO V
RC AL
O IDA
O V& &
VR
A
DH OV UT
LD RD OR
PI RE EF
N FP S
IN EL
& &
3
FAILB & AUTOHOLD & OVRDHLDPIN &
(VALIDA OR AUTOREFSEL OR OVRDREFPIN)
&
EL
FS &
E
N
R PI
TO EF
AU DR
& VR IN
DB O DP
LI & HL
A
V
D
V O
& RC VR
O
LA TO
I
FA AU
VALIDB & AUTORCOV & OVRDHLDPIN
VALIDA & AUTORCOV & OVRDHLDPIN
FAILA & AUTOHOLD & OVRDHLDPIN &
(VALIDB OR AUTOREFSEL OR OVRDREFPIN)
FAILB & VALIDA & AUTOREFSEL & OVRDREFPIN
4
REFB
&
HOLDOVER
REFERENCE A SELECTED
REFERENCE B SELECTED
HOLDOVER STATE
REFERENCE A FAILED
REFERENCE B FAILED
REFERENCE A VALIDATED
REFERENCE B VALIDATED
OVRDREFPIN:
OVRDHLDPIN:
AUTOREFSEL:
AUTORCOV:
AUTOHOLD:
||:
&:
%:
OVERRIDE REF SEL PIN
OVERRIDE HOLDOVER PIN
AUTOMATIC REFERENCE SELECT
AUTOMATIC HOLDOVER RECOVERY
AUTOMATIC HOLDOVER ENTRY
LOGICAL OR
LOGICAL AND
LOGICAL NOT
06744-037
ABBREVIATION KEY
REFA:
REFB:
HOLDOVER:
FAILA:
FAILB:
VALIDA:
VALIDB:
Figure 37. Holdover State Diagram
settings, the logic state of the REFSELECT and HOLDOVER
pins, and the occurrence of certain events (for example, a reference
failure).
Holdover and Reference Switchover State Machine
Figure 37 shows the interplay between the input reference
signals and holdover, as well as the various control signals
and the four states.
State 1 or State 2 is in effect when the device is not in the holdover
condition, and State 3 or State 4 is in effect when the holdover
condition is active. When REFA is selected as the active reference,
State 1 or State 3 is in effect. When REFB is selected as the active
reference, State 2 or State 4 is in effect. A transition between states
depends on the reference switchover and holdover control register
The state machine and its relationship to control register and
external pin stimuli are shown in Figure 37. The state machine
generates a derived reference selection and holdover state. The
actual control signal sent to the reference switchover logic and
the holdover logic, however, depends on the control signals
applied to the muxes. The dashed path leading to the REFSELECT
and HOLDOVER pins is active when the automatic mode is
selected for reference selection and/or holdover assertion.
Rev. D | Page 30 of 76
AD9549
Reference Validation Timers
Each of the two reference inputs has a dedicated validation
timer. The status of these timers is used by the holdover state
machine as part of the decision making process for reverting
to a previously faulty reference. For example, suppose that a
reference fails (that is, an LOR or OOL condition is in effect)
and that the device is programmed to revert automatically to
a valid reference when it recovers. When a reference returns to
normal operation, the LOR and OOL conditions are no longer
true. However, the state machine is not immediately notified of
the clearing of the LOR and OOL conditions. Instead, when
both the LOR and OOL conditions are cleared, the validation
timer for that particular reference is started. Expiration of the
validation timer is an indication to the state machine that the
reference is then available for selection. However, even though
the reference is then flagged as valid, actual transition to the
recovered reference depends on the programmed settings of the
various holdover control bits.
The validation timers are controlled via the I/O register map.
The user should be careful to make sure the validation timer is
at least two periods of the reference clock. Although there are
two independent validation timers, the programmed information is shared by both. The desired time interval is controlled via
a 5-bit word (T) such that 0 ≤ T ≤ 31 (default is T = 0). The
duration of the validation timers is given by
(
)
TRECOVER = T0 2T + 1 − 1
The output frequency in holdover mode depends on the
frequency of the SYSCLK input source and the value of the
FTW applied to the DDS. Therefore, the stability of the output
signal is completely dependent on the stability of the SYSCLK
source (and the SYSCLK PLL multiplier, if enabled).
Note that it is very important to power down an unused
reference input to avoid chattering on that input. In addition,
the reference validation timer must be set to at least one full
cycle of the signal coming out of the reference divider.
Holdover Sampler and Averager (HSA)
If activated via the I/O register map, the HSA continuously
monitors the data generated by the digital loop filter in the
background. It should be noted that the loop filter data is a time
sequence of frequency adjustments (Δf) to the DDS. The output
of the HSA is routed to a read-only register in the I/O register
map and to the holdover control logic.
The first of these destinations (the read-only register) serves as
a trace buffer that can be read by the user and the data processed
externally. The second destination (the holdover control logic)
uses the output of the HSA to peg the DDS at a specific frequency
upon entry into the holdover state. Hence, the DDS assumes a
frequency specified by the last value generated by the HSA just
prior to entering the holdover state.
The state of the output mux is established by programming the
I/O register map. The default state is such that the Δf values
pass through the HSA unaltered. In this mode, the output sample
rate is fS/P, the same as the sample rate of the digital loop filter.
where T0 is the sample rate of the digital loop filter, whose
period is
T0 =
monitoring both reference inputs and, as soon as one becomes
valid, the AD9549 automatically switches to that input.
2 PIO
fS
Note that P is the divide ratio of the P-divider (see the Digital
Loop Filter section), and fS is the DAC sample rate.
See the Digital Loop Filter section for more information.
Holdover Operation
When the holdover condition is asserted, the DDS output
frequency is no longer controlled by the phase lock feedback
loop. Instead, a static frequency tuning word (FTW) is applied
to the DDS to hold it at a specified frequency. The source of the
static FTW depends on the status of the appropriate control
register bits. During normal operation, the holdover averager and
sampler monitors and accumulates up to 65,000 FTW values as
they are generated, and, upon entering holdover, the holdover
state machine can use the averaged tuning word or the last valid
tuning word.
Exiting holdover mode is similar to the manner in which it is
entered. If manual holdover control is used, when the holdover
pin is deasserted, the phase detector starts comparing the
holdover signal with the reference input signal and starts to
adjust the phase/frequency using the holdover signal as its
starting point.
The behavior of the holdover state machine when it is automatically exiting holdover mode is very similar. The primary
difference is that the reference monitor is continuously
Alternatively, the mux can be set to select the averaging path.
In this mode, a block average is performed on a sequence of
samples. The length of the sequence is determined by programming the value of Y (a 4-bit number stored in the I/O register
map) and has a value of 2Y + 1. In averaging mode, the output
sample rate is given by fS/(P × 2Y + 1).
When the number of Δf samples that are specified by Y has
been collected, the averaged result is delivered to a two-stage
pipeline. The last stage of the pipeline contains the value that
is delivered to the holdover control logic when a transition into
the holdover state occurs. The pipeline is a guarantee that the
averaged Δf value delivered to the holdover control logic has
not been interrupted by the transition into the holdover state.
The pipeline provides an inherent delay of Δt = P × 2Y + 1/fS.
Hence, the DDS hold frequency is the average as it appeared Δt
to 2Δt seconds prior to entering the holdover state. Note that
the user has some control over the duration of Δt because it is
dependent on the programmed value of Y.
Rev. D | Page 31 of 76
AD9549
OUTPUT FREQUENCY RANGE CONTROL
artifacts of the sampling process and other spurs outside the
filter bandwidth. The signal is then brought back on-chip to
be converted to a square wave that is routed internally to the
output clock driver or the 2× DLL multiplier.
Under normal operating conditions, the output frequency is
dynamically changing in response to the output of the digital
loop filter. The loop filter can steer the DDS to any frequency
between dc and fS/2 (with 48-bit resolution). However, the user
is given the option of placing limits on the tuning range of the
DDS via two 48-bit registers in the I/O register map: the FTW
upper limit and the FTW lower limit. If the tuning word input
exceeds the upper or lower frequency limit boundaries, the
tuning word is clipped to the appropriate value. The default
setting for these registers is fS/2 and dc, respectively. The
frequency word tuning limits should be used with caution
because they may make the digital loop unstable.
Because the DAC constitutes a sampled system, its output must
be filtered so that the analog waveform accurately represents the
digital samples supplied to the DAC input. The unfiltered DAC
output contains the desired baseband signal, which extends from
dc to the Nyquist frequency (fS/2). It also contains images of the
baseband signal that theoretically extend to infinity. Note that
the odd images (shown in Figure 39) are mirror images of the
baseband signal. Furthermore, the entire DAC output spectrum
is affected by a sin(x)/x response, which is caused by the sampleand-hold nature of the DAC output signal.
It may be desirable to limit the output range of the DDS to a
narrow band of frequencies (for example, to achieve better jitter
performance in conjunction with a band pass filter). See the Use
of Narrow-Band Filter for High Performance section for more
information about this feature.
REF IN
÷R
PHASE
DETECTOR
LOOP
FILTER
The response of the reconstruction filter should preserve the
baseband signal (Image 0), while completely rejecting all other
images. However, a practical filter implementation typically
exhibits a relatively flat pass band that covers the desired output
frequency plus 20%, rolls off as steeply as possible, and then
maintains significant (though not complete) rejection of the
remaining images.
DDS/DAC
EXTERNAL
RECONSTRUCTION
FILTER
÷S
Because the DAC output signal serves as the feedback signal for
the digital PLL, the design of the reconstruction filter can have
a significant impact on the overall jitter performance. Hence,
good filter design and implementation techniques are important
for obtaining the best possible jitter results.
LOW PASS
FREQUENCY
LIMITER
Use of Narrow-Band Filter for High Performance
PHASE
DETECTOR
LOOP
FILTER
EXTERNAL
RECONSTRUCTION
FILTER
÷S
A distinct advantage of the AD9549 architecture is its ability to
constrain the frequency output range of the DDS. This allows
the user to employ a narrow-band reconstruction filter instead
of the low-pass response shown in Figure 39, resulting in less
jitter on the output. For example, suppose that the nominal
output frequency of the DDS is 150 MHz. One might then
choose a 5 MHz narrow band filter centered at 150 MHz. By
using the AD9549's DDS frequency limiting feature, the user
can constrain the output frequency to 150 MHz ± 4.9 MHz
(which allows for a 100 kHz margin at the pass-band edges).
This ensures that a feedback signal is always present for the
digital PLL. Such a design is extremely difficult to implement
with conventional PLL architectures.
DDS/DAC
BAND PASS
Figure 38. Application of the Frequency Limiter
RECONSTRUCTION FILTER
The origin of the output clock signal produced by the AD9549 is
the combined DDS and DAC. The DAC output signal appears as
a sinusoid sampled at fS. The frequency of the sinusoid is determined by the frequency tuning word (FTW) that appears at the
input to the DDS. The DAC output is typically passed through
an external reconstruction filter that serves to remove the
MAGNITUDE
(dB)
IMAGE 0
IMAGE 1
IMAGE 2
IMAGE 3
IMAGE 4
0
–20
–40
PRIMARY
SIGNAL
FILTER
RESPONSE
SIN(x)/x
ENVELOPE
–60
–80
SPURS
f
–100
fs/2
fs
3fs/2
2 fs
BASE BAND
Figure 39. DAC Spectrum vs. Reconstruction Filter Response
Rev. D | Page 32 of 76
5fs/2
06744-039
÷R
06744-038
REF IN
AD9549
FDBK_IN INPUTS
VDD
The feedback pins, FDBK_IN and FDBK_INB, serve as the input
to the feedback path of the digital PLL. Typically, these pins are
used to receive the signal generated by the DDS after it has been
band-limited by the external reconstruction filter.
+
VB
1pF
REFA_IN
(OR REFB_IN)
A diagram of the FDBK input pins is provided in Figure 40,
which includes some of the internal components used to bias
the input circuitry. Note that the FDBK input pins are internally
biased to a dc level of ~1 V. Care should be taken to ensure that
any external connections do not disturb the dc bias because this
may significantly degrade performance.
~1pF
8kΩ
~1pF
8kΩ
TO REFERENCE
MONITOR AND
SWITCHING LOGIC
GND
FDBK_IN
~1pF
15kΩ
~1pF
15kΩ
TO S-DIVIDER
AND CLOCK
OUTPUT SECTION
VSS
Figure 41. Reference Inputs
VSS
To accommodate a variety of input signal conditions, the value
of VB is programmable via a pair of bits in the I/O register map.
Table 6 gives the value of VB for the bit pattern in Register 0x040F.
FDBK_INB
~2pF
VSS
06744-040
+
~1V
06744-041
REFA_INB
(OR REFB_INB)
Table 6. Setting of Input Bias Voltage (VB)
Reference Bias Level, Register 0x040F[1:0]
00 (default)
01
10
11
Figure 40. Differential FDBK Inputs
REFERENCE INPUTS
Reference Clock Receiver
The reference clock receiver is the point at which the user
supplies the input clock signal that the synchronizer synthesizes
into an output clock. The clock receiver circuit is able to handle
a relatively broad range of input levels as well as frequencies
from 8 kHz up to 750 MHz.
SYSCLK INPUTS
Functional Description
The SYSCLK pins are where an external time base is connected
to the AD9549 for generating the internal high frequency
system clock (fS).
Figure 41 is a diagram of the REFA and REFB input pins, which
includes some of the internal components used to bias the input
circuitry. Note that the REF input pins are internally biased by a
dc source, VB. Care should be taken to ensure that any external
connections do not disturb the dc bias because such a disturbance
may significantly degrade performance.
The SYSCLK inputs can be operated in one of three modes:
•
•
•
Note that support for redundant reference clocks is achieved by
using the two reference clock receivers (REFA and REFB).
PD SYSCLK PLL
(I/O REGISTER BIT)
VB
AVDD3 − 800 mV
AVDD3 − 400 mV
AVDD3 − 1600 mV
AVDD3 − 1200 mV
SYSCLK PLL bypassed
SYSCLK PLL enabled with input signal generated externally
Crystal resonator with SYSCLK PLL enabled
A functional diagram of the system clock generator is shown in
Figure 42.
2× REFERENCE FREQUENCY DOUBLER
(I/O REGISTER BIT)
SYSCLK PLL BYPASSED
SYSCLKB
2
1
0
2
WITH EXTERNAL DRIVE
2
1
SYSCLK
PLL
ENABLED
2
0
0
1
WITH CRYSTAL
RESONATOR
CLKMODESEL
2
1
0 2
SYSCLK
PLL
MULTIPLIER
2
1
0
2
DAC
SAMPLE
CLOCK
BIPOLAR
EDGE
DETECTOR
LOOP_FILTER
Figure 42. System Clock Generator Block Diagram
Rev. D | Page 33 of 76
06744-042
SYSCLK
AD9549
The maintaining amp on the AD9549 SYSCLK pins is intended for
25 MHz, 3.2 mm × 2.5 mm AT cut fundamental mode crystals
with a maximum motional resistance of 100 Ω. The following
crystals, listed in alphabetical order, meet these criteria (as of
the revision date of this data sheet):
•
•
•
•
•
AVX/Kyocera CX3225SB
ECS ECX-32
Epson/Toyocom TSX-3225
Fox FX3225BS
NDK NX3225SA
The benefit offered by the doubler depends on the magnitude
of the subharmonic, the loop bandwidth of the SYSCLK PLL
multiplier, and the overall phase noise requirements of the
specific application. In many applications, the AD9549 clock
output is applied to the input of another PLL, and the
subharmonic is often suppressed by the relatively narrow
bandwidth of the downstream PLL.
Note that generally, the benefits of the SYSCLK PLL doubler are
realized for SYSCLK input frequencies of 25 MHz and above.
SYSCLK PLL Multiplier
When the SYSCLK PLL multiplier path is employed, the
frequency applied to the SYSCLK input pins must be limited so
as not to exceed the maximum input frequency of the SYSCLK
PLL phase detector. A block diagram of the SYSCLK generator
is shown in Figure 43.
SYSCLK PLL MULTIPLIER
ICP
(125µA, 250µA, 375µA)
2
FROM
SYSCLK
INPUT
SYSCLK PLL Doubler
The SYSCLK PLL multiplier path offers an optional SYSCLK
PLL doubler. This block comes before the SYSCLK PLL
multiplier and acts as a frequency doubler by generating a pulse
on each edge of the SYSCLK input signal. The SYSCLK PLL
multiplier locks to the falling edges of this regenerated signal.
The impetus for doubling the frequency at the input of the
SYSCLK PLL multiplier is that an improvement in overall phase
noise performance can be realized. The main drawback is that
the doubler output is not a rectangular pulse with a constant
duty cycle even for a perfectly symmetric SYSCLK input signal.
This results in a subharmonic appearing at the same frequency
as the SYSCLK input signal, and the magnitude of the subharmonic can be quite large. When employing the doubler, care
must be taken to ensure that the loop bandwidth of the SYSCLK
PLL multiplier adequately suppresses the subharmonic.
CHARGE
PUMP
VCO
DAC
SAMPLE
CLOCK
1GHz
Note that while these crystals meet the preceding criteria
according to their data sheets, Analog Devices, Inc., does not
guarantee their operation with the AD9549, nor does Analog
Devices endorse one supplier of crystals over another.
When the SYSCLK PLL multiplier path is disabled, the AD9549
must be driven by a high frequency signal source (500 MHz to
1 GHz). The signal thus applied to the SYSCLK input pins
becomes the internal DAC sampling clock (fS) after passing
through an internal buffer.
PHASE
FREQUENCY
DETECTOR
KVCO
(HI/LO)
~2pF
÷N
÷2
(N = 2 TO 33)
LOOP_FILTER
06744-043
The SYSCLK PLL multiplier path is enabled by a Logic 0
(default) in the PD SYSCLK PLL bit of the I/O register map.
The SYSCLK PLL multiplier can be driven from the SYSCLK
input pins by one of two means depending on the logic level
applied to the 1.8V CMOS CLKMODESEL pin. When
CLKMODESEL = 0, a crystal can be connected directly across
the SYSCLK pins. When CLKMODESEL = 1, the maintaining
amp is disabled, and an external frequency source (oscillator,
signal generator, etc.) can be connected directly to the SYSCLK
input pins. Note that CLKMODESEL = 1 does not disable the
system clock PLL.
Figure 43. Block Diagram of the SYSCLK PLL
The SYSCLK PLL multiplier has a 1 GHz VCO at its core. A phase/
frequency detector (PFD) and charge pump provide the steering
signal to the VCO in typical PLL fashion. The PFD operates on
the falling edge transitions of the input signal, which means that
the loop locks on the negative edges of the reference signal. The
charge pump gain is controlled via the I/O register map by selecting
one of three possible constant current sources ranging from 125 μA
to 375 μA in 125 μA steps. The center frequency of the VCO is
also adjustable via the I/O register map and provides high/low
gain selection. The feedback path from VCO to PFD consists of
a fixed divide-by-2 prescaler followed by a programmable divideby-N block, where 2 ≤ N ≤ 33. This limits the overall divider
range to any even integer from 4 to 66, inclusive. The value of
N is programmed via the I/O register map via a 5-bit word that
spans a range of 0 to 31, but the internal logic automatically adds
a bias of 2 to the value entered, extending the range to 33. Care
should be taken when choosing these values so as to not exceed
the maximum input frequency of the SYSCLK PLL phase detector
or SYSCLK PLL doubler. These values can be found in the AC
Specifications section.
Rev. D | Page 34 of 76
AD9549
External Loop Filter (SYSCLK PLL)
The loop bandwidth of the SYSCLK PLL multiplier can be
adjusted by means of three external components, as shown in
Figure 44. The nominal gain of the VCO is 800 MHz/V. The
recommended component values are shown in Table 7. They
establish a loop bandwidth of approximately 1.6 MHz with
the charge pump current set to 250 μA. The default case is
N = 40 and assumes a 25 MHz SYSCLK input frequency and
generates an internal DAC sampling frequency (fS) of 1 GHz.
EXTERNAL
LOOP FILTER
AVDD
R1
C2
C1
To reduce such a spur requires combining the original signal with
a replica of the spur, but offset in phase by 180°. This idea is the
foundation of the technique used to reduce harmonic spurs in
the AD9549. Because the DAC has 14-bit resolution, a −60dBc
spur can be synthesized using only the lower four bits of the DAC
full-scale range. That is, the 4 LSBs can create an output level that
is approximately 60 dB below the full-scale level of the DAC
(commensurate with a −60 dBc spur). This fact gives rise to
a means of digitally reducing harmonic spurs or their aliased
images in the DAC output spectrum by digitally adding a sinusoid
at the input of the DAC with similar magnitude as the offending
spur but shifted in phase to produce destructive interference.
LOOP_FILTER
26
29
CRYSTAL RESONATOR WITH
SYSCLK PLL ENABLED
MUX
~2pF
SYSCLK
VCO
06744-044
CHARGE
PUMP
31
AD9549
SYSCLKB
Figure 44. External Loop Filter for SYSCLK PLL
SYSCLK PLL ENABLED
Table 7. Recommended Loop Filter Values for a Nominal
1.5 MHz SYSCLK PLL Loop Bandwidth
Multiplier
<8
10
20
40 (default)
60
R1
390 Ω
470 Ω
1 kΩ
2.2 kΩ
2.7 kΩ
Series C1
1 nF
820 pF
390 pF
180 pF
120 pF
INTERNAL
CLOCK
AMP
~3pF
1kΩ
~3pF
1kΩ
INTERNAL
CLOCK
VSS
Shunt C2
82 pF
56 pF
27 pF
10 pF
5 pF
+
~1V
~2pF
VSS
SYSCLK PLL BYPASSED
Detail of SYSCLK Differential Inputs
~1.5pF
HARMONIC SPUR REDUCTION
The most significant spurious signals produced by the DDS are
harmonically related to the desired output frequency of the DDS.
The source of these harmonic spurs can usually be traced to the
DAC, and the spur level is in the −60 dBc range. This ratio
INTERNAL
CLOCK
VSS
A diagram of the SYSCLK input pins is provided in Figure 45.
Included are details of the internal components used to bias the
input circuitry. These components have a direct effect on the static
levels at the SYSCLK input pins. This information is intended to
aid in determining how best to interface to the device for a given
application.
Note that the SYSCLK PLL bypassed and SYSCLK PLL enabled
input paths are internally biased to a dc level of ~1 V. Care should
be taken to ensure that any external connections do not disturb
the dc bias because this may significantly degrade performance.
Generally, it is recommended that the SYSCLK inputs be
ac-coupled to the signal source (except when using a crystal
resonator).
500Ω
~1.5pF
500Ω
+
~1V
~2pF
VSS
06744-045
FERRITE
BEAD
represents a level that is about 10 bits below the full-scale
output of the DAC (10 bits down is 2−10, or 1/1024).
Figure 45. Differential SYSCLK Inputs
Although the worst spurs tend to be harmonic in origin, the fact
that the DAC is part of a sampled system results in the possibility
of some harmonic spurs appearing in nonharmonic locations in
the output spectrum. For example, if the DAC is sampled at 1 GHz
and generates an output sinusoid of 170 MHz, the fifth harmonic
would normally be at 850 MHz. However, because of the sampling
process, this spur appears at 150 MHz, only 20 MHz away from
the fundamental. Hence when attempting to reduce DAC spurs,
it is important to know the actual location of the harmonic spur
in the DAC output spectrum based on the DAC sample rate so
that its harmonic number can be reduced.
Rev. D | Page 35 of 76
AD9549
DDS
DDS
PHASE
OFFSET
48-BIT ACCUMULATOR
48
SPUR
CANCELLATION
ENABLE
14
I-SET
48-BIT
FREQUENCY
TURNING WORD
(FTW)
14
48
D Q
19
19
ANGLE TO
AMPLITUDE
CONVERSION
14
0
14
1
DAC
(14-BIT)
DDS+
DDS–
SYSCLK
CH1 CANCELLATION PHASE OFFSET
4
9
2-CHANNEL
HARMONIC
FREQUENCY
GENERATOR
HEADROOM
CORRECTION
0
CH1
CH2 HARMONIC NUMBER
CH2 CANCELLATION PHASE OFFSET
4
CH1 GAIN
9
0
CH2
CH1 CANCELLATION MAGNITUDE
CH2 CANCELLATION MAGNITUDE
1
SHIFT
SHIFT
1
8
CH2 GAIN
8
HARMONIC SPUR CANCELLATION
06744-046
CH1 HARMONIC NUMBER
Figure 46. Spur Reduction Technique
The mechanics of performing harmonic spur reduction are shown
in Figure 46. It essentially consists of two additional DDS cores
operating in parallel with the original DDS. This enables the user
to reduce two different harmonic spurs from the second to the
15th with nine bits of phase offset control (±π) and eight bits of
ampli-tude control.
The dynamic range of the cancellation signal is further augmented by a gain bit associated with each channel. When this
bit is set, the magnitude of the cancellation signal is doubled by
employing a 1-bit left-shift of the data. However, the shift
operation reduces the granularity of the cancellation signal
magnitude.
Note that the full-scale amplitude of a cancellation spur is
approximately −60 dBc when the gain bit is a Logic 0 and
approximately −54 dBc when the gain bit is a Logic 1.
OUTPUT CLOCK DRIVERS AND 2× FREQUENCY
MULTIPLIER
There are two output drivers provided by the AD9549. The
primary supports differential 1.8 V HSTL output levels while
the secondary supports either 1.8 V or 3.3 V CMOS levels,
depending on whether Pin 37 is driven at 1.8 V or 3.3 V.
The primary differential driver nominally provides an output
voltage with 100 Ω load applied differentially (VDD − VSS =
1.8 V). The source impedance of the driver is approximately
100 Ω for most of the output clock period; during transition
between levels, the source impedance reaches a maximum of
about 500 Ω. The driver is designed to support output
frequencies of up to and beyond the OC-12 network rate of
622.08 MHz.
The output clock can also be powered down by a control bit in
the I/O register map.
Primary 1.8 V Differential HSTL Driver
The DDS produces a sinusoidal clock signal that is sampled at
the system clock rate. This DDS output signal is routed off chip,
where it is passed through an analog filter and brought back on
chip for buffering and, if necessary, frequency doubling. Where
possible, for the best jitter performance, it is recommended that
the upconverter be bypassed.
The 1.8 V HSTL output driver should be ac-coupled, with
100 Ω termination at the destination. The driver design has low
jitter injection for frequencies in the range of 50 MHz to 750 MHz.
Refer to the AC Specifications section for the exact frequency
limits.
2× Frequency Multiplier
The AD9549 can be configured via the I/O register map with an
internal 2× delay-locked loop (DLL) multiplier at the input of
the primary clock driver. The extra octave of frequency gain
allows the AD9549 to provide output clock frequencies that
exceed the range available from the DDS alone. These settings
are found in Register 0x0010 and Register 0x0200.
The input to the DLL consists of the filtered DDS output signal
after it has been squared up by an integrated clock receiver circuit.
The DLL can accept input frequencies in the range of 200 MHz
to 400 MHz.
Rev. D | Page 36 of 76
AD9549
Single-Ended CMOS Output
For example, if fS = 1 GHz, PIO = 9, and δf/δt = 5 kHz/sec, then
In addition to the high speed differential output clock driver, the
AD9549 provides an independent, single-ended output, CMOS
clock driver. It serves as a relatively low speed (<150 MHz) clock
source. The origin of the signal generated by the CMOS clock
driver is determined by the appropriate control bits in the I/O
register map. The user can select one of two sources under
program control.
One source is the signal generated by the DDS after it has been
externally filtered and brought back on chip. In this configuration, the CMOS clock driver generates the same frequency as
appears at the output of the DDS.
Note that in this configuration, the DDS output frequency must
not exceed 50 MHz.
The other source is the output of the feedback divider (S-divider).
In this configuration, the CMOS clock driver generates the same
frequency as the input reference after optional prescaling by the
R-divider (that is, fCMOS = fR/R), which is inherently limited to
a maximum of 25 MHz.
FREQUENCY SLEW LIMITER
The frequency slew limiting capability enables users to specify the
maximum rate of frequency change that appears at the output.
The function is programmable via the I/O register map. Program
control a bit to enable/disable the function (the default condition
is disable) and a register that sets the desired slew rate.
The frequency slew limiter is located between the digital loop
filter and the CCI filter, as shown in Figure 47.
The frequency slew limiter sets a boundary on the rate of change of
the output frequency of the DDS. The frequency slew limiting
constant, KSLEW, is a 48-bit value stored in the I/O register map.
The value of the constant is determined by
δf
δt
where:
PIO is the value stored in the I/O register map for the P-divider.
fS is the DAC sample rate.
δf/δt is the desired frequency slew rate limitation.
REF IN
÷R
TIME
TO
DIGITAL
CONVERTER
DIGITAL
LOOP
FILTER
(PHASE
DETECTOR)
(5 10 3 = 721
The resulting slew rate can be calculated as
f 2
K SLEW 48 S P
IO
δt
2
δf
The preceding example yields δf/δt = 5.003 kHz/sec.
FREQUENCY ESTIMATOR
The frequency estimation function automatically sets the DDS
output frequency so that the feedback frequency (fDDS/S) and the
prescaled reference frequency (fREF_IN/R) are matched within an
error tolerance (ε0). Its primary purpose is to allow the PLL to
quickly lock when the reference frequency is not known. The error
tolerance is defined as a fractional error and is controlled by
a 16-bit programmable value (K) via the I/O register map.
The precision of any frequency measurement is dependent on
the following two factors:
The timing resolution of the measurement device (δt)
The duration of the measurement (Tmeas)
The frequency estimator uses fS as its measurement reference, so
δt = 1/fS (that is, δt = 1 ns for a 1 GHz DAC sample rate). The
duration of the measurement is controlled by K, which establishes
a measurement interval that is K cycles of the measured signal
such that Tmeas = KR/fREF_IN.
The frequency estimator uses a 17-bit counter to accumulate the
number of δt periods within the measurement interval. The finite
capacity of the counter puts an upper limit on the duration of the
measurement, which is constrained to Tmax = 217/fS. If fS = 1 GHz,
this equates to ~131 μs. The fact that the measurement time is
bounded by Tmax means there is a limit to the largest value of K
(KMAX) that can be used without causing the counter to overflow.
The value of KMAX is given by
65,535
KMAX = floor
ρ
where:
f R
ρ S
fR
R is the modulus of the feedforward divider.
fR is the input reference frequency.
0
FREQUENCY
SLEW
LIMITER
1
CCI
FILTER
TO
DDS
δf/δt
÷P
FROM “S”-DIVIDER
SLEW
LIMIT
VALUE
FREQUENCY
SLEW LIMIT
ENABLE
SYSCLK
Figure 47. Frequency Slew Limiter
Rev. D | Page 37 of 76
06744-047
2 48 P IO
K SLEW round
f S 2
2 48 9
K SLEW round 9 2
(10 )
AD9549
As an example, consider the following system conditions:
The measurement error (ε) associated with the frequency
estimator depends on the choice of the measurement interval
parameter (K). These are related by
ε=
ρK
floor (ρK ) − 1
fS = 400 MHz
R=8
fREF_IN = 155.52 MHz
ε0 = 0.00005 (that is, 50 ppm)
−1
These conditions yield KMAX = 3185, which is the largest K value
that can be programmed without causing the frequency estimator
counter to overflow. With K = KMAX, Tmeas = 163.84 μs, and ε =
30.2 ppm, KMAX generally (but not always) yields the smallest
value of ε, but this comes at the cost of the largest measurement
time (Tmeas).
With a specified fractional error (ε0), only those values of K
for which ε ≤ ε0 results in a frequency estimate that meets the
requirements. A plot of ε vs. K (for a given ρ) takes on the
general form that is shown in Figure 48.
1
ε
If the measurement time must be reduced, then KHIGH can be used
instead of KMAX. This yields KHIGH = 1945, Tmeas = 100.05 μs, and
ε = 39.4 ppm.
ε BOUNDED
BY ENVELOPE
ε < ε0 FOR
ε > ε0 FOR
ε < ε0 FOR
ALL K > K1
SOME K
(K0 < K < K1)
ALL K < K0
ε0
1
KLO
K0
K1
216
KHI
Figure 48. Frequency Estimator ε vs. K
An iterative technique is necessary to determine the exact values
of K0 and K1. However, a closed form exists for a conservative
estimate of K0 (KLOW) and K1 (KHIGH).
1
1
K LOW = ceil 1 +
ρ
ε
0
2
1
K HIGH = ceil 1 +
ρ ε0
06744-048
K
0
The measurement time can be further reduced (though
marginally) by using K1 instead of KHIGH. K1 is found by solving
the ε ≤ ε0 inequality iteratively. To do so, start with K = KHIGH
and decrement K successively while evaluating the inequality
for each value of K. Stop the process the first time that the
inequality is no longer satisfied and add 1 to the value of K
thus obtained. The result is the value of K1. For the preceding
example, K1 = 1912, Tmeas = 98.35 μs, and ε = 39.8 ppm.
If a further reduction of the measurement time is necessary,
K0 can be used. K0 is found in a manner similar to K1. Start with
K = KLOW and increment K successively while evaluating the
inequality for each value of K. Stop the process the first time that
the inequality is satisfied. The result is the value of K0. For the
preceding example, K0 = 1005, Tmeas = 51.70 μs, and ε = 49.0 ppm.
If external frequency division exists between the DAC output
and the FDBK_IN pins, the frequency estimator should not be
used because it will calculate the wrong initial frequency.
Rev. D | Page 38 of 76
AD9549
INTERNAL
STATUS FLAGS
REFA LOR
0
REFA OOL
1
REFA INVALID
0
REFB LOR
1
REFB OOL
0
REFB INVALID
1
REF LOR
REF OOL
REF INVALID
PHASE LOCK
PHASE LOCK DETECT
STATUS PIN
(1 OF 4)
FREQ. LOCK
FREQUENCY LOCK DETECT
IRQ
IRQ
REFAB LOR
REFAB OOL
REFAB INVALID
REFAB
PHASE LOCK
FREQUENCY LOCK
IRQ
06744-049
STATUS PIN
CONTROL REGISTER
(1 OF 4)
Figure 49. Status Pin Control
Default DDS Output Frequency on Power-Up
STATUS AND WARNINGS
Status Pins
Four pins (S1 to S4) are reserved for providing device status
information to the external environment. These four pins are
individually programmable (via the serial I/O port) as an OR'ed
combination of six possible status indications. Each pin has a
dedicated group of control register bits that determine which
internal status flags are used to provide an indication on a
particular pin, as shown in Figure 49.
Reference Monitor Status
In the case of reference monitoring status information, a pin
can be programmed for either REFA or REFB, but not both.
In addition, the OR'ed output configuration allows the user to
combine multiple status flags into a single status indication. For
example, if both the LOR and OOL control register bits are true,
the status pin associated with that particular control register
gives an indication if either the LOR or OOL status flag is
asserted for the selected reference (A or B).
The four status pins (S1 to S4) provide a completely separate
function at power-up. They can be used to define the output
frequency of the DDS at power-up even though the I/O registers
have not yet been programmed. This is made possible because
the status pins are designed with bidirectional drivers. At powerup, internal logic initiates a reset pulse of about 10 ns. During
this time, S1 to S4 briefly function as input pins and can be
driven externally. Any logic levels thus applied are transferred
to a 4-bit register on the falling edge of the internally initiated
pulse. The falling edge of the pulse also returns S1 to S4 to their
normal function as output pins. The same behavior occurs
when the RESET pin is asserted manually.
Setting up S1 to S4 for default DDS start-up is accomplished by
connecting a resistor to each pin (either pull-up or pull-down)
to produce the desired bit pattern, yielding 16 possible states
that are used both to address an internal 8 × 16 ROM and to
select the SYSCLK mode (see Table 8). The ROM contains eight
16-bit DDS frequency tuning words (FTWs), one of which is
selected by the state of the S1 to S3 pins. The selected FTW is
transferred to the FTW0 register in the I/O register map without
the need for an I/O update. This ensures that the DDS generates
the selected frequency even if the I/O registers have not been
programmed. The state of the S4 pin selects whether the internal
system clock is generated by means of the internal SYSCLK PLL
multiplier or not (see the SYSCLK Inputs section for details).
Rev. D | Page 39 of 76
AD9549
The DDS output frequency listed in Table 8 assumes that
the internal DAC sampling frequency (fS) is 1 GHz. These
frequencies scale 1:1 with fS, meaning that other startup
frequencies are available by varying the SYSCLK frequency.
Interrupt Request (IRQ)
Any one of the four status pins (S1 to S4) can be programmed as
an IRQ pin. If a status pin is programmed as an IRQ pin, the state
of the internal IRQ flag appears on that pin. An IRQ flag is
internally generated based on the change of state of any one of
the internal status flags. The individual status flags are routed to
a read-only I/O register (status register) so that the user can
interrogate the status of any of these flags at any time. Furthermore,
each status flag is monitored for a change in state. In some cases,
only a change of state in one direction is necessary (for example, the
frequency estimate done flag), but in most cases, the status flags are
monitored for a change of state in either direction (see Figure 50).
At startup, the internal frequency multiplier defaults to 40×
when the Xtal/PLL mode is selected via the status pins.
Note that when using this mode, the digital PLL loop is still open,
and the AD9549 is acting as a frequency synthesizer. The
frequency dividers and DPLL loop filter must still be
programmed before closing the loop.
Table 8. Default Power-Up Frequency Options for 1 GHz
System Clock
Whether or not a particular state change is allowed to generate
an IRQ is dependent on the state of the bits in the IRQ mask
register. The user programs the mask to enable those events,
which are to constitute cause for an IRQ. If an unmasked event
occurs, it triggers the IRQ latch and the IRQ flag is asserted
(active high). The state of the IRQ flag is made available
externally via one of the programmable status pins (see the
Status Pins section).
Output Frequency
(MHz)
0
38.87939
51.83411
61.43188
77.75879
92.14783
122.87903
155.51758
0
38.87939
51.83411
61.43188
77.75879
92.14783
122.87903
155.51758
The automatic assertion of the IRQ flag causes the contents of the
status register to be transferred to the IRQ status register. The
user can then read the IRQ status register any time after the
indication of an IRQ event (that is, assertion of the IRQ flag). By
noting the bit that is set in the IRQ register, the cause of the IRQ
event can be determined.
Once the IRQ register has been read, the user must set the IRQ
reset bit in the appropriate control register via the serial I/O port.
This restores the IRQ flag to its default state, clears the IRQ status
register, and resets the edge detection logic that monitors the
status flags in preparation for the next state change.
IRQ MASK REGISTER
20
STATUS
FLAGS
REF SELECTED (A/B)
EDGE
DETECT
NEW REF
FREQUENCY EST. DONE
EDGE
DETECT
FREQ. EST. DONE
HOLDOVER
EDGE
DETECT
PHASE LOCK
EDGE
DETECT
FREQUENCY LOCK
EDGE
DETECT
REFA LOR
EDGE
DETECT
REFB LOR
EDGE
DETECT
REFA OOL
EDGE
DETECT
ENTER HOLDOVER
EXIT HOLDOVER
PHASE LOCKED
PHASE UNLOCKED
FREQ. LOCKED
FREQ. UNLOCKED
0
IRQ
D Q
REFA LOR
S
REFA LOR
REFB LOR
REFB LOR
REFA OOL
IRQ
REG.
REFA OOL
REFB OOL
REFB OOL
EDGE
DETECT
REFA VALID
EDGE
DETECT
REFB VALID
EDGE
DETECT
REFB OOL
REFA VALID
REFA INVALID
REFB VALID
REFB INVALID
STATUS REGISTER
11
IRQ RESET
Figure 50. Interrupt Request Logic
Rev. D | Page 40 of 76
06744-050
S1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SYSCLK
Input Mode
Xtal/PLL
Xtal /PLL
Xtal /PLL
Xtal /PLL
Xtal /PLL
Xtal /PLL
Xtal /PLL
Xtal /PLL
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
RST
S4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Status Pin
S3 S2
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
AD9549
THERMAL PERFORMANCE
Table 9. Thermal Parameters
Symbol
θJA
θJMA
θJMA
θJB
θJC
ΨJT
Thermal Characteristic Using a JEDEC51-7 Plus JEDEC51-5 2S2P Test Board
Junction-to-ambient thermal resistance, 0.0 m/sec air flow per JEDEC JESD51-2 (still air)
Junction-to-ambient thermal resistance, 1.0 m/sec air flow per JEDEC JESD51-6 (moving air)
Junction-to-ambient thermal resistance, 2.0 m/sec air flow per JEDEC JESD51-6 (moving air)
Junction-to-board thermal resistance, 1.0 m/sec air flow per JEDEC JESD51-8 (moving air)
Junction-to-case thermal resistance (die-to-heat sink) per MIL-Std 883, Method 1012.1
Junction-to-top-of-package characterization parameter, 0 m/sec air flow per JEDEC JESD51-2 (still air)
The AD9549 is specified for a case temperature (TCASE). To ensure
that TCASE is not exceeded, an airflow source can be used.
Use the following equation to determine the junction temperature on the application PCB:
TJ = TCASE + (ΨJT × PD)
Value
25.2
22.0
19.8
13.9
1.7
0.1
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Values of θJA are provided for package comparison and PCB
design considerations. θJA can be used for a first-order
approximation of TJ by the equation
TJ = TA + (θJA × PD)
where TA is the ambient temperature (°C).
where:
TJ is the junction temperature (°C).
TCASE is the case temperature (°C) measured by customer at top
center of package.
ΨJT is the value from Table 9.
PD is the power dissipation (see the Total Power Dissipation
parameter in the Specifications section).
Values of θJC are provided for package comparison and PCB
design considerations when an external heat sink is required.
Values of θJB are provided for package comparison and PCB
design considerations.
The values in Table 9 apply to both 64-lead package options.
Rev. D | Page 41 of 76
AD9549
POWER-UP
POWER-ON RESET
On initial power-up, it is recommended that the user apply a
RESET pulse, at least 75 ns in duration, on Pin 59 after both of
the following two conditions are met:
•
•
The 3.3 V supply is greater than 2.35 V ± 0.1 V.
The 1.8 V supply is greater than 1.4 V ± 0.05 V.
The high-to-low transition of the RESET pulse is the active
edge of the pulse and therefore the user is afforded the option
of holding RESET high during power–up.
Less than 1 ns after RESET goes high, the S1 to S4 configuration
pins go high impedance and remain high impedance until RESET
is deactivated. This allows strapping and configuration during
RESET.
Because of this reset sequence, external power supply sequencing is not critical.
Use the following sequence when changing frequencies in the
AD9549:
1.
2.
3.
4.
5.
6.
Note the following:
•
PROGRAMMING SEQUENCE
The following sequence should be used when initializing the
AD9549:
•
1.
•
2.
3.
4.
Apply power. After the power supplies reach a threshold and
stabilize, it is recommended that an active high pulse be
asserted on the RESET pin (Pin 59), initiating a hard reset.
It is important to be sure that the desired configuration
registers have single-tone mode set (Register 0x0100, Bit 5)
and that the close loop bit (Register 0x0100[0]) is cleared.
If the close loop bit is set on initial loading, the AD9549
attempts to lock the loop before it has been configured.
When the registered are loaded, the OOL (out of limits)
and LOR (loss of reference) can be monitored to ensure
that a valid reference signal is present on REFA or REFB.
If a valid reference is present, Register 0x0100 can be
reprogrammed to clear single-tone mode and lock the loop.
Automatic holdover mode can then be used to make the
AD9549 immune to any disturbance on the reference inputs.
Open the loop and enter single-tone mode via
Register 0x0100.
Enter the new register settings.
Write 0x1E to Register 0x0012.
When the registers are loaded, the OOL (out of limits) and
LOR (loss of reference) can be monitored to ensure that
a valid reference signal is present on REFA or REFB.
If a valid reference is present, Register 0x0100 can be reprogrammed to clear single-tone mode and lock the loop.
Automatic holdover mode can then be used to make the
AD9549 immune to any disturbance on the reference
inputs.
Rev. D | Page 42 of 76
Attempting to lock the loop without a valid reference can
put the AD9549 into a state that requires a reset, or at a
minimum, writing 0xFF to Register 0x0012.
Automatic holdover mode is not available unless the loop
has been successfully closed.
If the user desires to open and close the loop manually, it is
recommended that 0x1E to be written to Register 0x0012
prior to closing the loop again.
AD9549
POWER SUPPLY PARTITIONING
The AD9549 features multiple power supplies, and their power
consumption varies with its configuration. This section covers
which power supplies can be grouped together and how the
consumption of each power block varies with frequency.
1.8 V SUPPLIES
DVDD (Pin 3, Pin 5, Pin 7)
The recommendations here are for typical applications, and for
these applications, there are four groups of power supplies:
3.3 V digital, 3.3 V analog, 1.8 V digital, and 1.8 V analog.
These pins should be grouped together and isolated from the
1.8 V AVDD supplies. For most applications, a ferrite bead
provides sufficient isolation, but a separate regulator may be
necessary for applications demanding the highest performance.
The current consumption of this group increases from about
160 mA at a system clock of 700 MHz to about 205 mA at a
system clock of 1 GHz. There is also a slight (~5%) increase as
fOUT increases from 50 MHz to 400 MHz.
Applications demanding the highest performance may require
additional power supply isolation.
AVDD (Pin 11, Pin 19, Pin 23, Pin 24, Pin 36, Pin 42, Pin 44,
and Pin 45)
Note that all power supply pins must receive power regardless of
whether that block is used.
These pins can be grouped together and should be isolated from
other 1.8 V supplies. A separate regulator is recommended. At a
minimum, a ferrite bead should be used for isolation.
The numbers quoted here are for comparison only. Refer to the
Specifications section for exact numbers. With each group, use
bypass capacitors of 1 μF in parallel with a 10 μF.
3.3 V SUPPLIES
AVDD (Pin 53)
DVDD_I/O (Pin 1) and AVDD3 (Pin 14)
Although one of these pins is analog and the other is digital,
these two 3.3 V supplies can be grouped together. The power
consumption on Pin 1 varies dynamically with serial port activity.
AVDD3 (Pin 37)
Pin 37 is the CMOS driver supply. It can be either 1.8 V or 3.3 V,
and its power consumption is a function of the output frequency
and loading of OUT_CMOS (Pin 38).
If the CMOS driver is used at 3.3 V, this supply should be isolated
from other 3.3 V supplies with a ferrite bead to avoid a spur at
the output frequency. If the HSTL driver is not used, AVDD3
(Pin 37) can be connected (using a ferrite bead) to AVDD3
(Pin 46, Pin 47, Pin 49). If the HSTL driver is used, connect
AVDD3 (Pin 37) to Pin 1 and Pin 14, using a ferrite bead.
If the CMOS driver is used at 1.8 V, AVDD3 (Pin 37) can be
connected to AVDD (Pin 36).
If the CMOS driver is not used, AVDD3 (Pin 37) can be tied
directly to the 1.8 V AVDD (Pin 36) and the CMOS driver
powered down using Register 0x0010.
AVDD3 (Pin 46, Pin 47, Pin 49)
These are 3.3 V DAC power supplies that typically consume
about 25 mA. At a minimum, a ferrite bead should be used to
isolate these from other 3.3 V supplies, with a separate regulator
being ideal.
This 1.8 V supply consumes about 40 mA. The supply can be
run off the same regulator as 1.8 V AVDD group, with a ferrite
bead to isolate Pin 53 from the rest of the 1.8 V AVDD group.
However, for applications demanding the highest performance,
a separate regulator is recommended.
AVDD (Pin 25, Pin 26, Pin 29, Pin 30)
These system clock PLL power pins should be grouped together
and isolated from other 1.8 V AVDD supplies.
At a minimum, it is recommended that Pin 25 and Pin 30 be
tied together and isolated from the aggregate AVDD 1.8 V supply
with a ferrite bead. Likewise, Pin 26 and Pin 29 can also be tied
together, with a ferrite bead isolating them from the same aggregate
1.8 V supply. The loop filter for the system clock PLL should
directly connect to Pin 26 and Pin 29 (see Figure 44).
Applications demanding the highest performance may require
that these four pins be powered by their own LDO.
If the system clock PLL is bypassed, the loop filter pin (Pin 31)
should be pulled down to analog ground using a 1 kΩ resistor.
Pin 25, Pin 26, Pin 29, and Pin 30 should be included in the large
1.8 V AVDD power supply group. In this mode, isolation of these
pins is not critical, and these pins consume almost no power.
Rev. D | Page 43 of 76
AD9549
SERIAL CONTROL PORT
The AD9549 serial control port is a flexible, synchronous, serial
communications port that allows an easy interface with many
industry-standard microcontrollers and microprocessors. Single
or multiple byte transfers are supported, as well as MSB first or
LSB first transfer formats. The AD9549 serial control port can
be configured for a single bidirectional I/O pin (SDIO only) or
for two unidirectional I/O pins (SDIO/SDO).
Note that many serial port operations (such as the frequency
tuning word update) depend on presence of the DAC system clock.
SERIAL CONTROL PORT PIN DESCRIPTIONS
SCLK (serial clock) is the serial shift clock. This pin is an input.
SCLK is used to synchronize serial control port reads and writes.
Write data bits are registered on the rising edge of this clock,
and read data bits are registered on the falling edge. This pin is
internally pulled down by a 30 kΩ resistor to ground.
The SDIO pin (serial data input/output) is a dual-purpose pin
that acts as input only or as input/output. The AD9549 defaults
to bidirectional pins for I/O. Alternatively, SDIO can be used
as a unidirectional I/O pin by writing to the SDO active bit
(Register 0x0000, Bit 0 = 1). In this case, SDIO is the input, and
SDO is the output.
The SDO (serial data out) pin is used only in the unidirectional
I/O mode (Register 0x0000, Bit 0 = 1) as a separate output pin for
reading back data. Bidirectional I/O mode (using SDIO as both
input and output) is active by default (the SDO active bit in
Register 0x0000, Bit 0 = 0).
The CSB (chip select bar) pin is an active low control that gates
the read and write cycles. When CSB is high, SDO and SDIO
are in a high impedance state. This pin is internally pulled up by
a 100 kΩ resistor to 3.3 V. It should not be left floating. See the
Operation of Serial Control Port section on the use of the CSB
pin in a communication cycle.
SDIO (PIN 63)
SDO (PIN 62)
CSB (PIN 61)
AD9549
SERIAL
CONTROL
PORT
06744-051
SCLK (PIN 64)
Figure 51. Serial Control Port
OPERATION OF SERIAL CONTROL PORT
Framing a Communication Cycle with CSB
A communication cycle (a write or a read operation) is gated by
the CSB line. CSB must be brought low to initiate a communication cycle.
CSB stall high is supported in modes where three or fewer bytes
of data (plus instruction data) are transferred ([W1:W0] must
be set to 00, 01, or 10; see Table 10). In these modes, CSB can
temporarily return high on any byte boundary, allowing time
for the system controller to process the next byte. CSB can go
high on byte boundaries only and can go high during either
part (instruction or data) of the transfer. During this period, the
serial control port state machine enters a wait state until all data
has been sent. If the system controller decides to abort the transfer
before all of the data is sent, the state machine must be reset by
either completing the remaining transfer or by returning the CSB
low for at least one complete SCLK cycle (but fewer than eight
SCLK cycles). Raising the CSB on a non-byte boundary terminates
the serial transfer and flushes the buffer.
In the streaming mode ([W1:W0] = 11), any number of data
bytes can be transferred in a continuous stream. The register
address is automatically incremented or decremented (see the
MSB/LSB First Transfers section). CSB must be raised at the end
of the last byte to be transferred, thereby ending the stream
mode.
Communication Cycle—Instruction Plus Data
There are two parts to a communication cycle with the AD9549.
The first part writes a 16-bit instruction word into the AD9549,
coincident with the first 16 SCLK rising edges. The instruction
word provides the AD9549 serial control port with information
regarding the data transfer, which is the second part of the communication cycle. The instruction word defines whether the upcoming
data transfer is a read or a write, the number of bytes in the data
transfer, and the starting register address for the first byte of the
data transfer.
Write
If the instruction word is for a write operation (I15 = 0), the
second part is the transfer of data into the serial control port
buffer of the AD9549. The length of the transfer (1, 2, 3 bytes,
or streaming mode) is indicated by two bits ([W1:W0]) in the
instruction byte. The length of the transfer indicated by [W1:W0]
does not include the 2-byte instruction. CSB can be raised after
each sequence of eight bits to stall the bus (except after the last
byte, where it ends the cycle). When the bus is stalled, the serial
transfer resumes when CSB is lowered. Stalling on nonbyte
boundaries resets the serial control port.
There are three types of registers on the AD9549: buffered, live,
and read-only. Buffered (also referred to as mirrored) registers
require an I/O update to transfer the new values from a temporary
buffer on the chip to the actual register and are marked with an M
in the Type column of the register map. Toggling the IO_UPDATE
pin or writing a 1 to the register update bit (Register 0x0005, Bit 0)
causes the update to occur. Because any number of bytes of data
can be changed before issuing an update command, the update
simultaneously enables all register changes occurring since any
previous update. Live registers do not require I/O update and
update immediately after being written. Read-only registers
ignore write commands and are marked RO in the Type column
of the register map. An AC in this column indicates that the
register is autoclearing.
Rev. D | Page 44 of 76
AD9549
Read
If the instruction word is for a read operation (I15 = 1), the next
N × 8 SCLK cycles clock out the data from the address specified
in the instruction word, where N is 1, 2, 3, 4, as determined by
[W1:W0]. In this case, 4 is used for streaming mode where four
or more words are transferred per read. The data readback is
valid on the falling edge of SCLK.
The default mode of the AD9549 serial control port is bidirectional mode, and the data readback appears on the SDIO pin. It
is possible to set the AD9549 to unidirectional mode by writing
to the SDO active bit at Register 0x0000[7] = 0; in that mode,
the requested data appears on the SDO pin.
SDO
CSB
SERIAL
CONTROL
PORT
UPDATE
REGISTERS
TOGGLE
IO_UPDATE
PIN
AD9549
CORE
06744-052
SDIO
CONTROL REGISTERS
SCLK
REGISTER BUFFERS
By default, a read request reads the register value that is currently
in use by the AD9549. However, setting Register 0x0004[0] = 1
causes the buffered registers to be read instead. The buffered
registers are the ones that take effect during the next I/O update.
Figure 52. Relationship Between Serial Control Port Register Buffers and
Control Registers of the AD9549
The AD9549 uses Register 0x0000 to Register 0x0509. Although
the AD9549 serial control port allows both 8-bit and 16-bit
instructions, the 8-bit instruction mode provides access to only
five address bits ([A4:A0]), which restricts its use to Address
Space 0x0000 to Address Space 0x0031. The AD9549 defaults
to 16-bit instruction mode on power-up, and 8-bit instruction
mode is not supported.
THE INSTRUCTION WORD (16 BITS)
The MSB of the instruction word is R/W, which indicates whether
the instruction is a read or a write. The next two bits, [W1:W0],
are the transfer length in bytes. The final 13 bits are the address
([A12:A0]) at which to begin the read or write operation.
For a write, the instruction word is followed by the number of
bytes of data indicated by Bits[W1:W0], which is interpreted
according to Table 10.
Bits[A12:A0] select the address within the register map that is
written to or read from during the data transfer portion of the
communications cycle. The AD9549 uses all of the 13-bit address
space. For multibyte transfers, this address is the starting byte
address.
Table 10. Byte Transfer Count
W1
0
0
1
1
W0
0
1
0
1
Bytes to Transfer
(Excluding the 2-Byte Instruction)
1
2
3
Streaming mode
MSB/LSB FIRST TRANSFERS
The AD9549 instruction word and byte data may be MSB first
or LSB first. The default for the AD9549 is MSB first. The LSB
first mode can be set by writing a 1 to Register 0x0000[6] and
requires that an I/O update be executed. Immediately after the
LSB first bit is set, all serial control port operations are changed
to LSB first order.
When MSB first mode is active, the instruction and data bytes
must be written from MSB to LSB. Multibyte data transfers in
MSB first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent
data bytes must follow in order from high address to low address.
In MSB first mode, the serial control port internal address
generator decrements for each data byte of the multibyte
transfer cycle.
When LSB first = 1 (LSB first), the instruction and data bytes
must be written from LSB to MSB. Multibyte data transfers in
LSB first format start with an instruction byte that includes the
register address of the least significant data byte followed by
multiple data bytes. The serial control port internal byte address
generator increments for each byte of the multibyte transfer cycle.
The AD9549 serial control port register address decrements
from the register address just written toward 0x0000 for multibyte I/O operations if the MSB first mode is active (default).
If the LSB first mode is active, the serial control port register
address increments from the address just written toward 0x1FFF
for multibyte I/O operations.
Unused addresses are not skipped during multibyte I/O operations.
The user should write the default value to a reserved register and
should write only 0s to unmapped registers. Note that it is more
efficient to issue a new write command than to write the default
value to more than two consecutive reserved (or unmapped)
registers.
Rev. D | Page 45 of 76
AD9549
Table 11. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB
I15
R/W
I14
W1
I13
W0
I12
A12
I11
A11
I10
A10
I9
A9
I8
A8
I7
A7
I6
A6
I5
A5
I4
A4
I3
A3
I2
A2
LSB
I0
A0
I1
A1
CSB
SCLK DON'T CARE
SDIO DON'T CARE
R/W W1 W0 A12 A11 A10 A9
A8
A7
A6 A5
A4 A3 A2
A1 A0
D7 D6 D5
16-BIT INSTRUCTION HEADER
D4 D3
D2 D1
D0
D7
REGISTER (N) DATA
D6 D5
D4 D3 D2
D1 D0
DON'T CARE
REGISTER (N – 1) DATA
06744-053
DON'T CARE
Figure 53. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes Data
CS
SCLK
DON'T CARE
SDIO
DON'T CARE
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
SDO DON'T CARE
REGISTER (N) DATA
REGISTER (N – 1) DATA
REGISTER (N – 2) DATA
REGISTER (N – 3) DATA
DON'T
CARE
06744-060
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
16-BIT INSTRUCTION HEADER
Figure 54. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes Data
tDS
tHI
tS
tDH
DON'T CARE
SDIO
DON'T CARE
DON'T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
A6
A5
D4
D3
D2
D1
D0
DON'T CARE
06744-055
SCLK
tH
tCLK
tLO
CSB
Figure 55. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements
CSB
SCLK
DATA BIT N
06744-056
tDV
SDIO
SDO
DATA BIT N – 1
Figure 56. Timing Diagram for Serial Control Port Register Read
CSB
SCLK DON'T CARE
A0 A1 A2 A3
A4
A5 A6
A7
A8
A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4
16-BIT INSTRUCTION HEADER
D5 D6
REGISTER (N) DATA
D7
D0
D1 D2
D6
REGISTER (N + 1) DATA
Figure 57. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes Data
Rev. D | Page 46 of 76
D3 D4 D5
D7
DON'T CARE
06744-057
SDIO DON'T CARE
DON'T CARE
AD9549
tH
tS
CSB
tCLK
tHI
SCLK
tLO
tDS
SDIO
BIT N
BIT N + 1
Figure 58. Serial Control Port Timing—Write
Table 12. Definitions of Terms Used in Serial Control Port Timing Diagrams
Parameter
tCLK
tDV
tDS
tDH
tS
tH
tHI
tLO
Description
Period of SCLK
Read data valid time (time from falling edge of SCLK to valid data on SDIO/SDO)
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Rev. D | Page 47 of 76
06744-058
tDH
AD9549
I/O REGISTER MAP
All address and bit locations that are left blank in Table 13 are unused. Accessing reserved registers should be avoided. In cases where
some of the bits in register are reserved, the user can rely on the default value in the I/O register map and write the same value back to the
reserved bits in that register.
Table 13.
Addr
Bit 7
Bit 6
Type1 Name
(Hex)
Serial port configuration and part identification
0x0000
Serial
SDO
LSB first
config.
active
(buffered)
0x0001
Reserved
0x0002
RO
Part ID
0x0003
RO
0x0004
Serial
options
0x0005
AC
Power-down and reset
0x0010
Powerdown and
enable
0x0011
Reserved
0x0012
M, AC Reset
0x0013
M
System clock
0x0020
0x0023
PFD
divider
PLL
control
0x0101
0x0102
0x0103
R-divider
0x0104
0x0105
0x0106
S-divider
0x0107
History
reset
Soft
reset
Long
inst.
Long
inst.
Reserved
Part ID
BIt 2
Bit 1
Bit 0
Default
(Hex)
Soft reset
LSB first
(buffered)
SDO active
0x18
Read buffer
register
Register
update
Enable
output
doubler
PD
SYSCLK
PLL
IRQ
reset
FPFD
reset
PD REFA
Reserved
CPFD
reset
S-div/2
reset
Reserved
2×
reference
VCO auto
range
Singletone
mode
Disable
freq.
estimator
Enable
freq.
slew
limiter
R-divider, Bits[15:0]
Digital PD
0x00
LF reset
CCI reset
DDS reset
0x00
R-div/2
reset
S-divider
reset
R-divider
reset
0x00
VCO range
0x12
Charge pump current,
Bits[1:0]
Reserved
Loop
polarity
Reserved
Reserved
P-divider
P-divider, Bits[4:0]
Rev. D | Page 48 of 76
0x04
0x05
Close loop
0x30
R-divider/2
0x00
0x00
0x00
S-divider/2
0x00
0x00
0x00
S-divider, Bits[15:0]
Falling
edge
triggered
0x00
Full PD
PFD divider, Bits[3:0]
(relationship between SYSCLK and PFD clock)
Reserved
0x82
0x09
0x00
PD REFB
N-divider, Bits[4:0]
Falling
edge
triggered
M
Bit 3
N-divider
Reserved
PLL
parameters
M
Enable
CMOS
driver
Bit 4
PD fund
DDS
0x0021
0x0022
DPLL
0x0100
PD HSTL
driver
Bit 5
0x05
AD9549
Addr
(Hex)
Type1
0x0108
M
0x0109
M
0x010A
M
0x010B
M
0x010C
M
0x010D
M
0x010E
M
0x010F
M
0x0110
M
0x0111
M
0x0112
0x0113
0x0114
0x0115
RO
0x0116
RO
0x0117
RO
0x0118
RO
0x0119
RO
0x011A
RO
0x011B
M
0x011C
M
0x011D
M
0x011E
M
0x011F
M
0x0120
M
0x0121
M
0x0122
M
0x0123
M
0x0124
M
0x0125
M
0x0126
M
0x0127
M
0x0128
M
0x0129
M
0x012A
M
0x012B
M
0x012C
M
0x012D
0x012E
0x012F
0x0130
Free-run mode
0x01A0
0x01A1
0x01A2
0x01A3
0x01A4
0x01A5
Name
Loop
coefficients
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Alpha-0, Bits[7:0]
BIt 2
Bit 1
Bit 0
Alpha-0, Bits[11:8]
Alpha-1, Bits[4:0]
Alpha-2, Bits[2:0]
Beta-0, Bits[7:0]
Beta-0, Bits[11:8]
Beta-1, Bits[2:0]
Gamma-0, Bits[7:0]
Gamma-0, Bits[11:8]
Gamma-1, Bits[2:0]
Reserved
FTW
estimate
FTW limits
FTW estimate, Bits[47:0]
(read only)
LSB: Register 0x0115
FTW lower limit, Bits[47:0]
LSB: Register 0x011B
FTW upper limit, Bits[47:0]
LSB: Register 0x0121
Slew limit
Frequency slew limit, Bits[47:0]
LSB: Register 0x0127
Reserved
Reserved
Reserved
Reserved
Rev. D | Page 49 of 76
Default
(Hex)
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
N/A
N/A
N/A
N/A
N/A
N/A
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0xFF
0xFF
0xFF
0x7F
0x00
0x00
0x00
0x00
0x00
0x00
AD9549
Addr
(Hex)
0x01A6
0x01A7
0x01A8
0x01A9
0x01AA
Type1
M
M
M
M
M
0x01AB
M
Name
FTW0
(open-loop
frequency
tuning
word)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
BIt 2
FTW0, Bits[47:0]
LSB: Register 0x01A6
Bit 1
Bit 0
0x01AC
M
Phase
and
(open loop
0x01AD
only)
Reference selector/holdover
0x01C0
M
Automatic
control
DDS phase word, Bits[15:0]
Holdover
mode
Reserved
0x01C1
Enable
line card
mode
Enable
REF_AB
Enable
Holdover
ref input
holdover
on/off
override
override
FTW windowed average size, Bits[3:0]
M
Override
0x01C2
Averaging
window
0x01C3
Reference
validation
Reserved
Doubler and output drivers
0x0200
HSTL
driver
0x0201
RO
0x0301
RO
0x0302
RO
0x0303
RO
Status
Reserved
Reserved
IRQ status
PFD freq.
too high
REFA
valid
PFD freq.
too high
REFA
valid
IRQ mask
0x0306
Reserved
0x0307
Reserved
0x0309
0x030A
0x030B
0x030C
Automatic
recover
PFD freq.
too low
REFA
LOR
PFD
freq. too
low
REFA
LOR
Reserved
S1 pin
config
S2 pin
config
S3 pin
config
S4 pin
config
Control
REF?
REF? LOR
REF?
REF? LOR
REF?
REF? LOR
REF?
REF? LOR
Enable
REFA LOR
Enable
REFA OOL
REFA
valid
REFB
valid
REF?
OOL
REF?
OOL
REF?
OOL
REF?
OOL
Enable
REFB
LOR
0x00
0x00
Reserved
0x05
Ref
selected
Freq. est.
done
Ref
selected
HSTL output doubler,
Bits[1:0]
CMOS mux
0x00
Ph. lock
detected
REFB LOR
Freq. lock
detected
REFB OOL
N/A
Free run
Phase lock
detected
Freq. lock
detected
0x00
REFB valid
REFB LOR
REFB OOL
0x00
Ref
changed
Leave
free run
Freq.
Unlock
REFA OOL
Enter
free run
Freq. lock
0x00
0x00
!REFA OOL
0x00
REFB OOL
!REFB OOL
0x00
Freq. lock
Reserved
IRQ
0x60
Freq. lock
Reserved
IRQ
0xE0
Freq. lock
Reserved
IRQ
0x08
Freq. lock
Reserved
IRQ
0x01
Enable
phase
lock det.
Enable
frequency
lock det.
0xA2
Free run
REFB valid
REFA OOL
Rev. D | Page 50 of 76
0x00
0x00
Freq. est.
done
REFA OOL
Freq. est.
done
!REFA
valid
!REFB
valid
REF? not
valid
REF? not
valid
REF? not
valid
REF? not
valid
Enable
REFB OOL
Automatic
holdover
Validation timer, Bits[4:0]
OPOL
(polarity)
0x0305
0x0308
0x00
CMOS
driver
Monitor
0x0300
0x0304
Automatic
selector
Default
(Hex)
0x00
0x00
0x00
0x00
Startup
cond.
Startup
cond.
Phase
unlock
REFA
LOR
REFB
LOR
Phase
lock
Phase
lock
Phase
lock
Phase
lock
Phase lock
!REFA LOR
!REFB LOR
N/A
AD9549
Addr
(Hex)
0x030E
0x030F
0x0310
0x0311
0x0312
0x0313
0x0314
0x0315
0x0316
0x0317
0x0318
Type1
RO
RO
RO
RO
RO
RO
M
M
M
M
M
Name
HFTW
0x0319
0x031A
0x031B
0x031C
0x031D
M
M
M
M
M
Frequency
lock
0x031E
0x031F
0x0320
0x0321
0x0322
0x0323
0x0324
0x0325
0x0326
0x0327
0x0328
0x0329
0x032A
0x032B
0x032C
0x032D
0x032E
0x032F
0x0330
0x0331
0x0332
0x0333
0x0334
0x0335
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
Loss of
reference
Phase lock
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
BIt 2
Bit 1
Average or instantaneous FTW, Bits[47:0]
(read only)
LSB: Register 0x030E
(An I/O update is required to refresh these registers.)
Phase lock detect threshold, Bits[31:0]
Phase unlock watchdog timer,
Phase lock watchdog timer, Bits[4:0]
Bits[2:0]
Frequency lock detect threshold, Bits[31:0]
Frequency unlock watchdog timer,
Bits[2:0]
Frequency lock watchdog timer, Bits[4:0]
REFA LOR divider, Bits[15:0]
REFB LOR divider, Bits[15:0]
Reference
out of
limits
REFA OOL divider, Bits[15:0]
REFA OOL upper limit, Bits[31:0]
REFA OOL lower limit, Bits[31:0]
REFB OOL divider, Bits[15:0]
REFB OOL upper limit, Bits[31:0]
REFB OOL lower limit, Bits[31:0]
Rev. D | Page 51 of 76
Bit 0
Default
(Hex)
N/A
N/A
N/A
N/A
N/A
N/A
0xFF
0x00
0x00
0x00
0xFF
0x00
0x00
0x00
0x00
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
AD9549
Addr
Bit 7
(Hex)
Type1 Name
Calibration (user-accessible trim)
0x0400
K-divider
0x0401
0x0402
M
CPFD gain
0x0403
M
0x0404
FPFD gain
0x0405
Reserved
0x0406
RO
Part
Part
version
version
0x0407
Reserved
0x0408
0x0409
M
PFD offset
0x040A
M
0x040B
DAC
full-scale
0x040C
current
Reserved
Reserved
Reference
bias level
0x0410
Reserved
Harmonic spur reduction
0x0500
M
Spur A
Bit 6
Bit 5
Bit 4
M
M
M
M
0x0505
M
0x0506
0x0507
0x0508
0x0509
M
M
M
M
1
BIt 2
Bit 1
Bit 0
K-divider, Bits[15:0]
Part
version
CPFD gain scale, Bits[2:0]
CPFD gain, Bits[5:0]
FPFD gain, Bits[7:0]
Reserved
Reserved
DPLL phase offset, Bits[7:0]
DPLL phase offset, Bits[13:8]
DAC full-scale current, Bits[7:0]
0x01
0x00
0x00
0x20
0xC8
0x00 or
0x40
0x00
0x00
0xFF
DAC full-scale current,
Bits[9:8]
Reserved
Reserved
DC input level, Bits[1:0]
0x01
0x10
0x00
Reserved
HSR-A
enable
Amplitude
gain × 2
Reserved
Spur A harmonic, Bits[3:0]
0x00
Spur A magnitude, Bits[7:0]
Spur A phase, Bits[7:0]
Spur A
phase,
Bit 8
Spur B
Default
(Hex)
Reserved
0x040D
0x040E
0x040F
0x0501
0x0502
0x0503
0x0504
Bit 3
HSR-B
enable
Amplitude
gain × 2
Reserved
Spur B harmonic[3:0]
0x00
Spur B magnitude, Bits[7:0]
Spur B phase, Bits[7:0]
Spur B
phase,
Bit 8
Types of registers: RO = read-only, AC = autoclear, M = mirrored (also called buffered). A mirrored register needs an I/O update for the new value to take effect.
Rev. D | Page 52 of 76
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
AD9549
I/O REGISTER DESCRIPTIONS
SERIAL PORT CONFIGURATION (REGISTER 0x0000 TO REGISTER 0x0005)
Register 0x0000—Serial Configuration
Table 14.
Bits
[7:4]
3
2
Bit Name
1
LSB first
0
SDO active
Long instruction
Soft reset
Description
These bits are the mirror image of Bits[3:0].
Read-only. The AD9549 supports only long instructions.
Resets register map, except for Register 0x0000. Setting this bit forces a soft reset, meaning that S1 to S4
are not tristated, nor is their state read when this bit is cleared. The AD9549 assumes the values of S1 to S4
that were present during the last hard reset. This bit is not self-clearing, and all other registers are restored
to their default values after a soft reset.
Sets bit order for serial port.
1 = LSB first.
0 = MSB first. I/O update must occur for MSB first to take effect.
Enables SDO pin.
1 = SDO pin enabled (4-wire serial port mode).
0 = 3-wire mode.
Register 0x0001—Reserved
Register 0x0002 and Register 0x0003—Part ID (Read Only)
Register 0x0004—Serial Options
Table 15.
Bits
0
Bit Name
Read buffer register
Description
For buffered registers, serial port readback reads from actual (active) registers instead of the buffer.
1 = reads the buffered values that take effect during the next I/O update.
0 = reads values that are currently in effect.
Register 0x0005—Serial Options (Self-Clearing)
Table 16.
Bits
0
Bit Name
Register update
Description
Software access to the register update pin function. Writing a 1 to this bit is identical to performing an I/O
update.
POWER-DOWN AND RESET (REGISTER 0x0010 TO REGISTER 0x0013)
Register 0x0010—Power-Down and Enable
Power-up default is defined by the startup pins.
Table 17.
Bits
7
Bit Name
PD HSTL driver
6
Enable CMOS driver
5
4
Enable output doubler
PD SYSCLK PLL
3
2
1
PD REFA
PD REFB
Full PD
0
Digital PD
Description
Power down HSTL output driver.
1 = HSTL driver powered down.
Power up CMOS output driver.
1 = CMOS driver on.
Power up output clock generator doubler. Output doubler must still be enabled in Register 0200.
System clock multiplier power-down.
1 = system clock multiplier powered down.
Power-down reference clock A input (and related circuits).
Power-down reference clock B input (and related circuits).
Setting this bit is identical to activating the PD pin and puts all blocks (except serial port) into power-down
mode. SYSCLK is turned off.
Remove clock from most of digital section; leave serial port usable. In contrast to full PD, setting this bit
does not debias inputs, allowing for quick wake-up.
Rev. D | Page 53 of 76
AD9549
Register 0x0011—Reserved
Register 0x0012—Reset (Autoclear)
To reset the entire chip, the user can also use the (nonself-clearing) soft reset bit in Register 0x0000. Except for IRQ reset, the user normally
would not need to use this bit. However, if the user attempts to lock the loop for the first time when no signal is present, the user should
write 1 to Bits[4:0] of this register before attempting to lock the loop again.
Table 18.
Bits
7
6
5
4
3
2
1
0
Bit Name
History reset
Reserved
IRQ reset
FPFD reset
CPFD reset
LF reset
CCI reset
DDS reset
Description
Setting this bit clears the FTW monitor and pipeline.
Reserved.
Clear IRQ signal and IRQ status monitor.
Fine phase frequency detector reset.
Coarse phase frequency detector reset.
Loop filter reset.
Cascaded comb integrator reset.
Direct digital synthesis reset.
Register 0x0013—Reset (Continued) (Not Autoclear)
Table 19.
Bits
7
Bit Name
PD fund DDS
3
2
1
0
S-div/2 reset
R-div/2 reset
S-divider reset
R-divider reset
Description
Setting this bit powers down the DDS fundamental output but does not power down the spurs. It is used
during tuning of the spur killer circuit.
Asynchronous reset for S prescaler.
Asynchronous reset for R prescaler.
Synchronous (to S-divider prescaler output) reset for integer divider.
Synchronous (to R-divider prescaler output) reset for integer divider.
SYSTEM CLOCK (REGISTER 0x0020 TO REGISTER 0x0023)
Register 0x0020—N-Divider
Table 20.
Bits
[4:0]
Bit Name
N-divider
Description
These bits set the feedback divider for system clock PLL. There is a fixed/2 preceding this block, as well as
an offset of 2 added to this value. Therefore, setting this register to 00000 translates to an overall feedback
divider ratio of 4. See Figure 43.
Register 0x0021—Reserved
Register 0x0022—PLL Parameters
Table 21.
Bits
7
[6:4]
3
Bit Name
VCO auto range
Reserved
2× reference
2
VCO range
[1:0]
Charge pump current
Description
Automatic VCO range selection. Enabling this bit allows Bit 2 of this register to be set automatically.
Reserved
Enables a frequency doubler prior to the SYSCLK PLL and can be useful in reducing jitter induced by the
SYSCLK PLL. See Figure 42.
Select low range or high range VCO.
0 = low range (700 MHz to 810 MHz).
1 = high range (900 MHz to 1000 MHz). For system clock settings between 810 MHz and 900 MHz, use the
VCO Auto Range (Bit 7) to set the correct VCO range automatically.
Charge pump current.
00 = 250 μA.
01 = 375 μA.
10 = off.
11= 125 μA.
Rev. D | Page 54 of 76
AD9549
Register 0x0023—PFD Divider
Table 22.
Bits
[3:0]
Bit Name
PFD divider
Description
Divide ratio for PFD clock from system clock. This is typically varied only in cases where the designer wishes
to run the DPLL phase detector fast while SYSCLK is run relatively slowly. The ratio is equal to PFD
divider × 4. For a 1 GHz system clock, the ADC runs at 1 GHz/20 = 50 MHz, and the DPLL phase detector
runs at half this speed, which, in this case, is 25 MHz.
DIGITAL PLL CONTROL AND DIVIDERS (REGISTER 0x0100 TO REGISTER 0X0130)
Register 0x0100—PLL Control
Table 23.
Bits
[7:6]
5
Bit Name
Reserved
Single-tone mode
4
Disable frequency
estimator
3
Enable frequency slew
limiter
2
1
0
Reserved
Loop polarity
Close loop
Description
Reserved
Setting this bit allows the AD9549 to output a tone open loop using FTW0 as DDS tuning word. This bit
must be cleared when Bit 0 (close loop) is set. This is very useful in debugging when the signal coming
into the AD9549 is questionable or nonexistent.
The frequency estimator is normally not used but is useful when the input frequency is unknown or
needs to be qualified. This estimate appears in Register 0x0115 to Register 0x011A. The frequency
estimator is not needed when FTW0 (Register 0x01A6 to Register 0x01AB) is programmed. See the
Frequency Estimator section.
This bit enables the frequency slew limiter that controls how fast the tuning word can change and is
useful for avoiding runt and stretched pulses during clock switchover and holdover transitions. These
values are set in Register 0x0127 to Register 0x012C. See the Frequency Slew Limiter section.
Reserved.
This bit reverses the polarity of the loop response.
Setting this bit closes the loop. If Bit 4 of this register is cleared, the frequency estimator is used. If this
bit is cleared and the loop is opened, reset the CCI and LF bits of Register 0x0012 before closing the
loop again. A valid input reference signal must be present the first time the loop is closed. If no input
signal is present during the first time the loop is closed, the user must reset the digital PLL blocks by
writing 0xFF to Register 0x0012 before attempting to close the loop again.
Register 0x0101—R-Divider (DPLL Feedforward Divider)
Table 24.
Bits
[7:0]
Bit Name
R-divider
Description
Feedforward divider (also called the reference divider) of the DPLL. Divide ratio = 1 − 65,536. See the
Feedforward Divider (Divide-by-R) section. If the desired feedforward ratio is greater than 65,536, or if
the reference input signal on REFA or REFB is greater than 400 MHz, Bit 0 of Register 0x0103 must be
set. Note that the actual R-divider is the value in this register plus 1; to have an R-divider of 1, Register
0x0101 and Register 0x0102 must both be 0x00. Register 0x0101 is the least significant byte.
Register 0x0102—R-Divider (DPLL Feedforward Divider) (Continued)
Table 25.
Bits
[15:8]
Bit Name
R-divider
Description
Feedforward divider (also called the reference divider) of the DPLL. Divide ratio = 1 − 65,536. See the
Feedforward Divider (Divide-by-R) section. If the desired feedforward ratio is greater than 65,536, or if
the reference input signal on REFA or REFB is greater than 400 MHz, Bit 0 of Register 0x0103 must be
set. Note that the actual R-divider is the value in this register plus 1; to have an R-divider of 1, Register
0x0101 and Register 0x0102 must both be 0x00. Register 0x0101 is the least significant byte.
Register 0x0103—R-Divider (Continued)
Table 26.
Bits
7
[6:1]
0
Bit Name
Falling edge triggered
Reserved
R-divider/2
Description
Setting this bit inverts the reference clock before the R-divider.
Reserved.
Setting this bit enables an additional /2 prescaler, effectively doubling the range of the feedforward
divider. If the desired feedforward ratio is greater than 65,536, or if the reference input signal on REFA or
REFB is greater than 400 MHz, then this bit must be set.
Rev. D | Page 55 of 76
AD9549
Register 0x0104—S-Divider (DPLL Feedback Divider)
Table 27.
Bits
[7:0]
Bit Name
S-divider
Description
Feedback divider. Divide ratio = 1 − 65,536. If the desired feedback ratio is greater than 65,536, or if
the feedback signal on FDBK_IN is greater than 400 MHz, then Bit 0 of Register 0x0106 must be set.
Note that the actual S-divider is the value in this register plus 1, so to have an R-divider of 1,
Register 0x0104 and Register 0x0105 must both be 0x00. Register 0x0104 is the least significant byte.
Register 0x0105—S-Divider (DPLL Feedback Divider) (Continued)
Table 28.
Bits
[15:8]
Bit Name
S-divider
Description
Feedback divider. Divide ratio = 1 − 65,536. If the desired feedback ratio is greater than 65,536, or if
the feedback signal on FDBK_IN is greater than 400 MHz, then Bit 0 of Register 0x0106 must be set.
Note that the actual S-divider is the value in this register plus 1, so to have an R-divider of 1,
Register 0x0104 and Register 0x0105 must both be 0x00. Register 0x0104 is the least significant byte.
Register 0x0106—S-Divider (DPLL Feedback Divider) (Continued)
Table 29.
Bits
7
[6:1]
0
Bit Name
Falling edge triggered
Reserved
S-divider/2
Description
Setting this bit inverts the reference clock before S-divider.
Reserved.
Setting this bit enables an additional /2 prescaler. See the Feedback Divider (Divide-by-S) section.
If the desired feedback ratio is greater than 65,536, or if the feedback signal on FDBK_IN is greater
than 400 MHz, then this bit must be set. An example of this case is when the PLL is locking to an
image of the DAC output that is above the Nyquist frequency.
Register 0x0107—P-Divider
Table 30.
Bits
[4:0]
Bit Name
P-divider
Description
Divide ratio. Controls the ratio of DAC sample rate to loop filter sample rate. See the Digital Loop
Filter section. Loop filter sample rate = DAC sample rate/2^(divide ratio[4:0]). For the default case
of 1 GHz DAC sample rate, and P-divider[4:0] of 5, the loop filter sample rate is 31.25 MHz. Note that
the DAC sample rate is the same as system clock.
Register 0x0108—Loop Coefficients
See the Digital Loop Filter Coefficients section. Note that the AD9549 evaluation software derives these values.
Table 31.
Bits
[7:0]
Bit Name
Alpha-0
Description
Linear coefficient for alpha coefficient.
Register 0x0109—Loop Coefficients (Continued)
Table 32.
Bits
[11:8]
Bit Name
Alpha-0
Description
Linear coefficient for alpha coefficient.
Rev. D | Page 56 of 76
AD9549
Register 0x010A—Loop Coefficients (Continued)
Table 33.
Bits
[4:0]
Bit Name
Alpha-1
Description
Power-of-2 multiplier for alpha coefficient.
Register 0x010B—Loop Coefficients (Continued)
Table 34.
Bits
[2:0]
Bit Name
Alpha-2
Description
Power-of-2 divider for alpha coefficient.
Register 0x010C—Loop Coefficients (Continued)
Table 35.
Bits
[7:0]
Bit Name
Beta-0
Description
Linear coefficient for beta coefficient.
Register 0x010D—Loop Coefficients (Continued)
Table 36.
Bits
[11:8]
Bit Name
Beta-0
Description
Linear coefficient for beta coefficient.
Register 0x010E—Loop Coefficients (Continued)
Table 37.
Bits
[2:0]
Bit Name
Beta-1
Description
Power-of-2 divider for beta coefficient.
Register 0x010F—Loop Coefficients (Continued)
Table 38.
Bits
[7:0]
Bit Name
Gamma-0
Description
Linear coefficient for gamma coefficient.
Register 0x0110—Loop Coefficients (Continued)
Table 39.
Bits
[11:8]
Bit Name
Gamma-0
Description
Linear coefficient for gamma coefficient.
Register 0x0111—Loop Coefficients (Continued)
Table 40.
Bits
[2:0]
Bit Name
Gamma-1
Description
Power-of-2 divider for gamma coefficient.
Register 0x0112 to Register 0x0114—Reserved
Rev. D | Page 57 of 76
AD9549
Register 0x0115—FTW Estimate (Read Only)
Table 41.
Bit
[7:0]
Bit Name
FTW estimate
Description
This frequency estimate is from the frequency estimator circuit and is informational only. It is useful for
verifying the input reference frequency. See the Frequency Estimator section for a description.
Register 0x0116—FTW Estimate (Read Only) (Continued)
Table 42.
Bit
[15:8]
Bit Name
FTW estimate
Description
This frequency estimate is from the frequency estimator circuit and is informational only. It is useful for
verifying the input reference frequency. See the Frequency Estimator section for a description.
Register 0x0117—FTW Estimate (Read Only) (Continued)
Table 43.
Bit
[23:16]
Bit Name
FTW estimate
Description
This frequency estimate is from the frequency estimator circuit and is informational only. It is useful for
verifying the input reference frequency. See the Frequency Estimator section for a description.
Register 0x0118—FTW Estimate (Read Only) (Continued)
Table 44.
Bit
[31:24]
Bit Name
FTW estimate
Description
This frequency estimate is from the frequency estimator circuit and is informational only. It is useful for
verifying the input reference frequency. See the Frequency Estimator section for a description.
Register 0x0119—FTW Estimate (Read Only) (Continued)
Table 45.
Bit
[39:32]
Bit Name
FTW estimate
Description
This frequency estimate is from the frequency estimator circuit and is informational only. It is useful for
verifying the input reference frequency. See the Frequency Estimator section for a description.
Register 0x011A—FTW Estimate (Read Only) (Continued)
Table 46.
Bit
[47:40]
Bit Name
FTW estimate
Description
This frequency estimate is from the frequency estimator circuit and is informational only. It is useful for
verifying the input reference frequency. See the Frequency Estimator section for a description.
Rev. D | Page 58 of 76
AD9549
Register 0x011B—FTW Lower Limit
Table 47.
Bits
[7:0]
Bit Name
FTW lower limit
Description
Lowest DDS tuning word in closed-loop mode. This feature is recommended when a band-pass
reconstruction filter is used. See the Output Frequency Range Control section.
Register 0x011C—FTW Lower Limit (Continued)
Table 48.
Bits
[15:8]
Bit Name
FTW lower limit
Description
Lowest DDS tuning word in closed-loop mode. This feature is recommended when a band-pass
reconstruction filter is used. See the Output Frequency Range Control section.
Register 0x011D—FTW Lower Limit (Continued)
Table 49.
Bits
[23:16]
Bit Name
FTW lower limit
Description
Lowest DDS tuning word in closed-loop mode. This feature is recommended when a band-pass
reconstruction filter is used. See the Output Frequency Range Control section.
Register 0x011E—FTW Lower Limit (Continued)
Table 50.
Bits
[31:24]
Bit Name
FTW lower limit
Description
Lowest DDS tuning word in closed-loop mode. This feature is recommended when a band-pass
reconstruction filter is used. See the Output Frequency Range Control section.
Register 0x011F—FTW Lower Limit (Continued)
Table 51.
Bits
[39:32]
Bit Name
FTW lower limit
Description
Lowest DDS tuning word in closed-loop mode. This feature is recommended when a band-pass
reconstruction filter is used. See the Output Frequency Range Control section.
Register 0x0120—FTW Lower Limit (Continued)
Table 52.
Bits
[47:40]
Bit Name
FTW lower limit
Description
Lowest DDS tuning word in closed-loop mode. This feature is recommended when a band-pass
reconstruction filter is used. See the Output Frequency Range Control section.
Rev. D | Page 59 of 76
AD9549
Register 0x0121—FTW Upper Limit
Table 53.
Bits
[7:0]
Bit Name
FTW upper limit
Description
Highest DDS tuning word in closed- loop mode. This feature is recommended when a band-pass
reconstruction filter is used. See the Output Frequency Range Control section.
Register 0x0122—FTW Upper Limit (Continued)
Table 54.
Bits
[15:8]
Bit Name
FTW upper limit
Description
Highest DDS tuning word in closed- loop mode. This feature is recommended when a band-pass
reconstruction filter is used. See the Output Frequency Range Control section.
Register 0x0123—FTW Upper Limit (Continued)
Table 55.
Bits
[23:16]
Bit Name
FTW upper limit
Description
Highest DDS tuning word in closed- loop mode. This feature is recommended when a band-pass
reconstruction filter is used. See the Output Frequency Range Control section.
Register 0x0124—FTW Upper Limit (Continued)
Table 56.
Bits
[31:24]
Bit Name
FTW upper limit
Description
Highest DDS tuning word in closed- loop mode. This feature is recommended when a band-pass
reconstruction filter is used. See the Output Frequency Range Control section.
Register 0x0125—FTW Upper Limit (Continued)
Table 57.
Bits
[39:32]
Bit Name
FTW upper limit
Description
Highest DDS tuning word in closed- loop mode. This feature is recommended when a band-pass
reconstruction filter is used. See the Output Frequency Range Control section.
Register 0x0126—FTW Upper Limit (Continued)
Table 58.
Bits
[47:40]
Bit Name
FTW upper limit
Description
Highest DDS tuning word in closed- loop mode. This feature is recommended when a band-pass
reconstruction filter is used. See the Output Frequency Range Control section.
Register 0x0127 to Register 0x012C—Frequency Slew Limit
Table 59.
Bits
[47:0]
Bit Name
Frequency slew limit
Description
See the Frequency Slew Limiter section.
Register 0x012D to Register 0x0130—Reserved
Rev. D | Page 60 of 76
AD9549
FREE-RUN (SINGLE-TONE) MODE (REGISTER 0x01A0 TO REGISTER 0x01AD)
Register 0x01A0 to Register 0x01A5—Reserved
Register 0x01A6—FTW0 (Frequency Tuning Word)
Table 60.
Bit
[7:0]
Bit Name
FTW0
Description
FTW (frequency tuning word) for DDS when the loop is not closed (see Register 0x0100, Bit 0). Also used as
the initial frequency estimate when the estimator is disabled (see Register 0x0100, Bit 4) Note that the
power-up default is defined by the startup of Pin S1 to Pin S4 (see the Default DDS Output Frequency on
Power-Up section). Updates to the FTW results in an instantaneous frequency jump but no phase discontinuity.
Register 0x01A7—FTW0 (Frequency Tuning Word) (Continued)
Table 61.
Bit
[15:8]
Bit Name
FTW0
Description
FTW (frequency tuning word) for DDS when the loop is not closed (see Register 0x0100, Bit 0). Also used as
the initial frequency estimate when the estimator is disabled (see Register 0x0100, Bit 4) Note that the
power-up default is defined by the startup of Pin S1 to Pin S4 (see the Default DDS Output Frequency on
Power-Up section). Updates to the FTW results in an instantaneous frequency jump but no phase discontinuity.
Register 0x01A8—FTW0 (Frequency Tuning Word) (Continued)
Table 62.
Bit
[23:16]
Bit Name
FTW0
Description
FTW (frequency tuning word) for DDS when the loop is not closed (see Register 0x0100, Bit 0). Also used as
the initial frequency estimate when the estimator is disabled (see Register 0x0100, Bit 4) Note that the
power-up default is defined by the startup of Pin S1 to Pin S4 (see the Default DDS Output Frequency on
Power-Up section). Updates to the FTW results in an instantaneous frequency jump but no phase discontinuity.
Register 0x01A9—FTW0 (Frequency Tuning Word) (Continued)
Table 63.
Bit
[31:24]
Bit Name
FTW0
Description
FTW (frequency tuning word) for DDS when the loop is not closed (see Register 0x0100, Bit 0). Also used as
the initial frequency estimate when the estimator is disabled (see Register 0x0100, Bit 4) Note that the
power-up default is defined by the startup of Pin S1 to Pin S4 (see the Default DDS Output Frequency on
Power-Up section). Updates to the FTW results in an instantaneous frequency jump but no phase discontinuity.
Register 0x01AA—FTW0 (Frequency Tuning Word) (Continued)
Table 64.
Bit
[39:32]
Bit Name
FTW0
Description
FTW (frequency tuning word) for DDS when the loop is not closed (see Register 0x0100, Bit 0). Also used as
the initial frequency estimate when the estimator is disabled (see Register 0x0100, Bit 4) Note that the
power-up default is defined by the startup of Pin S1 to Pin S4 (see the Default DDS Output Frequency on
Power-Up section). Updates to the FTW results in an instantaneous frequency jump but no phase discontinuity.
Register 0x01AB—FTW0 (Frequency Tuning Word) (Continued)
Table 65.
Bit
[47:40]
Bit Name
FTW0
Description
FTW (frequency tuning word) for DDS when the loop is not closed (see Register 0x0100, Bit 0). Also used as
the initial frequency estimate when the estimator is disabled (see Register 0x0100, Bit 4) Note that the
power-up default is defined by the startup of Pin S1 to Pin S4 (see the Default DDS Output Frequency on
Power-Up section). Updates to the FTW results in an instantaneous frequency jump but no phase discontinuity.
Rev. D | Page 61 of 76
AD9549
Register 0x01AC to Register 0x01AD—Phase
Table 66.
Bits
[7:0]
Bit Name
DDS phase word
Description
Allows user to vary the phase of the DDS output. See the Direct Digital Synthesizer section. Register
0x01AC is the least significant byte of the phase offset word (POW). Note that a momentary phase
discontinuity may occur as the phase passes through 45° intervals. Active only when the loop is not closed.
Register 0x01AD—Phase (Continued)
Table 67.
Bits
[15:8]
Bit Name
DDS phase word
Description
Allows user to vary the phase of the DDS output. See the Direct Digital Synthesizer section. Register
0x01AC is the least significant byte of the phase offset word (POW). Note that a momentary phase
discontinuity may occur as the phase passes through 45° intervals. Active only when the loop is not closed.
REFERENCE SELECTOR/HOLDOVER (REGISTER 0x01C0 TO REGISTER 0x01C3)
Register 0x01C0—Automatic Control
Table 68.
Bits
4
Bit Name
Holdover mode
3
2
1
0
Reserved
Automatic selector
Automatic recover
Automatic holdover
Description
This bit determines which frequency tuning word (FTW) is used in holdover mode.
0 = use last FTW at time of holdover.
1 = use averaged FTW at time of holdover, which is the recommended setting. The number of averages
used is set in Register 0x01C2.
Reserved.
Setting this bit permits state machine to switch the active reference clock input.
Setting this bit permits state machine to leave holdover mode.
Setting this bit permits state machine to enter holdover (free-run) mode.
Register 0x01C1—Override
Table 69.
Bits
4
Bit Name
Enable line card mode
3
Enable ref input
override
REF_AB
2
1
0
Enable holdover
override
Holdover on/off
Description
Enables line card mode of reference switch MUX, which eliminates the possibility of a runt pulse during
switchover. See the Use of Line Card Mode to Eliminate Runt Pulses section.
Setting this bit disables automatic reference switchover, and allows user to switch references manually
via Bit 2 of this register. Setting this bit overrides the REFSELECT pin.
This bit selects the input when Bit 3 of this register is set.
0 = REFA.
Setting this bit disables automatic holdover and allows user to enter/exit holdover manually via Bit 0
(see the description for Bit 0). Setting this bit overrides the HOLDOVER pin.
This bit controls the status of holdover when Bit 1 of this register is set.
Register 0x01C2—Averaging Window
Table 70.
Bits
[3:0]
Bit Name
FTW windowed
average size
Description
This register sets the number of FTWs (frequency tuning words) that are used for calculating the average
FTW. Bit 4 in Register 0x01C0 enables this feature. An average size of at least 32,000 is recommended for
most applications. The number of averages equals 2(FTW Windowed Average Size [3:0]). These samples are taken at
the rate of (fs/2PIO).
Rev. D | Page 62 of 76
AD9549
Register 0x01C3—Reference Validation
Table 71.
Bits
[7:5]
[4:0]
Bit Name
Reserved
Validation timer
Description
Reserved.
The value in this register sets the time required to validate a reference after an LOR or OOL event
before the reference can be used as the DPLL reference. This circuit uses the digital loop filter clock
(see Register 0x0107). Validation time = loop filter clock period × 2(Validation Timer [4:0] +1) − 1. Assuming
power-on defaults, the recovery time varies from 32 ns (00000) to 137 sec (11111). If longer valida-tion
times are required, the user can make the P-divider larger. The user should be careful to set the
validation timer to at least two periods of the OOL evaluation period. The OOL evaluation period is the
period of reference input clock times the OOL divider (Register 0x0322 to Register 0x0323).
DOUBLER AND OUTPUT DRIVERS (REGISTER 0x0200 TO REGISTER 0x0201)
Register 0x0200—HSTL Driver
Table 72.
Bits
4
[3:2]
[1:0]
Bit Name
OPOL
Reserved
HSTL output doubler
Description
Output polarity. Setting this bit inverts the HSTL driver output polarity.
Reserved.
HSTL output doubler.
01 = doubler disabled.
10 = doubler enabled. When using doubler, Register 0x0010[5] must also be set.
Register 0x0201—CMOS Driver
Table 73.
Bits
0
Bit Name
CMOS mux
Description
User mux control. This bit allows the user to select whether the CMOS driver output is divided by the
S-divider.
0 = S-divider input sent to CMOS driver.
1 = S-divider output sent to CMOS driver. See Figure 22.
Rev. D | Page 63 of 76
AD9549
MONITOR (REGISTER 0x0300 TO REGISTER 0x0335)
Register 0x0300—Status
This register contains the status of the chip. This register is read-only and live update.
Table 74.
Bits
7
6
Bit Name
Reserved
PFD frequency too high
5
PFD frequency too low
4
Frequency estimator done
3
Reference selected
2
1
Free run
Phase lock detect
0
Frequency lock detect
Description
Reserved.
This flag indicates that the frequency estimator failed and detected a PFD frequency that is too high.
This bit is relevant only if the user is relying on the frequency estimator to determine the input
frequency.
This flag indicates that the frequency estimator failed and detected a PFD frequency that is too low.
This bit is relevant only if the user is relying on the frequency estimator to determine the input
frequency.
True when the frequency estimator circuit has successfully estimated the input frequency. See the
Frequency Estimator section.
Reference selected.
0 = Reference A is active.
1 = Reference B is active.
DPLL is in holdover mode (free run).
This flag indicates that the phase lock detect circuit has detected phase lock. The amount of phase
adjustment is compared against a programmable threshold. Note that this bit can be set in single
tone and holdover modes and should be ignored in these cases.
This flag indicates that the frequency lock detect circuit has detected frequency lock. This feature
compares the absolute value of the difference of two consecutive phase detector edges against a
programmable threshold. Because of this, frequency lock detect is more rigorous than phase lock
detect, and it is possible to have phase lock detect without frequency lock detect.
Register 0x0301—Status (Continued)
This register contains the status of the chip. This register is read-only and live update.
Table 75.
Bits
7
6
5
4
3
2
1
0
Bit Name
Reserved
REFA valid
REFA LOR
REFA OOL
Reserved
REFB Valid
REFB LOR
REFB OOL
Description
Reserved.
The reference validation circuit has successfully determined that Reference A is valid.
A LOR (loss of reference) has occurred on Reference A.
The OOL (out of limits) circuit has determined that Reference A is out of limits.
Reserved.
The reference validation circuit has successfully determined that Reference B is valid.
A LOR (loss of reference) has occurred on Reference B.
The OOL (out of limits) circuit has determined that Reference B is out of limits.
Register 0x0302 and Register 0x0303—IRQ Status
These registers contain the chip status (Registers 0x0300 and Register 0x0301) at the time of IRQ. These bits are cleared with an IRQ reset
(see Register 0x0012, Bit 5).
Register 0x0304—IRQ Mask
Table 76.
Bits
[7:3]
2
1
0
Bit Name
Reserved
Reference changed
Leave free run
Enter free run
Description
Reserved.
Trigger IRQ when active reference clock selection changes.
Trigger IRQ when DPLL leaves free-run (holdover) mode.
Trigger IRQ when DPLL enters free-run (holdover) mode.
Rev. D | Page 64 of 76
AD9549
Register 0x0305—IRQ Mask (Continued)
Table 77.
Bits
4
3
2
1
0
Bit Name
Frequency estimator done
Phase unlock
Phase lock
Frequency unlock
Frequency lock
Description
Trigger IRQ when the frequency estimator is done.
Trigger IRQ on falling edge of phase lock signal.
Trigger IRQ on rising edge of phase lock signal.
Trigger IRQ on falling edge of frequency lock signal.
Trigger IRQ on rising edge of frequency lock signal.
Register 0x0306—IRQ Mask (Continued)
Table 78.
Bits
[7:6]
5
4
3
2
1
0
Bit Name
Reserved
REFA valid
!REFA valid
REFA LOR
!REFA LOR
REFA OOL
!REFA OOL
Description
Reserved.
Trigger IRQ on rising edge of Reference A’s valid.
Trigger IRQ on falling edge of Reference A’s valid.
Trigger IRQ on rising edge of Reference A’s LOR.
Trigger IRQ on falling edge of Reference A’s LOR.
Trigger IRQ on rising edge of Reference A’s OOL.
Trigger IRQ on falling edge of Reference A’s OOL.
Register 0x0307—IRQ Mask (Continued)
Table 79.
Bits
[7:6]
5
4
3
2
1
0
Bit Name
Reserved
REFB valid
!REFB valid
REFB LOR
!REFB LOR
REFB OOL
!REFB OOL
Description
Reserved.
Trigger IRQ on rising edge of Reference B’s valid.
Trigger IRQ on falling edge of Reference B’s valid.
Trigger IRQ on rising edge of Reference B’s LOR.
Trigger IRQ on falling edge of Reference B’s LOR.
Trigger IRQ on rising edge of Reference B’s OOL.
Trigger IRQ on falling edge of Reference B’s OOL.
Register0x0308—S1 Pin Configuration
See the Status and Warnings section. The choice of input for a given pin must be all REFA or all REFB and not a combination of both.
Table 80.
Bits
7
6
5
4
3
2
1
0
Bit Name
REF?
REF? LOR
REF? OOL
REF? not valid
Phase lock
Frequency lock
Reserved
IRQ
Description
Choose either REFA (0) or REFB (1) for use with Bits [4:6].
Select either REFA (0) or REFB (1) LOR signal for output on this pin.
Select either REFA (0) or REFB (1) OOL signal for output on this pin.
Select either REFA (0) or REFB (1). Not Valid signal for output on this pin.
Select phase lock signal for output on this pin.
Select frequency lock signal for output on this pin.
Reserved.
Select IRQ signal for output on this pin.
Register 0x0309—S2 Pin Configuration
Same as Register 0x0308, except applies to Pin S2. See Table 80.
Register 0x030A—S3 Pin Configuration
Same as Register 0x0308, except applies to Pin S3. See Table 80.
Register 0x030B—S4 Pin Configuration
Same as Register 0x0308, except applies to Pin S4. See Table 80.
Rev. D | Page 65 of 76
AD9549
Register 0x030C—Control
Table 81.
Bits
7
6
5
4
[3:2]
1
0
Bit Name
Enable REFA LOR
Enable REFA OOL
Enable REFB LOR
Enable REFB OOL
Reserved
Enable phase lock detector
Enable frequency lock detector
Description
The REFA LOR limits are set up in Registers 0x031E to Register 0x031F.
The REFA OOL limits are set up in Register 0x0322 to Register 0x032B.
The REFB LOR limits are set up in Register 0x0320 to Register 0x0321.
The REFB OOL limits are set up in Register 0x032C to Register 0x0335.
Reserved.
Register 0x0314 to Register 0x0318 must be set up to use this (see the Phase Lock Detection section).
Register 0x0319 must be set up to use this. See the Frequency Lock Detection section.
Register 0x030D—Reserved
Register 0x030E—HFTW (Read Only)
Table 82.
Bits
[7:0]
Bit Name
Average or instantaneous
FTW
Description
These read-only registers are the output of FTW monitor. Average or instantaneous is determined by
holdover mode (see Bit 4, Register 0x01C0). These registers must be manually refreshed by
issuing an I/O update.
Register 0x030F—HFTW (Read Only) (Continued)
Table 83.
Bits
[15:8]
Bit Name
Average or instantaneous
FTW
Description
These read-only registers are the output of FTW monitor. Average or instantaneous is determined by
holdover mode (see Bit 4, Register 0x01C0). These registers must be manually refreshed by
issuing an I/O update.
Register 0x0310—HFTW (Read Only) (Continued)
Table 84.
Bits
[23:16]
Bit Name
Average or instantaneous
FTW
Description
These read-only registers are the output of FTW monitor. Average or instantaneous is determined by
holdover mode (see Bit 4, Register 0x01C0). These registers must be manually refreshed by
issuing an I/O update.
Register 0x0311—HFTW (Read Only) (Continued)
Table 85.
Bits
[31:24]
Bit Name
Average or instantaneous
FTW
Description
These read-only registers are the output of FTW monitor. Average or instantaneous is determined by
holdover mode (see Bit 4, Register 0x01C0). These registers must be manually refreshed by
issuing an I/O update.
Register 0x0312—HFTW (Read Only) (Continued)
Table 86.
Bits
[39:32]
Bit Name
Average or instantaneous
FTW
Description
These read-only registers are the output of FTW monitor. Average or instantaneous is determined by
holdover mode (see Bit 4, Register 0x01C0). These registers must be manually refreshed by
issuing an I/O update.
Register 0x0313—HFTW (Read Only) (Continued)
Table 87.
Bits
[47:40]
Bit Name
Average or instantaneous
FTW
Description
These read-only registers are the output of FTW monitor. Average or instantaneous is determined by
holdover mode (see Bit 4, Register 0x01C0). These registers must be manually refreshed by
issuing an I/O update.
Rev. D | Page 66 of 76
AD9549
Register 0x0314—Phase Lock
Table 88.
Bits
[7:0]
Bit Name
Phase lock threshold
Description
See the Phase Lock Detection section.
Register 0x0315—Phase Lock (Continued)
Table 89.
Bits
[15:8]
Bit Name
Phase lock threshold
Description
See the Phase Lock Detection section.
Register 0x0316—Phase Lock (Continued)
Table 90.
Bits
[23:16]
Bit Name
Phase lock threshold
Description
See the Phase Lock Detection section.
Register 0x0317—Phase Lock (Continued)
Table 91.
Bits
[31:24]
Bit Name
Phase lock threshold
Description
See the Phase Lock Detection section.
Register 0x0318—Phase Lock (Continued)
Table 92.
Bits
[7:5]
[4:0]
Bit Name
Phase unlock watchdog timer
Phase lock watchdog timer
Description
See the Phase Lock Detection section.
See the Phase Lock Detection section.
Register 0x0319—Frequency Lock
Table 93.
Bits
[7:0]
Bit Name
Frequency lock threshold
Description
See the Frequency Lock Detection section
Register 0x031A—Frequency Lock (Continued)
Table 94.
Bits
[15:8]
Bit Name
Frequency lock threshold
Description
See the Frequency Lock Detection section
Register 0x031B—Frequency Lock (Continued
Table 95.
Bits
[31:16]
Bit Name
Frequency lock threshold
Description
See the Frequency Lock Detection section
Register 0x031C—Frequency Lock (Continued
Table 96.
Bits
[39:32]
Bit Name
Frequency lock threshold
Description
See the Frequency Lock Detection section
Register 0x031D—Frequency Lock (Continued)
Table 97.
Bits
[7:5]
[4:0]
Bit Name
Frequency unlock watchdog timer
Frequency lock watchdog timer
Description
See the Frequency Lock Detection section.
See the Frequency Lock Detection section.
Rev. D | Page 67 of 76
AD9549
Register 0x031E—Loss of Reference
Table 98.
Bits
[7:0]
Bit Name
REFA LOR divider
Description
See the Loss of Reference section.
Register 0x031F—Loss of Reference (Continued)
Table 99.
Bits
[15:8]
Bit Name
REFA LOR divider
Description
See the Loss of Reference section.
Register 0x0320—Loss of Reference (Continued)
Table 100.
Bits
[7:0]
Bit Name
REFB LOR divider
Description
See the Loss of Reference section.
Register 0x0321—Loss of Reference (Continued)
Table 101.
Bits
[15:8]
Bit Name
REFB LOR divider
Description
See the Loss of Reference section.
Register 0x0322—Reference Out Of Limits (OOL)
Table 102.
Bits
[7:0]
Bit Name
REFA OOL divider
Description
See the Reference Frequency Monitor section. R0322 is the LSB, and R0323 is the MSB.
Register 0x0323—Reference Out Of Limits (OOL) (Continued)
Table 103.
Bits
[15:8]
Bit Name
REFA OOL divider
Description
See the Reference Frequency Monitor section. R0322 is the LSB, and R0323 is the MSB.
Register 0x0324—Reference OOL (Continued)
Table 104.
Bits
[7:0]
Bit Name
REFA OOL upper limit
Description
See the Reference Frequency Monitor section.
Register 0x0325—Reference OOL (Continued)
Table 105.
Bits
[15:8]
Bit Name
REFA OOL upper limit
Description
See the Reference Frequency Monitor section.
Register 0x0326—Reference OOL (Continued)
Table 106.
Bits
[23:16]
Bit Name
REFA OOL upper limit
Description
See the Reference Frequency Monitor section.
Register 0x0327—Reference OOL (Continued)
Table 107.
Bits
[31:24]
Bit Name
REFA OOL upper limit
Description
See the Reference Frequency Monitor section.
Rev. D | Page 68 of 76
AD9549
Register 0x0328—Reference OOL (Continued)
Table 108.
Bits
[7:0]
Bit Name
REFA OOL lower limit
Description
See the Reference Frequency Monitor section.
Register 0x0329—Reference OOL (Continued)
Table 109.
Bits
[15:8]
Bit Name
REFA OOL lower limit
Description
See the Reference Frequency Monitor section.
Register 0x032A—Reference OOL (Continued)
Table 110.
Bits
[23:16]
Bit Name
REFA OOL lower limit
Description
See the Reference Frequency Monitor section.
Register 0x032B—Reference OOL (Continued)
Table 111.
Bits
[31:24]
Bit Name
REFA OOL lower limit
Description
See the Reference Frequency Monitor section.
Register 0x032C—Reference OOL (Continued)
Table 112.
Bits
[7:0]
Bit Name
REFB OOL divider
Description
See the Reference Frequency Monitor section. Register 0x032C is the LSB, and Register 0x032D is the
MSB.
Register 0x032D—Reference OOL (Continued)
Table 113.
Bits
[15:8]
Bit Name
REFB OOL divider
Description
See the Reference Frequency Monitor section. Register 0x032C is the LSB, and Register 0x032D is the
MSB.
Register 0x032E—Reference OOL (Continued)
Table 114.
Bits
[7:0]
Bit Name
REFB OOL upper limit
Description
See the Reference Frequency Monitor section.
Register 0x032F—Reference OOL (Continued)
Table 115.
Bits
[15:8]
Bit Name
REFB OOL upper limit
Description
See the Reference Frequency Monitor section.
Register 0x0330—Reference OOL (Continued)
Table 116.
Bits
[23:16]
Bit Name
REFB OOL upper limit
Description
See the Reference Frequency Monitor section.
Register 0x0331—Reference OOL (Continued)
Table 117.
Bits
[31:24]
Bit Name
REFB OOL upper limit
Description
See the Reference Frequency Monitor section.
Rev. D | Page 69 of 76
AD9549
Register 0x0332—Reference OOL (Continued)
Table 118.
Bits
[7:0]
Bit Name
REFB OOL lower limit
Description
See the Reference Frequency Monitor section.
Register 0x0333—Reference OOL (Continued)
Table 119.
Bits
[15:8]
Bit Name
REFB OOL lower limit
Description
See the Reference Frequency Monitor section.
Register 0x0334—Reference OOL (Continued)
Table 120.
Bits
[23:16]
Bit Name
REFB OOL lower limit
Description
See the Reference Frequency Monitor section.
Register 0x0335—Reference OOL (Continued)
Table 121.
Bits
[31:24]
Bit Name
REFB OOL lower limit
Description
See the Reference Frequency Monitor section.
CALIBRATION (USER-ACCESSIBLE TRIM) (REGISTER 0x0400 TO REGISTER 0x0410)
Register 0x0400—K-Divider
Table 122.
Bits
[7:0]
Bit Name
K-divider
Description
The K-divider alters precision of frequency estimator circuit. See the Frequency Estimator section.
Register 0x0401—K-Divider (Continued)
Table 123.
Bits
[15:8]
Bit Name
K-divider
Description
The K-divider alters precision of frequency estimator circuit. See the Frequency Estimator section.
Register 0x0402—CPFD Gain
Table 124.
Bits
[2:0]
Bit Name
CPFD gain scale
Description
This register is the coarse phase frequency power-of-2 multiplier (PDS). See the Phase Detector section. Note
that the correct value for this register is calculated by filter design software provided with the evaluation board.
Register 0x0403—CPFD Gain (Continued)
Table 125.
Bits
[5:0]
Bit Name
CPFD gain
Description
This register is the coarse phase frequency linear multiplier (PDG). See the Phase Detector section. Note
that the correct value for this register is calculated by filter design software provided with the evaluation board.
Register 0x0404—FPFD Gain
Table 126.
Bits
[7:0]
Bit Name
FPFD gain
Description
This register is the fine phase frequency detector linear multiplier (alters charge pump current). See the
Fine Phase Detector section. Note that the correct value for this register is calculated by filter design software
provided with the evaluation board.
Register 0x0405—Reserved
Rev. D | Page 70 of 76
AD9549
Register 0x0406—Part Version
Table 127.
Bits
[7:6]
Bit Name
Part version
[5:0]
Reserved
Description
01b = AD9549, Revision A
00b = AD9549, Revision 0
N/A
Register 0x0407 to Register 0x0408—Reserved
Register 0x0409—PFD Offset
Table 128.
Bits
[7:0]
Bit Name
DPLL phase offset
Description
This register controls the static time offset of the PFD (phase frequency detector) in closed-loop mode.
It has no effect when the DPLL is open.
Register 0x040A—PFD Offset (Continued)
Table 129.
Bits
[13:8]
Bit Name
DPLL phase offset
Description
This register controls the static time offset of the PFD (phase frequency detector) in closed-loop mode.
It has no effect when the DPLL is open.
Register 0x040B—DAC Full-Scale Current
Table 130.
Bits
[7:0]
Bit Name
DAC full-scale current
Description
DAC full-scale current, Bits[7:0]. See the DAC Output section.
Register 0x040C—DAC Full-Scale Current (Continued)
Table 131.
Bits
[9:8]
Bit Name
DAC full-scale current
Description
DAC full-scale current, Bits[9:8]. See Register 0x040B.
Register 0x040D to Register 0x040E—Reserved
Register 0x040F—Reference Bias Level
Table 132.
Bits
[7:2]
[1:0]
Bit Name
Reserved
DC input level
Description
Reserved.
This register sets the dc bias level for the reference inputs. The value should be chosen such that VIH is
as close as possible to, but does not exceed, 3.3 V.
00 = VDD3 − 800 mV.
01 = VDD3 − 400 mV.
10 = VDD3 − 1.6 V.
11 = VDD3 − 1.2 V.
Register 0x0410—Reserved
HARMONIC SPUR REDUCTION (REGISTER 0x0500 TO REGISTER 0x0509)
See the Harmonic Spur Reduction section.
Rev. D | Page 71 of 76
AD9549
Register 0x0500—Spur A
Table 133.
Bits
7
6
[5:4]
[3:0]
Bit Name
HSR-A enable
Amplitude gain × 2
Reserved
Spur A harmonic
Description
Harmonic Spur Reduction A enable.
Reserved.
Spur A Harmonic 1 to Spur A Harmonic 15.
Register 0x0501—Spur A (Continued)
Table 134.
Bits
[7:0]
Bit Name
Spur A magnitude
Description
Linear multiplier for Spur A magnitude.
Register 0x0503—Spur A (Continued)
Table 135.
Bits
[7:0]
Bit Name
Spur A phase
Description
Linear offset for Spur A phase.
Register 0x0504—Spur A (Continued)
Table 136.
Bits
8
Bit Name
Spur A phase
Description
Linear offset for Spur A phase.
Register 0x0505—Spur B
Table 137.
Bits
7
6
[5:4]
[3:0]
Bit Name
HSR-B enable
Amplitude gain × 2
Reserved
Spur B harmonic
Description
Harmonic Spur Reduction B enable.
Reserved.
Spur B Harmonic 1 to Spur B Harmonic 15.
Register 0x0506—Spur B (Continued)
Table 138.
Bits
[7:0]
Bit Name
Spur B magnitude
Description
Linear multiplier for Spur B magnitude.
Register 0x0508—Spur B (Continued)
Table 139.
Bits
[7:0]
Bit Name
Spur B phase
Description
Linear offset for Spur B phase.
Register 0x0509—Spur B (Continued)
Table 140.
Bits
8
Bit Name
Spur B phase
Description
Linear offset for Spur B phase.
Rev. D | Page 72 of 76
AD9549
APPLICATIONS INFORMATION
SAMPLE APPLICATIONS CIRCUIT
DIFF HSTL OUTPUT
AD9514
LVPECL
CMOS OUTPUT
INPUT A
INPUT B
OUT0/
OUT0B
/1...../32
FDBK_IN
FDBK_INB
REF A
LVPECL
CLK
DDS/
DAC
LOW-PASS
FILTER
OUT1/
OUT1B
/1...../32
CLKB
REF B
LDDS/CMOS
AD9549
/1...../32
SYNCB
OUT2/
OUT2B
06744-059
SYSCLK
Δt
Figure 59. AD9549 and AD9514 Precision Clock Distribution Circuit
Applications Circuit Features
•
Features of this applications circuit include the following:
•
•
•
Input frequencies down to 8 kHz; output frequencies up to
400 MHz
Programmable loop bandwidth down to <1 Hz
Automatic redundant clock switchover with user-selectable
rate-of-phase adjustment
•
•
•
Rev. D | Page 73 of 76
Automatic Stratum 3/3E clock holdover, depending on the
configuration
Phase noise (fC = 122.3 MHz and 100 Hz loop bandwidth);
100 Hz offset: −107 dBc/Hz; 1 kHz offset: −142 dBc/Hz;
100 kHz offset: −157 dBc/Hz; two zero-delay outputs with
programmable postdivider and synchronization
Two additional outputs (nonzero delay) on the AD9549
Programmable skew adjustment on one AD9514 output
AD9549
OUTLINE DIMENSIONS
9.10
9.00 SQ
8.90
0.60 MAX
0.60
MAX
48
64
49
1
PIN 1
INDICATOR
PIN 1
INDICATOR
8.85
8.75 SQ
8.65
0.50
BSC
0.50
0.40
0.30
33
32
0.05 MAX
0.02 NOM
0.30
0.23
0.18
0.25 MIN
0.20 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
062209-A
SEATING
PLANE
16
7.50 REF
0.80 MAX
0.65 TYP
12° MAX
17
BOTTOM VIEW
TOP VIEW
1.00
0.85
0.80
5.36
5.21 SQ
5.06
EXPOSED
PAD
Figure 60. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD9549ABCPZ
AD9549ABCPZ-REEL7
AD9549A/PCBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ
Evaluation Board
Z = RoHS Compliant Part.
Rev. D | Page 74 of 76
Package Option
CP-64-7
CP-64-7
AD9549
NOTES
Rev. D | Page 75 of 76
AD9549
NOTES
©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06744-0-12/10(D)
Rev. D | Page 76 of 76