LINER LTC2260UJ-12 12-bit, 125/105/80msps ultralow power 1.8v adc Datasheet

LTC2261-12
LTC2260-12/LTC2259-12
12-Bit, 125/105/80Msps
Ultralow Power 1.8V ADCs
FEATURES
DESCRIPTION
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The LTC ®2261-12/LTC2260-12/LTC2259-12 are sampling 12-bit A/D converters designed for digitizing high
frequency, wide dynamic range signals. They are perfect
for demanding communications applications with AC
performance that includes 70.8dB SNR and 85dB spurious
free dynamic range (SFDR). Ultralow jitter of 0.17psRMS
allows undersampling of IF frequencies with excellent
noise performance.
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70.8dB SNR
85dB SFDR
Low Power: 124mW/103mW/87mW
Single 1.8V Supply
CMOS, DDR CMOS or DDR LVDS Outputs
Selectable Input Ranges: 1VP-P to 2VP-P
800MHz Full-Power Bandwidth S/H
Optional Data Output Randomizer
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Serial SPI Port for Configuration
Pin Compatible 14-Bit and 12-Bit Versions
40-Pin (6mm × 6mm) QFN Package
APPLICATIONS
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DC specs include ±0.3LSB INL (typical), ±0.1LSB DNL
(typical) and no missing codes over temperature. The
transition noise is a low 0.3LSBRMS.
The digital outputs can be either full rate CMOS, double
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC+ and ENC– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of
clock duty cycles.
Communications
Cellular Base Stations
Software Defined Radios
Portable Medical Imaging
Multi-Channel Data Acquisition
Nondestructive Testing
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
1.8V
2-Tone FFT, fIN = 70MHz and 75MHz
1.2V
TO 1.8V
VDD
0
OVDD
–10
–20
ANALOG
INPUT
INPUT
S/H
–
12-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
D11
CMOS
•
OR
•
LVDS
•
D0
OUTPUT
DRIVERS
OGND
CLOCK
–40
–50
–60
–70
–80
–90
–100
CLOCK/DUTY
CYCLE
CONTROL
125MHz
–30
AMPLITUDE (dBFS)
+
–110
–120
GND
226112 TA01a
0
10
20
30
40
FREQUENCY (MHz)
50
60
226112 TA01b
226112f
1
LTC2261-12
LTC2260-12/LTC2259-12
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltages (VDD, OVDD) ....................... –0.3V to 2V
Analog Input Voltage (AIN+, AIN–,
PAR/SER, SENSE) (Note 3) ...........–0.3V to (VDD + 0.2V)
Digital Input Voltage (ENC+, ENC–, CS,
SDI, SCK) (Note 4) .................................... –0.3V to 3.9V
SDO (Note 4) ............................................ –0.3V to 3.9V
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)
Operating Temperature Range:
LTC2261C, LTC2260C, LTC2259C............. 0°C to 70°C
LTC2261I, LTC2260I, LTC2259I ............ –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
PIN CONFIGURATIONS
40 39 38 37 36 35 34 33 32 31
DNC
D8_9
DNC
D10_11
DNC
OF
VCM
VREF
VDD
D8
D9
D10
D11
DNC
OF
VCM
VREF
SENSE
VDD
SENSE
DOUBLE DATA RATE CMOS OUTPUT MODE
TOP VIEW
FULL-RATE CMOS OUTPUT MODE
TOP VIEW
40 39 38 37 36 35 34 33 32 31
AIN+ 1
30 D7
AIN+ 1
30 D6_7
AIN– 2
29 D6
AIN– 2
29 DNC
GND 3
28 CLKOUT+
GND 3
28 CLKOUT+
REFH 4
27 CLKOUT–
REFH 4
27 CLKOUT–
REFH 5
26 OVDD
REFH 5
25 OGND
REFL 6
REFL 7
24 D5
REFL 7
PAR/SER 8
23 D4
PAR/SER 8
VDD 9
22 D3
VDD 9
VDD 10
21 D2
VDD 10
25 OGND
24 D4_5
23 DNC
22 D2_3
21 DNC
D0_1
DNC
DNC
DNC
SDO
SDI
SCK
ENC+
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
CS
11 12 13 14 15 16 17 18 19 20
D1
D0
DNC
DNC
SDO
SDI
SCK
CS
ENC+
ENC–
11 12 13 14 15 16 17 18 19 20
26 OVDD
41
ENC–
41
REFL 6
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
TJMAX = 150°C, θJA = 32°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
TJMAX = 150°C, θJA = 32°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
D8_9–
D8_9+
D10_11–
D10_11+
OF–
OF+
VCM
VREF
SENSE
VDD
DOUBLE DATA RATE LVDS OUTPUT MODE
TOP VIEW
40 39 38 37 36 35 34 33 32 31
AIN+ 1
30 D6_7+
AIN– 2
29 D6_7–
GND 3
28 CLKOUT+
REFH 4
27 CLKOUT–
REFH 5
26 OVDD
41
REFL 6
25 OGND
REFL 7
24 D4_5+
PAR/SER 8
23 D4_5–
VDD 9
22 D2_3+
VDD 10
21 D2_3–
D0_1+
D0_1–
DNC
DNC
SDO
SDI
SCK
CS
ENC–
ENC+
11 12 13 14 15 16 17 18 19 20
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
TJMAX = 150°C, θJA = 32°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
226112f
2
LTC2261-12
LTC2260-12/LTC2259-12
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2261CUJ-12#PBF
LTC2261CUJ-12#TRPBF
LTC2261UJ-12
40-Lead (6mm × 6mm) Plastic QFN
0°C to 70°C
LTC2261IUJ-12#PBF
LTC2261IUJ-12#TRPBF
LTC2261UJ-12
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 85°C
LTC2260CUJ-12#PBF
LTC2260CUJ-12#TRPBF
LTC2260UJ-12
40-Lead (6mm × 6mm) Plastic QFN
0°C to 70°C
LTC2260IUJ-12#PBF
LTC2260IUJ-12#TRPBF
LTC2260UJ-12
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 85°C
LTC2259CUJ-12#PBF
LTC2259CUJ-12#TRPBF
LTC2259UJ-12
40-Lead (6mm × 6mm) Plastic QFN
0°C to 70°C
LTC2259IUJ-12#PBF
LTC2259IUJ-12#TRPBF
LTC2259UJ-12
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2261-12
PARAMETER
CONDITIONS
MIN
l
Resolution (No Missing Codes)
TYP
LTC2260-12
MAX
12
MIN
TYP
LTC2259-12
MAX
12
MIN
TYP
MAX
12
UNITS
Bits
Integral Linearity Error
Differential Analog Input (Note 6) l
–1
±0.3
1
–1
±0.3
1
–1
±0.3
1
LSB
Differential Linearity Error
Differential Analog Input
l
–0.4
±0.1
0.4
–0.4
±0.1
0.4
–0.4
±0.1
0.4
LSB
Offset Error
(Note 7)
l
–9
±1.5
9
–9
±1.5
9
–9
±1.5
9
mV
Gain Error
Internal Reference
External Reference
l
–1.5
±1.5
±0.4
1.5
–1.5
±1.5
±0.4
1.5
–1.5
±1.5
±0.4
1.5
%FS
%FS
Offset Drift
±20
±20
±20
μV/°C
Full-Scale Drift
Internal Reference
External Reference
±30
±10
±30
±10
±30
±10
ppm/°C
ppm/°C
Transition Noise
External Reference
0.3
0.3
0.3
LSBRMS
226112f
3
LTC2261-12
LTC2260-12/LTC2259-12
ANALOG INPUT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VIN
Analog Input Range (AIN+ – AIN–)
1.7V < VDD < 1.9V
l
VIN(CM)
Analog Input Common Mode (AIN+ + AIN–)/2
Differential Analog Input (Note 8)
l
VCM – 100mV
VCM
VCM + 100mV
V
VSENSE
External Voltage Reference Applied to SENSE External Reference Mode
l
0.625
1.250
1.300
V
IINCM
Analog Input Common Mode Current
Per Pin, 125Msps
Per Pin, 105Msps
Per Pin, 80Msps
IIN1
Analog Input Leakage Current
0 < AIN+, AIN– < VDD, No Encode
l
–1
1
μA
IIN2
PAR/SER Input Leakage Current
0 < PAR/SER < VDD
l
–3
3
μA
IIN3
SENSE Input Leakage Current
0.625V < SENSE < 1.3V
l
–6
6
μA
tAP
Sample-and-Hold Acquisition Delay Time
0
tJITTER
Sample-and-Hold Acquisition Delay Jitter
0.17
CMRR
Analog Input Common Mode Rejection Ratio
BW-3B
Full-Power Bandwidth
1 to 2
VP-P
155
130
100
Figure 6 Test Circuit
μA
μA
μA
ns
psRMS
80
dB
800
MHz
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
LTC2261-12
SYMBOL
PARAMETER
CONDITIONS
SNR
Signal-to-Noise Ratio
5MHz Input
70MHz Input
140MHz Input
SFDR
S/(N+D)
MIN
TYP
l
69.4
Spurious Free Dynamic Range 5MHz Input
2nd or 3rd Harmonic
70MHz Input
140MHz Input
l
Spurious Free Dynamic Range 5MHz Input
4th Harmonic or Higher
70MHz Input
140MHz Input
Signal-to-Noise Plus
Distortion Ratio
5MHz Input
70MHz Input
140MHz Input
MAX
LTC2260-12
MIN
TYP
70.8
70.7
70.4
69.4
76
88
85
82
l
83
l
68.6
MAX
LTC2259-12
MIN
TYP
MAX
UNITS
70.8
70.7
70.4
69.1
70.6
70.5
70.2
dB
dB
dB
76
88
85
82
79
88
85
82
dB
dB
dB
90
90
90
82
90
90
90
85
90
90
90
dB
dB
dB
70.6
70.4
70
68.6
70.6
70.4
70
68.8
70.4
70.3
69.9
dB
dB
dB
INTERNAL REFERENCE CHARACTERISTICS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
VCM Output Voltage
IOUT = 0
MIN
TYP
MAX
0.5 • VDD – 25mV
0.5 • VDD
0.5 • VDD + 25mV
VCM Output Temperature Drift
±25
VCM Output Resistance
–600μA < IOUT < 1mA
VREF Output Voltage
IOUT = 0
VREF Output Temperature Drift
1.250
±25
VREF Output Resistance
–400μA < IOUT < 1mA
VREF Line Regulation
1.7V < VDD < 1.9V
7
0.6
V
ppm/°C
4
1.225
UNITS
Ω
1.275
V
ppm/°C
Ω
mV/V
226112f
4
LTC2261-12
LTC2260-12/LTC2259-12
DIGITAL INPUTS AND OUTPUTS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ENCODE INPUTS (ENC+, ENC– )
Differential Encode Mode (ENC– Not Tied to GND)
VID
Differential Input Voltage
(Note 8)
l
0.2
VICM
Common Mode Input Voltage
Internally Set
Externally Set (Note 8)
l
1.1
1.6
V
V
l
0.2
3.6
V
V
1.2
VIN
Input Voltage Range
ENC+, ENC– to GND
RIN
Input Resistance
(See Figure 10)
10
kΩ
CIN
Input Capacitance
(Note 8)
3.5
pF
Single-Ended Encode Mode (ENC– Tied to GND)
VIH
High Level Input Voltage
VDD = 1.8V
l
VIL
Low Level Input Voltage
VDD = 1.8V
l
VIN
Input Voltage Range
ENC+ to GND
l
RIN
Input Resistance
(See Figure 11)
30
kΩ
CIN
Input Capacitance
(Note 8)
3.5
pF
1.2
V
0.6
0
3.6
V
V
DIGITAL INPUTS (CS, SDI, SCK)
VIH
High Level Input Voltage
VDD = 1.8V
l
VIL
Low Level Input Voltage
VDD = 1.8V
l
l
IIN
Input Current
VIN = 0V to 3.6V
CIN
Input Capacitance
(Note 8)
1.3
V
–10
0.6
V
10
μA
3
pF
200
Ω
SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)
ROL
Logic Low Output Resistance to GND
VDD = 1.8V, SDO = 0V
IOH
Logic High Output Leakage Current
SDO = 0V to 3.6V
COUT
Output Capacitance
(Note 8)
l
–10
10
μA
4
pF
1.790
V
DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE)
OVDD = 1.8V
VOH
High Level Output Voltage
IO = –500μA
l
VOL
Low Level Output Voltage
IO = 500μA
l
1.750
0.010
0.050
V
OVDD = 1.5V
VOH
High Level Output Voltage
IO = –500μA
1.488
V
VOL
Low Level Output Voltage
IO = 500μA
0.010
V
OVDD = 1.2V
VOH
High Level Output Voltage
IO = –500μA
1.185
V
VOL
Low Level Output Voltage
IO = 500μA
0.010
V
DIGITAL DATA OUTPUTS (LVDS MODE)
VOD
Differential Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
247
350
175
454
VOS
Common Mode Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
1.125
1.250
1.250
1.375
RTERM
On-Chip Termination Resistance
Termination Enabled, OVDD = 1.8V
100
mV
mV
V
V
Ω
226112f
5
LTC2261-12
LTC2260-12/LTC2259-12
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
LTC2261-12
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
1.8
LTC2260-12
MAX
MIN
TYP
1.9
1.7
1.8
1.9
1.1
LTC2259-12
MAX
MIN
TYP
1.9
1.7
1.8
1.9
1.1
MAX
UNITS
CMOS Output Modes: Full Data Rate and Double Data Rate
VDD
Analog Supply Voltage
(Note 10)
l
1.7
OVDD
Output Supply Voltage
(Note 10)
l
1.1
IVDD
Analog Supply Current
DC Input
Sine Wave Input
l
IOVDD
Digital Supply Current
Sine Wave Input, OVDD=1.2V
3.5
PDISS
Power Dissipation
l
DC Input
Sine Wave Input, OVDD=1.2V
124
130
68.7
70
81.1
57.1
58.3
67.4
48
49
2.9
146
1.9
V
1.9
V
56.6
mA
mA
2.2
103
108
122
mA
87
91
102
mW
mW
LVDS Output Mode
VDD
Analog Supply Voltage
(Note 10)
l
1.7
OVDD
Output Supply Voltage
(Note 10)
l
1.7
1.8
1.9
1.7
1.9
1.7
1.8
1.9
1.7
1.9
1.7
1.8
1.9
V
1.9
V
IVDD
Analog Supply Current
Sine Wave Input
l
73.6
86.9
61.9
73.1
52.7
62.2
mA
IOVDD
Digital Supply Current
(0VDD = 1.8V)
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
l
18.8
36.7
22.2
43.3
18.8
36.7
22.2
43.3
18.8
36.7
22.2
43.3
mA
mA
PDISS
Power Dissipation
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
l
166
199
196
235
145
177
172
210
129
161
152
190
mW
mW
All Output Modes
PSLEEP
Sleep Mode Power
0.5
0.5
0.5
mW
PNAP
Nap Mode Power
9
9
9
mW
PDIFFCLK
Power Increase with Differential Encode Mode Enabled
(No increase for Nap or Sleep Modes)
10
10
10
mW
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2261-12
MIN
TYP
LTC2260-12
SYMBOL
PARAMETER
CONDITIONS
MAX
MIN
fS
Sampling Frequency
(Note 10)
l
1
125
1
tL
ENC Low Time (Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
3.8
2.0
4
4
500
500
tH
ENC High Time (Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
3.8
2.0
4
4
500
500
tAP
Sample-and-Hold
Acquisition Delay Time
SYMBOL
PARAMETER
LTC2259-12
TYP
MAX
105
1
4.52
2.00
4.76
4.76
500
500
4.52
2.00
4.76
4.76
500
500
0
MIN
TYP
MAX
80
MHz
5.93
2.00
6.25
6.25
500
500
ns
ns
5.93
2.00
6.25
6.25
500
500
ns
ns
0
CONDITIONS
0
UNITS
ns
MIN
TYP
MAX
UNITS
Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
tD
ENC to Data Delay
CL = 5pF (Note 8)
l
1.1
1.7
3.1
ns
tC
ENC to CLKOUT Delay
CL = 5pF (Note 8)
l
1
1.4
2.6
ns
tSKEW
DATA to CLKOUT Skew
tD – tC (Note 8)
l
0
0.3
0.6
ns
Pipeline Latency
Full Data Rate Mode
Double Data Rate Mode
5.0
5.5
Cycles
Cycles
226112f
6
LTC2261-12
LTC2260-12/LTC2259-12
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Data Outputs (LVDS Mode)
tD
ENC to Data Delay
CL = 5pF (Note 8)
l
1.1
1.8
3.2
ns
tC
ENC to CLKOUT Delay
CL = 5pF (Note 8)
l
1
1.5
2.7
ns
tSKEW
DATA to CLKOUT Skew
tD – tC (Note 8)
l
0
0.3
0.6
ns
Pipeline Latency
5.5
Cycles
SPI Port Timing (Note 8)
l
l
40
250
ns
ns
CS to SCK Setup Time
l
5
ns
tH
SCK to CS Setup Time
l
5
ns
tDS
SDI Setup Time
l
5
ns
tDH
SDI Hold Time
l
5
tDO
SCK Falling to SDO Valid
tSCK
SCK Period
tS
Write Mode
Readback Mode, CSDO = 20pF, RPULLUP = 2k
Readback Mode, CSDO = 20pF, RPULLUP = 2k
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above VDD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 5: VDD = OVDD = 1.8V, fSAMPLE = 125MHz (LTC2261),
105MHz (LTC2260), or 80MHz (LTC2259), LVDS outputs with internal
ns
l
125
ns
termination disabled, differential ENC+/ENC– = 2VP-P sine wave, input
range = 2VP-P with differential drive, unless otherwise noted.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111 in
2’s complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: VDD = 1.8V, fSAMPLE = 125MHz (LTC2261), 105MHz (LTC2260),
or 80MHz (LTC2259), ENC+ = single-ended 1.8V square wave, ENC– = 0V,
input range = 2VP-P with differential drive, 5pF load on each digital output
unless otherwise noted.
Note 10: Recommended operating conditions.
TIMING DIAGRAMS
Full-Rate CMOS Output Mode Timing
All Outputs Are Single-Ended and Have CMOS Levels
tAP
ANALOG
INPUT
N+4
N+2
N
N+3
tH
N+1
tL
ENC–
ENC+
tD
N–5
D0-D11, OF
CLKOUT +
CLKOUT –
N–4
N–3
N–2
N–1
tC
226112 TD01
226112f
7
LTC2261-12
LTC2260-12/LTC2259-12
TIMING DIAGRAMS
Double Data Rate CMOS Output Mode Timing
All Outputs Are Single-Ended and Have CMOS Levels
tAP
ANALOG
INPUT
N+4
N+2
N
N+3
tH
N+1
tL
ENC–
ENC+
tD
D0_1
tD
D0N-5
D1N-5
D0N-4
D1N-4
D0N-3
D1N-3
D0N-2
D1N-2
D10N-5
D11N-5
D10N-4
D11N-4
D10N-3
D11N-3
D10N-2
D11N-2
••
•
D10_11
OFN-5
OF
OFN-4
OFN-2
tC
tC
CLKOUT+
OFN-3
CLKOUT –
226112 TD02
Double Data Rate LVDS Output Mode Timing
All Outputs Are Differential and Have LVDS Levels
tAP
ANALOG
INPUT
N+4
N+2
N
N+3
tH
N+1
tL
ENC–
ENC+
D0_1+
D0_1–
tD
tD
D0N-5
D1N-5
D0N-4
D1N-4
D0N-3
D1N-3
D0N-2
D1N-2
D10N-5
D11N-5
D10N-4
D11N-4
D10N-3
D11N-3
D10N-2
D11N-2
••
•
D10_11+
D10_11–
OF+
OF–
CLKOUT+
CLKOUT –
OFN-5
tC
OFN-4
OFN-3
OFN-3
tC
226112 TD03
226112f
8
LTC2261-12
LTC2260-12/LTC2259-12
TIMING DIAGRAMS
SPI Port Timing (Readback Mode)
tDS
tS
tDH
tSCK
tH
CS
SCK
tDO
SDI
A6
R/W
A5
A4
A3
A2
A1
A0
SDO
XX
D7
HIGH IMPEDANCE
XX
XX
D6
D5
XX
XX
D4
XX
D3
D2
XX
XX
D1
D0
SPI Port Timing (Write Mode)
CS
SCK
SDI
A6
R/W
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SDO
226112 TD04
HIGH IMPEDANCE
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2261-12: Integral
Nonlinearity (INL)
LTC2261-12: Differential
Nonlinearity (DNL)
LTC2261-12: 8k Point FFT, fIN = 5MHz
–1dBFS, 125Msps
1.0
1.0
0
0.8
0.8
–10
0.6
0.6
0.4
0.4
–20
0.2
0
–0.2
–0.4
0.2
0
–0.2
–0.4
–0.6
–0.6
–0.8
–0.8
–1.0
–1.0
0
1024
2048
3072
OUTPUT CODE
4096
226112 G01
AMPLITUDE (dBFS)
DNL ERROR (LSB)
INL ERROR (LSB)
–30
–40
–50
–60
–70
–80
–90
–100
0
1024
2048
3072
OUTPUT CODE
4096
226112 G02
–110
–120
0
10
20
30
40
FREQUENCY (MHz)
50
60
226112 G03
226112f
9
LTC2261-12
LTC2260-12/LTC2259-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2261-12: 8k Point FFT, fIN = 70MHz
–1dBFS, 125Msps
LTC2261-12: 8k Point FFT, fIN = 140MHz
–1dBFS, 125Msps
0
0
–10
–10
–20
–20
–20
–30
–30
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
0
–10
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
LTC2261-12: 8k Point FFT, fIN = 30MHz
–1dBFS, 125Msps
–40
–50
–60
–70
–80
–70
–80
–90
–100
–90
–100
–110
–120
–110
–120
–110
–120
10
20
30
40
FREQUENCY (MHz)
50
0
60
10
20
30
40
FREQUENCY (MHz)
50
0
60
20
30
40
FREQUENCY (MHz)
10
50
226112 G05
226112 G04
LTC2261-12: 8k Point 2-Tone FFT,
fIN = 70MHz, 75MHz, –1dBFS,
125Msps
0
60
226112 G06
LTC2261-12: SNR vs Input
Frequency, –1dB, 2V Range,
125Msps
LTC2261-12: Shorted Input
Histogram
18000
–10
72
16000
–20
71
14000
–30
–40
70
–60
–70
SNR (dBFS)
12000
–50
COUNT
10000
8000
–80
6000
–90
–100
4000
69
68
67
2000
–110
–120
0
10
20
30
40
FREQUENCY (MHz)
50
0
2041
60
2043
OUTPUT CODE
226112 G07
66
2045
95
100
90
80
75
SFDR (dBc AND dBFS)
80
70
60
LVDS OUTPUTS
70
dBc
50
40
65
CMOS OUTPUTS
60
30
20
70
350
dBFS
90
75
100 150 200 250 300
INPUT FREQUENCY (MHz)
LTC2261-12: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
110
80
50
226112 G09
LTC2261-12: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 125Msps
85
0
226112 G08
LTC2261-12: SFDR vs Input
Frequency, –1dB, 2V Range,
125Msps
IVDD (mA)
AMPLITUDE (dBFS)
–60
–90
–100
0
SFDR (dBFS)
–40
–50
55
10
65
0
50
100 150 200 250 300
INPUT FREQUENCY (MHz)
350
226112 G10
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
226112 G12
50
0
25
50
75
100
SAMPLE RATE (Msps)
125
226112 G13
226112f
10
LTC2261-12
LTC2260-12/LTC2259-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2261-12: IOVDD vs Sample
Rate, 5MHz Sine Wave Input,
–1dB, 5pF on Each Data Output
LTC2261-12: SNR vs Sample Rate
and Digital Output Mode,
30MHz Sine Wave Input, –1dB
LTC2261-12: SNR vs SENSE,
fIN = 5MHz, –1dB
72
72
45
40
3.5mA LVDS
71
71
35
25
1.75mA LVDS
20
SNR (dBFS)
SNR (dBFS)
IOVDD (mA)
CMOS
70
30
69
10
69
1.2V CMOS
0
25
68
50
75
100
SAMPLE RATE (Msps)
66
125
67
0.6
0.7
0.8
0.9
1
1.1
SENSE PIN (V)
226112 G14
1.2
0
1.3
0.8
0.8
0.6
0.6
0.4
0.4
–0.4
0
–0.2
–0.4
–0.6
–0.8
–0.8
–1.0
–1.0
1024
2048
3072
OUTPUT CODE
4096
–30
0.2
–0.6
0
–20
AMPLITUDE (dBFS)
DNL ERROR (LSB)
0
–10
0
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
1024
2048
3072
OUTPUT CODE
0
4096
LTC2260-12: 8k Point FFT, fIN = 70MHz
–1dBFS, 105Msps
–20
–20
–20
–30
–30
–30
–60
–70
–80
AMPLITUDE (dBFS)
0
–10
AMPLITUDE (dBFS)
0
–10
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–100
–90
–100
–90
–100
–110
–120
–110
–120
–110
–120
0
10
20
30
40
FREQUENCY (MHz)
50
226112 G24
0
10
20
30
40
FREQUENCY (MHz)
50
226112 G25
50
LTC2260-12: 8k Point FFT, fIN = 140MHz
–1dBFS, 105Msps
0
–50
20
30
40
FREQUENCY (MHz)
226112 G23
–10
–40
10
226112 G22
226112 G21
LTC2260-12: 8k Point FFT, fIN = 30MHz
–1dBFS, 105Msps
125
LTC2260-12: 8k Point FFT, fIN = 5MHz
–1dBFS, 105Msps
1.0
–0.2
50
75
100
SAMPLE RATE (Msps)
226112 G18
LTC2260-12: Differential
Nonlinearity (DNL)
1.0
0.2
25
226112 G15
LTC2260-12: Integral Nonlinearity
(INL)
INL ERROR (LSB)
DDR CMOS
67
1.8V CMOS
5
AMPLITUDE (dBFS)
70
68
15
0
LVDS
0
10
20
30
40
FREQUENCY (MHz)
50
226112 G26
226112f
11
LTC2261-12
LTC2260-12/LTC2259-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2260-12: 8k Point 2-Tone FFT,
fIN = 70MHz, 75MHz, –1dBFS,
105Msps
LTC2260-12: SNR vs Input
Frequency, –1dB, 2V Range,
105Msps
LTC2260-12: Shorted Input
Histogram
0
72
18000
–10
16000
71
–20
14000
–40
70
–60
–70
SNR (dBFS)
12000
–50
COUNT
10000
8000
–80
6000
–90
–100
4000
68
67
2000
–110
–120
0
10
20
30
40
FREQUENCY (MHz)
0
2044
50
2045
OUTPUT CODE
226112 G27
66
2048
90
65
SFDR (dBc AND dBFS)
90
60
LVDS OUTPUTS
80
70
dBc
60
50
40
55
CMOS OUTPUTS
50
30
45
20
70
350
dBFS
100
75
100 150 200 250 300
INPUT FREQUENCY (MHz)
LTC2260-12: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
110
95
80
50
226112 G29
LTC2260-12: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 105Msps
85
0
226112 G28
LTC2260-12: SFDR vs Input
Frequency, –1dB, 2V Range,
105Msps
SFDR (dBFS)
69
IVDD (mA)
AMPLITUDE (dBFS)
–30
10
65
0
50
100 150 200 250 300
INPUT FREQUENCY (MHz)
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
350
40
0
0
226112 G32
226112 G30
LTC2260-12: IOVDD vs Sample
Rate, 5MHz Sine Wave Input,
–1dB, 5pF on Each Data Output
LTC2259-12: Integral Nonlinearity
(INL)
72
1.0
0.8
3.5mA LVDS
71
0.6
70
SNR (dBFS)
IOVDD (mA)
30
INL ERROR (LSB)
35
25
1.75mA LVDS
20
69
68
15
0
0
0.2
0
–0.2
–0.6
67
1.8V CMOS
0.4
–0.4
10
5
100
226112 G33
LTC2260-12: SNR vs SENSE,
fIN = 5MHz, –1dB
45
40
25
50
75
SAMPLE RATE (Msps)
–0.8
1.2V CMOS
25
50
75
100
SAMPLE RATE (Msps)
226112 G34
66
–1.0
0.6
0.7
0.8
0.9
1
1.1
SENSE PIN (V)
1.2
1.3
226112 G35
0
1024
2048
3072
OUTPUT CODE
4096
226112 G41
226112f
12
LTC2261-12
LTC2260-12/LTC2259-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2259-12: Differential
Nonlinearity (DNL)
0
0
0.8
–10
–10
–20
–20
–30
–30
AMPLITUDE (dBFS)
DNL ERROR (LSB)
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1024
2048
3072
OUTPUT CODE
AMPLITUDE (dBFS)
1.0
0.6
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–100
–90
–100
–110
–120
–110
–120
4096
0
10
20
30
FREQUENCY (MHz)
226112 G42
0
40
LTC2259-12: 8k Point FFT, fIN = 140MHz
–1dBFS, 80Msps
–20
–20
–20
–30
–30
–30
–60
–70
–80
AMPLITUDE (dBFS)
0
–10
AMPLITUDE (dBFS)
0
–10
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–100
–90
–100
–90
–100
–110
–120
–110
–120
–110
–120
0
10
20
30
FREQUENCY (MHz)
0
40
10
20
30
FREQUENCY (MHz)
0
40
10
20
30
FREQUENCY (MHz)
LTC2259-12: SNR vs Input
Frequency, –1dB, 2V Range,
80Msps
LTC2259-12: Shorted Input
Histogram
18000
40
226114 G47
226114 G46
226112 G45
40
226112 G44
0
–50
20
30
FREQUENCY (MHz)
LTC2259-12: 8k Point 2-Tone FFT,
fIN = 70MHz, 75MHz, –1dBFS,
80Msps
–10
–40
10
226112 G43
LTC2259-12: 8k Point FFT, fIN = 70MHz
–1dBFS, 80Msps
AMPLITUDE (dBFS)
LTC2259-12: 8k Point FFT, fIN = 30MHz
–1dBFS, 80Msps
LTC2259-12: 8k Point FFT, fIN = 5MHz
–1dBFS, 80Msps
LTC2259-12: SFDR vs Input
Frequency, –1dB, 2V Range,
80Msps
72
95
71
90
70
85
16000
SNR (dBFS)
COUNT
12000
10000
8000
6000
4000
SFDR (dBFS)
14000
69
80
68
75
67
70
2000
0
2052
66
2054
OUTPUT CODE
2056
226112 G48
0
50
100 150 200 250 300
INPUT FREQUENCY (MHz)
350
226112 G49
65
0
50
100 150 200 250 300
INPUT FREQUENCY (MHz)
350
226112 G50
226112f
13
LTC2261-12
LTC2260-12/LTC2259-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2259-12: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 80Msps
LTC2259-12: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
55
110
100
dBFS
LVDS OUTPUTS
50
80
70
IVDD (mA)
SFDR (dBc AND dBFS)
90
dBc
60
50
45
CMOS OUTPUTS
40
30
40
20
10
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
35
0
0
20
40
60
SAMPLE RATE (Msps)
80
226112 G53
226112 G52
LTC2259-12: IOVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB, 5pF
on Each Data Output
LTC2259-12: SNR vs SENSE,
fIN = 5MHz, –1dB
45
72
40
3.5mA LVDS
71
35
70
SNR (dBFS)
IOVDD (mA)
30
25
1.75mA LVDS
20
15
68
10
1.2V CMOS
1.8V CMOS
5
0
69
0
20
40
60
SAMPLE RATE (Msps)
67
80
226112 G54
66
0.6
0.7
0.8
0.9 1.0 1.1
SENSE PIN (V)
1.2
1.3
226112 G55
PIN FUNCTIONS
PINS THAT ARE THE SAME FOR ALL DIGITAL OUTPUT
MODES
AIN+ (Pin 1): Positive Differential Analog Input.
AIN– (Pin 2): Negative Differential Analog Input.
GND (Pin 3): ADC Power Ground.
REFH (Pins 4, 5): ADC High Reference. Bypass to Pins
6, 7 with a 2.2μF ceramic capacitor and to ground with a
0.1μF ceramic capacitor.
REFL (Pins 6, 7): ADC Low Reference. Bypass to Pins
4, 5 with a 2.2μF ceramic capacitor and to ground with a
0.1μF ceramic capacitor.
PAR/SER (Pin 8): Programming Mode Selection Pin. Connect to ground to enable the serial programming mode.
CS, SCK, SDI, SDO become a serial interface that control
the A/D operating modes. Connect to VDD to enable the
parallel programming mode where CS, SCK, SDI become
parallel logic inputs that control a reduced set of the A/D
226112f
14
LTC2261-12
LTC2260-12/LTC2259-12
PIN FUNCTIONS
operating modes. PAR/SER should be connected directly
to ground or the VDD of the part and not be driven by a
logic signal.
VDD (Pins 9, 10, 40): 1.8V Analog Power Supply. Bypass
to ground with 0.1μF ceramic capacitors. Pins 9 and 10
can share a bypass capacitor.
ENC+ (Pin 11): Encode Input. Conversion starts on the
rising edge.
ENC – (Pin 12): Encode Complement Input. Conversion
starts on the falling edge.
CS (Pin 13): In serial programming mode, (PAR/SER =
0V), CS is the serial interface chip select input. When
CS is low, SCK is enabled for shifting data on SDI into
the mode control registers. In the parallel programming
mode (PAR/SER = VDD), CS controls the clock duty cycle
stabilizer. When CS is low, the clock duty cycle stabilizer is
turned off. When CS is high, the clock duty cycle stabilizer
is turned on. CS can be driven with 1.8V to 3.3V logic.
SCK (Pin 14): In serial programming mode, (PAR/SER =
0V), SCK is the serial interface clock input. In the parallel
programming mode (PAR/SER = VDD), SCK controls the
digital output mode. When SCK is low, the full-rate CMOS
output mode is enabled. When SCK is high, the double
data rate LVDS output mode (with 3.5mA output current)
is enabled. SCK can be driven with 1.8V to 3.3V logic.
SDI (Pin 15): In serial programming mode, (PAR/SER =
0V), SDI is the serial interface data input. Data on SDI is
clocked into the mode control registers on the rising edge
of SCK. In the parallel programming mode (PAR/SER =
VDD), SDI can be used to power down the part. When SDI
is low, the part operates normally. When SDI is high, the
part enters sleep mode. SDI can be driven with 1.8V to
3.3V logic.
SDO (Pin 16): In serial programming mode, (PAR/SER
= 0V), SDO is the optional serial interface data output.
Data on SDO is read back from the mode control registers
and can be latched on the falling edge of SCK. SDO is an
open-drain NMOS output that requires an external 2k
pull-up resistor to 1.8V-3.3V. If read back from the mode
control registers is not needed, the pull-up resistor is not
necessary and SDO can be left unconnected. In the parallel
programming mode (PAR/SER = VDD), SDO is not used
and should not be connected.
OGND (Pin 25): Output Driver Ground.
OVDD (Pin 26): Output Driver Supply. Bypass to ground
with a 0.1μF ceramic capacitor.
VCM (Pin 37): Common Mode Bias Output, Nominally
Equal to VDD/2. VCM should be used to bias the common
mode of the analog inputs. Bypass to ground with a 0.1μF
ceramic capacitor.
VREF (Pin 38): Reference Voltage Output. Bypass to ground
with a 1μF ceramic capacitor, nominally 1.25V.
SENSE (Pin 39): Reference Programming Pin. Connecting
SENSE to VDD selects the internal reference and a ±1V input
range. Connecting SENSE to ground selects the internal
reference and a ±0.5V input range. An external reference
between 0.625V and 1.3V applied to SENSE selects an
input range of ±0.8 • VSENSE.
FULL-RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OVDD)
D0 to D11 (Pins 19-24, 29-34): Digital Outputs. D11 is
the MSB.
CLKOUT– (Pin 27): Inverted version of CLKOUT+.
CLKOUT+ (Pin 28): Data Output Clock. The digital outputs
normally transition at the same time as the falling edge
of CLKOUT+. The phase of CLKOUT+ can also be delayed
relative to the digital outputs by programming the mode
control registers.
DNC (Pins 17, 18, 35): Do not connect these pins.
OF (Pin 36): Over/Under Flow Digital Output. OF is high
when an overflow or underflow has occurred.
DOUBLE DATA RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OVDD)
D0_1 to D10_11 (Pins 20, 22, 24, 30, 32, 34): Double Data
Rate Digital Outputs. Two data bits are multiplexed onto
each output pin. The even data bits (D0, D2, D4, D6, D8,
D10) appear when CLKOUT+ is low. The odd data bits (D1,
D3, D5, D7, D9, D11) appear when CLKOUT+ is high.
226112f
15
LTC2261-12
LTC2260-12/LTC2259-12
PIN FUNCTIONS
CLKOUT– (Pin 27): Inverted version of CLKOUT+.
CLKOUT+ (Pin 28): Data Output Clock. The digital outputs
normally transition at the same time as the falling and rising edges of CLKOUT+. The phase of CLKOUT+ can also
be delayed relative to the digital outputs by programming
the mode control registers.
DNC (Pins 17, 18, 19, 21, 23, 29, 31, 33, 35): Do not
connect these pins.
Internal 100Ω Termination Resistor Between the Pins
of Each LVDS Output Pair.
D0_1–/D0_1+ to D10_11–/D10_11+ (Pins 19/20, 21/22,
23/24, 29/30, 31/32, 33/34): Double Data Rate Digital
Outputs. Two data bits are multiplexed onto each differential
output pair. The even data bits (D0, D2, D4, D6, D8, D10)
appear when CLKOUT+ is low. The odd data bits (D1, D3,
D5, D7, D9, D11) appear when CLKOUT+ is high.
DOUBLE DATA RATE LVDS OUTPUT MODE
CLKOUT–/CLKOUT+ (Pins 27/28): Data Output Clock.
The digital outputs normally transition at the same time
as the falling and rising edges of CLKOUT+. The phase of
CLKOUT+ can also be delayed relative to the digital outputs
by programming the mode control registers.
All Pins Below Have LVDS Output Levels. The Output
Current Level is Programmable. There is an Optional
OF–/OF+ (Pins 35/36): Over/Under Flow Digital Output. OF+
is high when an overflow or underflow has occurred.
OF (Pin 36): Over/Under Flow Digital Output. OF is high
when an overflow or underflow has occurred.
FUNCTIONAL BLOCK DIAGRAM
AIN+
AIN–
VCM
INPUT
S/H
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
VDD
FIFTH PIPELINED
ADC STAGE
GND
VDD/2
0.1μF
VREF
1.25V
REFERENCE
SHIFT REGISTER
AND CORRECTION
1μF
RANGE
SELECT
SENSE
REFH
REF
BUF
REFL INTERNAL CLOCK SIGNALS
OVDD
OF
D11
DIFF
REF
AMP
MODE
CONTROL
REGISTERS
CLOCK/DUTY
CYCLE
CONTROL
•
•
•
OUTPUT
DRIVERS
D0
CLKOUT +
CLKOUT –
REFH
0.1μF
REFL
OGND
ENC+
ENC–
226112 F01
PAR/SER CS SCK SDI SDO
2.2μF
0.1μF
0.1μF
Figure 1. Functional Block Diagram
226112f
16
LTC2261-12
LTC2260-12/LTC2259-12
APPLICATIONS INFORMATION
CONVERTER OPERATION
The LTC2261-12/LTC2260-12/LTC2259-12 are low power
12-bit 125Msps/105Msps/80Msps A/D converters that are
powered by a single 1.8V supply. The analog inputs should
be driven differentially. The encode input can be driven
differentially or single-ended for lower power consumption. The digital outputs can be CMOS, double data rate
CMOS (to halve the number of output lines), or double
data rate LVDS (to reduce digital noise in the system.)
Many additional features can be chosen by programming
the mode control registers through a serial SPI port. See
the Serial Programming Mode section.
ANALOG INPUT
The analog input is a differential CMOS sample-and-hold
circuit (Figure 2). The inputs should be driven differentially
around a common mode voltage set by the VCM output
pin, which is nominally VDD/2. For the 2V input range, the
inputs should swing from VCM – 0.5V to VCM + 0.5V. There
should be 180° phase difference between the inputs.
INPUT DRIVE CIRCUITS
Input filtering
If possible, there should be an RC lowpass filter right at
the analog inputs. This lowpass filter isolates the drive
circuitry from the A/D sample-and-hold switching, and
also limits wideband noise from the drive circuitry. Figure 3
shows an example of an input RC filter. The RC component
values should be chosen based on the application’s input
frequency.
Transformer Coupled Circuits
Figure 3 shows the analog input being driven by an RF
transformer with a center-tapped secondary. The center
tap is biased with VCM, setting the A/D input at its optimal
DC level. At higher input frequencies a transmission line
50Ω
LTC2261-12
VDD
AIN+
RON
25Ω
10Ω
VDD
AIN–
0.1μF
ANALOG
INPUT
T1
1:1
25Ω
25Ω
RON
25Ω
10Ω
0.1μF
CSAMPLE
3.5pF
CPARASITIC
1.8pF
CSAMPLE
3.5pF
VDD
AIN+
LTC2261-12
0.1μF
12pF
25Ω
25Ω
T1: MA/COM MABAES0060
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
CPARASITIC
1.8pF
VCM
AIN–
226112 F03
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
1.2V
10k
ENC+
ENC–
10k
1.2V
226112 F02
Figure 2. Equivalent Input Circuit
226112f
17
LTC2261-12
LTC2260-12/LTC2259-12
APPLICATIONS INFORMATION
balun transformer (Figures 4 to 6) has better balance,
resulting in lower A/D distortion.
Amplifier Circuits
Figure 7 shows the analog input being driven by a high
speed differential amplifier. The output of the amplifier is AC
coupled to the A/D so the amplifier’s output common mode
voltage can be optimally set to minimize distortion.
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain
block is single-ended, then a transformer circuit (Figures 4
to 6) should convert the signal to differential before driving the A/D.
50Ω
VCM
0.1μF
0.1μF
50Ω
ANALOG
INPUT
VCM
AIN+
T2
T1
25Ω
LTC2261-12
0.1μF
0.1μF
0.1μF
ANALOG
INPUT
T2
T1
1.8pF
0.1μF
AIN+
25Ω
25Ω
AIN–
LTC2261-12
0.1μF
226112 F05
4.7pF
0.1μF
25Ω
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1LB
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
AIN–
226112 F04
T1: MA/COM MABA-007159-000000
T2: MA/COM MABAES0060
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
Figure 5. Recommended Front-End Circuit for Input
Frequencies from 170MHz to 270MHz
Figure 4. Recommended Front-End Circuit for Input
Frequencies from 70MHz to 170MHz
50Ω
VCM
0.1μF
0.1μF
2.7nH
ANALOG
INPUT
AIN+
LTC2261-12
0.1μF
25Ω
T1
0.1μF
25Ω
2.7nH
T1: MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
AIN–
226112 F06
Figure 6. Recommended Front-End Circuit for Input
Frequencies Above 270MHz
226112f
18
LTC2261-12
LTC2260-12/LTC2259-12
APPLICATIONS INFORMATION
Reference
The LTC2261-12/2260-12/2259-12 has an internal 1.25V
voltage reference. For a 2V input range using the internal
reference, connect SENSE to VDD. For a 1V input range
using the external reference, connect SENSE to ground.
For a 2V input range with an external reference, apply a
1.25V reference voltage to SENSE (Figure 9.)
The input range can be adjusted by applying a voltage to
SENSE that is between 0.625V and 1.30V. The input range
will then be 1.6 • VSENSE.
ANALOG
INPUT
200Ω
200Ω
25Ω
LTC2261-12
VREF
1.25V
0.1μF
AIN+
+
–
–
1.25V BANDGAP
REFERENCE
0.625V
RANGE
DETECT
AND
CONTROL
SENSE
BUFFER
INTERNAL ADC
HIGH REFERENCE
0.1μF
REFH
LTC2261-12
+
5Ω
1μF
TIE TO VDD FOR 2V RANGE;
TIE TO GND FOR 1V RANGE;
RANGE = 1.6 • VSENSE FOR
0.65V < VSENSE < 1.300V
VCM
HIGH SPEED
DIFFERENTIAL
0.1μF
AMPLIFIER
The VREF , REFH and REFL pins should be bypassed as
shown in Figure 8. The 0.1μF capacitor between REFH and
REFL should be as close to the pins as possible (not on
the back side of the circuit board).
12pF
0.1μF
25Ω
2.2μF
AIN–
226112 F07
0.1μF
0.8x
DIFF AMP
0.1μF
REFL
Figure 7. Front-End Circuit Using a High Speed
Differential Amplifier
INTERNAL ADC
LOW REFERENCE
226112 F08
Figure 8. Reference Circuit
VREF
1μF
LTC2261-12
1.25V
EXTERNAL
REFERENCE
SENSE
1μF
226112 F09
Figure 9. Using an External 1.25V Reference
226112f
19
LTC2261-12
LTC2260-12/LTC2259-12
APPLICATIONS INFORMATION
Encode Input
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10) and the single-ended encode mode
(Figure 11).
The differential encode mode is recommended for sinusoidal, PECL or LVDS encode inputs (Figures 12, 13). The
encode inputs are internally biased to 1.2V through 10k
equivalent resistance. The encode inputs can be taken
above VDD (up to 3.6V), and the common mode range
is from 1.1V to 1.6V. In the differential encode mode,
ENC– should stay at least 200mV above ground to avoid
falsely triggering the single-ended encode mode. For good
jitter performance ENC+ and ENC– should have fast rise
and fall times.
LTC2261-12
Clock Duty Cycle Stabilizer
For good performance the encode signal should have a
50%(±5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. If the encode
signal changes frequency or is turned off, the duty cycle
stabilizer circuit requires one hundred clock cycles to lock
onto the input clock. The duty cycle stabilizer is enabled
by mode control register A2 (serial programming mode),
or by CS (parallel programming mode).
25Ω
VDD
DIFFERENTIAL
COMPARATOR
VDD
The single-ended encode mode should be used with CMOS
encode inputs. To select this mode, ENC – is connected
to ground and ENC+ is driven with a square wave encode
input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V
to 3.3V CMOS logic levels can be used. The ENC+ threshold
is 0.9V. For good jitter performance ENC+ should have fast
rise and fall times.
0.1μF
ENC+
T1
1:4
100Ω
D1
LTC2261-12
100Ω
ENC–
15k
ENC+
0.1μF
226112 F12
T1: COILCRAFT WBC4 - 1WL
D1: AVAGO HSMS - 2822
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
ENC–
30k
226112 F10
Figure 12. Sinusoidal Encode Drive
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
0.1μF
PECL OR
LVDS
CLOCK
LTC2261-12
1.8V TO 3.3V
0V
ENC+
ENC–
ENC+
LTC2261-12
0.1μF
ENC–
30k
CMOS LOGIC
BUFFER
226112 F11
226112 F13
Figure 13. PECL or LVDS Encode Drive
Figure 11. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
226112f
20
LTC2261-12
LTC2260-12/LTC2259-12
APPLICATIONS INFORMATION
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken to
make the sampling clock have a 50%(±5%) duty cycle. The
duty cycle stabilizer should not be used below 5Msps.
When using double data rate CMOS at high sample rates
the SNR will degrade slightly (see Typical Performance
Characteristics section). DDR CMOS is not recommended
for sample frequencies above 100MHz.
Double Data Rate LVDS Mode
DIGITAL OUTPUTS
Digital Output Modes
The LTC2261-12/LTC2260-12/LTC2259-12 can operate in
three digital output modes: full rate CMOS, double data
rate CMOS (to halve the number of output lines), or double
data rate LVDS (to reduce digital noise in the system). The
output mode is set by mode control register A3 (serial
programming mode), or by SCK (parallel programming
mode). Note that double data rate CMOS cannot be selected
in the parallel programming mode.
Full-Rate CMOS Mode
In full-rate CMOS mode the 12 digital outputs (D0-D11),
overflow (OF), and the data output clocks (CLKOUT+,
CLKOUT–) have CMOS output levels. The outputs are
powered by OVDD and OGND which are isolated from the
A/D core power and ground. OVDD can range from 1.1V to
1.9V, allowing 1.2V through 1.8V CMOS logic outputs.
In double data rate LVDS mode, two data bits are multiplexed and output on each differential output pair.
There are 6 LVDS output pairs (D0_1+/D0_1– through
D10_11+/D10_11–) for the digital output data. Overflow
(OF+/OF –) and the data output clock (CLKOUT+/CLKOUT–)
each have an LVDS output pair.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode voltage. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OVDD and OGND which are
isolated from the A/D core power and ground. In LVDS
mode, OVDD must be 1.8V.
Programmable LVDS Output Current
For good performance the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
In LVDS mode, the default output driver current is 3.5mA.
This current can be adjusted by serially programming mode
control register A3. Available current levels are 1.75mA,
2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
Double Data Rate CMOS Mode
Optional LVDS Driver Internal Termination
In double data rate CMOS mode, two data bits are
multiplexed and output on each data pin. This reduces
the number of data lines by seven, simplifying board
routing and reducing the number of input pins needed
to receive the data. The 6 digital outputs (D0_1, D2_3,
D4_5, D6_7, D8_9, D10_11), overflow (OF), and the data
output clocks (CLKOUT+, CLKOUT–) have CMOS output
levels. The outputs are powered by OVDD and OGND which
are isolated from the A/D core power and ground. OVDD
can range from 1.1V to 1.9V, allowing 1.2V through 1.8V
CMOS logic outputs.
In most cases using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addition, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A3. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is increased by 1.6x to maintain about the same output
voltage swing.
For good performance the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
226112f
21
LTC2261-12
LTC2260-12/LTC2259-12
APPLICATIONS INFORMATION
Overflow Bit
The overflow output bit (OF) outputs a logic high when
the analog input is either overranged or underranged.
The overflow bit has the same pipeline latency as the
data bits.
Phase Shifting the Output Clock
In full-rate CMOS mode the data output bits normally
change at the same time as the falling edge of CLKOUT+,
so the rising edge of CLKOUT+ can be used to latch the
output data. In double data rate CMOS and LVDS modes
the data output bits normally change at the same time as
the falling and rising edges of CLKOUT+. To allow adequate
setup-and-hold time when latching the data, the CLKOUT+
signal may need to be phase shifted relative to the data
output bits. Most FPGAs have this feature; this is generally
the best place to adjust the timing.
The LTC2261-12/LTC2260-12/LTC2259-12 can also phase
shift the CLKOUT+/CLKOUT– signals by serially programming mode control register A2. The output clock can be
shifted by 0°, 45°, 90° or 135°. To use the phase shifting
feature the clock duty cycle stabilizer must be turned
on. Another control register bit can invert the polarity of
CLKOUT+ and CLKOUT–, independently of the phase shift.
The combination of these two features enables phase
shifts of 45° up to 315° (Figure 14).
DATA FORMAT
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially programming mode control register A4.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V RANGE)
OF
D11-D0
(OFFSET BINARY)
D11-D0
(2’s COMPLEMENT)
>+1.000000V
1
1111 1111 1111
0111 1111 1111
+0.999512V
0
1111 1111 1111
0111 1111 1111
+0.999024V
0
1111 1111 1110
0111 1111 1110
+0.000488V
0
1000 0000 0001
0000 0000 0001
0.000000V
0
1000 0000 0000
0000 0000 0000
–0.000488V
0
0111 1111 1111
1111 1111 1111
–0.000976V
0
0111 1111 1110
1111 1111 1110
–0.999512V
0
0000 0000 0001
1000 0000 0001
–1.000000V
0
0000 0000 0000
1000 0000 0000
≤–1.000000V
1
0000 0000 0000
1000 0000 0000
ENC+
D0-D11, OF
MODE CONTROL BITS
PHASE
SHIFT
CLKINV
CLKPHASE1
CLKPHASE0
0°
0
0
0
45°
0
0
1
90°
0
1
0
135°
0
1
1
180°
1
0
0
225°
1
0
1
270°
1
1
0
315°
1
1
1
CLKOUT+
226112 F14
Figure 14. Phase Shifting CLKOUT
226112f
22
LTC2261-12
LTC2260-12/LTC2259-12
APPLICATIONS INFORMATION
Digital Output Randomizer
Alternate Bit Polarity
Interference from the A/D digital outputs is sometimes
unavoidable. Digital interference may be from capacitive or
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
Another feature that reduces digital feedback on the circuit
board is the alternate bit polarity mode. When this mode
is enabled, all of the odd bits (D1, D3, D5, D7, D9, D11)
are inverted before the output buffers. The even bits (D0,
D2, D4, D6, D8, D10), OF and CLKOUT are not affected.
This can reduce digital currents in the circuit board ground
plane and reduce digital noise, particularly for very small
analog input signals.
The digital output is “randomized” by applying an exclusive-OR logic operation between the LSB and all other
data output bits. To decode, the reverse operation is applied—an exclusive-OR operation is applied between the
LSB and all other bits. The LSB, OF and CLKOUT outputs
are not affected. The output randomizer is enabled by
serially programming mode control register A4.
When there is a very small signal at the input of the A/D
that is centered around midscale, the digital outputs toggle
between mostly 1s and mostly 0s. This simultaneous
switching of most of the bits will cause large currents in
the ground plane. By inverting every other bit, the alternate bit polarity mode makes half of the bits transition
high while half of the bits transition low. To first order,
this cancels current flow in the ground plane, reducing
the digital noise.
CLKOUT
CLKOUT
PC BOARD
OF
OF
D11
D11/D0
D10
D2
RANDOMIZER
ON
D1
CLKOUT FPGA
OF
D11/D0
D10/D0
D11
•
•
•
D10/D0
D2/D0
D1/D0
LTC2261-12
D10
D2/D0
•
•
•
D2
D1/D0
D0
D1
D0
116112 F15
D0
D0
Figure 15. Functional Equivalent of Digital Output Randomizer
116112 F15
Figure 16. Unrandomizing a Randomized Digital
Output Signal
226112f
23
LTC2261-12
LTC2260-12/LTC2259-12
APPLICATIONS INFORMATION
The digital output is decoded at the receiver by inverting
the odd bits (D1, D3, D5, D7, D9, D11). The alternate bit
polarity mode is independent of the digital output randomizer—either, both or neither function can be on at the same
time. When alternate bit polarity mode is on, the data
format is offset binary and the 2’s complement control bit
has no effect. The alternate bit polarity mode is enabled
by serially programming mode control register A4.
Digital Output Test Patterns
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes that force the A/D data
outputs (OF, D11-D0) to known values:
REFH, and REFL. For the suggested values in Figure 8,
the A/D will stabilize after 2ms.
In nap mode the A/D core is powered down while the
internal reference circuits stay active, allowing faster
wake-up than from sleep mode. Recovering from nap
mode requires at least 100 clock cycles. If the application
demands very accurate DC settling then an additional
50μs should be allowed so the on-chip references can
settle from the slight temperature shift caused by the
change in supply current as the A/D leaves nap mode.
Nap mode is enabled by mode control register A1 in the
serial programming mode.
All 1s: All outputs are 1
DEVICE PROGRAMMING MODES
All 0s: All outputs are 0
The operating modes of the LTC2261-12 can be programmed by either a parallel interface or a simple serial
interface. The serial interface has more flexibility and
can program all available modes. The parallel interface
is more limited and can only program some of the more
commonly used modes.
Alternating: Outputs change from all 1s to all 0s on
alternating samples
Checkerboard: Outputs change from 1010101010101
to 0101010101010 on alternating samples
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the test patterns override all other formatting modes: 2’s
complement, randomizer, alternate-bit-polarity.
Output Disable
The digital outputs may be disabled by serially programming mode control register A3. All digital outputs including
OF and CLKOUT are disabled. The high impedance disabled
state is intended for long periods of inactivity—it is too
slow to multiplex a data bus between multiple converters
at full speed.
Sleep and Nap Modes
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire A/D converter is powered
down, resulting in 0.5mW power consumption. Sleep mode
is enabled by mode control register A1 (serial programming mode), or by SDI (parallel programming mode).
The amount of time required to recover from sleep mode
depends on the size of the bypass capacitors on VREF ,
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to VDD. The CS, SCK and SDI pins are binary logic
inputs that set certain operating modes. These pins can
be tied to VDD or ground, or driven by 1.8V, 2.5V or 3.3V
CMOS logic. Table 2 shows the modes set by CS, SCK
and SDI.
Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD)
PIN
DESCRIPTION
CS
Clock Duty Cycle Stabilizer Control Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
SCK
Digital Output Mode Control Bit
0 = Full-Rate CMOS Output Mode
1 = Double Data Rate LVDS Output Mode
(3.5mA LVDS Current, Internal Termination Off)
SDI
Power Down Control Bit
0 = Normal Operation
1 = Sleep Mode
226112f
24
LTC2261-12
LTC2260-12/LTC2259-12
APPLICATIONS INFORMATION
Serial Programming Mode
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become
a serial interface that program the A/D mode control
registers. Data is written to a register with a 16-bit serial
word. Data can also be read back from a register to verify
its contents.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first 16 rising edges of
SCK. Any SCK rising edges after the first 16 are ignored.
The data transfer ends when CS is taken high again.
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be written to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the timing
diagrams). During a read back command the register is
not updated and data on SDI is ignored.
The SDO pin is an open-drain output that pulls to ground
with a 200Ω impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required.
If serial data is only written and read back is not needed,
then SDO can be left floating and no pull-up resistor is
needed.
Table 3 shows a map of the mode control registers.
Software Reset
If serial programming is used, the mode control registers
should be programmed as soon as possible after the power
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset, bit D7 in the
reset register is written with a logic 1. After the reset is
complete, bit D7 is automatically set back to zero.
Table 3. Serial Programming Mode Register Map
REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7
D6
RESET
Bit 7
X
RESET
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
Software Reset Bit
0 = Not Used
1 = Software Reset. All Mode Control Registers are Reset to 00h. This Bit is Automatically Set Back to Zero After the Reset is Complete
Bits 6-0
Unused, Don’t Care Bits.
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
D7
X
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
PWROFF1
PWROFF0
Bits 7-2
Unused, Don’t Care Bits.
Bits 1-0
PWROFF1:PWROFF0
00 = Normal Operation
01 = Nap Mode
10 = Not Used
11 = Sleep Mode
Power Down Control Bits
226112f
25
LTC2261-12
LTC2260-12/LTC2259-12
APPLICATIONS INFORMATION
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
D7
X
D6
D5
D4
D3
D2
D1
D0
X
X
X
CLKINV
CLKPHASE1
CLKPHASE0
DCS
Bits 7-4
Unused, Don’t Care Bits.
Bit 3
CLKINV
Output Clock Invert Bit
0 = Normal CLKOUT Polarity (As Shown in the Timing Diagrams)
1 = Inverted CLKOUT Polarity
Bits 2-1
CLKPHASE1:CLKPHASE0
Output Clock Phase Delay Bits
00 = No CLKOUT Delay (As Shown in the Timing Diagrams)
01 = CLKOUT+/CLKOUT– Delayed by 45° (Clock Period • 1/8)
10 = CLKOUT+/CLKOUT– Delayed by 90° (Clock Period • 1/4)
11 = CLKOUT+/CLKOUT– Delayed by 135° (Clock Period • 3/8)
Note: If the CLKOUT Phase Delay Feature is Used, the Clock Duty Cycle Stabilizer Must Also be Turned On
Bit 0
DCS
Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h)
D7
D6
D5
D4
D3
D2
D1
D0
X
ILVDS2
ILVDS1
ILVDS0
TERMON
OUTOFF
OUTMODE1
OUTMODE0
Bit 7
Unused, Don’t Care Bit.
Bits 6-4
ILVDS2:ILVDS0 LVDS Output Current Bits
000 = 3.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
Bit 3
TERMON
LVDS Internal Termination Bit
0 = Internal Termination Off
1 = Internal Termination On. LVDS Output Driver Current is 1.6× the Current Set by ILVDS2:ILVDS0
Bit 2
OUTOFF
Output Disable Bit
0 = Digital Outputs are Enabled
1 = Digital Outputs are Disabled and Have High Output Impedance
Bits 1-0
OUTMODE1:OUTMODE0
Digital Output Mode Control Bits
00 = Full-Rate CMOS Output Mode
01 = Double Data Rate LVDS Output Mode
10 = Double Data Rate CMOS Output Mode
11 = Not Used
226112f
26
LTC2261-12
LTC2260-12/LTC2259-12
APPLICATIONS INFORMATION
REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h)
D7
X
D6
D5
D4
D3
D2
D1
D0
X
OUTTEST2
OUTTEST1
OUTTEST0
ABP
RAND
TWOSCOMP
Bit 7-6
Unused, Don’t Care Bits.
Bits 5-3
OUTTEST2:OUTTEST0
Digital Output Test Pattern Bits
000 = Digital Output Test Patterns Off
001 = All Digital Outputs = 0
011 = All Digital Outputs = 1
101 = Checkerboard Output Pattern. OF, D11-D0 Alternate Between 1 0101 1010 0101 and 0 1010 0101 1010
111 = Alternating Output Pattern. OF, D11-D0 Alternate Between 0 0000 0000 0000 and 1 1111 1111 1111
Note: Other Bit Combinations are not Used
Bit 2
ABP
Alternate Bit Polarity Mode Control Bit
0 = Alternate Bit Polarity Mode Off
1 = Alternate Bit Polarity Mode On
Bit 1
RAND
Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
Bit 0
TWOSCOMP Two’s Complement Mode Control Bit
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
Note: ABP = 1 forces the output format to be Offset Binary
GROUNDING AND BYPASSING
The LTC2261-12 requires a printed circuit board with a
clean unbroken ground plane. A multilayer board with
an internal ground plane is recommended. Layout for
the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital track
alongside an analog signal track or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, VREF, REFH and REFL pins. Bypass
capacitors must be located as close to the pins as possible.
Of particular importance is the 0.1μF capacitor between
REFH and REFL. This capacitor should be on the same
side of the circuit board as the A/D, and as close to the
device as possible (1.5mm or less). Size 0402 ceramic
capacitors are recommended. The larger 2.2μF capacitor
between REFH and REFL can be somewhat further away.
The VCM capacitor should be located as close to the pin
as possible. To make space for this the capacitor on VREF
can be further away or on the back of the PC board. The
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
The analog inputs, encode signals, and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
HEAT TRANSFER
Most of the heat generated by the LTC2261-12 is transferred
from the die through the bottom-side exposed pad and
package leads onto the printed circuit board. For good
electrical and thermal performance, the exposed pad must
be soldered to a large grounded pad on the PC board.
226112f
27
LTC2261-12
LTC2260-12/LTC2259-12
TYPICAL APPLICATIONS
LTC2261 Schematic
T2
MABAES0060
•
R9 10Ω
•
SENSE
R39
33.2Ω
1%
ANALOG INPUT
R10 10Ω
R40
33.2Ω
1%
C23
1μF
R14
1k
C51
4.7pF
C17
1μF
R16
100Ω
R15 100Ω
C12
0.1μF
C13
1μF
C19
0.1μF
40
39
38
37
VDD SENSE VREF VCM
R27 10Ω 1
R28 10Ω 2
3
4
C15
0.1μF
5
C20
2.2μF
6
7
C21
0.1μF
PAR/SER
8
9
10
C18
0.1μF
35
OF–
34
33
D11 D10
32
D9
DIGITAL
OUTPUTS
31
D8
30
AIN+
D7
AIN–
D6
GND
CLKOUT+
28
REFH
CLKOUT–
27
LTC2261CUJ
REFH
OVDD
REFL
OGND
REFL
D5
PAR/SER
D4
VDD
D3
VDD
D2
GND
41
ENCODE CLOCK
36
OF+
ENC+ ENC–
11
12
CS
13
SCK
SDI SDO DNC DNC
14
15
16
17
18
D0
19
D1
20
29
26
25
0VDD
C37
0.1μF
24
23
22
21
DIGITAL
OUTPUTS
R13
100Ω
226112 TA02
SPI BUS
226112f
28
LTC2261-12
LTC2260-12/LTC2259-12
TYPICAL APPLICATIONS
Silkscreen Top
Top Side
226112 TA04
226112 TA03
Inner Layer 2 GND
Inner Layer 3
226112 TA05
226112 TA06
226112f
29
LTC2261-12
LTC2260-12/LTC2259-12
TYPICAL APPLICATIONS
Inner Layer 4
Inner Layer 5 Power
226112 TA07
226112 TA08
Bottom Side
226112 TA09
226112f
30
LTC2261-12
LTC2260-12/LTC2259-12
PACKAGE DESCRIPTION
UJ Package
40-Lead Plastic QFN (6mm × 6mm)
(Reference LTC DWG # 05-08-1728 Rev Ø)
0.70 ±0.05
6.50 ±0.05
5.10 ±0.05
4.42 ±0.05
4.50 ±0.05
(4 SIDES)
4.42 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
6.00 ± 0.10
(4 SIDES)
0.75 ± 0.05
R = 0.10
TYP
R = 0.115
TYP
39 40
0.40 ± 0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
2
PIN 1 NOTCH
R = 0.45 OR
0.35 s 45°
CHAMFER
4.50 REF
(4-SIDES)
4.42 ±0.10
4.42 ±0.10
(UJ40) QFN REV Ø 0406
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25 ± 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
226112f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC2261-12
LTC2260-12/LTC2259-12
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PART NUMBER
DESCRIPTION
COMMENTS
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LTC2202
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LTC2203
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LTC2205
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LTC2206
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LTC2207
16-Bit, 105Msps, 3.3V ADC
900mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN
LTC2208
16-Bit, 130Msps, 3.3V ADC, LVDS Outputs
1250mW, 77.7dB SNR, 100dB SFDR, 64-Pin QFN
LTC2209
16-Bit, 160Msps, 3.3V ADC, LVDS Outputs
1450mW, 77.1dB SNR, 100dB SFDR, 64-Pin QFN
LTC2220
12-Bit, 170Msps ADC
890mW, 67.5dB SNR, 9mm × 9mm QFN Package
LTC2220-1
12-Bit, 185Msps, 3.3V ADC, LVDS Outputs
910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN
LTC2224
12-Bit, 135Msps, 3.3V ADC, High IF Sampling
630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN
LTC2249
14-Bit, 80Msps ADC
230mW, 73dB SNR, 5mm × 5mm QFN Package
LTC2250
10-Bit, 105Msps ADC
320mW, 61.6dB SNR, 5mm × 5mm QFN Package
LTC2251
10-Bit, 125Msps ADC
395mW, 61.6dB SNR, 5mm × 5mm QFN Package
LTC2252
12-Bit, 105Msps ADC
320mW, 70.2dB SNR, 5mm × 5mm QFN Package
LTC2253
12-Bit, 125Msps ADC
395mW, 70.2dB SNR, 5mm × 5mm QFN Package
LTC2254
14-Bit, 105Msps ADC
320mW, 72.5dB SNR, 5mm × 5mm QFN Package
LTC2255
14-Bit, 125Msps, 3V ADC, Lowest Power
395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN
LTC2259-14/
LTC2260-14/
LTC2261-14
14-Bit, 80/105/125Msps 1.8V ADCs,
Ultra-Low Power
89mW/106mW/127mW, 73.4dB SNR, 85dB SFDR
DDR LVDS/DDR CMOS/CMOS Outputs, 6mm × 6mm QFN Package
LTC2284
14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk
540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN
LTC2299
Dual 14-Bit, 80Msps ADC
230mW, 71.6dB SNR, 5mm × 5mm QFN Package
LTC5517
40MHz to 900MHz Direct Conversion Quadrature
Demodulator
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LTC5527
400MHz to 3.7GHz High Linearity Downconverting
Mixer
24.5dBm IIP3 at 900MHz, 23.5dBm IIP3 at 3.5GHz, NF = 12.5dB,
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LTC5557
400MHz to 3.8GHz High Linearity Downconverting
Mixer
23.7dBm IIP3 at 2.6GHz, 23.5dBm IIP3 at 3.5GHz, NF = 13.2dB,
3.3V Supply Operation, Integrated Transformer
LTC5575
800MHz to 2.7GHz Direct Conversion Quadrature
Demodulator
High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator
Integrated RF and LO Transformer
LTC6400-20
1.8GHz Low Noise, Low Distortion Differential ADC
Driver for 300MHz IF
Fixed Gain 10V/V, 2.1nV√Hz Total Input Noise, 3mm × 3mm QFN-16 Package
LTC6604-2.5/
LTC6604 -5/
LTC6604-10/
LTC6604-15
Dual Matched 2.5MHz, 5MHz, 10MHz, 15MHz Filter
with ADC Driver
Dual Matched 4th Order LP Filters with Differential Drivers. Low Noise, Low
Distortion Amplifiers
226112f
32 Linear Technology Corporation
LT 1208 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2008