LR645 High Input Voltage SMPS Start-up / Linear Regulator Features General Description ► ► ► ► ► ► The Supertex LR645 is a high input voltage, low output current linear regulator. It has a 3-terminal fixed output voltage version available in TO-92, TO-220 and SOT-89 packages, as well as an adjustable voltage version available in an 8lead SOIC package. The 3-terminal version functions like any other low voltage 3-terminal regulator except it allows the use of much higher input voltages. When used in a SMPS startup circuit, it eliminates the need for large power resistors. In this application, current is drawn from the high voltage line only during start-up. Only leakage current flows after start-up, thereby reducing the continuous power dissipation to a few milliwatts. Accepts inputs from 15V to 450V Output currents up to 3.0mA continuous, 30mA peak Supply current typically 50µA Line regulation typically 0.1mV/V Output can be trimmed from 8.0V to 12V Output current can be increased to 150mA with external FET Applications ► Off-line SMPS startup circuits (pulse loads) ► Low power off-line regulators ► Regulators for noisy inputs The adjustable voltage version allows trimming of the output voltage from 8.0V to 12V. This version can also be connected to an external depletion mode MOSFET for increased output current. When used in conjunction with Supertex depletion mode MOSFET DN2540N5, an output current of up to 150mA is achieved. Caution! The LR645 does NOT provide galvanic isolation. When operated from an AC line, potentially lethal voltages can be present on the IC. Adequate means of protecting the end user from such voltages must be provided by the circuit developer. Block Diagram VIN LR645 VOUT TRIM – + GATE GND LR645 Pin Configurations Ordering Information Device LR645 1 Package Option TO-92 TO-243AA TO-220 8-Lead SOIC LR645N3 LR645N8 LR645N5 LR645LG 8 TAB LR645N3-G LR645N8-G LR645N5-G LR645LG-G 1 8-Lead SOIC -G indicates package is RoHS compliant (‘Green’) 3 2 TO-243AA (SOT-89) TAB Thermal Characteristics 1 Package Power Dissipation @TA = 25OC SOIC 0.31W 156 400* TO-92 0.74W 125 170 TO-220 1.8W 8.3 70 TO-243AA 1.6W 15 78* θJC C/W θJA C/W O O 1 3 3 2 2 TO-220 TO-92 +VIN GND VOUT TRIM GATE TO-92 1 2 3 - - TO-243AA 1 2, TAB 3 - - TO-220 1 2, TAB 3 - - 8-Lead SO 1 3 4 5 7 * Mounted on FR4 board; 25mm x 25mm x 1.57mm Significant PD increase possible on ceramic substrate Package Markings Absolute Maximum Ratings Parameter Value YYWW Input voltage 450V LR645 Output voltage 15.5V Operating and storage temperature LLLL 8-Lead SOIC -55°C to +150OC Soldering temperature YY = Year Sealed WW = Week Sealed L = Lot Number = “Green” Packaging 300OC Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. LR6 = 2-week alpha date code TO-243AA Electrical Characteristics (Test conditions unless otherwise specified: TA = 25°C; VIN = 15 to 450V, COUT = 0.01µF) Symbol VOUT ΔVOUT Parameter Min Typ Max Units Conditions Output voltage 9.3 10 10.7 V No load Output voltage over temperature1 9.0 10 11.5 V TJ = - 40°C ≤ to + 125°C, No load Line regulation - 40 200 mV VIN = 15V to 400V, No load Load regulation - 150 400 mV VIN = 50V, IOUT = 0 to 3.0mA 15 - 450 V --- VIN Operating input voltage range IINQ Input quiescent current - 50 150 µA No Load IOFF VIN off-state leakage current - 0.1 10 µA VAUX ≥ VOUT +1V applied to VOUT pin 2 LR645 Symbol Parameter Min Typ Max Units Conditions IAUX Input current to VOUT - - 200 µA VAUX ≥ VOUT +1V applied to VOUT pin ΔVOUT/ ΔVIN Ripple rejection ratio1 50 60 - dB 120Hz, No Load Noise voltage1 - 25 - µV 0.01 to 100KHz IPEAK Output peak current2 - 30 - mA COUT = 10µF, VIN = 400V VAUX External voltage applied to VOUT - - 13.2 V --- No load en 8-lead, adjustable output voltage version only: Test conditions unless otherwise specified: TA = 25°C; VIN = 15 to 450V, COUT = 0.01µF VOUT ΔVOUT Output regulation trim range1 Load regulation at 8V trim 1 Load regulation at 12V trim1 8 - 12 V - 200 400 mV VIN = 15V, IOUT = 0 to 1.0mA - 100 400 mV VIN = 50V, IOUT = 0 to 3.0mA Notes: 1. Guaranteed by design, not tested in production. 2. Pulse test duration < 1.0msec, Duty cycle < 2% LR645: SMPS Start-Up Circuit One of the main applications for the LR645 is a start-up circuit for off-line switch-mode power supplies (SMPS), as shown in Figure1. A minimum output capacitance of 0.01µF is recommended for stability. The wide operating input voltage range of the LR645 allows the SMPS to operate and start-up from rectified AC or a DC voltage of 15V to 450V without adjustment. than the output voltage the LR645 turns OFF its internal high voltage input line and output voltage, allowing the auxiliary voltage to power the VCC line of the PWM IC. The input current drawn by the LR645 from the high voltage line after start-up will therefore only be leakage current of the internal MOSFET switch, which is typically 0.1µA. The 3-terminal version shown in Figure 1 has load regulation guaranteed from 0 to 3.0mA at a fixed nominal output voltage of 10V. Applications requiring higher output current and/or a different output voltage can use the 8 pin adjustable version. During start-up, the LR645 powers the VCC line of the PWM IC with a nominal output voltage of 10V. The auxiliary voltage connected through a diode to the VOUT pin of the LR645 will start to increase. When the auxiliary voltage becomes larger Figure 1: SMPS Start-Up Circuit + + 5.0V – VAUX = 12V 15V to 450V VCC VIN LR6 CIN GND PWM IC COUT – 3 LR645 LR645: High Current SMPS Start-Up Circuit The 8 lead version of the LR645 has connections for an external depletion-mode MOSFET for higher output current and external resistors for adjustable output voltage. As shown in Figure 2, the output current is increased to 150mA by using the Supertex 400V depletion-mode MOSFET DN2540. The maximum operating input voltage will be limited by the drainto-source breakdown voltage of the external MOSFET, but cannot exceed the 450V rating of the LR645. The output voltage can be adjusted from 8V to 12V with 2external resistors, R1 and R2. The ratio of R2/R1 determines the output voltage. R2 is connected between the VOUT and TRIM pins. R1 is connected between TRIM and GND pins. Figure 5 is a curve showing output voltage versus resistor ratio R2/R1. The optimum range for R1 + R2 is 200KΩ to 300KΩ. This minimizes loading and optimizes accuracy of the output voltage. Figure 5 uses an R1 + R2 of 250KΩ. Figure 2: High Current SMPS Start-Up Circuit + + 5.0V DN2540 – VAUX = 12V GATE 15V to 400V VCC VOUT LR645 CIN PWM IC R2 COUT TRIM GND R1 – Note: When used with the DN25, +VIN is not connected on the LR6. LR645: Off Line Linear Regulator Circuits requiring low voltages to operate logic and analog circuits benefit from the LR645. The conventional use of step down transformers can be eliminated, thereby saving space and cost. Some examples of these applications are: proximity controlled light switches, street lamp controls, and low voltage power supplies for appliances such as washing machines, dishwashers, and refrigerators. Figure 3 shows the LR645 as a pre-regulator to a precisionregulator for high precision regulation. Higher output current is also possible by using an external depletion-mode MOSFET DN2540N5 as shown in Figure 4. Power Dissipation Considerations The LR645 is a true linear regulator. Its power dissipation istherefore a function of input voltage and output load current. Forexample, if the LR645 is providing a continuous load current of 3mAat 10V while its input voltage is 400V, total dissipation in the LR645 will be: PDISS= (VIN - VOUT) x (IOUT + IMAX QUIESCENT) = (400V - 10V) x (3.0mA + 150µA) = 1.23 Watts The wide operating input voltage range of 15V to 450V as well as the ripple rejection ratio of 50dB minimum allows the use of a small, high voltage input capacitor. The input AC line can be either full-wave or half-wave rectified. A minimum output capacitance of 0.01µF is recommended for output stability. Figure 3: Cascading for Precision Max 875 ACSA LR6 AC Line 24V to 277V CIN 1.0µF COUT 0.1µF The 1.23 watts is for continuous operation. This is within the dissipation capabilities of the TO-220 and SOT-89 packages. See the thermal characteristics chart on page 2 for deratings. For SMPS start-up applications, the output current is usually required only during start-up. This duration depends upon the auxiliary supply output capacitor and COUT, but is typically a few hundred milliseconds. All package types of the LR645 have been characterized for use with a COUT of at least 10µF, and an AC line of 277V. 5.000V ± 0.002V @ 0 to 3mA 4 LR645 Figure 4: High Current Regulation DN2540N5 AC Line 24V to 277V GATE VOUT LR645LG 5.0V REG CIN COUT GND Figure 5: Typical Output Voltage vs Resistor Ratio Output Voltage (V) 12 10 R1 + R2 = 250KΩ 8 2.5 3.0 3.5 Resistor Ratio (R2/R1) 5 4.0 5.0V + 0 to 150mA – LR645 8-Lead SOIC (Narrow Body) Package Outline (LG/TG) 4.9x3.9mm body, 1.75mm height (max), 1.27mm pitch D θ1 8 E E1 L2 Note 1 (Index Area D/2 x E1/2) L 1 θ L1 Top View Gauge Plane Seating Plane View B A View B Note 1 h h A2 A Seating Plane b e A1 A Side View View A-A Note 1: This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. Symbol MIN Dimension (mm) NOM MAX A A1 A2 b D E E1 1.35 0.10 1.25 0.31 4.80 5.80 3.80 1.75 0.25 1.50 0.51 4.90 5.00 6.00 6.20 JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005. Drawings not to scale. 6 3.90 4.00 e 1.27 BSC h L 0.25 0.40 0.50 1.27 L1 1.04 REF L2 0.25 BSC θ θ1 0O 5O - - 8 O 15O LR645 3-Lead TO-92 Package Outline (N3) D A 1 Seating Plane 2 3 L b C e1 e Side View Front View E1 E 3 1 2 Bottom View Symbol Dimension (inches) A b C D E E1 e e1 L MIN .170 .014 .014 .175 .125 .800 .095 .045 .500 NOM - - - - - - - - - MAX .210 .022 .022 .205 .165 .105 .105 .055 - Drawings not to scale. 7 LR645 3-Lead TO-220 (Power Package) Package Outline (N5) A E E2 Seating Plane A ΦP Thermal Pad E A1 Q H1 4 D2 D D1 Chamfer Optional 1 3 2 E1 L Detail B A2 c e Front View A Side View 1 View A - A 3 2 L1 b b2 Detail B Symbol Dimension (inches) A A1 A2 b b2 c D D1 D2 E E1 E2 MIN .140 .020 .080 .015 .045 .014 .560 .330 .480 .380 .270 - NOM - - - .027 .057 - - - - - - - MAX .190 .055 .115 .040 .070 .024 .650 .355 .507 .420 .350 .030 JEDEC Registration TO-220, Variation AB, Issue K, April 2002. Drawings not to scale. 8 e .100 BSC H1 L L1 Q ΦP .230 .500 - .100 .139 - - - - - .270 .580 .250 .135 .161 LR645 3-Lead TO-243AA (SOT-89) Package Outline (N8) D D1 C 4 E1 E H 1 3 2 L b e b1 A e1 Top View Symbol MIN Dimensions (mm) Side View A b b1 C D D1 E E1 1.40 0.44 0.36 0.35 4.40 1.62 2.29 2.13 NOM - - - - - - - - MAX 1.60 0.56 0.48 0.44 4.60 1.83 2.60 2.29 e e1 1.50 BSC 3.00 BSC H L 3.94 0.89 - - 4.25 1.20 JEDEC Registration TO-243, Variation AA, Issue C, July 1986. Drawings not to scale. (The package drawings in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-LR645 B050807 9