AD ADA4661-2ARMZ-RL 18 v, precision, 725 a, 4 mhz, cmos rrio operational amplifier Datasheet

18 V, Precision, 725 µA, 4 MHz,
CMOS RRIO Operational Amplifier
ADA4661-2
Data Sheet
PIN CONNECTION DIAGRAMS
Low power at high voltage (18 V): 725 μA maximum
Low offset voltage
150 µV maximum at VSY/2
300 µV maximum over entire common-mode range
Low input bias current: 15 pA maximum
Gain bandwidth product: 4 MHz typical at AV = 100
Unity-gain crossover: 4 MHz typical
−3 dB closed-loop bandwidth: 2.1 MHz typical
Single-supply operation: 3 V to 18 V
Dual-supply operation: ±1.5 V to ±9 V
Unity-gain stable
OUT A 1
ADA4661-2
+IN A 3
TOP VIEW
(Not to Scale)
V– 4
8
V+
7
OUT B
6
–IN B
5
+IN B
Figure 1. 8-Lead MSOP
OUT A 1
+IN A 3
8 V+
ADA4661-2
TOP VIEW
(Not to Scale)
V– 4
7 OUT B
6 –IN B
5 +IN B
NOTES
1. CONNECT THE EXPOSED PAD TO V– OR
LEAVE IT UNCONNECTED.
11366-002
–IN A 2
APPLICATIONS
Figure 2. 8-Lead LFCSP
Current shunt monitors
Active filters
Portable medical equipment
Buffer/level shifting
High impedance sensor interfaces
Battery powered instrumentation
250
VSY = 18V
200
150
VOS (μV)
100
GENERAL DESCRIPTION
50
0
–50
The ADA4661-2 is a dual, precision, rail-to-rail input/output
amplifier optimized for low power, high bandwidth, and wide
operating supply voltage range applications.
The ADA4661-2 is specified over the extended industrial
temperature range (−40°C to +125°C) and is available in
8-lead MSOP and 8-lead LFCSP (3 mm × 3 mm) packages.
–100
–150
–200
–250
0
1.5
3.0
4.5
6.0
7.5
9.0 10.5 12.0 13.5 15.0 16.5 18.0
VCM (V)
11366-011
The ADA4661-2 performance is guaranteed at 3.0 V, 10 V,
and 18 V power supply voltages. It is an excellent selection for
applications that use single-ended supplies of 3.3 V, 5 V, 10 V, 12
V and 15 V, and dual supplies of ±2.5 V, ±3.3 V, and ±5 V. It
uses the Analog Devices, Inc., patented DigiTrim® trimming
technique, which achieves low offset voltage. Additionally, the
unique design architecture of the ADA4661-2 allows it to have
excellent power supply rejection, common-mode rejection, and
offset voltage when operating in the common-mode voltage
range of −VSY + 1.5 V to +VSY − 1.5 V.
Rev. 0
–IN A 2
11366-001
FEATURES
Figure 3. Input Offset Voltage vs. Common-Mode Voltage
Table 1. Precision Low Power Op Amps (<1 mA)
Supply Voltage
Single
Dual
Quad
5V
ADA4505-1
AD8500
ADA4505-2
AD8502
AD8506
ADA4505-4
AD8504
AD8508
12 V to 16 V
OP196
30 V
OP777
AD8657
OP296
ADA4661-2
ADA4666-2
AD8659
OP496
ADA4096-2
OP727
AD8682
AD8622
ADA4096-4
OP747
AD8684
AD8624
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Technical Support
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ADA4661-2
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Stage ................................................................................... 22
Applications ....................................................................................... 1
Gain Stage .................................................................................... 23
General Description ......................................................................... 1
Output Stage................................................................................ 23
Pin Connection Diagrams ............................................................... 1
Maximum Power Dissipation ................................................... 23
Revision History ............................................................................... 2
Rail-to-Rail Input and Output .................................................. 23
Specifications..................................................................................... 3
Comparator Operation .............................................................. 24
Electrical Characteristics—18 V Operation ............................. 3
EMI Rejection Ratio .................................................................. 25
Electrical Characteristics—10 V Operation ............................. 5
Current Shunt monitor .............................................................. 25
Electrical Characteristics—3.0 V Operation ............................ 7
Active Filters ............................................................................... 25
Absolute Maximum Ratings ............................................................ 9
Capacitive Load Drive ............................................................... 26
Thermal Resistance ...................................................................... 9
Noise Considerations with High Impedance Sources ........... 28
ESD Caution .................................................................................. 9
Outline Dimensions ....................................................................... 29
Pin Configurations and Function Descriptions ......................... 10
Ordering Guide .......................................................................... 29
Typical Performance Characteristics ........................................... 11
Applications Information .............................................................. 22
REVISION HISTORY
7/13—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
Data Sheet
ADA4661-2
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—18 V OPERATION
VSY = 18 V, VCM = VSY/2 V, TA = 25°C, unless otherwise specified.
Table 2.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Offset Voltage Drift
Input Bias Current
Symbol
Test Conditions/Comments
Min
VOS
ΔVOS/ΔT
IB
VCM = 1.5 V to 16.5 V
VCM = 1.5 V to 16.5 V; −40°C ≤ TA ≤ +125°C
VCM = 0 V to 18 V
VCM = 0 V to 18 V; −40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Typ
Max
Unit
30
150
150
500
300
600
3.1
15
100
900
11
30
300
18
µV
µV
µV
µV
µV
μV/°C
pA
pA
pA
pA
pA
pA
V
dB
dB
dB
dB
dB
dB
0.6
0.5
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
Large Signal Voltage Gain
Input Resistance
Differential Mode
Common Mode
Input Capacitance
Differential Mode
Common Mode
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Continuous Output Current
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current per Amplifier
CMRR
AVO
VCM = 1.5 V to 16.5 V
VCM = 1.5 V to 16.5 V; −40°C ≤ TA ≤ +125°C
VCM = 0 V to 18 V
VCM = 0 V to 18 V; −40°C ≤ TA ≤ +125°C
RL = 100 kΩ, VOUT = 0.5 V to 17.5 V
−40°C ≤ TA ≤ +125°C
0
115
110
100
91
120
120
135
118
147
RINDM
RINCM
>10
>10
GΩ
GΩ
CINDM
CINCM
8.5
3
pF
pF
17.97
40
±220
V
V
V
V
mV
mV
mV
mV
mA
mA
0.2
Ω
145
dB
dB
µA
µA
VOH
VOL
IOUT
ISC
ZOUT
PSRR
ISY
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 1 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 1 kΩ to VCM
−40°C ≤ TA ≤ +125°C
Dropout voltage = 1 V
Pulse width = 10 ms; refer to the Maximum
Power Dissipation section
f = 100 kHz, AV = 1
17.95
17.94
17.6
17.58
VSY = 3.0 V to 18 V
−40°C ≤ TA ≤ +125°C
IOUT = 0 mA
−40°C ≤ TA ≤ +125°C
120
120
Rev. 0 | Page 3 of 32
17.79
14
120
630
25
40
200
300
725
975
ADA4661-2
Parameter
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Unity-Gain Crossover
−3 dB Closed-Loop Bandwidth
Phase Margin
Settling Time to 0.1%
Channel Separation
EMI Rejection Ratio of +IN x
f = 400 MHz
f = 900 MHz
f = 1800 MHz
f = 2400 MHz
NOISE PERFORMANCE
Total Harmonic Distortion Plus
Noise
Bandwidth = 80 kHz
Bandwidth = 500 kHz
Peak-to-Peak Noise
Voltage Noise Density
Current Noise Density
Data Sheet
Symbol
Test Conditions/Comments
SR
GBP
UGC
f−3 dB
ΦM
tS
CS
EMIRR
RS = 1 kΩ, RL = 10 kΩ, CL = 10 pF, AV = 1
VIN = 10 mV p-p, RL = 10 kΩ, CL = 10 pF, AV = 100
VIN = 10 mV p-p, RL = 10 kΩ, CL = 10 pF, AVO = 1
VIN = 10 mV p-p, RL = 10 kΩ, CL = 10 pF, AV = 1
VIN = 10 mV p-p, RL = 10 kΩ, CL = 10 pF, AVO = 1
VIN = 1 V step, RL = 10 kΩ, CL = 10 pF
VIN = 17.9 V p-p, f = 10 kHz, RL = 10 kΩ
VIN = 100 mV peak (200 mV p-p)
THD + N
en p-p
en
in
Min
Typ
Max
Unit
2
4
4
2.1
60
1.3
80
V/µs
MHz
MHz
MHz
Degrees
µs
dB
34
42
50
60
dB
dB
dB
dB
0.0004
0.0008
3
18
14
360
%
%
µV p-p
nV/√Hz
nV/√Hz
fA/√Hz
AV = 1, VIN = 5.4 V rms at 1 kHz
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 10 kHz
f = 1 kHz
Rev. 0 | Page 4 of 32
Data Sheet
ADA4661-2
ELECTRICAL CHARACTERISTICS—10 V OPERATION
VSY = 10 V, VCM = VSY/2 V, TA = 25°C, unless otherwise specified.
Table 3.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Offset Voltage Drift
Input Bias Current
Symbol
Test Conditions/Comments
Min
VOS
ΔVOS/ΔT
IB
VCM = 1.5 V to 8.5 V
VCM = 1.5 V to 8.5 V; −40°C ≤ TA ≤ +125°C
VCM = 0 V to 10 V
VCM = 0 V to 10 V; −40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Typ
Max
Unit
30
150
150
450
300
600
3.1
15
80
750
11
30
270
10
µV
µV
µV
µV
µV
μV/°C
pA
pA
pA
pA
pA
pA
V
dB
dB
dB
dB
dB
dB
0.6
0.25
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
Large Signal Voltage Gain
Input Resistance
Differential Mode
Common Mode
Input Capacitance
Differential Mode
Common Mode
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Continuous Output Current
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current per Amplifier
CMRR
AVO
VCM = 1.5 V to 8.5 V
VCM = 1.5 V to 8.5 V; −40°C ≤ TA ≤ +125°C
VCM = 0 V to 10 V
VCM = 0 V to 10 V; −40°C ≤ TA ≤ +125°C
RL = 100 kΩ, VOUT = 0.5 V to 9.5 V
−40°C ≤ TA ≤ +125°C
0
115
115
95
86
120
120
140
114
145
RINDM
RINCM
>10
>10
GΩ
GΩ
CINDM
CINCM
8.5
3
pF
pF
9.98
40
±220
V
V
V
V
mV
mV
mV
mV
mA
mA
0.2
Ω
145
dB
dB
µA
µA
VOH
VOL
IOUT
ISC
ZOUT
PSRR
ISY
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 1 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 1 kΩ to VCM
−40°C ≤ TA ≤ +125°C
Dropout voltage = 1 V
Pulse width = 10 ms; refer to the Maximum
Power Dissipation section
f = 100 kHz, AV = 1
9.96
9.96
9.7
9.7
VSY = 3.0 V to 18 V
−40°C ≤ TA ≤ +125°C
IOUT = 0 mA
−40°C ≤ TA ≤ +125°C
120
120
Rev. 0 | Page 5 of 32
9.88
10
77
620
15
30
110
200
725
975
ADA4661-2
Parameter
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Unity-Gain Crossover
−3 dB Closed-Loop Bandwidth
Phase Margin
Settling Time to 0.1%
Channel Separation
EMI Rejection Ratio of +IN x
f = 400 MHz
f = 900 MHz
f = 1800 MHz
f = 2400 MHz
NOISE PERFORMANCE
Total Harmonic Distortion Plus Noise
Bandwidth = 80 kHz
Bandwidth = 500 kHz
Peak-to-Peak Noise
Voltage Noise Density
Current Noise Density
Data Sheet
Symbol
Test Conditions/Comments
SR
GBP
UGC
f−3 dB
ΦM
tS
CS
EMIRR
RS = 1 kΩ, RL = 10 kΩ, CL = 10 pF, AV = 1
VIN = 10 mV p-p, RL = 10 kΩ, CL = 10 pF, AV = 100
VIN = 10 mV p-p, RL = 10 kΩ, CL = 10 pF, AVO = 1
VIN = 10 mV p-p, RL = 10 kΩ, CL = 10 pF, AV = 1
VIN = 10 mV p-p, RL = 10 kΩ, CL = 10 pF, AVO = 1
VIN = 1 V step, RL = 10 kΩ, CL = 10 pF
VIN = 9.9 V p-p, f = 10 kHz, RL = 10 kΩ
VIN = 100 mV peak (200 mV p-p)
THD + N
en p-p
en
in
Min
Typ
Max
Unit
1.8
4
4
2.1
60
1.3
85
V/µs
MHz
MHz
MHz
Degrees
µs
dB
34
42
50
60
dB
dB
dB
dB
0.0004
0.0008
3
18
14
360
%
%
µV p-p
nV/√Hz
nV/√Hz
fA/√Hz
AV = 1, VIN = 2.2 V rms at 1 kHz
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 10 kHz
f = 1 kHz
Rev. 0 | Page 6 of 32
Data Sheet
ADA4661-2
ELECTRICAL CHARACTERISTICS—3.0 V OPERATION
VSY = 3.0 V, VCM = VSY/2 V, TA = 25°C, unless otherwise specified.
Table 4.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Offset Voltage Drift
Input Bias Current
Symbol
Test Conditions/Comments
Min
VOS
ΔVOS/ΔT
IB
VCM = VSY/2; −40°C ≤ TA ≤ +125°C
VCM = 0 V to 3.0 V
VCM = 0 V to 3.0 V; −40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Typ
Max
Unit
30
150
450
300
600
3.1
8
45
650
11
30
270
3
µV
µV
µV
µV
μV/°C
pA
pA
pA
pA
pA
pA
V
dB
dB
dB
dB
0.6
0.15
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
CMRR
Large Signal Voltage Gain
AVO
Input Resistance
Differential Mode
Common Mode
Input Capacitance
Differential Mode
Common Mode
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Continuous Output Current
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current per Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Unity-Gain Crossover
−3 dB Closed-Loop Bandwidth
Phase Margin
Settling Time to 0.1%
Channel Separation
VCM = 0 V to 3.0 V
VCM = 0 V to 3.0 V; −40°C ≤ TA ≤ +125°C
RL = 100 kΩ, VOUT = 0.5 V to 2.5 V
−40°C ≤ TA ≤ +125°C
0
85
75
105
105
100
130
RINDM
RINCM
>10
>10
GΩ
GΩ
CINDM
CINCM
8.5
3
pF
pF
2.99
30
±220
V
V
V
V
mV
mV
mV
mV
mA
mA
0.2
Ω
145
dB
dB
µA
µA
VOH
VOL
IOUT
ISC
ZOUT
PSRR
ISY
SR
GBP
UGC
f−3 dB
ΦM
tS
CS
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 1 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 1 kΩ to VCM
−40°C ≤ TA ≤ +125°C
Dropout voltage = 1 V
Pulse width = 10 ms; refer to the Maximum
Power Dissipation section
f = 100 kHz, AV = 1
2.98
2.98
2.9
2.9
VSY = 3.0 V to 18 V
−40°C ≤ TA ≤ +125°C
IOUT = 0 mA
−40°C ≤ TA ≤ +125°C
120
120
RS = 1 kΩ, RL = 10 kΩ, CL = 10 pF, AV = 1
VIN = 10 mV p-p, RL = 10 kΩ, CL = 10 pF, AV = 100
VIN = 10 mV p-p, RL = 10 kΩ, CL = 10 pF, AVO = 1
VIN = 10 mV p-p, RL = 10 kΩ, CL = 10 pF, AV = 1
VIN = 10 mV p-p, RL = 10 kΩ, CL = 10 pF, AVO = 1
VIN = 1 V step, RL = 10 kΩ, CL = 10 pF
VIN = 2.9 V p-p, f = 10 kHz, RL = 10 kΩ
Rev. 0 | Page 7 of 32
2.96
4
25
615
1.7
4
4
1.7
60
1.3
90
8
15
40
65
725
975
V/µs
MHz
MHz
MHz
Degrees
µs
dB
ADA4661-2
Parameter
EMI Rejection Ratio of +IN x
f = 400 MHz
f = 900 MHz
f = 1800 MHz
f = 2400 MHz
NOISE PERFORMANCE
Total Harmonic Distortion Plus Noise
Bandwidth = 80 kHz
Bandwidth = 500 kHz
Peak-to-Peak Noise
Voltage Noise Density
Current Noise Density
Data Sheet
Symbol
EMIRR
THD + N
en p-p
en
in
Test Conditions/Comments
VIN = 100 mV peak (200 mV p-p)
Min
Typ
Max
Unit
34
42
50
60
dB
dB
dB
dB
0.002
0.003
3
18
14
360
%
%
µV p-p
nV/√Hz
nV/√Hz
fA/√Hz
AV = 1, VIN = 0.44 V rms at 1 kHz
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 10 kHz
f = 1 kHz
Rev. 0 | Page 8 of 32
Data Sheet
ADA4661-2
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 5.
Parameter
Supply Voltage
Input Voltage
Input Current1
Differential Input Voltage
Output Short-Circuit
Duration to GND
Temperature Range
Storage
Operating
Junction
Lead Temperature
(Soldering, 60 sec)
ESD
Human Body Model2
Machine Model3
Field-Induced ChargedDevice Model (FICDM)4
Rating
20.5 V
(V−) − 300 mV to (V+) + 300 mV
±10 mA
Limited by maximum input
current
Refer to the Maximum Power
Dissipation section
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages using a
standard 4-layer JEDEC board. The exposed pad of the LFCSP
package is soldered to the board.
Table 6. Thermal Resistance
Package Type
8-Lead MSOP
8-Lead LFCSP
1
θJA
142
83.5
θJC is measured on the top surface of the package.
ESD CAUTION
4 kV
400 V
1.25 kV
The input pins have clamp diodes to the power supply pins and to each
other. Limit the input current to 10 mA or less when input signals exceed the
power supply rail by 0.3 V.
2
Applicable standard: MIL-STD-883, Method 3015.7.
3
Applicable standard: JESD22-A115-A (ESD machine model standard of
JEDEC).
4
Applicable Standard JESD22-C101C (ESD FICDM standard of JEDEC).
1
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 9 of 32
θJC
45
48.51
Unit
°C/W
°C/W
ADA4661-2
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
OUT A 1
+IN A 3
–IN A 2
ADA4661-2
+IN A 3
TOP VIEW
(Not to Scale)
V– 4
8
V+
7
OUT B
6
–IN B
5
+IN B
V– 4
ADA4661-2
TOP VIEW
(Not to Scale)
7 OUT B
6 –IN B
5 +IN B
NOTES
1. CONNECT THE EXPOSED PAD TO V– OR
LEAVE IT UNCONNECTED.
11366-004
OUT A 1
8 V+
Figure 4. Pin Configuration, 8-Lead MSOP
11366-005
–IN A 2
Figure 5. Pin Configuration, 8-Lead LFCSP
Table 7. Pin Function Descriptions
Pin No. 1
8-Lead MSOP 8-Lead LFCSP
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
N/A
92
1
2
Mnemonic
OUT A
−IN A
+IN A
V−
+IN B
−IN B
OUT B
V+
EPAD
Description
Output, Channel A.
Negative Input, Channel A.
Positive Input, Channel A.
Negative Supply Voltage.
Positive Input, Channel B.
Negative Input, Channel B.
Output, Channel B.
Positive Supply Voltage.
Exposed Pad. For the 8-lead LFCSP only, connect the exposed pad to V− or leave it
unconnected.
N/A means not applicable.
The exposed pad is not shown in the pin configuration diagram, Figure 5.
Rev. 0 | Page 10 of 32
Data Sheet
ADA4661-2
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
80
90
VSY = 3V
VCM = VSY/2
600 CHANNELS
VSY = 18V
VCM = VSY/2
600 CHANNELS
80
NUMBER OF AMPLIFIERS
60
50
40
30
20
70
60
50
40
30
140
11366-009
120
80
100
60
40
0
20
–20
–40
–60
Figure 9. Input Offset Voltage Distribution
18
VSY = 3V
VCM = VSY/2
–40°C ≤ TA ≤ +125°C
100 CHANNELS
14
12
10
8
6
14
12
10
8
6
4
4
2
2
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
TCVOS (µV/°C)
0
11366-007
0
0
VSY = 18V
VCM = VSY/2
–40°C ≤ TA ≤ +125°C
100 CHANNELS
16
NUMBER OF AMPLIFIERS
16
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
TCVOS (µV/°C)
Figure 7. Input Offset Voltage Drift Distribution
11366-010
18
Figure 10. Input Offset Voltage Drift Distribution
250
250
VSY = 3V
20 CHANNELS
200
150
100
100
50
50
VOS (μV)
150
0
0
–50
–100
–150
–150
–200
–200
–250
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
VCM (V)
3.0
11366-008
–50
–100
0
VSY = 18V
20 CHANNELS
200
Figure 8. Input Offset Voltage vs. Common-Mode Voltage
–250
0
1.5
3.0
4.5
6.0
7.5
9.0 10.5 12.0 13.5 15.0 16.5 18.0
VCM (V)
Figure 11. Input Offset Voltage vs. Common-Mode Voltage
Rev. 0 | Page 11 of 32
11366-011
NUMBER OF AMPLIFIERS
–80
VOS (µV)
Figure 6. Input Offset Voltage Distribution
VOS (μV)
–100
–140
140
VOS (µV)
11366-006
120
80
100
60
40
0
20
–20
–40
–60
0
–80
0
–100
10
–120
10
–120
20
–140
NUMBER OF AMPLIFIERS
70
ADA4661-2
Data Sheet
350
350
VSY = 18V
20 CHANNELS AT –40°C AND +85°C
VSY = 3V
20 CHANNELS AT –40°C AND +85°C
250
250
150
VOS (μV)
50
–50
50
–50
–150
–150
–250
–250
16.5
VCM (V)
11366-015
VCM (V)
18.0
3.0
15.0
2.7
13.5
2.4
12.0
2.1
10.5
1.8
9.0
1.5
7.5
1.2
6.0
0.9
4.5
0.6
3.0
0.3
11366-012
0
0
–350
–350
1.5
VOS (μV)
150
Figure 15. Input Offset Voltage vs. Common-Mode Voltage
Figure 12. Input Offset Voltage vs. Common-Mode Voltage
350
350
VSY = 18V
20 CHANNELS AT –40°C AND +125°C
VSY = 3V
20 CHANNELS AT –40°C AND +125°C
250
250
150
VOS (μV)
VOS (μV)
150
50
50
–50
–50
–150
–150
–250
–250
18.0
Figure 16. Input Offset Voltage vs. Common-Mode Voltage
Figure 13. Input Offset Voltage vs. Common-Mode Voltage
0
0
VSY = 10V
ΔVCM = 400mV
VSY = 10V
ΔVSY = 400mV
–20
SMALL SIGNAL PSRR (dB)
–20
–40
–60
–80
–100
–120
–40
PSRR–
PSRR+
–60
–80
–100
–120
–140
–140
0
1
2
3
4
5
6
7
8
9
VCM (V)
10
Figure 14. Small Signal CMRR vs. Common-Mode Voltage
–180
0
1
2
3
4
5
6
VCM (V)
7
8
9
Figure 17. Small Signal PSRR vs. Common-Mode Voltage
Rev. 0 | Page 12 of 32
10
11366-168
–160
11366-216
SMALL SIGNAL CMRR (dB)
16.5
VCM (V)
11366-016
VCM (V)
15.0
3.0
13.5
2.7
12.0
2.4
10.5
2.1
9.0
1.8
7.5
1.5
6.0
1.2
4.5
0.9
3.0
0.6
1.5
0.3
11366-013
0
0
–350
–350
Data Sheet
ADA4661-2
1000
1000
VSY = 3V
VCM = VSY/2
VSY = 18V
VCM = VSY/2
100
IB (pA)
IB (pA)
100
10
10
|IB–|
|IB–|
|IB+|
|IB+|
1
50
75
100
125
TEMPERATURE (°C)
0.1
25
11366-014
0.1
25
50
Figure 18. Input Bias Current vs. Temperature
125
3
VSY = 3V
VCM = VSY/2
2
1
1
0
0
–1
25°C
85°C
125°C
–2
VSY = 18V
VCM = VSY/2
2
IB (nA)
–1
25°C
85°C
125°C
–2
0
0.5
1.0
1.5
VCM (V)
2.0
2.5
3.0
–4
11366-018
–4
0
Figure 19. Input Bias Current vs. Common-Mode Voltage
OUTPUT VOLTAGE (VOH) TO SUPPLY RAIL (mV)
VSY = 3V
1000
100
–40°C
+25°C
+85°C
+125°C
0.01
0.1
1
10
100
LOAD CURRENT (mA)
11366-019
1
0.001
4
6
8
10
VCM (V)
12
14
16
18
Figure 22. Input Bias Current vs. Common-Mode Voltage
10000
10
2
11366-021
–3
–3
Figure 20. Output Voltage (VOH) to Supply Rail vs. Load Current
10000
VSY = 18V
1000
100
10
1
0.001
–40°C
+25°C
+85°C
+125°C
0.01
0.1
1
10
100
LOAD CURRENT (mA)
Figure 23. Output Voltage (VOH) to Supply Rail vs. Load Current
Rev. 0 | Page 13 of 32
11366-022
IB (nA)
100
Figure 21. Input Bias Current vs. Temperature
3
OUTPUT VOLTAGE (VOH) TO SUPPLY RAIL (mV)
75
TEMPERATURE (°C)
11366-017
1
Data Sheet
VSY = 3V
1000
–40°C
+25°C
+85°C
+125°C
100
10
1
0.1
0.001
0.1
0.01
1
10
10000
VSY = 18V
1000
100
LOAD CURRENT (mA)
100
10
1
0.1
0.001
100
2.98
2.97
2.96
RL = 10kΩ
17.95
RL = 10kΩ
OUTPUT VOLTAGE (VOH) (V)
RL = 1kΩ
2.95
17.90
17.85
RL = 1kΩ
17.80
17.75
VSY = 3V
25
50
75
100
125
TEMPERATURE (°C)
Figure 25. Output Voltage (VOH) vs. Temperature
–25
0
25
50
75
TEMPERATURE (°C)
100
125
11366-027
0
11366-024
–25
VSY = 18V
17.70
–50
Figure 28. Output Voltage (VOH) vs. Temperature
50
200
VSY = 18V
VSY = 3V
180
OUTPUT VOLTAGE (VOL) (mV)
40
RL = 1kΩ
30
20
10
RL = 10kΩ
0
25
50
140
RL = 1kΩ
120
100
80
60
40
RL = 10kΩ
20
75
100
TEMPERATURE (°C)
125
11366-025
–25
160
Figure 26. Output Voltage (VOL) vs. Temperature
0
–50
–25
0
25
50
75
100
TEMPERATURE (°C)
Figure 29. Output Voltage (VOL) vs. Temperature
Rev. 0 | Page 14 of 32
125
11366-028
OUTPUT VOLTAGE (VOH) (V)
10
18.00
2.99
OUTPUT VOLTAGE (VOL) (mV)
1
Figure 27. Output Voltage (VOL) to Supply Rail vs. Load Current
3.00
0
–50
0.1
0.01
LOAD CURRENT (mA)
Figure 24. Output Voltage (VOL) to Supply Rail vs. Load Current
2.94
–50
–40°C
+25°C
+85°C
+125°C
11366-023
OUTPUT VOLTAGE (VOL) TO SUPPLY RAIL (mV)
10000
11366-020
OUTPUT VOLTAGE (VOL) TO SUPPLY RAIL (mV)
ADA4661-2
Data Sheet
ADA4661-2
1000
1000
VSY = 18V
900
900
800
800
ISY PER AMPLIFIER (μA)
700
600
500
400
–40°C
+25°C
+85°C
+125°C
300
200
700
600
500
400
200
100
100
1.0
0.5
0
2.5
2.0
1.5
3.0
VCM (V)
0
11366-026
0
3
0
6
12
9
18
15
VCM (V)
Figure 30. Supply Current vs. Common-Mode Voltage
Figure 33. Supply Current vs. Common-Mode Voltage
1000
1000
VCM = VSY/2
VCM = VSY/2
900
800
ISY PER AMPLIFIER (µA)
800
ISY PER AMPLIFIER (µA)
–40°C
+25°C
+85°C
+125°C
300
11366-029
ISY PER AMPLIFIER (μA)
VSY = 3V
600
400
–40°C
+25°C
+85°C
+125°C
200
700
600
500
400
VSY = 3V
VSY = 10V
VSY = 18V
300
200
4
6
8
10
12
14
16
18
VSY (V)
0
–50
–25
0
25
50
80
135
80
90
60
GAIN
20
–20
10k
0
OPEN-LOOP GAIN (dB)
45
100k
1M
–90
10M
FREQUENCY (Hz)
PHASE
135
90
45
40
GAIN
0
20
0
–45
11366-033
OPEN-LOOP GAIN (dB)
40
PHASE (Degrees)
PHASE
CL = 0pF
CL = 10pF
CL = 0pF
CL = 10pF
125
VSY = 18V
RL = 10kΩ
VSY = 3V
RL = 10kΩ
0
100
Figure 34. Supply Current vs. Temperature
Figure 31. Supply Current vs. Supply Voltage
60
75
TEMPERATURE (°C)
–20
10k
–45
CL = 0pF
CL = 10pF
CL = 0pF
CL = 10pF
100k
1M
–90
10M
FREQUENCY (Hz)
Figure 35. Open-Loop Gain and Phase vs. Frequency
Figure 32. Open-Loop Gain and Phase vs. Frequency
Rev. 0 | Page 15 of 32
PHASE (Degrees)
2
11366-036
0
11366-030
0
11366-133
100
ADA4661-2
Data Sheet
60
60
VSY = 3V
CL = 5pF
VSY = 18V
CL = 5pF
AV = 100
40
AV = 100
40
AV = 10
GAIN (dB)
AV = 1
0
AV = 1
0
–20
10k
100k
FREQUENCY (Hz)
1M
10M
–40
1k
11366-232
–40
1k
Figure 36. Closed-Loop Gain vs. Frequency
10k
100
100
ZOUT (Ω)
1k
ZOUT (Ω)
1k
AV = 100
AV = 10
1
10M
VSY = 18V
VCM = VSY/2
AV = 100
10
1
AV = 10
AV = 1
AV = 1
0.1
0.1
1k
10k
100k
1M
10M
FREQUENCY (Hz)
0.01
100
11366-038
0.01
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 37. Output Impedance vs. Frequency
Figure 40. Output Impedance vs. Frequency
120
100
100
80
80
CMRR (dB)
120
60
60
40
40
20
20
VSY = 3V
VCM = VSY/2
0
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
11366-039
CMRR (dB)
1M
Figure 39. Closed-Loop Gain vs. Frequency
VSY = 3V
VCM = VSY/2
10
100k
FREQUENCY (Hz)
11366-041
10k
10k
11366-235
–20
20
Figure 38. CMRR vs. Frequency
VSY = 18V
VCM = VSY/2
0
100
1k
10k
100k
FREQUENCY (Hz)
Figure 41. CMRR vs. Frequency
Rev. 0 | Page 16 of 32
1M
10M
11366-042
GAIN (dB)
AV = 10
20
Data Sheet
100
100
VSY = 3V
VSY = 18V
PSRR+
PSRR–
80
80
60
60
PSRR (dB)
40
PSRR+
PSRR–
40
10k
100k
1M
10M
FREQUENCY (Hz)
0
1k
11366-040
0
1k
10k
Figure 42. PSRR vs. Frequency
10M
Figure 45. PSRR vs. Frequency
VSY = 3V
VIN = 100mV p-p
AV = 1
RL = 10kΩ
50
VSY = 18V
VIN = 100mV p-p
AV = 1
RL = 10kΩ
50
OS–
30
OVERSHOOT (%)
40
OS+
20
40
OS–
30
OS+
20
10
10
20
30
40
50
0
CAPACITANCE (pF)
0
10
20
30
40
11366-047
0
11366-044
10
50
CAPACITANCE (pF)
Figure 43. Small Signal Overshoot vs. Load Capacitance
Figure 46. Small Signal Overshoot vs. Load Capacitance
VSY = ±1.5V
VIN = 2.5V p-p
AV = 1
RL = 10kΩ
CL = 10pF
RS = 1kΩ
VSY = ±9V
VIN = 17V p-p
AV = 1
RL = 10kΩ
CL = 10pF
RS = 1kΩ
TIME (5µs/DIV)
11366-045
VOLTAGE (2V/DIV)
VOLTAGE (0.5V/DIV)
OVERSHOOT (%)
1M
60
60
0
100k
FREQUENCY (Hz)
11366-043
20
20
TIME (5µs/DIV)
Figure 44. Large Signal Transient Response
Figure 47. Large Signal Transient Response
Rev. 0 | Page 17 of 32
11366-048
PSRR (dB)
ADA4661-2
Data Sheet
VOLTAGE (20mV/DIV)
VOLTAGE (20mV/DIV)
ADA4661-2
TIME (2µs/DIV)
TIME (2µs/DIV)
0
15
1.5
1.0
INPUT VOLTAGE (V)
VOUT
–1
0.5
VSY = ±1.5V
AV = –10
RL = 10kΩ
CL = 10pF
VIN = 225mV
–1
–2
–0.5
TIME (2µs/DIV)
VIN
9
6
–4
–6
3
VSY = ±9V
AV = –10
RL = 10kΩ
CL = 10pF
VIN = 1.35V
2.0
9
2
0
1.0
–0.2
0.5
–0.4
0
–0.6
–0.5
–1.0
VSY = ±1.5V
AV = –10
RL = 10kΩ
CL = 10pF
VIN = 225mV
VOUT
–1.2
TIME (2µs/DIV)
6
0
3
–1
0
–2
–3
–3
–6
VSY = ±9V
AV = –10
RL = 10kΩ
CL = 10pF
VIN = 1.35V
VOUT
–4
–1.5
–2.0
11366-051
–0.8
1
–5
TIME (2µs/DIV)
Figure 53. Negative Overload Recovery
Figure 50. Negative Overload Recovery
Rev. 0 | Page 18 of 32
–9
–12
11366-054
1.5
INPUT VOLTAGE (V)
0.2
OUTPUT VOLTAGE (V)
VIN
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
–3
Figure 52. Positive Overload Recovery
VIN
–1.0
0
TIME (2µs/DIV)
Figure 49. Positive Overload Recovery
0.4
12
VOUT
–3
–5
0
11366-050
–1.4
3.0
2.0
–0.8
–1.2
18
2.5
–0.4
–0.6
1
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
–0.2
VIN
3.5
11366-053
0
Figure 51. Small Signal Transient Response
OUTPUT VOLTAGE (V)
Figure 48. Small Signal Transient Response
0.2
11366-049
VSY = ±9V
VIN = 100mV p-p
AV = 1
RL = 10kΩ
CL = 10pF
11366-046
VSY = ±1.5V
VIN = 100mV p-p
AV = 1
RL = 10kΩ
CL = 10pF
Data Sheet
ADA4661-2
ERROR BAND
11366-052
VSY = ±1.5V
VIN = 1V p-p
RL = 10kΩ
CL = 10pF
AV = –1
TIME (400ns/DIV)
TIME (400ns/DIV)
VOLTAGE (500mV/DIV)
VOLTAGE (1mV/DIV)
TIME (400ns/DIV)
TIME (400ns/DIV)
Figure 58. Negative Settling Time to 0.1%
Figure 55. Negative Settling Time to 0.1%
1k
11366-059
VSY = ±9V
VIN = 1V p-p
RL = 10kΩ
CL = 10pF
AV = –1
11366-056
VSY = ±1.5V
VIN = 1V p-p
RL = 10kΩ
CL = 10pF
AV = –1
OUTPUT
ERROR BAND
1k
VOLTAGE NOISE DENSITY (nV/√Hz)
VSY = 3V
VCM = VSY/2
AV = 1
VSY = 18V
VCM = VSY/2
AV = 1
100
100
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
11366-057
10
10
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 59. Voltage Noise Density vs. Frequency
Figure 56. Voltage Noise Density vs. Frequency
Rev. 0 | Page 19 of 32
10M
11366-060
VOLTAGE (500mV/DIV)
OUTPUT
ERROR BAND
VOLTAGE (1mV/DIV)
INPUT
INPUT
VOLTAGE NOISE DENSITY (nV/√Hz)
VSY = ±9V
VIN = 1V p-p
RL = 10kΩ
CL = 10pF
AV = –1
Figure 57. Positive Settling Time to 0.1%
Figure 54. Positive Settling Time to 0.1%
1
10
VOLTAGE (1mV/DIV)
OUTPUT
11366-055
OUTPUT
ERROR BAND
VOLTAGE (500mV/DIV)
INPUT
VOLTAGE (1mV/DIV)
VOLTAGE (500mV/DIV)
INPUT
ADA4661-2
Data Sheet
VSY = 3V
VCM = VSY/2
AV = 1
TIME (2s/DIV)
11366-061
11366-058
VOLTAGE (1µV/DIV)
VOLTAGE (1µV/DIV)
VSY = 18V
VCM = VSY/2
AV = 1
TIME (2s/DIV)
Figure 60. 0.1 Hz to 10 Hz Noise
Figure 63. 0.1 Hz to 10 Hz Noise
20
3.5
18
3.0
2.0
1.5
1.0
0
10
12
10
8
6
4
2
100
1k
10k
100k
1M
FREQUENCY (Hz)
0
10
11366-062
0.5
VSY = 3V
VIN = 2.9V
RL = 10kΩ
CL = 10pF
AV = 1
14
1k
10k
100k
1M
Figure 64. Output Swing vs. Frequency
1
80kHz LOW-PASS FILTER
500kHz LOW-PASS FILTER
VSY = 3V
AV = 1
RL = 10kΩ
VIN = 440mV rms
100
FREQUENCY (Hz)
Figure 61. Output Swing vs. Frequency
1
VSY = 18V
VIN = 17.9V
RL = 10kΩ
CL = 10pF
AV = 1
11366-065
OUTPUT SWING (V)
OUTPUT SWING (V)
16
2.5
80kHz LOW-PASS FILTER
500kHz LOW-PASS FILTER
VSY = 18V
AV = 1
RL = 10kΩ
VIN = 5.4V rms
0.1
THD + N (%)
THD + N (%)
0.1
0.01
0.01
100
1k
10k
FREQUENCY (Hz)
100k
0.0001
10
100
1k
10k
FREQUENCY (Hz)
Figure 65. THD + N vs. Frequency
Figure 62. THD + N vs. Frequency
Rev. 0 | Page 20 of 32
100k
11366-066
0.001
10
11366-063
0.001
Data Sheet
100
ADA4661-2
100
VSY = 3V
AV = 1
RL = 10kΩ
f = 1kHz
10
10
VSY = 18V
AV = 1
RL = 10kΩ
f = 1kHz
THD + N (%)
THD + N (%)
1
1
0.1
0.1
0.01
0.01
1
0.1
10
AMPLITUDE (V rms)
0.0001
0.001
1
10
0
CHANNEL SEPARATION (dB)
–20
–40
–60
–80
–100
–120
VSY = 3V
AV = 100
RL = 10kΩ
500kHz LOW-PASS FILTER
–140
–160
100
1k
10k
FREQUENCY (Hz)
100k
VIN = 0.5V p-p
VIN = 9V p-p
VIN = 17.9V p-p
–40
–60
–80
–100
–120
VSY = 18V
AV = 100
RL = 10kΩ
500kHz LOW-PASS FILTER
–140
–160
10
100
1k
10k
FREQUENCY (Hz)
Figure 69. Channel Separation vs. Frequency
Figure 67. Channel Separation vs. Frequency
Rev. 0 | Page 21 of 32
100k
11366-069
VIN = 0.5V p-p
VIN = 1.5V p-p
VIN = 2.9V p-p
11366-068
CHANNEL SEPARATION (dB)
0.1
Figure 68. THD + N vs. Amplitude
0
10
0.01
AMPLITUDE (V rms)
Figure 66. THD + N vs. Amplitude
–20
80kHz LOW-PASS FILTER
500kHz LOW-PASS FILTER
11366-067
0.01
11366-064
0.001
0.001
0.001
80kHz LOW-PASS FILTER
500kHz LOW-PASS FILTER
ADA4661-2
Data Sheet
APPLICATIONS INFORMATION
V+
HIGH VOLTAGE PROTECTION
I2
M11
M12
M9
M10
M19
M20
M17
M18
M22
+IN x
R1
M3
D1
M4
C2
C1
Q1
Q2
OUT x
D2
V1
–IN x
C3
R2
M1
M2
M7
M8
I1
M5
M6
I3
HIGH VOLTAGE PROTECTION
V–
M16
M13
M14
11366-169
M21
M15
Figure 70. Simplified Schematic
The ADA4661-2 is a low power, rail-to-rail input and output,
precision CMOS amplifier that operates over a wide supply
voltage range of 3 V to 18 V. This amplifier uses the Analog
Devices DigiTrim technique to achieve a higher degree of
precision than is available from other CMOS amplifiers. The
DigiTrim technique is a method of trimming the offset voltage
of an amplifier after assembly. The advantage of postpackage
trimming is that it corrects any offset voltages caused by
mechanical stresses of assembly. To achieve a rail-to-rail input
and output range with very low supply current, the ADA4661-2
uses unique input and output stages.
INPUT STAGE
Figure 70 shows the simplified schematic of the ADA4661-2.
The amplifier uses a three-stage architecture with a fully
differential input stage to achieve excellent dc performance
specifications.
The input stage comprises two differential transistor pairs—
a NMOS pair (M1, M2) and a PMOS pair (M3, M4)—and
folded-cascode transistors (M5 to M12). The input commonmode voltage determines which differential pair is active. The
PMOS differential pair is active for most of the input commonmode range. The NMOS pair is required for input voltages up
to and including the upper supply rail. This topology allows the
amplifier to maintain a wide dynamic input voltage range and
maximize signal swing to both supply rails.
The proprietary high voltage protection circuitry in the
ADA4661-2 minimizes the common-mode voltage changes
seen by the amplifier input stage for most of the input commonmode range. This results in the amplifier having excellent
disturbance rejection when operating in this preferred
common-mode range. The performance benefits of operating
within this preferred range are shown in the PSRR vs. VCM (see
Figure 17), CMRR vs. VCM (see Figure 14), and VOS vs. VCM
graphs (see Figure 8, Figure 11, Figure 12, Figure 13, Figure 15,
and Figure 16). The CMRR performance benefits of the reduced
common-mode range are guaranteed at final test and shown in the
electrical characteristics (see Table 2 to Table 4).
For most of the input common-mode voltage range, the PMOS
differential pair is active. When the input common-mode
voltage is within a few volts of the power supplies, the input
transistors are exposed to these voltage changes. As the
common-mode voltage approaches the positive power supply,
the active differential pair changes from the PMOS pair to the
NMOS pair. Differential pairs commonly exhibit different offset
voltages. The handoff of control from one differential pair to the
other creates a step like characteristic that is visible in the VOS vs.
VCM graphs (see Figure 8, Figure 11, Figure 12, Figure 13, Figure 15,
and Figure 16). This characteristic is inherent in all rail-to-rail
input amplifiers that use the dual differential pair topology.
Additional steps in the VOS vs. VCM graphs are visible as the
common-mode voltage approaches the negative power supply.
These changes are a result of the load transistors (M5, M6)
running out of headroom. As the load transistors are forced into
the triode region of operation, the mismatch of their drain
impedance becomes a significant portion of the amplifier offset.
This effect can also be seen in the VOS vs. VCM graphs (see Figure 8,
Figure 11, Figure 12, Figure 13, Figure 15, and Figure 16).
Current Source I2 drives the PMOS transistor pair. As the input
common-mode voltage approaches the upper power supply,
this current is reduced to zero. At the same time, a replica
current source, I1, is increased from zero to enable the NMOS
transistor pair.
The ADA4661-2 achieves its high performance specifications by
using low voltage MOS devices for its differential inputs. These
low voltage MOS devices offer excellent noise and bandwidth
per unit of current. The input stage is isolated from the high
Rev. 0 | Page 22 of 32
Data Sheet
ADA4661-2
GAIN STAGE
The second stage of the amplifier is composed of an NPN
differential pair (Q1, Q2) and folded-cascode transistors (M13
to M20). The amplifier features nested Miller compensation
(C1 to C3).
1.6
TJ MAX = 150°C
1.4
1.2
8-LEAD LFCSP
θJA = 83.5°C/W
1.0
0.8
8-LEAD MSOP
θJA = 142°C/W
0.6
0.4
0.2
0
0
25
50
75
100
125
150
AMBIENT TEMPERATURE (°C)
OUTPUT STAGE
The ADA4661-2 features a complementary output stage consisting
of the M21 and M22 transistors. These transistors are configured
in a Class AB topology and are biased by the voltage source, V1.
This topology allows the output voltage to go within millivolts
of the supply rails, achieving a rail-to-rail output swing. The
output voltage is limited by the output impedance of the transistors, which are low RON MOS devices. The output voltage swing
is a function of the load current and can be estimated using the
output voltage to supply rail vs. load current graphs (see Figure 20,
Figure 23, Figure 24, and Figure 27). The high voltage and high
current capability of the ADA4661-2 output stage requires the
user to ensure that it operates within the thermal safe operating
area (see the Maximum Power Dissipation section).
11366-371
The input devices are also protected from large differential
input voltages by clamp diodes (D1 and D2). These diodes are
buffered from the inputs with two 120 Ω resistors (R1 and R2).
The diodes conduct significant current whenever the differential voltage exceeds approximately 600 mV; in this condition,
the differential input resistance falls to 240 Ω. It is possible for a
significant amount of current to flow through these protection
diodes. The user must ensure that current flowing into the input
pins is limited to the absolute maximum of 10 mA.
destroy the device. To ensure proper operation, it is necessary to
observe the maximum power derating curves. Figure 71 shows
the maximum safe power dissipation in the package vs. the
ambient temperature on a standard 4-layer JEDEC board. The
exposed pad of the LFCSP package is soldered to the board.
MAXIMUM POWER DISSIPATION (W)
system voltages with proprietary protection circuitry. This regulation circuitry protects the input devices from the high supply
voltages at which the amplifier can operate.
Figure 71. Maximum Power Dissipation vs. Ambient Temperature
Refer to Technical Article MS-2251, Data Sheet Intricacies—
Absolute Maximum Ratings and Thermal Resistances, for more
information.
RAIL-TO-RAIL INPUT AND OUTPUT
The ADA4661-2 features rail-to-rail input and output with a
supply voltage from 3 V to 18 V. Figure 72 shows the input and
output waveforms of the ADA4661-2 configured as a unity-gain
buffer with a supply voltage of ±9 V. With an input voltage of
±9 V, the ADA4661-2 allows the output to swing very close to
both rails. Additionally, it does not exhibit phase reversal.
10
VIN
VOUT
8
MAXIMUM POWER DISSIPATION
6
4
TJ = PD × θJA + TA
2
0
–2
–4
–6
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated by the
output stage transistor. It can be calculated as follows:
–8
–10
VSY = ±9V
VIN = ±9V
AV = 1
RL = 10kΩ
CL = 10pF
TIME (200µs/DIV)
Figure 72. Rail-to-Rail Input and Output
PD = (VSY × ISY) + (VSY − VOUT) × ILOAD
where:
VSY is the power supply rail.
ISY is the quiescent current.
VOUT is the output of the amplifier.
ILOAD is the output load.
Do not exceed the maximum junction temperature for the
device, 150°C. Exceeding the junction temperature limit can
cause degradation in the parametric performance or even
Rev. 0 | Page 23 of 32
11366-072
VOLTAGE (V)
The ADA4661-2 is capable of driving an output current up
to 220 mA. However, the usable output load current drive is
limited to the maximum power dissipation allowed by the
device package. The absolute maximum junction temperature
for the ADA4661-2 is 150°C (see Table 5). The junction
temperature can be estimated as follows:
ADA4661-2
Data Sheet
An op amp is designed to operate in a closed-loop configuration
with feedback from its output to its inverting input. Figure 73
shows the ADA4661-2 configured as a voltage follower with an
input voltage that is always kept at the midpoint of the power
supplies. The same configuration is applied to the unused
channel. A1 and A2 indicate the placement of ammeters to
measure supply current. ISY+ refers to the current flowing from
the upper supply rail to the op amp, and ISY− refers to the
current flowing from the op amp to the lower supply rail. As
shown in Figure 74, in normal operating conditions, the total
current flowing into the op amp is equivalent to the total current
flowing out of the op amp, where ISY+ = ISY− = 630 μA per amplifier
at VSY = 18 V.
Figure 75 and Figure 76 show the ADA4661-2 configured as a
comparator, with 100 kΩ resistors in series with the input pins.
Any unused channels are configured as buffers with the input
voltage kept at the midpoint of the power supplies.
+VSY
A1
100kΩ
ADA4661-2
VOUT
1/2
100kΩ
ISY–
A2
+VSY
A1
ISY+
11366-268
COMPARATOR OPERATION
–VSY
Figure 75. Comparator A
ISY+
+VSY
100kΩ
A1
ADA4661-2
1/2
A2
ISY+
100kΩ
ADA4661-2
ISY–
VOUT
1/2
11366-266
100kΩ
VOUT
–VSY
100kΩ
A2
ISY–
–VSY
Figure 76. Comparator B
600
ISY PER AMPLIFIER (µA)
11366-269
Figure 73. Voltage Follower
700
Figure 77 shows the supply currents for both comparator
configurations. In comparator mode, the ADA4661-2 does not
power up completely. For more information about configuring
using on op amps as comparators, see the AN-849 Application
Note, Using Op Amps as Comparators.
500
400
300
700
200
600
2
4
6
8
10
VSY (V)
12
14
16
18
Figure 74. Supply Current vs. Supply Voltage (Voltage Follower)
In contrast to op amps, comparators are designed to work in an
open-loop configuration and to drive logic circuits. Although
op amps are different from comparators, occasionally an unused
section of a dual op amp is used as a comparator to save board
space and cost; however, this is not recommended for the
ADA4661-2.
500
COMPARATOR A
COMPARATOR B
400
300
200
100
0
0
2
4
6
8
10
VSY (V)
12
14
16
18
11366-074
0
ISY PER AMPLIFIER (µA)
0
11366-071
100
Figure 77. Supply Current vs. Supply Voltage (ADA4661-2 as a Comparator)
Rev. 0 | Page 24 of 32
Data Sheet
ADA4661-2
EMI REJECTION RATIO
Circuit performance is often adversely affected by high frequency
electromagnetic interference (EMI). When signal strength is
low and transmission lines are long, an op amp must accurately
amplify the input signals. However, all op amp pins—the
noninverting input, inverting input, positive supply, negative
supply, and output pins—are susceptible to EMI signals. These
high frequency signals are coupled into an op amp by various
means, such as conduction, near field radiation, or far field
radiation. For instance, wires and PCB traces can act as antennas
and pick up high frequency EMI signals.
Amplifiers do not amplify EMI or RF signals due to their
relatively low bandwidth. However, due to the nonlinearities of
the input devices, op amps can rectify these out-of-band signals.
When these high frequency signals are rectified, they appear as
a dc offset at the output.
Figure 79 shows a low-side current sensing circuit, and Figure 80
shows a high-side current sensing circuit. Current flowing
through the shunt resistor creates a voltage drop. The ADA4661-2,
configured as a difference amplifier, amplifies the voltage drop
by a factor of R2/R1. Note that for true difference amplification,
matching of the resistor ratio is very important, where R2/R1 =
R4/R3. The rail-to-rail output feature of the ADA4661-2 allows
the output of the op amp to almost reach its positive supply.
This allows the current shunt monitor to sense up to approximately VSY/(R2/R1 × RS) amperes of current. For example, with
VSY = 18 V, R2/R1 = 100, and RS = 100 mΩ, this current is
approximately 1.8 A.
I
SUPPLY
RS
I
R1
VOUT*
R2
VSY
To describe the ability of the ADA4661-2 to perform as
intended in the presence of electromagnetic energy, the
electromagnetic interference rejection ratio (EMIRR) of the
noninverting pin is specified in Table 2, Table 3, and Table 4
of the Specifications section. A mathematical method of
measuring EMIRR is defined as follows:
1/2
ADA4661-2
*VOUT = AMPLIFIER GAIN × VOLTAGE ACROSS RS = R2/R1 × RS × I
11366-079
R4
R3
Figure 79. Low-Side Current Sensing Circuit
EMIRR = 20 log (VIN_PEAK/ΔVOS)
RS
I
SUPPLY
140
VSY = 3V TO 18V
RL
I
R3
120
R4
VSY
VOUT*
100
1/2
ADA4661-2
R1
80
R2
*VOUT = AMPLIFIER GAIN × VOLTAGE ACROSS RS = R2/R1 × RS × I
60
Figure 80. High-Side Current Sensing Circuit
VIN = 100mV PEAK
VIN = 50mV PEAK
ACTIVE FILTERS
100M
1G
FREQUENCY (Hz)
10G
11366-075
40
20
10M
11366-080
EMIRR (dB)
RL
Figure 78. EMIRR vs. Frequency
CURRENT SHUNT MONITOR
Many applications require the sensing of signals near the
positive or negative rail. Current shunt monitors are one such
application and are mostly used for feedback control systems.
They are also used in a variety of other applications, including
power metering, battery fuel gauging, and feedback controls in
electrical power steering. In such applications, it is desirable to
use a shunt with very low resistance to minimize the series
voltage drop. This not only minimizes wasted power but also
allows the measurement of high currents while saving power.
The low input bias current, low offset voltage, and rail-to-rail
feature of the ADA4661-2 makes the amplifier an excellent
choice for precision current monitoring.
Active filters are used to separate signals, passing those of
interest and attenuating signals at unwanted frequencies. For
example, low-pass filters are often used as antialiasing filters
in data acquisition systems or as noise filters to limit high
frequency noise.
The high input impedance, high bandwidth, low input bias
current, and dc precision of the ADA4661-2 make it a good fit
for active filter applications. Figure 81 shows the ADA4661-2 in
a four-pole Sallen-Key Butterworth low-pass filter configuration.
The four-pole low-pass filter has two complex conjugate pole
pairs and is implemented by cascading two two-pole low-pass
filters. Section A and Section B are configured as two-pole lowpass filters in unity gain. Table 8 shows the Q requirement and
pole position associated with each stage of the Butterworth
filter. Refer to Chapter 8, “Analog Filters,” in Linear Circuit
Design Handbook, available at www.analog.com/AnalogDialogue,
for pole locations on the S plane and Q requirements for filters
of a different order.
Rev. 0 | Page 25 of 32
ADA4661-2
Data Sheet
C2
6.8nF
VIN
R1
R2
2.55kΩ 2.55kΩ
C1
5.6nF
C4
6.8nF
+VSY
R3
6.19kΩ
R4
6.19kΩ
+VSY
1/2
VOUT1
ADA4661-2
VOUT2
1/2
C3
1nF
–VSY
ADA4661-2
SECTION A
11366-081
–VSY
SECTION B
Figure 81. Four-Pole Low-Pass Filter
CAPACITIVE LOAD DRIVE
Table 8. Q Requirements and Pole Positions
Poles
−0.9239 ± j0.3827
−0.3827 ± j0.9239
Q
0.5412
1.3065
The Sallen-Key topology is widely used due to its simple design
with few circuit elements. This topology provides the user the
flexibility of implementing either a low-pass or a high-pass filter
by simply interchanging the resistors and capacitors. The
ADA4661-2 is configured in unity gain with a corner frequency
at 10 kHz. An active filter requires an op amp with a unity-gain
bandwidth that is at least 100 times greater than the product of
the corner frequency, fC, and the quality factor, Q. The resistors
and capacitors are also important in determining the performance over manufacturing tolerances, time, and temperature.
At least 1% or better tolerance resistors and 5% or better
tolerance capacitors are recommended.
Figure 82 shows the frequency response of the low-pass SallenKey filter, where:
VOUT1 is the output of the first stage.
The ADA4661-2 can safely drive capacitive loads of up to 50 pF
in any configuration. As with most amplifiers, driving larger
capacitive loads than specified may cause excessive overshoot
and ringing, or even oscillation. Heavy capacitive load reduces
phase margin and causes the amplifier frequency response to
peak. Peaking corresponds to overshooting or ringing in the
time domain. Therefore, it is recommended that external
compensation be used if the ADA4661-2 must drive a load
exceeding 50 pF. This compensation is particularly important
in the unity-gain configuration, which is the worst case for
stability.
A quick and easy way to stabilize the op amp for capacitive load
drive is by adding a series resistor, RISO, between the amplifier
output terminal and the load capacitance, as shown in Figure 83.
RISO isolates the amplifier output and feedback network from
the capacitive load. However, with this compensation scheme,
the output impedance as seen by the load increases, and this
reduces gain accuracy.
+VSY
VOUT2 is the output of the second stage.
RISO
1/2
VOUT1 shows a 40 dB/decade roll-off and VOUT2 shows an
80 dB/decade roll-off. The transition band becomes sharper as
the order of the filter increases.
VIN
CL
Figure 83. Stability Compensation with Isolating Resistor, RISO
20
Figure 84 shows the effect of the compensation scheme on the
frequency response of the amplifier in unity-gain configuration
driving 250 pF of load.
0
–20
VOUT1
GAIN (dB)
ADA4661-2
–VSY
VOUT
11366-083
Section
A
B
–40
VOUT2
–60
–80
VSY = ±9V
VIN = 50mV p-p
–120
100
1k
10k
100k
FREQUENCY (Hz)
1M
11366-082
–100
Figure 82. Low-Pass Filter: Gain vs. Frequency
Rev. 0 | Page 26 of 32
Data Sheet
ADA4661-2
10
–20
–30
–40
–50
10k
VSY = ±9V
VIN = 100mV p-p
AV = 1
CL = 250pF
RISO = 301Ω
RISO = 0Ω
RISO = 210Ω
RISO = 301Ω
RISO = 499Ω
100k
1M
10M
FREQUENCY (Hz)
TIME (10µs/DIV)
11366-087
VOLTAGE (20mV/DIV)
–10
11366-084
CLOSED-LOOP GAIN (dB)
0
Figure 87. Output Response (RISO = 301 Ω)
VOLTAGE (50mV/DIV)
VSY = ±9V
VIN = 100mV p-p
AV = 1
CL = 250pF
RISO = 750Ω
TIME (10µs/DIV)
VSY = ±9V
VIN = 100mV p-p
AV = 1
CL = 250pF
RISO = 0Ω
TIME (10µs/DIV)
11366-085
Figure 88. Output Response (RISO = 750 Ω)
VSY = ±9V
VIN = 100mV p-p
AV = 1
CL = 250pF
RISO = 210Ω
TIME (10µs/DIV)
11366-086
VOLTAGE (20mV/DIV)
Figure 85. Output Response with No Compensation (RISO = 0 Ω)
Figure 86. Output Response (RISO = 210 Ω)
Rev. 0 | Page 27 of 32
11366-088
Figure 85 shows the output response of the unity-gain amplifier
driving 250 pF of capacitive load. With no compensation, the
amplifier is unstable. Figure 86 to Figure 88 show the amplifier
output response with 210 Ω, 301 Ω, and 750 Ω of RISO compensation. Note that with lower RISO values, ringing is still noticeable,
whereas with higher RISO values, higher frequency signals are
filtered out.
VOLTAGE (20mV/DIV)
Figure 84. Frequency Response of Compensation Scheme
ADA4661-2
Data Sheet
The blowback noise spectrum has a high-pass response at low
frequencies due to CGS coupling. At high frequencies, the
spectrum tends to roll off with two poles: an internal pole due
to parasitic capacitances of the tail current source and an
external pole due to parasitic capacitances on the PCB.
Figure 89 shows the voltage noise density of the ADA4661-2
with source impedances of 1 MΩ and 10 MΩ. At low frequencies
(<1 Hz to 10 Hz), the amplifier 1/f voltage noise dominates the
spectrum. At moderate frequencies, the spectrum flattens due
to the thermal noise of the source resistors. As the frequency
increases, blowback noise dominates and causes the voltage
noise spectrum to increase. The noise spectrum continues to
increase until it reaches either the internal or external pole
frequency. After these poles, the spectrum starts to decrease.
1
RS = 10MΩ
0.1
0.01
0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
11366-300
RS = 1MΩ
Figure 89. Voltage Noise Density vs. Frequency (with Input Series Resistor RS)
1
NOISE BANDWIDTH
LIMITATION
RS = 1MΩ
RS = 10MΩ
0.1
NOISE MEASUREMENT
LIMITATION
0.01
0.01
0.1
1
10
100
1k
10k
FREQUENCY (Hz)
100k
11366-301
For the ADA4661-2, the more relevant discussion centers
around an effect referred to as blowback noise. The blowback
effect comes from noise in the tail current source of the
amplifier, which is capacitively coupled to the amplifier inputs
through the gate-to-source capacitance (CGS) of the input
transistors. This blowback noise is multiplied by the source
impedance and appears as voltage noise at the input terminal. A
10× increase in the source impedance results in a 10× increase
in the voltage noise due to blowback.
VOLTAGE NOISE DENSITY (µV/√Hz)
Current noise from input terminals can become a dominant
contributor to the total circuit noise when an amplifier is driven
with a high impedance source. Unlike bipolar amplifiers,
CMOS amplifiers like the ADA4661-2 do not have an intrinsic
shot noise source at the input terminals. The small amount of
shot noise present is produced by the reverse saturation current
in the ESD protection diodes. This current noise is typically on
the order of 1 fA/√Hz to 10 fA/√Hz. Therefore, to measure
current noise in this range, a large source impedance of greater
than 10 GΩ is required.
10
CURRENT NOISE DENSITY (pA/√Hz)
NOISE CONSIDERATIONS WITH HIGH IMPEDANCE
SOURCES
Figure 90. Current Noise Density vs. Frequency
Figure 90 shows the current noise density of the ADA4661-2
with source impedances of 1 MΩ and 10 MΩ. This current
noise is extracted only from the voltage noise density curves in
the frequency band where blowback noise is the dominant
contributor. At low frequencies, the noise measurement is
dominated by resistor thermal noise and amplifier 1/f noise. At
high frequencies, parasitic capacitances dominate the source
impedance. The uncertainty of this scale factor prevents an
accurate current noise measurement for the entire frequency
range.
Blowback noise is present in all amplifiers. The magnitude of
the effect depends on the size of the input transistors and the
construction of the biasing circuitry. CMOS amplifiers typically
have more blowback noise than JFET amplifiers due to noisier
MOS transistor biasing. On the other hand, bipolar amplifiers
typically do not exhibit blowback noise because the large base
current shot noise masks any blowback noise present.
Rev. 0 | Page 28 of 32
Data Sheet
ADA4661-2
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
3.20
3.00
2.80
1
5.15
4.90
4.65
5
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.40
0.25
0.80
0.55
0.40
0.23
0.09
6°
0°
10-07-2009-B
0.15
0.05
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 91. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
2.44
2.34
2.24
3.10
3.00 SQ
2.90
0.50 BSC
8
5
0.50
0.40
0.30
0.80
0.75
0.70
0.30
0.25
0.20
1
4
BOTTOM VIEW
TOP VIEW
SEATING
PLANE
1.70
1.60
1.50
EXPOSED
PAD
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
0.20 MIN
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-229-WEED
11-28-2012-C
PIN 1 INDEX
AREA
Figure 92. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-11)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADA4661-2ACPZ-R7
ADA4661-2ACPZ-RL
ADA4661-2ARMZ
ADA4661-2ARMZ-RL
ADA4661-2ARMZ-R7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
Z = RoHS Compliant Part.
Rev. 0 | Page 29 of 32
Package Option
CP-8-11
CP-8-11
RM-8
RM-8
RM-8
Branding
A33
A33
A33
A33
A33
ADA4661-2
Data Sheet
NOTES
Rev. 0 | Page 30 of 32
Data Sheet
ADA4661-2
NOTES
Rev. 0 | Page 31 of 32
ADA4661-2
Data Sheet
NOTES
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11366-0-7/13(0)
Rev. 0 | Page 32 of 32