ICST ICS83908AG-02T Low skew, 1-to-8 crystal-to-lvcmos/lvttl fanout buffer Datasheet

PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83908-02
LOW SKEW, 1-TO-8
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS83908-02 is a low skew, high performance
1-to-8 Crystal Oscillator/3.3V LVCMOS-to-3.3V
HiPerClockS™ LVCMOS fanout buffer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS83908-02 has
selectable single ended clock or two crystal-oscillator inputs.
There is an output enable to disable the outputs by placing them
into a high-impedance state.
• 8 LVCMOS/LVTTL outputs (19Ω typical output impedance)
ICS
• 2 Crystal oscillator input pairs
1 LVCMOS/LVTTL clock input
• Crystal input frequencry range: 10MHz - 40MHz
• Output frequency: 200MHz (typical) CLK0
• Output Skew: TBD
• Part to Part Skew: TBD
Guaranteed output and part-to-part skew characteristics
make the ICS83908-02 ideal for those applications demanding
well defined performance and repeatability.
• RMS phase jitter @ 25MHz (100Hz - 1MHz):
0.22ps (typical) VDD = VDDO = 3.3V
Offset
Noise Power
100Hz .............. -111.4 dBc/Hz
1kHz .............. -139.9 dBc/Hz
10kHz .............. -157.3 dBc/Hz
100kHz .............. -157.5 dBc/Hz
• Supply Voltage Modes:
(Core/Output)
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• 0°C to 70°C ambient operating temperature
• Industrial temperature available upon request
BLOCK DIAGRAM
OE
CLK_SEL0
PIN ASSIGNMENT
Pullup
VDD
XTAL_IN0
XTAL_OUT0
VDDO
Q0
Q1
GND
Q2
Q3
VDDO
CLK_SEL0
CLK0
Pulldown
CLK_SEL1 Pulldown
XTAL_IN0
OSC
0 0
XTAL_OUT0
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
GND
XTAL_IN1
XTAL_OUT1
VDDO
Q7
Q6
GND
Q5
Q4
VDDO
CLK_SEL1
OE
Q0
ICS83908-02
XTAL_IN1
OSC
8 LVCMOS Outputs
0 1
XTAL_OUT1
24-Lead, 173-MIL TSSOP
4.4mm x 7.8mm x 0.92mm
body package
G Package
Top View
Q7
CLK0
Pulldown
1 0
1 1
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
83908AG-02
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1
REV. A JULY 20, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83908-02
LOW SKEW, 1-TO-8
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
VDD
XTAL_IN0,
XTAL_OUT0
VDDO
Q0, Q1, Q2,
Q3, Q4, Q5,
Q6, Q7
GND
CLK_SEL0,
CLK_SEL1
CLK0
2, 3
4, 10, 15, 21
5, 6, 8,
9, 16, 17,
19, 20
7, 18, 24
11,
14
12
Type
Power
Description
Power
Core supply pin.
Crystal oscillator interface. XTAL_IN0 is the input.
XTAL_OUT0 is the output.
Output supply pins.
Output
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Input
Power
Power supply ground.
Clock select inputs. See Table 3, Input Reference Function Table.
Input Pulldown
LVCMOS / LVTTL interface levels.
Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
Output enable. When LOW, outputs are in HIGH impedance state.
13
OE
Input
Pullup
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
Crystal oscillator interface. XTAL_IN1 is the input.
XTAL_OUT1,
22, 23
Input
XTAL_OUT1 is the output.
XTAL_IN1
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
Test Conditions
Minimum
Typical
4
Maximum
Units
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
VDDO = 3.465V
7
pF
CPD
Power Dissipation Capacitance
(per output)
VDDO = 2.625V
7
pF
VDDO = 2V
6
pF
Output Impedance
ROUT
VDDO = 3.3V ± 5%
19
Ω
VDDO = 2.5V ± 5%
TBD
Ω
VDDO = 1.8V ± 0.2V
TBD
Ω
TABLE 3. INPUT REFERENCE FUNCTION TABLE
Control Inputs
CLK_SEL1
CLK_SEL0
0
0
Reference
XTAL0 (default)
0
1
XTAL1
1
0
CLK0
1
1
CLK0
83908AG-02
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REV. A JULY 20, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83908-02
LOW SKEW, 1-TO-8
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDDO + 0.5V
Package Thermal Impedance, θJA
70°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDO
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
25
mA
IDDO
Output Supply Current
121
mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDO
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
26
mA
IDDO
Output Supply Current
82
mA
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol
Parameter
VDD
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
1.6
1.8
2.0
VDDO
Output Supply Voltage
IDD
Power Supply Current
26
mA
V
IDDO
Output Supply Current
53
mA
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
VDDO
Core Supply Voltage
2.375
2. 5
2.625
V
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
13
mA
IDDO
Output Supply Current
77
mA
TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
2.375
2.5
2.625
V
1.6
1.8
2.0
V
VDD
Core Supply Voltage
VDDO
Output Supply Voltage
IDD
Power Supply Current
13
mA
IDDO
Output Supply Current
51
mA
83908AG-02
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REV. A JULY 20, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83908-02
LOW SKEW, 1-TO-8
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 4F. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C
Symbol
VIH
VIL
IIH
IIL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
VOH
CLK0,
CLK_SEL0:1
OE
CLK0,
CLK_SEL0:1
OE
Output HighVoltage
Test Conditions
Minimum
Maximum
Units
VDD = 3.3V ± 5%
2.0
Typical
VDD + 0.3
V
VDD = 2.5V ± 5%
1.7
VDD + 0.3
V
VDD = 3.3V ± 5%
-0.3
0. 8
V
VDD = 2.5V ± 5%
-0.3
0. 7
V
VDD = 3.3V or 2.5V ± 5%
150
µA
VDD = 3.3V or 2.5V ± 5%
5
µA
VDD = 3.3V or 2.5V ± 5%
-5
µA
VDD = 3.3V or 2.5V ± 5%
-150
µA
VDDO = 3.3V ± 5%; NOTE 1
2.6
V
VDDO = 2.5V ± 5%; NOTE 1
1.8
V
VDDO = 1.8V ± 0.2V; NOTE 1
1.5
V
VDDO = 3.3V ± 5%; NOTE 1
VOL
Output Low Voltage
0.5
V
VDDO = 2.5V ± 5%; NOTE 1
0.5
V
VDDO = 1.8V ± 0.2V; NOTE 1
0. 4
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation / cut
Typical Maximum
Units
Fundamental
Frequency
40
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
83908AG-02
10
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REV. A JULY 20, 2005
PRELIMINARY
Integrated
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ICS83908-02
LOW SKEW, 1-TO-8
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 6A. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = 0°C TO 70°C
Symbol Parameter
fMAX
tpLH
t sk(o)
t sk(pp)
tR / tF
Par t-to-Par t Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 2, 4
Output Rise/Fall Time
odc
Output Duty Cycle
tEN
Output Enable Time; NOTE 5
tjit(Ø)
Test Conditions
Minimum
w/External
Output Frequency XTAL
w/External CLK
Propagation Delay, Low-to-High;
NOTE 1
Output Skew; NOTE 2
Typical
Maximum
Units
40
MHz
10
200
MHz
2
ns
TBD
ps
TBD
ps
25MHz, (100Hz - 1MHz)
0.22
ps
20% to 80%
457
ps
50
%
10
ns
8
ns
Maximum
Units
40
MHz
Output Disable Time; NOTE 5
tDIS
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
TABLE 6B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0°C TO 70°C
Symbol Parameter
fMAX
tpLH
t sk(o)
t sk(pp)
tR / tF
Par t-to-Par t Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 2, 4
Output Rise/Fall Time
odc
Output Duty Cycle
tEN
Output Enable Time; NOTE 5
tjit(Ø)
Test Conditions
w/External
Output Frequency XTAL
w/External CLK
Propagation Delay, Low-to-High;
NOTE 1
Output Skew; NOTE 2
Minimum
Typical
10
200
MHz
2.2
ns
TBD
ps
TBD
ps
25MHz, (100Hz - 1MHz)
0.21
ps
20% to 80%
463
ps
50
Output Disable Time; NOTE 5
tDIS
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
83908AG-02
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5
%
10
ns
8
ns
REV. A JULY 20, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83908-02
LOW SKEW, 1-TO-8
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 6C. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter
fMAX
tpLH
t sk(o)
t sk(pp)
tR / tF
Par t-to-Par t Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 2, 4
Output Rise/Fall Time
odc
Output Duty Cycle
tEN
Output Enable Time; NOTE 5
tjit(Ø)
Test Conditions
w/External
Output Frequency XTAL
w/External CLK
Propagation Delay, Low-to-High;
NOTE 1
Output Skew; NOTE 2
Minimum
Typical
Maximum
Units
40
MHz
10
200
MHz
2.5
ns
TBD
ps
TBD
ps
25MHz, (100Hz - 1MHz)
0.22
ps
20% to 80%
487
ps
50
%
10
ns
8
ns
Maximum
Units
40
MHz
Output Disable Time; NOTE 5
tDIS
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
TABLE 6D. AC CHARACTERISTICS, VDD = VDDO = 2.5V ± 5%, TA = 0°C TO 70°C
Symbol Parameter
fMAX
tpLH
t sk(o)
t sk(pp)
tR / tF
Par t-to-Par t Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 2, 4
Output Rise/Fall Time
odc
Output Duty Cycle
tEN
Output Enable Time; NOTE 5
tjit(Ø)
Test Conditions
w/External
Output Frequency XTAL
w/External CLK
Propagation Delay, Low-to-High;
NOTE 1
Output Skew; NOTE 2
Minimum
Typical
10
200
MHz
2.3
ns
TBD
ps
TBD
ps
25MHz, (100Hz - 1MHz)
0.29
ps
20% to 80%
470
ps
50
Output Disable Time; NOTE 5
tDIS
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
83908AG-02
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6
%
10
ns
8
ns
REV. A JULY 20, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83908-02
LOW SKEW, 1-TO-8
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 6E. AC CHARACTERISTICS, VDD = 2.5V ± 5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter
fMAX
tpLH
t sk(o)
t sk(pp)
tR / tF
Par t-to-Par t Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 2, 4
Output Rise/Fall Time
odc
Output Duty Cycle
tEN
Output Enable Time; NOTE 5
tjit(Ø)
Test Conditions
w/External
Output Frequency XTAL
w/External CLK
Propagation Delay, Low-to-High;
NOTE 1
Output Skew; NOTE 2
Minimum
Typical
Maximum
Units
40
MHz
10
200
MHz
2.6
ns
TBD
ps
TBD
ps
25MHz, (100Hz - 1MHz)
0.3
ps
20% to 80%
518
ps
50
%
Output Disable Time; NOTE 5
tDIS
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
83908AG-02
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7
10
ns
8
ns
REV. A JULY 20, 2005
PRELIMINARY
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Systems, Inc.
ICS83908-02
LOW SKEW, 1-TO-8
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
25MHz
RMS Phase Jitter (Random)
100Hz to 1MHz = 0.22ps (typical)
-90
-100
-110
-120
-130
-140
-150
-160
Raw Phase Noise Data
➤
NOISE POWER dBc
Hz
TYPICAL PHASE NOISE AT 25MHZ @ 3.3V
0
-10
-20
-30
-40
-50
-60
-70
-80
-170
-180
-190
100
1k
10k
100k
1M
OFFSET FREQUENCY (HZ)
83908AG-02
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ICS83908-02
LOW SKEW, 1-TO-8
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
1.25V±5%
SCOPE
VDD,
VDDO
LVCMOS
SCOPE
VDD ,
VDDO
Qx
Qx
LVCMOS
GND
GND
-1.65V±5%
-1.25V±5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.05V±5%
2.4V±0.065V 0.9V±0.1V
1.25V±5%
SCOPE
VDD
VDDO
LVCMOS
SCOPE
VDD
VDDO
Qx
Qx
LVCMOS
GND
GND
-0.9V±0.1V
-1.25V±5%
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
1.6V±0.025V 0.9V±0.1V
Part 1
SCOPE
V DD
VDDO
LVCMOS
V
Qx
DDO
2
Qx
Part 2
GND
Qy
V
DDO
2
tsk(pp)
-0.9V±0.1V
2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
83908AG-02
PART-TO-PART SKEW
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LOW SKEW, 1-TO-8
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
VDD
CLK0
ICS83908-02
80%
80%
tR
tF
2
VDDO
Q0:Q7
Clock
Outputs
2
tpLH
PROPAGATION DELAY
20%
20%
OUTPUT RISE/FALL TIME
V
DDO
2
Q0:Q7
t PW
t
odc =
PERIOD
t PW
x 100%
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
83908AG-02
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ICS83908-02
LOW SKEW, 1-TO-8
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
APPLICATION INFORMATION
CRYSTAL INPUT INTERFACE
quencies with accuracy suitable for most applications. Additional
accuracy can be achieved by adding two small capacitors C1
and C2 as shown in Figure 1. Typical results using parallel 18pF
crystals are shown in Table 5.
A crystal can be characterized for either series or parallel mode
operation. The ICS83908-02 has a built-in crystal oscillator
circuit. This interface can accept either a series or parallel
crystal without additional components and generate fre-
XTAL_OUT
C1
15p
X1
18pF Parallel Crystal
XTAL_IN
C2
15p
Figure 1. Crystal Input Interface
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating. Though
not required, but for additional protection, a 1kΩ resister can be
tied from XTAL_IN to ground.
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. We recommend
that there is no trace attached.
CLK INPUT:
For applications not requiring the use of the test clock, it can be
left floating. Though not required, but for additional protection, a
1kΩ resister can be tied from the CLK input to ground.
SELECT PINS:
All select pins have internal pull-ups and pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resister can be used.
83908AG-02
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ICS83908-02
LOW SKEW, 1-TO-8
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
FOR
24 LEAD TSSOP
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
70°C/W
65°C/W
62°C/W
TRANSISTOR COUNT
The transistor count for ICS83908-02 is: 277
83908AG-02
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PACKAGE OUTLINE - G SUFFIX
ICS83908-02
LOW SKEW, 1-TO-8
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
FOR
24 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
N
Maximum
24
A
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
7.70
7.90
E
E1
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MO-153
83908AG-02
www.icst.com/products/hiperclocks.html
13
REV. A JULY 20, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83908-02
LOW SKEW, 1-TO-8
CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS83908AG-02
ICS83908AG-02
24 Lead TSSOP
tube
0°C to 70°C
ICS83908AG-02T
ICS83908AG-02
24 Lead TSSOP
2500 tape & reel
0°C to 70°C
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
83908AG-02
www.icst.com/products/hiperclocks.html
14
REV. A JULY 20, 2005
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