ADS8481 SLAS385A – FEBRUARY 2006 – REVISED MARCH 2006 18-BIT, 1-MSPS, PSEUDO-DIFFERENTIAL UNIPOLAR INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • • 0 to 1 MSPS Sampling Rate 18-Bit NMC Ensured Over Temperature Low ±0.1 mV Offset Error Low 0.2 ppm/°C Offset Error Temperature Drift Low 0.6 ppm/°C Gain Error Temperature Drift Zero Latency Low Power: 220 mW at 1 MSPS Unipolar Single-Ended Input Range: 0 V to Vref Onboard Reference Onboard Reference Buffer High-Speed Parallel Interface Wide Digital Supply 2.7 V ~ 5.25 V 8-/16-/18-Bit Bus Transfer 7x7 QFN Package Medical Instruments Optical Networking Transducer Interface High Accuracy Data Acquisition Systems Magnetometers DESCRIPTION The ADS8481 is an 18-bit, 1-MSPS A/D converter with an internal 4.096-V reference and a pseudo-differential unipolar single-ended input. The device includes a 18-bit capacitor-based SAR A/D converter with inherent sample and hold. The ADS8481 offers a full 18-bit interface, a 16-bit option where data is read using two read cycles, or an 8-bit bus option using three read cycles. The ADS8481 is available in a 7x7 QFN package and is characterized over the industrial –40°C to 85°C temperature range. HIGH SPEED SAR CONVERTER FAMILY TYPE/SPEED 18-Bit Pseudo-Diff 500 kHz 580 kHz ADS8383 ADS8381 750 kHz 1 MHz 1.25 MHz 2 MHz ADS8401 ADS8411 3 MHz 4MHz ADS8481 ADS8380(S) 18-Bit Pseudo-Bipolar, Fully Diff ADS8382(S) ADS8482 ADS8371 16-Bit Pseudo-Diff ADS8471 ADS8405 ADS8472 16-Bit Pseudo-Bipolar, Fully Diff ADS8402 ADS8412 ADS8406 14-Bit Pseudo-Diff ADS7890 (s) 12-Bit Pseudo-Diff ADS7886 SAR +IN −IN + _ CDAC ADS7891 ADS7883 Output Latches and 3-State Drivers ADS7881 BYTE 16-/8-Bit Parallel DATA Output Bus BUS 18/16 Comparator REFIN REFOUT 4.096-V Internal Reference Clock Conversion and Control Logic CONVST BUSY CS RD Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated ADS8481 www.ti.com SLAS385A – FEBRUARY 2006 – REVISED MARCH 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) MODEL MAXIMUM INTEGRAL LINEARITY (LSB) ADS8481I ADS8481IB (1) ±5 ±3.5 MAXIMUM DIFFERENTIAL LINEARITY (LSB) NO MISSING CODES RESOLUTION (BIT) PACKAGE TYPE 18 7x7 48 Pin QFN 18 7x7 48 Pin QFN –1 to +2.5 –1 to +1.5 PACKAGE DESIGNATOR TEMPERATURE RANGE RGZ –40°C to 85°C RGZ –40°C to 85°C ORDERING INFORMATION TRANSPORT MEDIA QTY. ADS8482IRGZT Tape and reel 250 ADS8481IRGZR Tape and reel 1000 ADS8481IBRGZT Tape and reel 250 ADS8481IBRGZR Tape and reel 1000 For the most current specifications and package information, refer to our website at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) Voltage VALUE UNIT +IN to AGND –0.4 to +VA + 0.1 V –IN to AGND –0.4 to 0.5 V +VA to AGND –0.3 to 7 V +VBD to BDGND –0.3 to 7 V –0.3 to 2.55 V Digital input voltage to BDGND –0.3 to +VBD + 0.3 V Digital output voltage to BDGND +VA to +VBD –0.3 to +VBD + 0.3 V TA Operating free-air temperature range –40 to 85 °C Tstg Storage temperature range –65 to 150 °C 150 °C Junction temperature (TJ max) QFN package Lead temperature, soldering (1) 2 Power dissipation (TJMax – TA)/θJA θJA thermal impedance 22 °C/W Vapor phase (60 sec) 215 °C Infrared (15 sec) 220 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback ADS8481 www.ti.com SLAS385A – FEBRUARY 2006 – REVISED MARCH 2006 SPECIFICATIONS TA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1 MSPS (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-scale input voltage (1) +IN – (–IN) Absolute input voltage 0 Vref +IN –0.2 Vref +0.2 –IN –0.2 0.2 Input capacitance Input leakage current V V 65 pF 1 nA SYSTEM PERFORMANCE Resolution No missing codes Integral linearity (2) (3) Differential linearity Offset error (4) 18 ADS8481I 18 ADS8481IB 18 ADS8481I Bits –5 –1.5/+1.9 5 3.5 ADS8481I –1 –0.5/+0.7 2.5 ADS8481IB –1 –0.5/+0.7 1.5 ADS8481I –0.5 ±0.1 0.5 ADS8481IB –0.5 ±0.1 0.5 ±0.2 Vref = 4.096 V –0.075 ±0.05 0.075 ADS8481IB Vref = 4.096 V –0.075 ±0.05 0.075 Noise At 3FFFFh output code LSB (18 bit) LSB (18 bit) mV ppm/°C ADS8481I Gain error temperature drift Power supply rejection ratio 18 –3.5 –1.5/+1.9 ADS8481IB Offset error temperature drift Gain error (4) (5) Bits %FS %FS ±0.6 ppm/°C 30 µV RMS 60 dB SAMPLING DYNAMICS Conversion time 650 Acquisition time 710 250 ns ns Throughput rate 1 MHz Aperture delay 4 ns Aperture jitter 5 ps Step response 150 ns Over voltage recovery 150 ns (1) (2) (3) (4) (5) Ideal input span, does not include gain or offset error. LSB means least significant bit This is endpoint INL, not best fit. Measured relative to an ideal full-scale input [+IN – (–IN)] of 4.096 V This specification does not include the internal reference voltage error and drift. Submit Documentation Feedback 3 ADS8481 www.ti.com SLAS385A – FEBRUARY 2006 – REVISED MARCH 2006 SPECIFICATIONS (Continued) TA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1 MSPS (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC CHARACTERISTICS ADS8481I ADS8481IB Total harmonic distortion (THD) (1) ADS8481I ADS8481IB ADS8481I ADS8481IB ADS8481I ADS8481IB Signal to noise ratio (SNR) (1) ADS8481I ADS8481IB ADS8481I ADS8481IB ADS8481I ADS8481IB Signal to noise + distortion (SINAD) (1) ADS8481I ADS8481IB ADS8481I ADS8481IB ADS8481I ADS8481IB Spurious free dynamic range (SFDR) (1) ADS8481I ADS8481IB ADS8481I ADS8481IB –110 VIN = 4 Vpp at 1 kHz –112 –106 VIN = 4 Vpp at 10 kHz dB –108 –98 VIN = 4 Vpp at 100 kHz –99 92 VIN = 4 Vpp at 1 kHz 94 91 VIN = 4 Vpp at 10 kHz dB 93 90 VIN = 4 Vpp at 100 kHz 92 91 VIN = 4 Vpp at 1 kHz 93 90 VIN = 4 Vpp at 10 kHz dB 92 89 VIN = 4 Vpp at 100 kHz 91 110 VIN = 4 Vpp at 1 kHz 112 108 VIN = 4 Vpp at 10 kHz dB 107 98 VIN = 4 Vpp at 100 kHz 98 –3dB Small signal bandwidth 15 MHz VOLTAGE REFERENCE INPUT Reference voltage at REFIN, Vref Reference Reference current drain (1) (2) 4 3.0 resistance (2) 4.096 4.2 500 fs = 1 MHz Calculated on the first nine harmonics of the input frequency. Can vary ±20% Submit Documentation Feedback V kΩ 1 mA ADS8481 www.ti.com SLAS385A – FEBRUARY 2006 – REVISED MARCH 2006 SPECIFICATIONS (Continued) TA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1 MSPS (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 120 ms INTERNAL REFERENCE OUTPUT Internal reference start-up time From 95% (+VA), with 1-µF storage capacitor Reference voltage range, Vref IO = 0 A Source current Static load Line regulation +VA = 4.75 V to 5.25 V 60 µV Drift IO = 0 A ±6 PPM/C 4.081 4.096 4.111 V 10 µA DIGITAL INPUT/OUTPUT Logic family – CMOS Logic level VIH IIH = 5 µA +VBD–1 +VBD +0.3 VIL IIL = 5 µA –0.3 0.8 VOH IOH = 2 TTL loads VOL IOL = 2 TTL loads +VBD– 0.6 V 0.4 Data format – Straight Binary POWER SUPPLY REQUIREMENTS Power supply voltage +VBD 2.7 +VA 3.3 5.25 4.75 V 5 5.25 Supply current (1) fs = 1 MHz 44 48 mA V Power dissipation (1) fs = 1 MHz 220 240 mW 85 °C TEMPERATURE RANGE Operating free-air (1) –40 This includes only +VA current. +VBD current is typical 1 mA with 5 pF load capacitance on all output pins. Submit Documentation Feedback 5 ADS8481 www.ti.com SLAS385A – FEBRUARY 2006 – REVISED MARCH 2006 TIMING CHARACTERISTICS All specifications typical at –40°C to 85°C, +VA =+VBD = 5 V (1) (2) (3) PARAMETER MIN TYP UNIT 710 ns Conversion time t(ACQ) Acquisition time t(HOLD) Sample capacitor hold time 25 ns tpd1 CONVST low to BUSY high 40 ns tpd2 Propagation delay time, end of conversion to BUSY low 15 ns tpd3 Propagation delay time, start of convert state to rising edge of BUSY 15 ns tw1 Pulse duration, CONVST low 40 ns tsu1 Setup time, CS low to CONVST low 20 ns tw2 Pulse duration, CONVST high 20 250 CONVST falling edge jitter ns ns 10 t(ACQ)min ps tw3 Pulse duration, BUSY signal low tw4 Pulse duration, BUSY signal high th1 Hold time, first data bus transition (RD low, or CS low for read cycle, or BYTE or BUS18/16 input changes) after CONVST low td1 Delay time, CS low to RD low tsu2 Setup time, RD high to CS high tw5 Pulse duration, RD low ten Enable time, RD low (or CS low for read cycle) to data valid td2 Delay time, data hold from RD high td3 Delay time, BUS18/16 or BYTE rising edge or falling edge to data valid 10 tw6 Pulse duration, RD high 20 ns tw7 Pulse duration, CS high 20 ns th2 Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge 50 ns tpd4 Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge 0 ns td4 Delay time, BYTE edge to BUS18/16 edge skew 0 ns tsu3 Setup time, BYTE or BUS18/16 transition to RD falling edge 10 ns th3 Hold time, BYTE or BUS18/16 transition to RD falling edge 10 tdis Disable time, RD high (CS high for read cycle) to 3-stated data bus td5 Delay time, BUSY low to MSB data valid delay td6 Delay time, CS rising edge to BUSY falling edge 50 ns td7 Delay time, BUSY falling edge to CS rising edge 50 ns tsu5 BYTE transition setup time, from BYTE transition to next BYTE transition, or BUS18/16 transition setup time, from BUS18/16 to next BUS18/16. 50 ns (1) (2) (3) ns 710 ns 0 ns 0 ns ns 20 5 60 All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2. See timing diagrams. All timing are measured with 20-pF equivalent loads on all data bits and BUSY pins. Submit Documentation Feedback ns 40 50 tsu(ABORT) Setup time from the falling edge of CONVST (used to start the valid conversion) to the next falling edge of CONVST (when CS = 0 and CONVST are used to abort) or to the next falling edge of CS (when CS is used to abort). 6 MAX t(CONV) ns ns 20 ns ns 20 ns 0 ns 610 ns ADS8481 www.ti.com SLAS385A – FEBRUARY 2006 – REVISED MARCH 2006 TIMING CHARACTERISTICS All specifications typical at –40°C to 85°C, +VA = 5 V +VBD = 3 V (1) (2) (3) PARAMETER MIN TYP MAX UNIT 710 ns t(CONV) Conversion time t(ACQ) Acquisition time t(HOLD) Sample capacitor hold time 25 ns tpd1 CONVST low to BUSY high 40 ns tpd2 Propagation delay time, end of conversion to BUSY low 25 ns tpd3 Propagation delay time, start of convert state to rising edge of BUSY 25 ns tw1 Pulse duration, CONVST low 40 ns tsu1 Setup time, CS low to CONVST low 20 ns tw2 Pulse duration, CONVST high 20 250 CONVST falling edge jitter ns ns 10 t(ACQ)min ps tw3 Pulse duration, BUSY signal low tw4 Pulse duration, BUSY signal high th1 Hold time, first data bus transition (RD low, or CS low for read cycle, or BYTE or BUS18/16 input changes) after CONVST low td1 Delay time, CS low to RD low tsu2 Setup time, RD high to CS high tw5 Pulse duration, RD low ten Enable time, RD low (or CS low for read cycle) to data valid td2 Delay time, data hold from RD high td3 Delay time, BUS18/16 or BYTE rising edge or falling edge to data valid 10 tw6 Pulse duration, RD high 20 ns tw7 Pulse duration, CS high 20 ns th2 Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge 50 ns tpd4 Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge 0 ns td4 Delay time, BYTE edge to BUS18/16 edge skew 0 ns tsu3 Setup time, BYTE or BUS18/16 transition to RD falling edge 10 ns th3 Hold time, BYTE or BUS18/16 transition to RD falling edge 10 tdis Disable time, RD high (CS high for read cycle) to 3-stated data bus td5 Delay time, BUSY low to MSB data valid delay td6 Delay time, CS rising edge to BUSY falling edge 50 ns td7 Delay time, BUSY falling edge to CS rising edge 50 ns tsu5 BYTE transition setup time, from BYTE transition to next BYTE transition, or BUS18/16 transition setup time, from BUS18/16 to next BUS18/16. 50 ns ns 40 ns 0 ns 0 ns 50 ns 30 5 tsu(ABORT) Setup time from the falling edge of CONVST (used to start the valid conversion) to the next falling edge of CONVST (when CS = 0 and CONVST are used to abort) or to the next falling edge of CS (when CS is used to abort). (1) (2) (3) ns 710 70 ns ns 30 ns ns 30 ns 0 ns 620 ns All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2. See timing diagrams. All timing are measured with 20-pF equivalent loads on all data bits and BUSY pins. Submit Documentation Feedback 7 ADS8481 www.ti.com SLAS385A – FEBRUARY 2006 – REVISED MARCH 2006 PIN ASSIGNMENTS BUSY DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 BDGND RGZ PACKAGE (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 +VBD DB10 DB11 DB12 DB13 DB14 DB15 DB16 DB17 AGND AGND +VA AGND AGND −IN AGND +VA +VA +IN AGND NC +VA REFIN 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 REFOUT +VBD BUS18/16 BYTE CONVST RD CS +VA AGND AGND +VA REFM REFM NC − No internal connection NOTE: The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. 8 Submit Documentation Feedback ADS8481 www.ti.com SLAS385A – FEBRUARY 2006 – REVISED MARCH 2006 PIN ASSIGNMENTS (continued) TERMINAL FUNCTIONS NAME NO RGZ I/O AGND 8, 9, 17, 20, 23, 24, 26, 27 DESCRIPTION – Analog ground BDGND 37 – Digital ground for bus interface digital supply BUSY 48 O Status output. High when a conversion is in progress. BUS18/16 2 I Bus size select input. Used for selecting 18-bit or 16-bit wide bus transfer. 0: Data bits output on the 18-bit data bus pins DB[17:0]. 1: Last two data bits D[1:0] from 18-bit wide bus output on: a) the low byte pins DB[9:2] if BYTE = 0 b) the high byte pins DB[17:10] if BYTE = 1 BYTE 3 I Byte select input. Used for 8-bit bus reading. 0: No fold back 1: Low byte D[9:2] of the 16 most significant bits is folded back to high byte of the 16 most significant pins DB[17:10]. CONVST 4 I Convert start. The falling edge of this input ends the acquisition period and starts the hold period. CS 6 I Chip select. The falling edge of this input starts the acquisition period. 8-BIT BUS Data Bus 16-BIT BUS 18-BIT BUS BYTE = 0 BYTE = 1 BYTE = 1 BYTE = 0 BYTE = 0 BYTE = 0 BUS18/16 = 0 BUS18/16 = 0 BUS18/16 = 1 BUS18/16 = 0 BUS18/16 = 1 BUS18/16 = 0 DB17 28 O D17 (MSB) D9 All ones D17 (MSB) All ones D17 (MSB) DB16 29 O D16 D8 All ones D16 All ones D16 DB15 30 O D15 D7 All ones D15 All ones D15 DB14 31 O D14 D6 All ones D14 All ones D14 DB13 32 O D13 D5 All ones D13 All ones D13 DB12 33 O D12 D4 All ones D12 All ones D12 DB11 34 O D11 D3 D1 D11 All ones D11 DB10 35 O D10 D2 D0 (LSB) D10 All ones D10 DB9 38 O D9 All ones All ones D9 All ones D9 DB8 39 O D8 All ones All ones D8 All ones D8 DB7 40 O D7 All ones All ones D7 All ones D7 DB6 41 O D6 All ones All ones D6 All ones D6 DB5 42 O D5 All ones All ones D5 All ones D5 DB4 43 O D4 All ones All ones D4 All ones D4 DB3 44 O D3 All ones All ones D3 D1 D3 DB2 45 O D2 All ones All ones D2 D0 (LSB) D2 DB1 46 O D1 All ones All ones D1 All ones D1 DB0 47 O D0 (LSB) All ones All ones D0 (LSB) All ones D0 (LSB) –IN 19 I Inverting input channel +IN 18 I Noninverting input channel NC 15 REFIN 13 I Reference input REFOUT 14 O Reference output. Add 1-µF capacitor between the REFOUT pin and REFM pin when internal reference is used. 11, 12 I Reference ground RD 5 I Synchronization pulse for the parallel output. When CS is low, this serves as output enable and puts the previous conversion results on the bus. +VA 7, 10, 16, 21, 22, 25 – Analog power supplies, 5-V DC 1, 36 – Digital power supply for bus REFM +VBD No connection Submit Documentation Feedback 9 ADS8481 www.ti.com SLAS385A – FEBRUARY 2006 – REVISED MARCH 2006 TYPICAL CHARACTERISTICS INTERNAL REFERENCE VOLTAGE vs FREE-AIR TEMPERATURE DC HISTOGRAM (8192 Conversion Outputs) Frequency 2000 4.098 4.0975 1683 1626 1003 785 4.0965 4.096 0 4 4.095 -40 131079 32 30 131065 131066 131067 131068 131069 131070 131071 131072 131073 131074 131075 131076 131077 131078 6 4.09717 4.09716 4.09715 4.09714 4.0955 0 4.09718 111 132 0 4.097 488 446 500 TA = 25°C 4.09719 1846 1500 1000 4.0972 +VA = 5 V, +VBD = 5 V Reference Voltage - V +VA = 5 V, +VBD = 5 V, TA = 25°C, fi = 1 MSPS, Vref = 4.096 V, Input = Midscale Reference Voltage - V 2500 INTERNAL REFERENCE VOLTAGE vs SUPPLY VOLTAGE -25 -10 5 20 35 50 65 4.09713 4.75 80 4.85 4.95 5.05 5.15 Supply Voltage - V 5.25 TA - Free-Air Temperature - °C Output Code Figure 1. Figure 2. Figure 3. SUPPLY CURRENT vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs SUPPLY VOLTAGE SUPPLY CURRENT vs SAMPLE RATE 44.2 43.6 43.4 44 TA = 25°C, fi = 1 MSPS, Vref = 4.096 V 43 43.8 43.6 43.4 43.2 42.5 42 41.5 41 40.5 40 43 43.2 39.5 42.8 43 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 42.6 4.75 4.85 4.95 5.05 5.15 Supply Voltage - V 5.25 500 750 Sample Rate - KSPS 1000 Figure 5. Figure 6. DIFFERENTIAL NONLINEARITY vs FREE-AIR TEMPERATURE INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE DIFFERENTIAL NONLINEARITY vs SUPPLY VOLTAGE 4 1.5 3 Max 1 2 Max 0.5 0 Min 1 0 -1 Max +VA = 5 V, +VBD = 5 V, fi = 1 MSPS, Vref = 4.096 V DNL - LSBs +VA = 5 V, +VBD = 5 V, fi = 1 MSPS, Vref = 4.096 V INL - LSBs 1 39 38.5 250 Figure 4. 1.5 DNL - LSBs +VA = 5 V, +VBD = 5 V, TA = 25°C, Vref = 4.096 V 43.5 Supply Current - mA +VA = 5 V, +VBD = 5 V, fi = 1 MSPS, Vref = 4.096 V Supply Current - mA Supply Current - mA 43.8 44 44.4 44 Min 0.5 0 +VA = 5 V, +VBD = 5 V, TA = 25°C fi = 1 MSPS, Vref = 4.096 V Min -2 -0.5 -0.5 -3 -1 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C Figure 7. 10 80 -4 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C Figure 8. Submit Documentation Feedback 80 -1 4.75 4.85 4.95 5.05 5.15 Supply Voltage - V Figure 9. 5.25 ADS8481 www.ti.com SLAS385A – FEBRUARY 2006 – REVISED MARCH 2006 TYPICAL CHARACTERISTICS (continued) INTEGRAL NONLINEARITY vs SUPPLY VOLTAGE DIFFERENTIAL NONLINEARITY vs REFERENCE VOLTAGE 4 4 1.5 VDD = 5 V, TA = 25°C fi = 1 MSPS 3 1 Max DNL - LSBs 0 -1 0.5 0 Min -2 -1 -4 4.75 4.85 4.95 5.05 5.15 Min -4 3.2 3 5.25 Supply Voltage - V 3.2 3.4 3.6 3.8 Reference Voltage - V 4 4.2 OFFSET ERROR vs FREE-AIR TEMPERATURE OFFSET ERROR vs SUPPLY VOLTAGE OFFSET ERROR vs REFERENCE VOLTAGE -0.02 -0.02 -0.03 -0.03 -0.04 -0.05 -0.06 -0.07 +VA = 5 V, +VBD = 5 V, fi = 1 MSPS, Vref = 4.096 V -0.08 -0.09 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C -0.04 -0.05 -0.06 -0.03 -0.04 -0.05 -0.06 -0.07 -0.07 -0.08 -0.08 -0.09 -0.09 -0.1 4.75 80 0 VDD = 5 V, -0.01 T = 25°C, A -0.02 fi = 1 MSPS TA = 25°C, fi = 1 MSPS, Vref = 4.096 V Offset Error - mV 0 -0.01 -0.1 4.85 4.95 5.05 5.15 3 5.25 3.2 Supply Voltage - V 3.4 3.6 3.8 Reference Voltage - V 4 Figure 13. Figure 14. Figure 15. GAIN ERROR vs SUPPLY VOLTAGE GAIN ERROR vs FREE-AIR TEMPERATURE GAIN ERROR vs REFERENCE VOLTAGE -0.01 -0.03 Gain Error - %FS -0.04 -0.05 -0.06 -0.07 4.85 4.95 5.05 Supply Voltage - V Figure 16. 5.15 5.25 -0.035 +VA = 5 V, +VBD = 5 V, fi = 1 MSPS, Vref = 4.096 V 0.06 -0.04 -0.045 -0.05 0.04 0.02 0 -0.02 -0.055 -0.04 -0.06 -0.06 -0.065 -0.08 -0.07 -40 VDD = 5 V, TA = 25°C, fi = 1 MSPS 0.08 Gain Error - %FS -0.025 4.2 0.1 -0.02 TA = 25°C, fi = 1 MSPS, Vref = 4.096 -0.03 -0.08 4.75 3 4.2 Figure 12. 0 -0.02 4 Figure 11. -0.01 -0.1 -40 3.6 3.8 3.4 Reference Voltage - V Figure 10. Offset Error - mV Offset Error - mV 0 -1 -3 -3 Gain Error - %FS 1 -2 Min -0.5 Max 2 Max +VA = 5 V, +VBD = 5 V, TA = 25°C fi = 1 MSPS, Vref = 4.096 V 1 VDD = 5 V, TA = 25°C fi = 1 MSPS 3 INL - LSBs 2 INL - LSBs INTEGRAL NONLINEARITY vs REFERENCE VOLTAGE -0.1 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C Figure 17. Submit Documentation Feedback 80 3 3.2 3.4 3.6 3.8 4 4.2 Reference Voltage - V Figure 18. 11 ADS8481 www.ti.com SLAS385A – FEBRUARY 2006 – REVISED MARCH 2006 TYPICAL CHARACTERISTICS (continued) OFFSET ERROR TEMPERATURE DRIFT DISTRIBUTION (25 Samples) 12 +VA = 5 V, +VBD = 5 V, fi = 1 MSPS Vref = 4.096 V 8 8 -110 +VA = 5 V, +VBD = 5 V, fi = 1 MSPS, Vref = 4.096 V 10 THD - Total Harmonic Distortion - dB 10 10 Frequency Frequency 8 6 5 4 4 4 3 7 6 4 3 2 2 2 1 0.02 0.06 0.10 0.14 0.18 Offset Drift - ppm/C -112 +VA = 5 V, +VBD = 5 V, fs = 1 MSPS, TA = 25°C, fi = 2 kHz -113 -114 -115 -116 2.5 2.7 1.30 2.9 3.1 3.3 3.5 3.7 3.9 4.1 Vref - Reference Voltage - V Figure 20. Figure 21. SIGNAL-TO-NOISE RATIO vs REFERENCE VOLTAGE SIGNAL-TO-NOISE + DISTORTION vs REFERENCE VOLTAGE TOTAL HARMONIC DISTORTION vs FREE-AIR TEMPERATURE 90 89 88 2.7 93 92 +VA = 5 V, +VBD = 5 V, fs = 1 MSPS, TA = 25°C, fi = 2 kHz 91 90 89 88 87 2.5 2.9 3.1 3.3 3.5 3.7 3.9 4.1 Vref - Reference Voltage - V -112 94 THD - Total Harmonic Distortion - dB SINAD - Signal-to-Noise + Distortion - dB 91 2.7 -112.50 -113 -113.50 +VA = 5 V, +VBD = 5 V, fs = 1 MSPS, Vref = 4.096 V, fi = 2 kHz -114 -114.50 -115 -115.50 -116 -40 -25 2.9 3.1 3.3 3.5 3.7 3.9 4.1 Vref - Reference Voltage - V -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 Figure 22. Figure 23. Figure 24. SPURIOUS FREE DYNAMIC RANGE vs FREE-AIR TEMPERATURE SIGNAL-TO-NOISE RATIO vs FREE-AIR TEMPERATURE SIGNAL-TO-NOISE + DISTORTION vs FREE-AIR TEMPERATURE 94.5 116 115.5 115 114.5 114 113.5 -40 +VA = 5 V, +VBD = 5 V, fs = 1 MSPS, Vref = 4.096 V, fi = 2 kHz -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C Figure 25. 94 93.5 SINAD - Signal-to-Noise + Distortion - dB 95 116.5 SNR - Signal-to-Noise Ratio - dB SNR - Signal-to-Noise Ratio - dB SFDR - Spurious Free Dynamic Range - dB -0.16 0.21 0.59 0.97 Gain Error Drift - ppm/C -111 Figure 19. +VA = 5 V, +VBD = 5 V, fs = 1 MSPS, TA = 25°C, fi = 2 kHz 87 2.5 12 1 -0.54 0.22 94 92 2 0 0 93 TOTAL HARMONIC DISTORTION vs REFERENCE VOLTAGE GAIN ERROR TEMPERATURE DRIFT DISTRIBUTION (25 Samples) +VA = 5 V, +VBD = 5 V, fs = 1 MSPS, Vref = 4.096 V, fi = 2 kHz 93 92.5 92 91.5 91 90.5 80 90 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C Figure 26. Submit Documentation Feedback 80 95 94.5 94 93.5 +VA = 5 V, +VBD = 5 V, fs = 1 MSPS, Vref = 4.096 V, fi = 2 kHz 93 92.5 92 91.5 91 90.5 90 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C Figure 27. 80 ADS8481 www.ti.com SLAS385A – FEBRUARY 2006 – REVISED MARCH 2006 TYPICAL CHARACTERISTICS (continued) DNL 1.5 +VA = 5 V, +VBD = 5 V, TA = 25°C, fi = 1 MSPS, Vref = 4.096 V DNL - LSBs 1 0.5 0 -0.5 -1 -1.5 0 65536 131072 Output Code Figure 28. 196608 262144 196608 262144 INL 3.5 +VA = 5 V, +VBD = 5 V, TA = 25°C, fi = 1 MSPS, Vref = 4.096 V INL - LSBs 2.5 1.5 0.5 0 -0.5 -1.5 -2.5 -3.5 0 65536 131072 Output Code Figure 29. FFT 0 +VA = 5 V, +VBD = 5 V, TA = 25°C, fs = 1 MSPS, Vref = 4.096 V, fi = 100 kHz, 32768 Points -25 Amplitude - dB -50 -75 -100 -125 -150 -175 -200 -225 0 100 200 300 f - Frequency - kHz Figure 30. Submit Documentation Feedback 400 500 13 ADS8481 www.ti.com SLAS385A – FEBRUARY 2006 – REVISED MARCH 2006 TYPICAL CHARACTERISTICS (continued) TIMING DIAGRAMS tw2 tw1 CONVST tpd1 tpd2 tw4 tw3 BUSY tsu1 CS tpd3 tw7 td7 td6 CONVERT† t(CONV) t(CONV) t(HOLD) SAMPLING† (When CS Toggle) t(ACQ) tsu(ABORT) tsu(ABORT) BYTE tsu5 th1 BUS 18/16 tsu5 tsu2 tpd4 th2 td1 RD tdis ten DB[17:12] Hi−Z D[17:12] Hi−Z D[9:4] MSB DB[11:10] DB[9:0] †Signal Hi−Z Hi−Z D[11:10] D[3:2] D[1:0] D[9:0] internal to device Figure 31. Timing for Conversion and Acquisition Cycles With CS and RD Toggling 14 Submit Documentation Feedback Hi−Z Hi−Z ADS8481 www.ti.com SLAS385A – FEBRUARY 2006 – REVISED MARCH 2006 TYPICAL CHARACTERISTICS (continued) tw1 tw2 CONVST tpd1 tpd2 tw4 tw3 BUSY tsu1 tw7 td7 CS tpd3 td6 CONVERT† t(CONV) t(CONV) t(HOLD) SAMPLING† (When CS Toggle) t(ACQ) tsu(ABORT) tsu(ABORT) BYTE tsu5 th1 BUS 18/16 tpd4 th2 RD = 0 ten DB[17:12] DB[11:10] DB[9:0] †Signal ten tdis Previous Hi−Z D[17:12] Hi−Z Hi−Z Previous D[11:10] Previous D [9:0] Hi−Z Hi−Z Hi−Z tdis ten MSB D[17:12] D[11:10] D[9:0] Hi−Z D[9:4] D[3:2] D[1:0] Hi−Z Hi−Z Repeated D[17:12] Repeated D[11:10] Repeated D [9:0] internal to device Figure 32. Timing for Conversion and Acquisition Cycles With CS Toggling, RD Tied to BDGND Submit Documentation Feedback 15 ADS8481 www.ti.com SLAS385A – FEBRUARY 2006 – REVISED MARCH 2006 TYPICAL CHARACTERISTICS (continued) tw1 tw2 CONVST tpd1 tpd2 tw4 tw3 BUSY CS = 0 CONVERT† t(CONV) t(CONV) t(HOLD) t(ACQ) SAMPLING† (When CS = 0) tsu(ABORT) tsu(ABORT) BYTE tsu5 th1 BUS 18/16 tsu5 tpd4 th2 RD tdis ten MSB DB[17:12] DB[11:10] DB[9:0] †Signal Hi−Z Hi−Z Hi−Z D[17:12] D[9:4] D[11:10] D[3:2] D[9:0] Hi−Z D[1:0] Hi−Z Hi−Z internal to device Figure 33. Timing for Conversion and Acquisition Cycles With CS Tied to BDGND, RD Toggling 16 Submit Documentation Feedback ADS8481 www.ti.com SLAS385A – FEBRUARY 2006 – REVISED MARCH 2006 TYPICAL CHARACTERISTICS (continued) tw2 tw1 CONVST tpd1 tw4 tpd2 tw3 BUSY CS = 0 CONVERT† t(CONV) t(CONV) tpd3 tpd3 t(HOLD) t(HOLD) t(ACQ) SAMPLING† (When CS = 0) tsu(ABORT) tsu(ABORT) BYTE tsu5 tsu5 BUS 18/16 tsu5 tsu5 th1 th1 RD = 0 td5 DB[17:12] DB[11:10] DB[9:0] †Signal D[17:12] Previous LSB D[11:10] D[9:4] D[3:2] D[9:0] Next D[17:12] D[1:0] Next D[11:10] Next D[9:0] internal to device Figure 34. Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND - Auto Read Submit Documentation Feedback 17 ADS8481 www.ti.com SLAS385A – FEBRUARY 2006 – REVISED MARCH 2006 TYPICAL CHARACTERISTICS (continued) CS RD BYTE tsu5 BUS 18/16 ten ten DB[17:0] Hi−Z tdis Valid Hi−Z td3 tdis td3 Valid Valid Figure 35. Detailed Timing for Read Cycles 18 Submit Documentation Feedback Hi−Z ADS8481 www.ti.com SLAS385A – FEBRUARY 2006 – REVISED MARCH 2006 APPLICATION INFORMATION MICROCONTROLLER INTERFACING ADS8481 to 8-Bit Microcontroller Interface Figure 36 shows a parallel interface between the ADS8481 and a typical microcontroller using the 8-bit data bus. The BUSY signal is used as a falling-edge interrupt to the microcontroller. Analog 5 V 0.1 µF AGND 10 µF Ext Ref Input 0.1 µF Micro Controller −IN Digital 3 V Data Bus D[17:0] CS AD8481 BYTE BUS18/16 CONVST RD DB[17:10] 0.1 µF BDGND BDGND +VBD Figure 36. ADS8481 Application Circuitry Analog 5 V 0.1 µF AGND 10 µF 0.1 µF AGND AGND REFM REFIN REFOUT 1 µF +VA GPIO GPIO GPIO GPIO RD AD[7:0] +IN +VA REFIN REFM AGND Analog Input ADS8481 Figure 37. ADS8481 Using Internal Reference Submit Documentation Feedback 19 ADS8481 www.ti.com SLAS385A – FEBRUARY 2006 – REVISED MARCH 2006 PRINCIPLES OF OPERATION The ADS8481 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The architecture is based on charge redistribution which inherently includes a sample/hold function. See Figure 36 for the application circuit for the ADS8481. The conversion clock is generated internally. The conversion time of 710 ns is capable of sustaining a 1 MHz throughput. The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. REFERENCE The ADS8481 can operate with an external reference with a range from 3.0 V to 4.2 V. The reference voltage on the input pin #1 (REFIN) of the converter is internally buffered. A clean, low noise, well-decoupled reference voltage on this pin is required to ensure good performance of the converter. A low noise band-gap reference like the REF3240 can be used to drive this pin. A 0.1-µF decoupling capacitor is required between REFIN and REFM pins (pin #13 and pin #12) of the converter. This capacitor should be placed as close as possible to the pins of the device. Designers should strive to minimize the routing length of the traces that connect the terminals of the capacitor to the pins of the converter. An RC network can also be used to filter the reference voltage. A 100-Ω series resistor and a 0.1-µF capacitor, which can also serve as the decoupling capacitor can be used to filter the reference voltage. REFM 0.1 mF 100 W ADS8481 REFIN REF3240 Figure 38. Reference Circuit The ADS8481 also has limited low pass filtering capability built into the converter. The equivalent circuitry on the REFIN input is as shown in Figure 39. 10 kW REFIN + _ 300 pF REFM To CDAC 830 pF To CDAC Figure 39. Reference Circuit The REFM input of the ADS8481 should always be shorted to AGND. A 4.096-V internal reference is included. When internal reference is used, pin 14 (REFOUT) is connected to pin 13 (REFIN) with a 0.1-µF decoupling capacitor and 1-nF storage capacitor between pin 14 (REFOUT) and pins 11 and 12 (REFM) (see Figure Figure 37). The internal reference of the converter is double buffered. If an external reference is used, the second buffer provides isolation between the external reference and the CDAC. This buffer is also used to recharge all of the capacitors of the CDAC during conversion. Pin 14 (REFOUT) can be left unconnected (floating) if an external reference is used. 20 Submit Documentation Feedback ADS8481 www.ti.com SLAS385A – FEBRUARY 2006 – REVISED MARCH 2006 PRINCIPLES OF OPERATION (continued) ANALOG INPUT When the converter enters the hold mode, the voltage difference between the +IN and –IN inputs is captured on the internal capacitor array. The voltage on the -IN input is limited between –0.2 V and 0.2 V, allowing the input to reject small signals which are common to both the +IN and –IN inputs. The +IN input has a range of –0.2 V to Vref + 0.2 V. The input span [+IN – (–IN)] is limited to 0 V to Vref. The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and source impedance. Essentially, the current into the ADS8481 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (65 pF) to an 18-bit settling level within the acquisition time (250 ns) of the device. When the converter goes into the hold mode, the input impedance is greater than 1 GΩ. Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the +IN and –IN inputs and the span [+IN – (–IN)] must be within the limits specified. Outside of these ranges, the converter's linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass filters are used. Care must be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are matched. If this is not observed, the two inputs could have different settling times. This may result in offset error, gain error, and linearity error which varies with temperature and input voltage. The analog input to the converter needs to be driven with a low noise, high-speed op-amp like the THS4031. An RC filter is recommended at the input pins to low-pass filter the noise from the source. A series resistor of 20 Ω and a decoupling capacitor of 680 pF is recommended. The input to the converter is a uni-polar input voltage in the range 0 to Vref. The THS4031 can be used in the source follower configuration to drive the converter. Low-Pass Filter VIN + 20 W INP THS4031 _ 50 W ADS8481 680 pF INM Figure 40. Input Circuit In systems, where the input is bi-polar, the THS4031 can be used in the inverting configuration with an additional DC bias applied to its + input so as to keep the input to the ADS8481 within its rated operating voltage range. This configuration is also recommended when the ADS8481 is used in signal processing applications where good SNR and THD performance is required. The DC bias can be derived from the REF3220 or the REF3240 reference voltage ICs. The input configuration shown below is capable of delivering better than 92dB SNR and -100db THD at an input frequency of 100 kHz. In case band-pass filters are used to filter the input, care should be taken to ensure that the signal swing at the input of the band-pass filter is small so as to keep the distortion introduced by the filter minimal. In such cases, the gain of the circuit shown below can be increased to keep the input to the ADS8481 large to keep the SNR of the system high. Note that the gain of the system from the + input to the output of the THS4031 in such a configuration is a function of the gain of the AC signal. A resistor divider can be used to scale the output of the REF3220 or REF3240 to reduce the voltage at the DC input to THS4031 to keep the voltage at the input of the converter within its rated operating range. Submit Documentation Feedback 21 ADS8481 www.ti.com SLAS385A – FEBRUARY 2006 – REVISED MARCH 2006 PRINCIPLES OF OPERATION (continued) Bipolar to Unipolar Conversion Low-Pass Filter 380 W VIN Vdc _ 380 W 20 W INP THS4031 + ADS8481 680 pF INM Figure 41. Input Circuit DIGITAL INTERFACE Timing and Control See the timing diagrams in the specifications section for detailed information on timing signals and their requirements. The ADS8481 uses an internal oscillator generated clock which controls the conversion rate and in turn the throughput of the converter. No external clock input is required. Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum requirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8481 switches from the sample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of this signal is important to the performance of the converter. The BUSY output is brought high immediately following CONVST going low. BUSY stays high throughout the conversion process and returns low when the conversion has ended. Sampling starts with the falling edge of the BUSY signal when CS is tied low or starts with the falling edge of CS when BUSY is low. Both RD and CS can be high during and before a conversion with one exception (CS must be low when CONVST goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the parallel output bus with the conversion. Reading Data The ADS8481 outputs full parallel data in straight binary format as shown in Table 1. The parallel output is active when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of CONVST. This is 50 ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data read should attempted within this zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTE and BUS18/16 are used for multiword read operations. BYTE is used whenever lower bits on the bus are output on the higher byte of the bus. BUS18/16 is used whenever the last two bits on the 18-bit bus is output on either bytes of the higher 16-bit bus. Refer to Table 1 for ideal output codes. 22 Submit Documentation Feedback ADS8481 www.ti.com SLAS385A – FEBRUARY 2006 – REVISED MARCH 2006 Table 1. Ideal Input Voltages and Output Codes DESCRIPTION ANALOG VALUE Full scale range +Vref DIGITAL OUTPUT STRAIGHT BINARY Least significant bit (LSB) (+Vref)/262144 BINARY CODE HEX CODE +Full scale (+Vref) – 1 LSB 11 1111 1111 1111 1111 3FFFF (+Vref)/2 10 0000 0000 0000 0000 20000 (+Vref)/2 – 1 LSB 01 1111 1111 1111 1111 1FFFF 0V 00 0000 0000 0000 0000 00000 Midscale Midscale – 1 LSB Zero The output data is a full 18-bit word (D17–D0) on DB17–DB0 pins (MSB–LSB) if both BUS18/16 and BYTE are low. The result may also be read on an 16-bit bus by using only pins DB17–DB2. In this case two reads are necessary: the first as before, leaving both BUS18/16 and BYTE low and reading the 16 most significant bits (D17–D2) on pins DB17–DB2, then bringing BUS18/16 high while holding BYTE low. When BUS18/16 is high, the lower two bits (D1–D0) appear on pins DB3–DB2. The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB17–DB10. In this case three reads are necessary: the first as before, leaving both BUS18/16 and BYTE low and reading the 8 most significant bits on pins DB17–DB10, then bringing BYTE high while holding BUS18/16 low. When BYTE is high, the medium bits (D9–D2) appear on pins DB17–DB10. The last read is done by bringing BUS18/16 high while holding BYTE high. When BUS18/16 is high, the lower two bits (D1–D0) appear on pins DB11–DB10. The last read cycle is not necessary if only the first 16 most significant bits are of interest. All of these multiword read operations can be performed with multiple active RD (toggling) or with RD held low for simplicity. This is referred to as the AUTO READ operation. Table 2. Conversion Data Read Out DATA READ OUT BYTE BUS18/16 PINS DB17–DB12 High High Low High High Low Low Low PINS DB11–DB10 PINS DB9–DB4 PINS DB3–DB2 PINS DB1–DB0 All One's D1–D0 All One's All One's All One's All One's All One's All One's D1–D0 All One's D9–D4 D3–D2 All One's All One's All One's D17–D12 D11–D10 D9–D4 D3–D2 D1–D0 RESET On power-up, internal POWER-ON RESET circuitry generates the reset required for the device. The first three conversions after power-up are used to load factory trimming data for a specific device to assure high accuracy of the converter. The results of the first three conversions are invalid and should be discarded. The device can also be reset through the use of the combination fo CS and CONVST. Since the BUSY signal is held at high during the conversion, either one of these conditions triggers an internal self-clear reset to the converter. • Issue a CONVST when CS is low and the internal convert state is high. The falling edge of CONVST starts a reset. • Issue a CS (select the device) while the internal convert state is high. The falling edge of CS causes a reset. Once the device is reset, all output latches are cleared (set to zeroes) and the BUSY signal is brought low. A new sampling period is started at the falling edge of the BUSY signal immediately after the instant of the internal reset. Submit Documentation Feedback 23 ADS8481 www.ti.com SLAS385A – FEBRUARY 2006 – REVISED MARCH 2006 LAYOUT For optimum performance, care must be taken with the physical layout of the ADS8481 circuitry. As the ADS8481 offers single-supply operation, it is often used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to achieve good performance from the converter. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving any single conversion for an n-bit SAR converter, there are at least n windows in which large external transient voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, or high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. On average, the ADS8481 draws very little current from an external reference as the reference voltage is internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypass capacitor or capacitors without oscillation. A 0.1-µF capacitor is recommended from pin 13 (REFIN) directly to pin 12 (REFM). REFM and AGND must be shorted on the same ground plane under the device. The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the analog ground. Avoid connections which are too close to the grounding point of a microcontroller or digital signal processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal layout consists of an analog ground plane dedicated to the converter and associated analog circuitry. As with the AGND connections, +VA should be connected to a 5-V power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. Power to the ADS8481 should be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the device as possible. See Table 3 for the placement of the capacitor. In addition, a 1-µF to 10-µF capacitor is recommended. In some situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors—all designed to essentially low-pass filter the 5-V supply, removing the high frequency noise. Table 3. Power Supply Decoupling Capacitor Placement POWER SUPPLY PLANE CONVERTER DIGITAL SIDE CONVERTER ANALOG SIDE SUPPLY PINS Pin pairs that require shortest path to decoupling capacitors (7,8), (9,10), (16,17), (20,21), (22,23), (25,26) 36, 37 Pins that require no decoupling 24, 26 1 24 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS8481IBPFBR PREVIEW TQFP PFB 48 1000 TBD Call TI Call TI ADS8481IBPFBT PREVIEW TQFP PFB 48 250 TBD Call TI Call TI ADS8481IBRGZR ACTIVE QFN RGZ 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8481IBRGZRG4 ACTIVE QFN RGZ 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8481IBRGZT ACTIVE QFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8481IBRGZTG4 ACTIVE QFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8481IPFBR PREVIEW TQFP PFB 48 1000 TBD Call TI Call TI ADS8481IPFBT PREVIEW TQFP PFB 48 250 TBD Call TI Call TI ADS8481IRGZR ACTIVE QFN RGZ 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8481IRGZRG4 ACTIVE QFN RGZ 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8481IRGZT ACTIVE QFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8481IRGZTG4 ACTIVE QFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS8481PFBR PREVIEW TQFP PFB 48 250 TBD Call TI Call TI ADS8481RGZR PREVIEW QFN RGZ 48 250 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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