FEDL7105-002-01 Issue Date: June. 10, 2013 ML7105-002 ® Bluetooth Low Energy ■Overview ML7105-002 is a Bluetooth® Low Energy (here in after LE) LSI integrating RF, Baseband, microproccessor core and each peripherals, which has Bluetooth® LE compliant 2.4GHz band radio communication capability. ML7105-002 (hereafter "ML7105") is suitable for applications such as Wrist Watch, Remote Controller or PC peripherals. ■Features • Bluetooth® SIG Core Spec v4.0 compliant • Ultra Low Power RF block • Cortex-M0 Micro processor, it has interrupt controller and Sys-Tick Timer • 64KB ROM (CODE_ROM) for Program, 16KB RAM (DATA_RAM) for Data • 12KB RAM (CODE_RAM) for user Program ® • Bluetooth LE single mode compliant Baseband controller ® • UART interface for Bluetooth Host Controller Interface (HCI) • SPI (Slave mode) interface for Custom Host Controller Interface • I2C (Master & Slave) interface for EEPROM or Custom Host Controller Interface • GPIO ports • System Clock Timer and External Low Power Clock Timer • Low Power operating mode • Single power supply 1.6V to 3.6V • Operating Temperature -20 deg.C to 70 deg.C • Current Consumptions Deep Sleep Mode below 0.7uA (with external Low Power Clock) below 2.9uA (with internal Low Power Clock oscillator circuit) Idle Mode below 3.0mA TX mode below 9.0mA RX mode below 9.0mA • Package 32pins WQFN (P-WQFN32-0505-0.50-A63) Pb Free, RoHS compliant 1/30 FEDL7105-002-01 ML7105-002 ■Block Diagram ●1chip overview ●Bluetooth® LE Controller 2/30 FEDL7105-002-01 ML7105-002 ■Pin assignment I2C_SCL VDDIO UART_RXD UART_TXD SPICLK SPIXCS SPIDOUT SPIDIN 32pins WQFN 24 23 22 21 20 19 18 17 I2C_SDA 25 16 VDDCORE GPIO0 26 15 EFUSE GPIO1 27 14 XON GPIO2 28 13 XOP GNDPKG RESETB 31 10 LPCLKBUS A0 32 9 1 2 3 4 5 6 7 8 REGOUT LPCLKIN PLLLPF 11 VDDVCO 30 SWTX TMODE SWRX REGC SWOUT 12 VDDRF 29 A1 GPIO3 VDDBAT TOP VIEW Note: Centre of the chip at bottom side is GND (symbol : Package GND) 3/30 FEDL7105-002-01 ML7105-002 ■Pin definitions No. Pin Name I/O ANA/DIG IO TYPE 1 A1 IN ANA DIRIO 2 VDDRF --- PWR VCC 3 SWOUT INOUT ANA DIRIO_RF RF signal RX/TX inout 4 SWRX INOUT ANA DIRIO_RF RX SW control signal 5 SWTX INOUT ANA DIRIO_RF TX SW control signal 6 VDDVCO --- PWR VCC Function General purpose analog input Power supply for RF block (1.2V) Power supply for RF-VCO (1.2V) 7 PLLLPF OUT ANA DIRIO PLL Loop Filter 8 REGOUT OUT ANA DIRIO Regulator output 9 VDDBAT --- PWR VCC 10 LPCLKBUS INOUT ANA DIRIO 11 LPCLKIN INOUT ANA DIRIO Low power clock/Xtal input 12 REGC OUT ANA DIRIO Decoupling capacitor pin for internal regulator 13 XOP INOUT ANA DIRIO Positive inout pin for XTAL oscillator block 14 XON INOUT ANA DIRIO Negative inout pin for XTAL oscillator block 15 EFUSE --- DIG DIRIO Power supply for E-Fuse (fixed to GND in normal) 16 VDDCORE --- PWR VCC 17 SPIDIN IN DIG 18 SPIDOUT INOUT DIG 19 SPIXCS IN DIG Power supply from Battery (=VDDIO) (1.6V to 3.6V) Low power clock output/ Power supply for digital core (1.2V) CMOS, IN SPI Slave Data input CMOS, BiDIR SPI Slave Data output CMOS, IN SPI Slave Chip Select 20 SPICLK IN DIG CMOS, IN SPI Slave Clock 21 UART_TXD OUT DIG CMOS, OUT UART TXD output 22 UART_RXD IN DIG CMOS, IN UART RXD input 23 VDDIO --- PWR 24 I2C_SCL INOUT DIG 25 I2C_SDA INOUT DIG INOUT DIG INOUT DIG INOUT DIG INOUT DIG 26 27 28 29 GPIO0 /RF_ACTIVE GPIO1 /WAKEUP GPIO2 /IRQ GPIO3 /PS_CONTROL VCC CMOS, BiDIR CMOS, BiDIR CMOS, BiDIR CMOS, BiDIR CMOS, BiDIR CMOS, BiDIR Power supply for digital IO (1.6V to 3.6V) I2C_SCL I2C_SDA GPIO inout/RF_ACTIVE GPIO inout/WAKEUP GPIO inout/IRQ GPIO inout/external control switch control 30 TMODE IN DIG CMOS, IN TESTMODE input 31 RESETB IN DIG CMOS, IN Reset input 32 A0 IN ANA DIRIO General purpose analog input G GNDPKG --- GND GND Package GND 4/30 FEDL7105-002-01 ML7105-002 ■Pin definition I/O definitions IRF I Ipd IA IAH ISH XSH XM O2 B2 OA OAH : : : : : : : : : : : : RF input and output Digital input Digital input with pull-down resistor Analog input Analog input support 3V Low-Power Clock input X’tal pin for Low-Power Clock X’tal pin for Master Clock Digital output with 2mA load capability Digital inout with 2mA load capability Analog output Analog output support 3V ●RF analog pins No Pin Name Status in reset I/O Active Level 3 SWOUT Hi-Z IRF --- RF signal RX/TX inout 4 SWRX Hi-Z IRF --- RX SW control signal 5 SWTX Hi-Z IRF --- TX SW control signal 32 A0 Hi-Z IAH --- General purpose analog input Function 1 A1 Hi-Z IAH, --- General purpose analog input 7 PLLLPF Hi-Z OA --- PLL Loop Filter ●XO, LPXO pins No Pin Name Status in reset I/O Active Level 13 XOP Hi-Z XM --- Positive inout pin for Master clock oscillator block 14 XON Hi-Z XM --- Negative inout pin for Master clock oscillator block 10 LPCLKBUS 0V XSH --- Low power clock Xtal output 11 LPCLKIN ISH XSH, ISH --- Low power clock/Xtal input No Pin Name Status in reset I/O Active Level 17 SPIDIN Input I --- SPI SLAVE Data input 18 SPIDOUT Output B2 --- SPI SLAVE Data output 19 SPIXCS Input I Low SPI SLAVE Chip Select 20 SPICLK Input I --- Function ●SPI pins Function SPI SLAVE Clock 5/30 FEDL7105-002-01 ML7105-002 ●UART pins No Pin Name Status in reset I/O Active Level 21 UART_TXD High output O2 --- UART TXD output 22 UART_RXD input Ipd --- UART RXD input No Pin Name Status in reset I/O Active Level 24 I2C_SCL Input B2 --- I2C_SCL 25 I2C_SDA Input B2 --- I2C_SDA Status in reset I/O Active Level B2 --- GPIO inout/RF_ACTIVE (default : RF_ACTIVE) B2 --- GPIO inout/WAKEUP (default : WAKEUP) B2 --- GPIO inout/IRQ (default : IRQ) B2 --- GPIO inout/external switch control (default : PS_CONTROL) I/O Active Level Function ●I2C pins Function ●GPIO pins No 26 27 28 29 Pin Name GPIO0 Low output /RF_ACTIVE GPIO1 Input /WAKEUP GPIO2 High output /IRQ GPIO3 Low output /PS_CONTROL Function ●Miscellaneous pins No Pin Name Status in reset 31 RESETB input I Low 15 EFUSE --- --- --- Power supply for E-Fuse (fixed to GND in normal) 30 TMODE input I --- TESTMODE input (Low = normal mode) Status in reset I/O Active Level Function Reset input (Low = Reset) ●Regulator pins No Pin Name Function 8 REGOUT Hi-Z OAH --- Regulator output 12 REGC 1.2V output OAH --- Decoupling capacitor pin for internal regulator 6/30 FEDL7105-002-01 ML7105-002 ●Power Supply pin Pin Name Status in reset 2 VDDRF --- --- --- Power supply for RF block (1.2V) 6 VDDVCO --- --- --- Power supply for RF-VCO (1.2V) 9 VDDBAT --- --- --- Power supply from Battery (=VDDIO) (1.6V to 3.6V) 16 VDDCORE --- --- --- Power supply for digital core (1.2V) 23 VDDIO --- --- --- Power supply for digital IO (1.6V to 3.6V) G GNDPKG --- --- --- Package GND No I/O Active Level Function ●Unused pins Followings are recommendation for pins are not used. No Pin Name Recommendation 1 A1 Open 10 LPCLKBUS Open 15 EFUSE Fix to GND 17 SPIDIN Fix to VDDIO 18 SPIDOUT Fix to VDDIO 19 SPIXCS Fix to VDDIO 20 SPICLK Fix to VDDIO 21 UART_TXD Open 22 UART_RXD Fix to GND (See operating mode section) 24 I2C_SCL Fix to VDDIO 25 I2C_SDA Fix to GND 26 GPIO0 Open 27 GPIO1 Fix to VDDIO or GND (See operating mode section) 28 GPIO2 Open 29 GPIO3 Open 32 A0 Open Note Leaving input pins open with Hi-Z status, current consumption will be increased. It is highly recommended that input or inout pins should not be left open. 7/30 FEDL7105-002-01 ML7105-002 ■Electrical Characteristics ●Absolute Maximum Rating Item Symbol Rating Unit Power supply 3.3V (*1) VDDIO1 VDDIO2 Condition –0.3 to +4.6 V Power supply 1.2V (*2) VDDRF –0.3 to +1.8 V Digital input voltage (*4) VDIN –0.3 to VDDIO+0.3 V Digital output voltage (*5) VDO Ta = −20 to +70 deg.C –0.3 to VDDIO+0.3 V Analog IO voltage (*6) VA GND= 0 V (*3) –0.3 to VDDRF+0.3 V Analog HV IO voltage (*7) VAH VDDRF=VDDVCO –0.3 to VDDIO+0.3 V Digital IO load current IDO =VDDCORE, –10 to +10 mA Analog IO current (*6)(*7) IA VDDBAT=VDDIO, –2 to +2 mA Power Dissipation PD 1.0 W Storage temperature Tstg –55 to +125 deg.C – (*1) VDDBAT, VDDIO pins (*2) VDDRF, VDDVCO, VDDCORE, (*3) GND: GND pin (Package GND) (*4) IO pins with I, IPD, B2 symbol in pin definition (*5) IO pins with O2,B2 symbol in pin definition (*6) IO pins with IA, OA, XM symbol in pin definition (*7) IO pins with IAH, OAH, ISH, XSH, symbol in pin definition ●Recommended Operating Conditions Item Symbol Power Supply VDDIO1 Power Supply VDDIO2 Condition VDDIO pin （VDDBAT≧VDDIO） VDDBAT pin （VDDBAT≧VDDIO） – Min Typ Max Unit 1.6 3.3 3.6 V 1.6 3.3 3.6 V –20 +25 +85 °C Ambient Temperature Ta Rising time digital input pins tIR1 Digital input/inout pins – – 20 Ns Falling time digital input pins Load capacitance digital tIF1 Digital input/inout pins – – 20 Ns CDL Digital output/inout pins – – 20 pF Master Clock (26 MHz) crystal oscillator frequency FMCK1 Connect cristal oscillator between XOP－XON pins （*1）, (*2) –40 ppm 26 +40 ppm MHz Low Power Clock (32.768 kHz) crystal oscillator frequency FLPCK1 LPCLKIN pin, LPCLKBUS pin (*2) –250 ppm 32.768 +250 ppm kHz Low Power Clock Input Duty Ratio DLPCK1 External input from LPCLKIN, LPCLKBUS pin left OPEN 30 50 70 % 2402 – 2480 MHz -10 dBm RF Channel frequency (*2) FRF SWOUT pin RF input level PRFIN -70 – (*1) Cristal oscillator is recommended (*2) The cristal should be used the one that meet the specification include peripheral circuit. (*3) Frequency range F = 2402 + 2 x k [MHz] here k=0, 1,2,…,39. 8/30 FEDL7105-002-01 ML7105-002 ●Current consumption (Ta = −20 to +70 deg.C) Item Symbol IDD1 IDD2 Current Consumption (*1) IDD3 Condition Deep Sleep state (External Low Power Clock) Deep Sleep state (Internal Low Power Clock oscillation) Idle state RF RX state RF TX state (-6dBm) IDD5 RF TX state (0dBm) (*1) Condition: Ta = 25deg. VDDHV = 3.3V Min Typ Max Unit – 0.7 – uA – 2.9 – uA – 3 – mA 9 – mA – 9 – mA – 10.9 – mA IDD4 ●DC characteristics Item Symbol Condition Min (Ta = −20 to +70 deg.C) Typ Max Unit H level Voltage Input VIH1 (*1) (*2) (*5) VDDIO X0.7 L level Voltage input VIL1 (*1) (*2) (*5) 0 – VDDIO X0.3 V LPCLKIN pin H level Voltage Input VIH2 (*3) 1 – VDDIO V LPCLKIN pin L level Voltage input VIL2 (*3) 0 – 0.3 V – VDDIO V IIH1 VIH = VDDIO (*1) (*5) –1 – 1 uA Input leak current IIH2 VIH = VDDIO (*2) 5 – 250 uA IIL1 VIL = 0 V –-1 – 1 uA Tri-state output leak current IOZH VOH = VDDIO (*4) (*5) –1 – 1 uA IOZL VOL = 0 V –1 – 1 uA H level Voltage Output VOH IOH = −2mA (*4) (*5) VDDIO = VDDRF = 1.6V to 3.6V VDDIO × 0.75 – VDDIO V L level Voltage Output VOL IOL = 2mA 0 – VDDIO × 0.25 V Input pin capacitance CIN F=1MHz – 8 – pF (*1) (*2) (*3) (*4) (*5) (*1) (*2) (*5) (*4) (*5) (*4) (*5) (*1) (*2) (*4) (*5) IO pins with I symbol in pin definition IO pins with IPD symbol in pin definition IO pins with ISH symbol in pin definition IO pins with O2 symbol in pin definition IO pins with B2 symbol in pin definition 9/30 FEDL7105-002-01 ML7105-002 ●RF Characteristics (Ta = −20 to +70 deg.C) Item Symbol Condition Min Typ Max Unit TX TX power POUT1 0dBm setting –3 0 3 dBm POUT2 -18dBm setting – –18 – dBm Centre Frequency tolerance FCERR Master Clock tolerance < 40 ppm –40 – 40 ppm Modulation data rate DRATE – – 1 – Mbps Modulation index FIDX – 0.45 0.50 0.55 – Bandwidth-bit rate products BT BT GFSK – 0.5 – – Modulation characteristics F1avg Frequency deviation of 10101010 pattern 225 250 275 kHz FRATE Frequency deviation ratio between 10101010 and 00001111 sequence 80 – – % FDELTA Minimum Frequency Deviation 185 – – kHz POS1 2MHz apart from carrier frequency in a 1MHz bandwidth – – -20 dBm POS2 3MHz apart from carrier frequency in a 1MHz bandwidth – – -30 dBm PSENS PER = 30.8% (*1) – -85 -70 dBm CICO Co-channel interference C/I 21 – – dB CIS1 Adjacent (1MHz) interference C/I 15 – – dB CIS2 -17 – – dB -27 – – dB -9 – – dB -15 – – dB PBLK1 Adjacent (2MHz) interference C/I Adjacent (>=3MHz) interference C/I Image frequency interference (-4MHz) C/I Adjacent (1MHz) interference to image frequency (-3MHz,-5MHz)) C/I 30MHz to 2000MHz BW 10MHz -30 PBLK2 -35 PBLK3 2484 to 2997MHz BW 3MHz 3000MHz to 12.75GHz BW 25MHz -35 – – – – – – dBm 2003 to 2399MHz BW 3MHz -30 – – dBm In-band spurious RX Receiver Sensitivity Interference performance PER<30.8% Wanted signal :-67dBm Interfering signal : modulated signal (*2) CIS3 CIIMG CIIMGS1 Out of band blocking PER<30.8% Wanted signal :-67dBm Interfering signal:CW (*2) (*3) PBLK4 dBm dBm 10/30 FEDL7105-002-01 ML7105-002 Intermodulation PER<30.8% Wanted signal :-64dBm (*2) PIM Maximum input level(*2) PRXMAX PRSSIMA RSSI detection range (*2) X PRSSIMIN CW interering signal +/-3MHz Modulated interfering signal +/-6MHz or CW interfering signal +/-4MHz Modulated interfering signal +/-8MHz or CW interfering signal +/-5MHz Modulated interfering signal +/-10MHz PER = 30.8% (*1) Upper Lower -50 – – dBm – – -10 dBm -40 – – dBm – – -80 dBm (*1) PER=30.8% is corresponding to BER=0.1% (*2) Condition: Ta = 25deg.、VDDHV = 3.3V (*3) Follow RCV-LE/CA/04/C test spec of Bluetooth SIG 11/30 FEDL7105-002-01 ML7105-002 ●SPI interface (Ta = −20 to +70 deg.C) Item SPICLK Clock Frequency Symbol Min Typ Max Unit FSCLK 16.384 32.768 1625 kHz SPIXCS input setup time TCESU 1/Fsclk − − ms SPIXCS input hold time TCEH 1/Fsclk − − ms TWCKH 250 − − ns TWCKL 250 − − ns SPICLK minimum high pulse width SPICLK minimum low pulse width SPIDIN input setup time TDISU SPIDIN input hold time TDIH SPICLK output delay time SPIDOUT output hold time SPIXCS enable delay time SPIXCS disable delay time Condition Load capacitance CL=20pF 5 − − ns 250 − − ns TCKOD − − 250 ns TDOH 5 − − ns TCEEN 0 − 300 ns TCEDIS 150 − − ns Note: When using the width of the following SPICLK edge from the data output trigger SPICLK edge within 250 ns, there is possibility that the output timing of SPIDOUT becomes simultaneous with the following edge. Consider the data input setup time of HOST and set pulse width. Remarks: All timing specification is defined at VDDIO x 20% and VDDIO x 80% SPIXCS input setup/hold time have to be at least 1cycle of SPICLK clock frequency Measurement point 0.8VDDIO Measurement Point 0.2VDDIO 0.8VDDIO 0.2VDDIO SPIXCS TCEH FSCLK TWCKL SPICLK TCESU SPIDIN TWCKH TDISU TDIH MSB IN BITS6-1 LSB IN TCKOD TCEEN SPIDOUT TCKOD MSB OUT TCEDIS TDOH BITS6-1 LSB OUT 12/30 FEDL7105-002-01 ML7105-002 ●UART interface (Ta = −20 to +70 deg.C) Item Baud Rate Symbol FBAUD Condition Load capacitance CL=20pF Min Typ Max − 57600 − Unit bps(H z) 13/30 FEDL7105-002-01 ML7105-002 ●I2C interface (Ta = −20 to +70 deg.C) Item Symbol SCL clock frequency SCL minimum high pulse width SCL minimum low pulse width Start condition hold time Min Typ Max Unit FSCL Condition − − 400 kHz TWSCKH 10 − − us TWSCKL 10 − − us 5 − − us 5 − − us 5 − − us TDSTAH Load capacitance CL=20pF Start condition setup time TDSTAS Stop condition setup time TDSTOS SDA output hold time TDSOH 5 − − us SCL output delay time TDSOS 5 − − us SDA input setup time TDSIS 80 − − ns SDA input hold time TDSIH 0 − − ns Note: SCL clock frequency is fixed to 400kHz Start condition （SDA falling edge while SCL=１）, Stop condition （SDA rising edge while SCL=１） FSCL TWSCKL TWSCKH SCL SDA(output ) TDSTAS TX/RX case TDSTAH TDSTOS Stop Condition Start Condition SCL TDSOS TDSOH SDA(output) TDSIS TDSIH SDA(input) 14/30 FEDL7105-002-01 ML7105-002 ●Reset operation (Ta = −20 to +70 deg.C) Item RESETB propagation delay time （Power on） Symbol Condition Min Typ Max Unit TRDL Start supplying power (VDDBAT,VDDIO) 20 − − ms RESETB Pulse width TRPLS RESETB pin 1 − − us VDD level VDDBAT, VDDIO GND level TRDL RESETB Power on reset function Reset function from RESETB pin It is possible to reset internal circuit by asserting RESETB after power supply is on. It is possible to reset internal circuit by same way even if it is not power sequence. Internal circuit will move to normal state after oscillation circuit become stable by clock stabilizing circuit after reset function. ●Power on Item Symbol Condition Min (Ta = −20 to +70 deg.C) Typ Max Unit TPWON While power on VDD pins (VDDBAT,VDDIO) 0.2 1 5 ms Time difference between VDD pin while power on state TPWONdly While power on VDD pins (VDDBAT,VDDIO) 0 - - ms Time difference between VDD pin while power off state TPWOFdly While power off VDD pins (VDDBAT,VDDIO) 0 - - ms VDD pin rising time TPWON VDDBAT, 90% 10% TPWON VDDIO 90% 10% 15/30 FEDL7105-002-01 ML7105-002 ■Operating mode Following 4 operating modes are available to use BACI Mode: Application mode using SPI-SLAVE interface HCI Mode: HCI mode (Bluetooth LE standard compliant) using UART interface. RAM Mode: Function extension mode downloading user program to internal memory Debug Mode: Debugging mode to have access to I2C-EEPROM write and read. ■Operating mode configuration Configuration of operating mode will be done by pin status shown in table below. The symbol “X“ is don’t care, it has to be used as normal function. When configure operating mode, reset has to be issued. RAM mode and Debug mode is distinguished by configuration parameter. Operating mode Pin confitions UART_RXD BLI Mode Low HCI Mode ※1 High RAM Mode X Debug Mode X (*) Fix Wakeup pin to Low on HCI mode. See anootations on Section about Power State Transition 16/30 FEDL7105-002-01 ML7105-002 ■Boot Sequence Operating mode will be deciede by boot sequence shown below. Start (Power On & Hardware Reset） Reset Handler Wakeup or Config is Valid Retention Status Register? Not Wakeup or Config is Ivalid Check external pins by GPIO “EEPROM_IS_CONNECTED” Yes Load Config from EEPROM I2C_SDA == High ? No “EEPROM_IS_NOT_CONNECTED” Is Config Valid? No (== 0x5A) “EEPROM_IS_NOT_VALID” Yes “EEPROM_IS_VALID” Check external pins by GPIO UART_RX == High ? No No SPI_SLAVE (BACI) Initialization for Loading I/F Yes Check external pins by GPIO is not required UART0 (HCI) Initialization for Loading I/F Load Config Parameters (Debug Mode) 17/30 FEDL7105-002-01 ML7105-002 Check Parameter Value RAM Mode ROM or RAM Mode ? ROM Mode Check external pins by GPIO Yes UART_RX == High? No Go to GATT & GAP I/F (SPI_SLAVE) for Application and TEST (BACI Mode) Go to HCI I/F (UART0) for Application and TEST (HCI Mode) Go to User Application (RAM Mode) Disable Pull-Down of UART_RXD pin Download User Application to CODE_RAM Restore Remap Normal Operation Call Reset Handler No Can Shutdown? Yes No Wakeup Pin == High ? Yes Store & Retention Status = Wakeup 18/30 FEDL7105-002-01 ML7105-002 ■Power Management ●Power Mode Following Power modes are available. Active mode Idle mode Deep sleep mode Application Sleep [Active mode] Active Mode will be used during RF connection state. [Idle mode] Idle mode is low power consumption mode. It can be used between connection events with short time interval which is equal to or less than 40msec. [Deep sleep mode] Deep sleep mode will be used between connection evenrs or system function is suspended. Oscillation block in RF block is suspeded, communication time interval will be counted by low power clock supplied from external pin. [Application Sleep] Application Sleep mode will suspend oscillation in RF block, and stand by with low power clock supplied from external pin. This is low power mode used in the case communications is unnecessary. Sleep command issue by host cpu makes become this mode, and this mode is kept till wake up from external pin. 19/30 FEDL7105-002-01 ML7105-002 ●Power State Transition Power mode transition is described in Fig.1 [Power On] Power Supply On Hardware Reset Active Mode [Boot State] Initialization and Parameter Load from EEPROM [Connection State] Active Mode [Short Interval or Application Processing State] Idle mode HCI mode Hardware Control (Wakeup Factor) Application Sleep [Sleep State] Deep sleep mode [Long Interval State] BACI mode Fig. 1 Power state transition and operating mode [Power On] Assert hardware reset pin for a definite period when power supply is started.ML7105 will become oot state When hardware reset is released. [Boot State] Booting operation will be started when hardware reset is released. Booting program will execute to initileze peripheral blocks and download of parameters. [Connection State] Communication setting and application processing will be performed in Active mode. [Short Interval or Application Processing State] Short period (≦40msec) between communications and simple application processing will be performed in Sleep mode. [Long Interval State] Deep sleep mode will be used during a long period of waiting for radio commutication or when no access is made by HOST for a certain time in a non-communication period. Deep sleep mode is kept with 32.768KHz low power clock from an external pin. (Note) In this state, the communication interval is counted by the internal timer, enabling ML7105 to return from the Deep Sleep mode temporarily at the timer expiration (at about 40-second interval). When you want to keep the Deep Sleep state, make a transition to the Sleep State. 20/30 FEDL7105-002-01 ML7105-002 [Sleep State] It is allowed to become Shutdown state if all operations can be temporarily stopped, by BACI command or HCI vender command. Sleep mode will suspend 26MHz clock in RF block, and be kept with 32.768KHz low power clock from external pin till wakeup. (Note) In the HCI Mode, the transition to the Long Interval State or Sleep State is not performed. ●Wakeup Factor Wakeup Factor is necessary to return from Deep sleep mode or Application Sleep. Wakeup Factor, low state of GPIO1 pin or WAKEUP pin, will be detected, and RF block clock will start to oscillate. ●Current Profile Following example shows current consumption and power state transition waking up from Deep sleep mode, perform RX and TX and return to Deep sleep mode. Current Irash Itx, Irx Iifs Iboot Irfinit Iidle Istby Idsm Time Tdsm Trash Txo-idle Tboot Status Trfinit Tinit Trx Tifs Ttx Tdwn Definition Tdsm Deepsleep period depend on connection interval Trash Spike from voltage regulator wake-up Txo_idle Start up time for xtal oscillator block for systems clock 26MHz Tboot System is in booting operation Trfinit Initialize RF register Tinit Pre-processing after deep sleep mode Trx Packet reception Tifs Time between RX to TX operation Ttx Packet transmission Tdwn Post processing before moving to deep sleep operation 21/30 FEDL7105-002-01 ML7105-002 ■HOST interfaces ●Overview There are two host interfaces available shown below. 《SPI interface – BACI Mode》 SPI-SLAVE intrerface will be used as HOST interface. HOSTsystem can send command or receive event information via through SPI inrerface. 《UART interface – HCI Mode & Debug Mode》 UART intrerface will be used as HOST interface. HOST system can send command or receive event information via through UART interface. ●Connection with HOST system Connection with HOST system consist of serial interface (UART or SPI-SLAVE) and 3pins of GPIO. Following example shows SPI-SLAVE used as HOST interface. Lapis U8 3pins of GPIO have following functionality. RF_ACTIVE: Indicates Bluetooth communication is active or trans from Deep Sleep to IDLE/(shows higher current load). When ML7105 wake-up from DeepSleep by internal timer, RF_ACTIVE Indicates rush current . But when ML7105 wakes-up from DeepSleep by WAKEUP pin, or wake-up from PowerDown, RF_ACTIVE indicates nothing. WAKEUP: Control signal indicate REQUEST or READY status from HOST system to ML7105. It has to be asserted Low before start SPI communication (REQUEST). IRQ: IRQ indicates REQUEST or READY status from ML7105 to HOST system. Once ML7105 receive REQUEST from HOST system and it become READY, ML7105 set IRQ signal to Low. Reporting REQUEST from ML7105 will be done by asserting IRQ signal to low. 22/30 FEDL7105-002-01 ML7105-002 Behavior of each pins are described below. The normal state of the RF_ACTIVE pin is Low. The normal states of the WAKEUP, IRQ, and SPIXCS pins are High. The SPI communication is performed in the following sequence: - Communication request from HOST 1. HOST toggles the WAKEUP pin to Low. 2. When ML7105 detects WAKEUP and goes to the READY state, ML7105 toggles the IRQ pin to Low. 3. HOST starts the SPI communication. During the communication, HOST toggles the SPIXCS pin to Low. 4. When the SPI communication is completed, HOST toggles the WAKEUP pin to High. 5. When ML7105 detects that the WAKEUP pin turns to High, ML7105 toggles the IRQ pin to High. [Note] When transmitting dummy data other than BACI packet from HOST, be sure to transmit 0xFF. - Communication request from ML7105 (when transmitting one BACI packet ) 1. ML7105 toggles the IRQ pin to Low. 2. When HOST detects IRQ and goes to the READY state, HOST toggles the WAKEUP pin to Low. 3. HOST starts the SPI communication. During the communication, HOST toggles the SPIXCS pin to Low. ML7105 outputs the dummy data (0xFF) and then starts the transmission of the BACI packet. 4. ML7105 starts transmitting the BACI packet. 5. When HOST completes receiving the BACI packet, HOST must toggle the WAKEUP pin to High. 6. When ML7105 detects that the WAKEUP pin turns to High, ML7105 toggles the IRQ pin to High. - Timing control when a communication request from HOST is made After toggling the IRQ signal to High, ML7105 transitions to the Deep Sleep mode if no communication request from HOST is made for a specified period (about 1 ms). During this transition to the Deep Sleep mode, no communication request from HOST is accepted. Therefore, insert a WAIT of 3 ms or more after toggling the WAKEUP signal to High before toggling it to Low, so that a communication request from HOST can be accepted. If there is no IRQ signal response to the communication request from HOST, perform the retry process (toggle the WAKEUP signal back to High and then toggle it to Low again). 23/30 FEDL7105-002-01 ML7105-002 WAKEUP Default High READY READY IRQ Default High REQUEST REQUEST 1st DATA Transfer (ML7105→HOST) 2nd DATA Transfer (ML7105→HOST) SPI SPIXCS - FF FF Default High Communication request from ML7105 (when transmitting two BACI packets continuously) 1. ML7105 toggles the IRQ pin to Low. 2. When HOST detects IRQ and goes to the READY state, HOST toggles the WAKEUP pin to Low. 3. HOST starts the SPI communication. During the communication, HOST toggles the SPIXCS pin to Low. ML7105 outputs the dummy data (0xFF) and then starts the transmission of the BACI packet. 4. When HOST completes receiving the BACI packet, HOST must toggle the WAKEUP pin to High. 5. If there are more BACI packets to be transmitted continuously, ML7105 keeps IRQ in the Low state. 6. When HOST detects that IRQ is in the Low state, HOST must toggle the WAKEUP pin to Low. 7. HOST starts the SPI communication. During the communication, HOST toggles the SPIXCS pin to Low. ML7105 outputs the dummy data (0xFF) and then starts the transmission of the second BACI packet. 8. When HOST completes receiving the BACI packet, HOST must toggle the WAKEUP pin to High. 9. When ML7105 detects that the WAKEUP pin turns to High, ML7105 toggles the IRQ pin to High. 24/30 FEDL7105-002-01 ML7105-002 Behavior of RF_ACTIVE is shown below. The RF_ACTIVE pin outputs High during the period of RF communication or calibration where an increased current is required. The RF_ACTIVE pin outputs High also at return from Deep Sleep by the internal timer, since the current increases due to the rush current. The RF_ACTIVE pin outputs High during the T_rf_act period before the current increases. The value of T_rf_act varies depending on the cause to be notified. When RF_ACTIVE notifies the current increase due to RF communication, T_rf_act is 625 µsec * 2 = about 1.2 msec or 625 µsec *3 = about 1.8 msec. On the other hand, T_rf_act is about 1 msec at return from Deep Sleep. The RF_ACTIVE pin is toggled to Low when the RF communication is completed or at transition to Deep Sleep. While the RF communication continues, the RF_ACTIVE pin always outputs High. At a return from power-down or at a return to IDLE from Deep Sleep by the WAKEUP pin, the current increases due to the rush current just like the case at the return from Deep Sleep by the internal timer. However, the RF_ACTIVE pin does not output High in this case. 25/30 FEDL7105-002-01 ML7105-002 ●SPI interface description Possible combination of parameters are described below when SPI-SLAVE block are used as HOST interface. Table 1 SPI_SLAVE Settings Parameter Spec SPI mode Typ. 32.768KHz Max. 1.625MHz Motorola SPI (Mode 3) Data size 8 bits Chip select Low Active Bit rate ●UART interface description Possible combination of parameters are described below when UART block are used as HOST interface. Parameter Table 2 UART Settings Spec Baud rate 57600bps Data size 8 bits Parity bit No parity Stop bit 1 stop bit Flow control No 26/30 FEDL7105-002-01 ML7105-002 ■Package dimensions Notes for Mounting the Surface Mount Type Packages The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact ROHM's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 27/30 FEDL7105-002-01 ML7105-002 ■Application example The following circuit shows the typical application circuit. This circuit may vary depending on the shipment time or other factor. This circuit shows ML7105 Application example and does not guarantee the characteristics. It is recommended that choosing and finalize the best component valuse by evaluationg on the target board. GNDPKG GPIO2 (28) (9) VDDBAT (23) VDDIO GPIO1 (27) GPIO0 (26) A0 (32) (8) REGOUT A1 (1) EFUSE (15) TMODE (30) (16) VDDCORE (29) GPIO3 XO P (13) (6) VDDVCO XO N (14) GNDPKG has to be connected GND pattern of PCB 28/30 FEDL7105-002-01 ML7105-002 ■Revision History Document No. FEDL7105-002-01 Date June, 10, 2013 Page Previous Current Edition Edition – – Description st Final 1 Edition 29/30 FEDL7105-002-01 ML7105-002 NOTES No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co., Ltd. The content specified herein is subject to change for improvement without notice. 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If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Copyright 2013 LAPIS Semiconductor Co., Ltd. 30/30