TI1 LM3475 Hysteretic pfet buck controller Datasheet

LM3475
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LM3475 Hysteretic PFET Buck Controller
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FEATURES
1
•
•
•
•
•
•
•
•
•
2
DESCRIPTION
Easy to Use Control Methodology
0.8V to VIN Adjustable Output Range
High Efficiency (90% Typical)
±0.9% (±1.5% Over Temp) Feedback Voltage
100% Duty Cycle Capable
Maximum Operating Frequency up to 2MHz
Internal Soft-Start
Enable Pin
SOT-23-5 Package
The LM3475 is a hysteretic P-FET buck controller
designed to support a wide range of high efficiency
applications in a very small SOT-23-5 package. The
hysteretic control scheme has several advantages,
including simple system design with no external
compensation, stable operation with a wide range of
components, and extremely fast transient response.
Hysteretic control also provides high efficiency
operation, even at light loads. The PFET architecture
allows for low component count as well as 100% duty
cycle and ultra-low dropout operation.
APPLICATIONS
•
•
•
•
•
•
•
TFT Monitor
Auto PC
Vehicle Security
Navigation Systems
Notebook Standby Supply
Battery Powered Portable Applications
Distributed Power Systems
Typical Application Circuit
L1
10 PH
Q1
Si2343
VIN = 5V
VOUT = 2.5V/2A
COUT
CIN
10 PF
D1
5
PGATE
4
GND
VIN
2
CFF
1 nF
LM3475
3
EN
FB
100 PF
RFB1
2.15k
1
RFB2
1k
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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Connection Diagram
1
2
3
FB
PGATE
5
GND
4
EN
VIN
Figure 1. Top View
5 Lead Plastic SOT-23-5
See Package Number DBV0005A
PIN DESCRIPTION
2
Pin Name
Pin Number
Description
FB
1
Feedback input. Connect to a resistor divider between the output and GND.
GND
2
Ground.
EN
3
Enable. Pull this pin above 1.5V (typical) for normal operation. When EN is low, the device
enters shutdown mode.
VIN
4
Power supply input.
PGATE
5
Gate drive output for the external PFET.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2)
VIN
−0.3V to 16V
PGATE
−0.3V to 16V
−0.3V to 5V
FB
−0.3V to 16V
EN
Storage Temperature
−65°C to 150°C
(3)
440mW
Power Dissipation
ESD Susceptibilty
Human Body Model
(4)
2.5kV
Lead Temperature
Vapor Phase (60 sec.)
Infared (15 sec.)
(1)
(2)
(3)
(4)
215°C
220°C
Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the
device is intended to be functional, but device parameter specifications may not be guaranteed. For guaranteed specifications and test
conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
The maximum allowable power dissipation is a function of the maximum junction temperature, TJ_MAX, the junction-to-ambient thermal
resistance, θJA and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated
using:PD_MAX = (TJ_MAX - TA)/θJA. The maximum power dissipation of 0.44W is determined using TA = 25°C, θJA = 225°C/W, and TJ_MAX
= 125°C.
The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin.
Operating Ratings
(1)
Supply Voltage
2.7V to 10V
−40°C to +125°C
Operating Junction Temperature
(1)
Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the
device is intended to be functional, but device parameter specifications may not be guaranteed. For guaranteed specifications and test
conditions, see the Electrical Characteristics.
Electrical Characteristics
Specifications in Standard type face are for TJ = 25°C, and in bold type face apply over the full Operating Temperature
Range (TJ = −40°C to +125°C). Unless otherwise specified, VIN = EN = 5.0V. Datasheet min/max specification limits are
guaranteed by design, test, or statistical analysis.
Symbol
IQ
Parameter
Quiescent Current
Conditions
EN = VIN (PGATE Open)
Min
Typ
Max
170
260
320
4
7
10
0.788
0.8
0.812
EN = 0V
VFB
Feedback Voltage
%ΔVFB/ΔVIN
Feedback Voltage Line
Regulation
VHYST
Comparator Hysteresis
IFB
FB Bias Current
VthEN
IEN
RPGATE
Enable Threshold Voltage
Driver Resistance
µA
V
2.7V < VIN < 10V
0.01
2.7V < VIN < 10V
−40°C to +125°C
21
21
28
32
mV
50
600
nA
1.5
1.8
Increasing
Hysteresis
Enable Leakage Current
Unit
1.2
%/V
365
EN = 10V
.025
Source
ISOURCE = 100mA
2.8
Sink
ISink = 100mA
1.8
V
mV
1
µA
Ω
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Electrical Characteristics (continued)
Specifications in Standard type face are for TJ = 25°C, and in bold type face apply over the full Operating Temperature
Range (TJ = −40°C to +125°C). Unless otherwise specified, VIN = EN = 5.0V. Datasheet min/max specification limits are
guaranteed by design, test, or statistical analysis.
Symbol
IPGATE
Parameter
Driver Output Current
Conditions
Typ
0.475
Sink
VPGATE = 3.5V
CPGATE = 1nF
1.0
TSS
Soft-Start Time
2.7V < VIN < 10V (EN
Rising)
TONMIN
Minimum On-Time
PGATE Open
VUVD
Under Voltage Detection
Measured at the FB Pin
4
Min
Source
VPGATE = 3.5V
CPGATE = 1nF
Max
Unit
A
4
ms
180
0.487
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0.56
ns
0.613
V
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Typical Performance Characteristics
Unless specified otherwise, all curves taken at VIN = 5V, VOUT = 2.5V, L = 10 µH, COUT = 100 µF, ESR = 100mΩ, and TA =
25°C.
Quiescent Current
vs
Input Voltage
Feedback Voltage
vs
Temperature
Figure 2.
Figure 3.
Hysteresis Voltage
vs
Input Voltage
Hysteresis Voltage
vs
Temperature
Figure 4.
Figure 5.
Efficiency
vs
Load Current
Efficiency
vs
Input Voltage
IOUT = 2A
100
98
80
94
EFFICIENCY (%)
EFFICIENCY (%)
96
92
90
88
60
40
20
86
0
84
0.5
1
1.5
4
2
OUTPUT CURRENT (A)
5
6
7
8
9
10
INPUT VOLTAGE (VIN)
Figure 6.
Figure 7.
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Typical Performance Characteristics (continued)
Unless specified otherwise, all curves taken at VIN = 5V, VOUT = 2.5V, L = 10 µH, COUT = 100 µF, ESR = 100mΩ, and TA =
25°C.
1 ms/DIV
6
VSW
2.5V/DIV
VRIPPLE
Output Ripple Voltage
20 mV/DIV
VIN
2V/DIV
VOUT
1V/DIV
Start Up
2 Ps/DIV
Figure 8.
Figure 9.
Load Transient Response with External Ramp
(Circuit from Figure 14)
Load Transient Response
(Typical Application Circuit from Figure 16)
Figure 10.
Figure 11.
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Block Diagram
reset
Internal
Regulator
Level
Shift
PGATE
UVD-Disable
+
VCC
EN
Pdrive
en
VIN
en
UVD
Comp
Blanking
Timer
FB
UVD-Disable
70% VREF
Band Gap
Reference
Hysteretic
Comp
+
-
VREF
Vref Ramp
Current
Bias
reset
Soft-Start
GND
OPERATION DESCRIPTION
OVERVIEW
The LM3475 is a buck (step-down) DC-DC controller that uses a hysteretic control architecture, which results in
Pulse Frequency Modulated (PFM) regulation. The hysteretic control scheme does not utilize an internal
oscillator. Switching frequency depends on external components and operating conditions. Operating frequency
decreases at light loads, resulting in excellent efficiency compared to PWM architectures. Because switching is
directly controlled by the output conditions, hysteretic control provides exceptional load transient response.
HYSTERETIC CONTROL CIRCUIT
The LM3475 uses a comparator-based voltage control loop. The voltage on the feedback pin is compared to a
0.8V reference with 21mV of hysteresis. When the FB input to the comparator falls below the reference voltage,
the output of the comparator goes low. This results in the driver output, PGATE, pulling the gate of the PFET low
and turning on the PFET.
With the PFET on, the input supply charges COUT and supplies current to the load through the PFET and the
inductor. Current through the inductor ramps up linearly, and the output voltage increases. As the FB voltage
reaches the upper threshold (reference voltage plus hysteresis) the output of the comparator goes high, and the
PGATE turns the PFET off. When the PFET turns off, the catch diode turns on, and the current through the
inductor ramps down. As the output voltage falls below the reference voltage, the cycle repeats. The resulting
output, inductor current, and switch node waveforms are shown in Figure 12.
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VIN
tON
tOFF
-VD
Switch Voltage
Iout
'IL
Inductor Current
td
VOUT
VOUT
ripple
(DC)
VHYST
td
Output Voltage
Figure 12. Hysteretic Waveforms
The LM3475 operates in discontinuous conduction mode at light load current and continuous conduction mode at
heavy load current. In discontinuous conduction mode, current through the inductor starts at zero and ramps up
to the peak, then ramps down to zero. The next cycle starts when the FB voltage reaches the reference voltage.
Until then, the inductor current remains zero. Operating frequency is low, as are switching losses. In continuous
conduction mode, current always flows through the inductor and never ramps down to zero.
SOFT-START
The LM3475 includes an internal soft-start function to protect components from excessive inrush current and
output voltage overshoot. As VIN rises above 2.7V (typical), the internal bias circuitry becomes active. When EN
goes high, the device enters soft-start. During soft-start, the reference voltage is ramped up to the nominal value
of 0.8V in approximately 4ms. Duty cycle and output voltage will increase as the reference voltage is ramped up.
UNDER VOLTAGE DETECTION
When the output voltage falls below 70% (typical) of the normal voltage, as measured at the FB pin, the device
turns off PFET and restarts a new soft-start cycle. In short circuit, the PFET is always on, and the converter is
effectively a resistor divider from input to output to ground. Whether the part restarts depends on the power path
resistance and the short circuit resistance. This feature should not be considered as overcurrent protection or
output short circuit protection.
PGATE
During switching, the PGATE pin swings from VIN (off) to ground (on). As input voltage increases, the time it
takes to slew the gate of the PFET on and off also increases. Also, as the PFET gate voltage approaches VIN,
the PGATE current driving capability decreases. This can cause a significant additional delay in turning the
switch off when using a PFET with a low threshold voltage. These two effects will increase power dissipation and
reduce efficiency. Therefore, a PFET with relatively high threshold voltage and low gate capacitance is
recommended.
MINIMUM ON/OFF TIME
To ensure accurate comparator switching, the LM3475 imposes a blanking time after each comparator state
change. This blanking time is 180ns typically. Immediately after the comparator goes high or low, it will be held in
that state for the duration of the blanking time. This helps keep the hysteretic comparator from improperly
responding to switching noise spikes (See REDUCING SWITCHING NOISE) and ESL spikes (See OUTPUT
CAPACITOR SELECTION) at the output.
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At very low or very high duty cycle operation, maximum frequency will be limited by the blanking time. The
maximum operating frequency can be determined by the following equations:
FMAX = D / tonmin
FMAX = (1-D) / toffmin
(1)
where
•
•
D is the duty cycle, defined as VOUT/VIN, and tonmin
toffmin is the sum of the blanking time, the propagation delay time, and the PFET delay time (see Figure 12) (2)
ENABLE PIN (EN)
The LM3475 provides a shutdown function via the EN pin to disable the device. The device is active when the
EN pin is pulled above 1.5V (typ) and in shutdown mode when EN is below 1.135V (typ). In shutdown mode,
total quiescent current is less than 10µA. The EN pin can be directly connected to VIN for always-on operation.
Design Information
SETTING OUTPUT VOLTAGE
The output voltage is programmed using a resistor divider between VOUT and GND as shown in Figure 13. The
feedback resistors can be calculated as follows:
R 1 + R2
VOUT =
R2
x VFB
where
•
Vfb is 0.8V typically
(3)
The feedback resistor ratio, α = (R1+R2) / R2, will also be used below to calculate output ripple and operating
frequency.
PGATE
VOUT
L
PMOS_drv
+
COUT
R1
Cff
FB
+
-
R2
Hyst Comp
Reference
Voltage
+
VHYST = 21 mV
VFB = 0.8V
PGATE
Figure 13. Hysteretic Window
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SETTING OPERATING FREQUENCY AND OUTPUT RIPPLE
Although hysteretic control is a simple control scheme, the operating frequency and other performance
characteristics depend on external conditions and components. If the inductance, output capacitance, ESR, VIN,
or Cff is changed, there will be a change in the operating frequency and possibly output ripple. Therefore, care
must be taken to select components which will provide the desired operating range. The best approach is to
determine what operating frequency is desirable in the application and then begin with the selection of the
inductor and output capacitor ESR. The design process usually involves a few iterations to select appropriate
standard values that will result in the desired frequency and ripple.
Without the feedforward capacitor (Cff), the operating frequency (F) can be approximately calculated using the
formula:
VOUT
F=
VIN
(VIN - VOUT) x ESR
x
(VHYST x D x L) + (VIN x delay x ESR)
where
•
•
Delay is the sum of the LM3475 propagation delay time and the PFET delay time
The propagation delay is 90ns typically
(4)
Minimum output ripple voltage can be determined using the following equation:
VOUT_PP = VHYST ( R1 + R2 ) / R2
(5)
USING A FEED-FORWARD CAPACITOR
The operating frequency and output ripple voltage can also be significantly influenced using a speed up
capacitor, Cff, as shown in Figure 13. Cff is connected in parallel with the high side feedback resistor, R1. The
output ripple causes a current to be sourced or sunk through this capacitor. This current is essentially a square
wave. Since the input to the feedback pin (FB) is a high impedance node, the bulk of the current flows through
R2. This superimposes a square wave ripple voltage on the FB node. The end result is a reduction in output
ripple and an increase in operating frequency. When adding Cff, calculate the formula above with α= 1. The value
of Cff depends on the desired operating frequency and the value of R2. A good starting point is 1nF ceramic at
100kHz decreasing linearly with increased operating frequency. Also note that as the output voltage is
programmed below 1.6V, the effect of Cff will decrease significantly.
INDUCTOR SELECTION
The most important parameters for the inductor are the inductance and the current rating. The LM3475 operates
over a wide frequency range and can use a wide range of inductance values. Minimum inductance can be
calculated using the following equation:
VIN - VSD - VOUT
x
L=
'I
D
F
where
•
•
D is the duty cycle, defined as VOUT/VIN
ΔI is the allowable inductor ripple current
(6)
Maximum allowable inductor ripple current should be calculated as a function of output current (IOUT) as shown
below:
ΔImax = IOUT x 0.3
The inductor must also be rated to handle the peak current (IPK) and RMS current given by:
IPK = (IOUT + ΔI/2) x 1.1
(7)
2
IRMS = IOUT2 + 'I
3
(8)
The inductance value and the resulting ripple is one of the key parameters controlling operating frequency.
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OUTPUT CAPACITOR SELECTION
Once the desired operating frequency and inductance value are selected, ESR must be selected based on
Equation 4. This process may involve a few iterations to select standard ESR and inductance values.
In general, the ESR of the output capacitor and the inductor ripple current create the output ripple of the
regulator. However, the comparator hysteresis sets the first order value of this ripple. Therefore, as ESR and
ripple current vary, operating frequency must also vary to keep the output ripple voltage regulated. The hysteretic
control topology is well suited to using ceramic output capacitors. However, ceramic capacitors have a very low
ESR, resulting in a 90° phase shift of the output voltage ripple. This results in low operating frequency and
increased output ripple. To fix this problem a low value resistor could be added in series with the ceramic output
capacitor. Although counter intuitive, this combination of a ceramic capacitor and external series resistance
provide highly accurate control over the output voltage ripple. Another method is to add an external ramp at the
FB pin as shown in Figure 14. By proper selection of R1 and C2, the FB pin sees faster voltage change than the
output ripple can cause. As a result, the switching frequency is higher while the output ripple becomes lower. The
switching frequency is approximately:
VIN
F=
2S x R1 x C2 x VHYS
(9)
Other types of capacitor, such as Sanyo POSCAP, OS-CON, and Nichicon ’NA’ series are also recommended
and may be used without additional series resistance. For all practical purposes, any type of output capacitor
may be used with proper circuit verification.
Capacitors with high ESL (equivalent series inductance) values should not be used. As shown in Figure 12, the
output ripple voltage contains a small step at both the high and low peaks. This step is caused by and is directly
proportional to the output capacitor’s ESL. A large ESL, such as in an electrolytic capacitor, can create a step
large enough to cause abnormal switching behavior.
INPUT CAPACITOR SELECTION
A bypass capacitor is required between VIN and ground. It must be placed near the source of the external PFET.
The input capacitor prevents large voltage transients at the input and provides the instantaneous current when
the PFET turns on. The important parameters for the input capacitor are the voltage rating and the RMS current
rating. Follow the manufacturer’s recommended voltage de-rating. RMS current and power dissipation (PD) can
be calculated with the equations below:
IOUT
IRMS_CIN =
VIN
VOUT x (VIN - VOUT)
(10)
L1
10 PH
Q1
Si2343
VIN
VOUT = 0.9V/2A
COUT
CIN
10 PF
D1
5
4
PGATE
VIN
GND
100 PF
2
EN
RFB1
1.27k
C1
3.9 nF
LM3475
3
R1
200k
FB
1
C2
390 pF
RFB2
10k
Figure 14. External Ramp
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DIODE SELECTION
The catch diode provides the current path to the load during the PFET off time. Therefore, the current rating of
the diode must be higher than the average current through the diode, which be calculated as shown:
ID_AVE = IOUT x (1 − D)
(11)
The peak voltage across the catch diode is approximately equal to the input voltage. Therefore, the diode’s peak
reverse voltage rating should be greater than 1.3 times the input voltage.
A Schottky diode is recommended, since a low forward voltage drop will improve efficiency.
For high temperature applications, diode leakage current may become significant and require a higher reverse
voltage rating to achieve acceptable performance.
P-CHANNEL MOSFET SELECTION
The PFET switch should be selected based on the maximum Drain-Source voltage (VDS), Drain current rating
(ID), maximum Gate-Source voltage (VGS), on resistance (RDSON), and Gate capacitance. The voltage across the
PFET when it is turned off is equal to the sum of the input voltage and the diode forward voltage. The VDS must
be selected to provide some margin beyond the sum of the input voltage and Vd.
Since the current flowing through the PFET is equal to the current through the inductor, ID must be rated higher
than the maximum IPK. During switching, PGATE swings the PFET’s gate from VIN to ground. Therefore, A PFET
must be selected with a maximum VGS larger than VIN. To insure that the PFET turns on completely and quickly,
refer to the PGATE section.
The power loss in the PFET consists of switching losses and conducting losses. Although switching losses are
difficult to precisely calculate, the equation below can be used to estimate total power dissipation. Increasing
RDSON will increase power losses and degrade efficiency. Note that switching losses will also increase with lower
gate threshold voltages.
PDswitch = RDSONx (IOUT)2x D + F x IOUTx VINx (ton + toff)/2
where
•
•
•
ton = FET turn on time
toff = FET turn off time
A value of 10ns to 50ns is typical for ton and toff
(12)
Note that the RDSON has a positive temperature coefficient. At 100°C, the RDSON may be as much as 150% higher
than the value at 25°C.
The Gate capacitance of the PFET has a direct impact on both PFET transition time and the power dissipation in
the LM3475. Most of the power dissipated in the LM3475 is used to drive the PFET switch. This power can be
calculated as follows:
The amount of average gate driver current required during switching (IG) is:
IG = Qg x F
(13)
And the total power dissipated in the device is:
IqVIN + IGVIN
where
•
Iq is typically 260µA as shown in Electrical Characteristics
(14)
As gate capacitance increases, operating frequency may need to be reduced, or additional heat sinking may be
required to lower the power dissipation in the device.
In general, keeping the gate capacitance below 2000pF is recommended to keep transition times (switching
losses), and power losses low.
REDUCING SWITCHING NOISE
Although the LM3475 employs internal noise suppression circuitry, external noise may continue to be excessive.
There are several methods available to reduce noise and EMI.
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MOSFETs are very fast switching devices. The fast increase in PFET current coupled with parasitic trace
inductance can create unwanted noise spikes at both the switch node and at VIN. Switching noise will increase
with load current and input voltage. This noise can also propagate through the ground plane, sometimes causing
unpredictable device performance. Slowing the rise and fall times of the PFET can be very effective in reducing
this noise. Referring to Figure 15, the PFET can be slowed down by placing a small (1Ω-10Ω) resistor in series
with PGATE. However, this resistor will increase the switching losses in the PFET and will lower efficiency.
Therefore it should be kept as small as possible and only used when necessary. Another method to reduce
switching noise (other than good PCB layout, see Layout) is to use a small RC filter or snubber. The snubber
should be placed in parallel with the catch diode, connected close to the drain of the PFET, as shown in
Figure 15. Again, the snubber should be kept as small as possible to limit its impact on system efficiency. A
typical range is a 10Ω-100Ω resistor and a 470pF to 2.2nF ceramic capacitor.
RPGATE
5
Q1
PGATE
3.3:
L1
CSNUB
D1
RSNUB
Figure 15. PGATE Resistor and Snubber
Layout
PC board layout is very important in all switching regulator designs. Poor layout can cause EMI problems, excess
switching noise and poor operation.
As shown in Figure 17 and Figure 18, place the ground of the input capacitor as close as possible to the anode
of the diode. This path also carries a large AC current. The switch node, the node connecting the diode cathode,
inductor, and PFET drain, should be kept as small as possible. This node is one of the main sources for radiated
EMI.
The feedback pin is a high impedance node and is therefore sensitive to noise. Be sure to keep all feedback
traces away from the inductor and the switch node, which are sources of noise. Also, the resistor divider should
be placed close to the FB pin. The gate pin of the external PFET should be located close to the PGATE pin.
Using a large, continuous ground plane is also recommended, particularly in higher current applications.
L1
10 PH
Q1
Si2343
VIN = 5V
VOUT = 2.5V/2A
COUT
CIN
10 PF
D1
5
PGATE
4
GND
VIN
100 PF
2
CFF
1 nF
LM3475
3
EN
FB
RFB1
2.15k
1
RFB2
1k
Figure 16.
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Table 1. Bill of Materials
Designator
Description
Part Number
Vendor
CIN
10µF, 16V, X5R
EMK325BJ106MN
TAIYO YUDEN
COUT
100µF, 6V, Ta
TPSY107M006R0100
AVX
CFF
1nF, 25V, X7R
VJ1206Y102KXXA
Vishay
D1
Schottky, 20V, 2A
CMSH2-20L
Central Semiconductor
L1
10µH, 3.1A
CDRH103R100
Sumida
30V, 2.5A
Si2343
Vishay
1kΩ, 0805, 1%
CRW08051001F
Vishay
RFB1
2.15kΩ, 0805, 1%
CRCW08052151F
Vishay
D1
Cin
GN
D
Q1
Cout
Q1
RFB2
RFB2
Vou
t
RFB1
L
1
CFF
0 Ohm
EN
Vin
Figure 17. Top Layer (Standard Board)
(2:1 Scale)
Cin
D1
Q1
Cout
GND
RFB2
Vou
t
L
1
C1
R1
C2
RFB1
0 Ohm
EN
Vi
n
Figure 18. Top Layer (with External Ramp)
(2:1 Scale)
Figure 19. Bottom Layer
(2:1 Scale)
14
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Product Folder Links: LM3475
PACKAGE OPTION ADDENDUM
www.ti.com
9-Mar-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LM3475MF
ACTIVE
SOT-23
DBV
5
1000
TBD
Call TI
Call TI
-40 to 125
S65B
LM3475MF/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
S65B
LM3475MFX
ACTIVE
SOT-23
DBV
5
3000
TBD
Call TI
Call TI
-40 to 125
S65B
LM3475MFX/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
S65B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
LM3475MF
SOT-23
DBV
5
1000
178.0
8.4
LM3475MF/NOPB
SOT-23
DBV
5
1000
178.0
LM3475MFX
SOT-23
DBV
5
3000
178.0
LM3475MFX/NOPB
SOT-23
DBV
5
3000
178.0
3.2
3.2
1.4
4.0
8.0
Q3
8.4
3.2
3.2
1.4
4.0
8.0
Q3
8.4
3.2
3.2
1.4
4.0
8.0
Q3
8.4
3.2
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM3475MF
SOT-23
DBV
5
1000
203.0
190.0
41.0
LM3475MF/NOPB
SOT-23
DBV
5
1000
203.0
190.0
41.0
LM3475MFX
SOT-23
DBV
5
3000
206.0
191.0
90.0
LM3475MFX/NOPB
SOT-23
DBV
5
3000
206.0
191.0
90.0
Pack Materials-Page 2
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