¡ Semiconductor MSM58321 ¡ Semiconductor MSM58321 REAL TIME CLOCK/CALENDAR DESCRIPTION The MSM 58321 is a metal gate CMOS Real Time Clock/Calendar with a battery backup function for use in bus-oriented microprocessor applications. The time is read with 4-bit DATA I/O, ADDRESS WRITE, READ, and BUSY; it is written with 4-bit DATA I/O, ADDRESS WRITE, WRITE, and BUSY. The 4-bit bidirectional bus line method is used for the data I/O circuit; the clock is set, corrected, or read by accessing the memory. FEATURES • 7 Function-Second, Minute, Hour, Day, Day-of-Week, Month, Year • Automatic leap year calender • 12/24 hour format • Frequency divider 5-poststage reset • Reference signal output • • • • 32.768 kHz crystal controlled operation Single 5V power supply Back-up battery operation to VDD = 2.2V Low power dissipation 90 µW max. at VDD = 3V 2.5 mW max. at VDD = 5V • 16 pin plastic DIP (DIP 16-P-300) FUNCTIONAL BLOCK DIAGRAM 5-poststage (O11~O15) XT RFB 215 1/60 Hz 1 Hz 1 OSC XT 1024 Hz 1/3600 Hz BUSY R R BUSY \DATA BUS STOP SWITCH 3 4 3 4 4 E-F N 4 3 W S1 S10 MI1 MI10 H1 H10 1/10 1/6 1/10 1/6 1/12 or 1/24 1/7 SECOND MINUTE HOUR WEEK S1 S10 MI1 MI10 H1 H10 TEST Rp TEST 1 Hz D Rp WRITE WRIETE WRITE Rp W READ Rp READ CS1 Rp DATA BUS CS TEST-P CS2 Rp 4 D0 D1 TRI-STATE D2 D3 CONTROL ADDRESS LATCH ADDRESS WRITE Rp 4 4 MO1 MO10 Y1 Y10 1/10 1/3 1/12 1/10 1/10 DAY MONTH YEAR D1 D10 ADDRESS DECODER 0 1 2 3 4 5 6 7 8 9 A B C D E-F S1 S10 MI1 MI10 H1 H10 W D1 D10 MO1 MO10 Y1 Y10 D E-F 4 4 WRITE D1 D10 MO1 MO10 Y1 Y10 Rp = 200 k TYP 7 MSM58321 ¡ Semiconductor PIN CONFIGURATION 16 pin Plastic DIP (top View) CS2 1 16 VDD WRITE 2 15 XT READ 3 14 XT D0 4 13 CS1 D1 5 12 TEST D2 6 11 STOP D3 7 10 BUSY GND 8 9 ADDRESS WRITE REGISTER TABLE Address input Address D0 (A0) D1 (A1) D2 (A2) D3 (A3) 0 0 0 0 0 1 1 0 0 0 2 0 1 0 0 3 1 1 0 4 0 0 5 1 6 7 Count value Remarks D0 D1 D2 D3 S1 * * * * S10 * * * MI1 * * * 0 MI10 * * * 1 0 H1 * * * 0 1 0 H10 * * * 0 1 1 0 W * * * 0 to 6 1 1 1 0 D1 * * * * 0 to 9 8 0 0 0 1 D10 * * * * 0 to 3 9 1 0 0 1 MO1 * * * * 0 to 9 A 0 1 0 1 MO10 * 0 to 1 B 1 1 0 1 Y1 * * * * 0 to 9 C 0 0 1 1 Y10 * * * * 0 to 9 D 1 0 1 1 A selector to reset 5 poststages in the 1/215 frequency divider and the BUSY circuit. They are reset when this code is latched with ADDRESS LATCH and the WRITE input goes to 1. E~F 0/1 1 1 1 A selector to obtain reference signal output. Reference signals are output to D0 – D3 when this code is latched with ADDRESS LATCH and READ input goes to 1. Note: (1) (2) (3) 8 Data input/ output Register Name 0 to 9 0 to 5 0 to 9 0 to 5 * 0 to 9 * D2 = 1 specifies PM, D2 = 0 specifies AM, D3 = 1 specifies 24-hour timer, and 0~1 or 0~2 D3 = 0 specifies 12-hour timer. When D3 = 1 is written, the D2 bit is reset inside the IC. * The D2 and D3 bits in D10 are used to select a leap year. Remainder obtained by dividing the Calendar D 2 D3 year number by 4 Gregorian calendar 0 0 0 1 0 3 0 1 2 1 1 1 There are no bits in blank fields for data input/output. 0 signals are output by reading and data is not stored by writing because there are no bits. The bit with marked * is used to select the 12/24-hour timer and the bits marked * are used to select a leap year. These three bits can be read or written. When signals are input to bus lines D0 – D3 and ADDRESS WRITE goes to 1 for address input, ADDRESS information is latched with ADDRESS LATCH. ¡ Semiconductor MSM58321 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Rating Symbol Condition Value Unit Power voltage VDD Ta = 25°C –0.3 to 6.5 V Input voltage VI Ta = 25°C –0.3 to VDD+0.3 V Output voltage VO Ta = 25°C –0.3 to VDD+0.3 V Storage temperature Tstg – –55 to +150 °C Symbol Condition Value Unit Power voltage VDD – 4.5 to 6 V Date hold voltage VDH – 2.2 to 6 V Crystal frequency ƒ(XT) – 32.768 kHz TOP – –30 to +85 °C Operating Conditions Rating Operating temperature Note: The data hold voltage guarantees the clock operations, though it does not guarantee operations outside the IC and data input/output. DC Characteristics (VDD = 5V ±5%, Ta = –30 ~ +85°C) Rating H input voltage Min. Typ. Max. – Note 1 3.6 – – – Note 2 VDD–0.5 – – Symbol Condition VIH1 VIH2 Unit V L input voltage VIL – – – 0.8 V L output voltage VOL IO = 1.6 mA – – 0.4 V mA IOL VO = 0.4 V 1.6 – – IIH1 VI = VDD Note3 10 30 80 IIH2 VI = VDD Note4 – – 1 L input current IIL VI = 0V – – –1 µA Input capacity CI ƒ = 1 MHz – 5 – pF Current consumption IDD ƒ = 32.768 kHz VDD = 5V/VDD = 3V – 100/15 500/30 µA L output current H input current Note: 1. 2. 3. 4. µA CS2, WRITE, READ, ADDRESS WRITE, STOP, TEST, D0 ~ D3 CS1 CS1, CS2, WRITE, READ, ADDRESS WRITE, STOP, TEST D0 ~ D3 9 MSM58321 ¡ Semiconductor Switching Characteristics (1) WRITE mode (VDD = 5V ±5%, Ta = 25°C) Rating Symbol Condition Min. Typ. Max. CS setup time tCS – 0 – – µs CS hold time tCH – 0 – – µs Address setup time tAS – 0 – – µs Address write pulse width tAW – 0.5 – – µs Address hold time tAH – 0.1 – – µs Data setup time tDS – 0 – – µs Write pulse width tWW – 2 – – µs Data hold time tDH – 0 – – µs H CS1 CS2 tCS L D0 ~ D3 (ADDRESS/DATA) ,, ,, tAS ,, ,, ,, ,, ,, ,, ,, ,Impedance High ,, , , ,, ,, , IC internal ADDRESS IC internal DATA ADDRESS DATA Write Cycle Note: ADDRESS WRITE and WRITE inputs are activated by the level, not by the edge. 10 tCH tAW tAH tDS tWW tDH ADDRESS WRITE WRITE Unit ¡ Semiconductor MSM58321 (2) READ mode (VDD = 5V ±5%, Ta = 25°C) Rating Symbol Condition Min. Typ. Max. CS setup time tCS – 0 – – µs CS hold time tCH – 0 – – µs Address setup time tAS – 0 – – µs Address write pulse width tAW – 0.5 – – µs Address hold time tAH – 0.1 – – µs Read access time tRA – – – see Note 1 µs Read delay time tDD – – – 1 µs Read inhibit time tRI – 0 – – µs Note 1. tRA = 1 µs + CR ln ( CS2 tRI tCS L tAS tAW tRH DATA VALID tRA DATA INVALID tDD tCH ,, D0 ~ D3 (ADDRESS/DATA) ,, ,, ,, ,, ,, ADDRESS WRITE VDD ) VDD – VIH min H CS1 Unit ,, ,, ,, ,, ,, ,, ,, ,, ,, , ,, , , High Impedance ,, ,, READ ADDRESS ,, ,, ,, , DATA Read Cycle Note: ADDRESS WRITE and READ inputs are activated by the level, not by the edge. 11 MSM58321 ¡ Semiconductor (3) WRITE & READ mode (VDD = 5V ±5%, Ta = 25°C) Rating Symbol Condition Min. Typ. Max. Unit CS setup time tCS – 0 – – µs CS hold time tCH – 0 – – µs Address setup time tAS – 0 – – µs Address write pulse width tAW – 0.5 – – µs Address hold time tAH – 0.1 – – µs Data setup time tDS – 0 – – µs Write pulse width tWW – 2 – – µs Data hold time tDH – 0 – – µs Read access time tRA – – – see Note 1 µs Read delay time tDD – – – 1 µs Read inhibit time tRI – 0 – – µs Note 1. tRA = 1 µs + CR ln ( VDD ) VDD – VIH min DATA INVALID DATA VALID CS1 CS2 H tRI tCS L tAS tAW tAH tDS tWW tDH D0 ~ D3 (ADDRESS/DATA) tRA tDD tCH , ,, ,, ,, ,, ,, ADDRESS WRITE ,,,,,, ,, ,, , ,, ,, WRITE ,, READ IC internal ADDRESS IC internal DATA ADDRESS DATA WRITE DATA READ Read & Write Cycle 12 ,, High Impedance ,, ,, , ¡ Semiconductor MSM58321 PIN DESCRIPTION Name Pin No. Description CS2 1 Chip select pins. These pins enable the interface with the external circuit when both of these pins are set at H level simultaneously. CS1 13 If one of these pins is set at L level, STOP, TEST, WRITE, READ, ADDRESS WRITE pins and D0 ~ D3 pins are inactivated. Since the threshold voltage VT for the CS1 pin is higher than that for other pins, it shuold be connected to the detector of power circuit and peripherals and CS2 is to be connected to the microcontroller. WRITE 2 WRITE pin is used to write data; it is activated when it is at the H level. Data bus data inside the IC is loaded to the object digit while this WRITE pin is at the H level, not at the WRITE input edge. Refer to Figure 1 below. (S1 digit) D0 D3 Q S Q R S R WRITE D0 D1 D2 D3 DATA BUS S1 CS1 = CS2 = "H" D0 H S1 WRITE F/F D0-θ Figure 1 13 MSM58321 ¡ Semiconductor Name Pin No. READ 3 Description READ pin is used to read data; it is activated when it is at the H level. Address contents are latched with ADDRESS LATCH inside the IC at the D0 ~ D3 and ADDRESS WRITE pins to select the object digit, then an H-level signal is input to the READ pin to read data. If a count operation is continued by setting the STOP input to the L level, read operation must be performed, in principle, while the BUSY output is at the H level. While the BUSY output is at the L level, count operations are performed by digit counters and read data is not guaranteed, therefore, read operations are inhibited in this period. Figure 2 shows a time chart of the BUSY output, 1 Hz signal inside the IC, and READ input. A read operation is stopped temporarily within a period of 244 µs from the BUSY output trailing edge and it is restarted when the BUSY output goes to the H level again. 427 µs BUSY 1 Hz (inside IC) The counter inside the IC starts counting at the 1 Hz signal leading edge. Read-enabled period 244 µs 122 µs 61 µs Read-enabled period Read-inhibited period Read operation is enabled in this period: however, it is used for program switching. BUSY 1 Hz (inside IC) READ input 1 sec Figure 2 If the counter operation is stopped by setting the STOP input to the H level, read operations are enabled regardless of the BUSY output. A read operation is enabled by microcomputer software regardless of the BUSY output during the counter operation by setting the STOP input to the L level. In this method, read operations are performed two or more times continuously and data that matches twice is used as guaranteed data. 14 ¡ Semiconductor MSM58321 Name Pin No. Description D0 ~ D3 4~7 Data input/output pins. (Bidirectional bus). The output is a open-drain type and 4.7 kΩ ~ 10 kΩ pull-up registers are required utilize these pins as output pins. GND 8 Ground pin. ADDRESS WRITE 9 ADDRESS WRITE pin is used to load address information from the D0 ~ D3 I/O bus pins to the ADDRESS LATCH inside the IC; it is activated when it is at the H level. This input is activated by the level, not by the edge. Figure 3 shows the relationships between the D0 address input, ADDRESS WRITE input, and ADDRESS LATCH input/output. D0 input ADDRESS WRITE DI0 ADDRESS LATCH (inside IC) L DO0 LATCH output Figure 3 BUSY 10 BUSY pin outputs the IC operation state. It is N-channel MOSFET open-drain output. An external pull-up resistor of 4.6 kΩ or more must be connected (see Figure 4) to use the BUSY output. The signals are output in negative logics. If the oscillator oscillates at 32.768 kHz, the frequency is always 1 Hz regardless of the CS1 and CS2 unless the D output of the ADDRESS DECODER inside the IC is H (CODE = H•L•H•H) and CS1 = CS2 = WRITE = H. Figure 5 shows the BUSY output time chart. (peripheral circuit power) 4.7 kΩ or more +5V BUSY BUSY RESET N MSM58321RS WRITE D Figure 4 The counter inside the IC starts counting at the 1 Hz signal leading edge. BUSY 1 Hz (inside IC) 244 µs 122 µs 61 µs 427 µs Read/write-inhibited period BUSY 1 Hz (inside IC) 1 sec Figure 5 15 MSM58321 ¡ Semiconductor Name Pin No. Description STOP 11 The STOP pin is used to input on/off control for a 1 Hz signal. When this pin goes to the H level, 1 Hz signals are inhibited and counting for all digits succeeding the S1 digit is stopped. When this pin goes to the L level, normal operations are performed; the digits are counted up. This STOP input controls stopping digit counting. Writing of external data in digits can be assured by setting the STOP input to the H level to stop counting, then writing sequentially from the low-order digits. TEST 12 The TEST pin is used to test this IC; it is normally open or connected to GND. It is recommended to connect it to GND to safeguard against malfunctions from noise. The TEST pulse can be input to the following nine digits: S1, S10, MI10, H1, D1 (W), M01, Y1 and Y10 When a TEST pulse is input to the D1 digit, the W digit is also counted up simultaneously. Input a TEST pulse as follows: Set the address to either digit explained above, then input a pulse to the TEST pin while CS1 = CS2 = STOP = H and WRITE = L. The specified and succeeding digits are counted up. (See Figure 6) 0~9 1 Hz 0~5 C10 C10 S1 TEST 0~9 C1 Rp C10 S10 MI1 TEST-P C-S S1 S10 0~9 MI1 0~6 C0 D1 D1 C1 C1 W D10 Rp = 200 kΩ TYP Figure 6 A digit is counted up at the leading edge (changing point from L to H) of a TEST pin input pulse. The pulse condition for TEST pin input at VDD = 5V ±5% is described in Figure 7 below. tH tL tH = 10 µs MIN tL = 10 µs MIN Figure 7 16 ¡ Semiconductor MSM58321 Name Pin No. Description XT XT 14 15 Oscillator pin. A 32.768 kHz crystal oscillator, capacitor and trim capacitor for frequency adjustment are to be connected as shown in Figure 8 below. RFB = 10 MΩ TYP XT C1 XT GND or VDD RS = 200 kΩ typ RFB RS MSM58321 C2 X-TAL 32.768 kHz, The crystal impedance is 30 kΩ or less. Figure 8 If an external clock is to be used for MSM58321's oscillation source, the external clock is to be input to XT, while XT should be left open. Refer to the Figure 9 below. CMOS XT or +5V XT MSM58321 TTL Figure 9 VDD 16 Power supply pin. Refer to the application circuit. 17 MSM58321 ¡ Semiconductor REFERENCE SIGNAL OUTPUT Reference signals are output from the D0 ~ D3 pins under the following conditions: Output pin Reference signal frequency Pulse width Output logic WRITE = L D0 1024 Hz 488.3 µs Pisitive logic READ = H D1 1 Hz 122.1 µs Negative logic CS1 = CS2 = H D2 1/60 Hz 122.1 µs Negative logic ADDRESS = E or F D3 1/3600 Hz 122.1 µs Netgative logic Conditions 488.3 µs 488.3 µs 1024 Hz 1 Hz 1/60 Hz 1/3600 Hz 1 Hz (inside IC) BUSY 244 µs 122 µs 61 µs -3 122.1 µs = 10 x4 32,768 -3 488.3 µs = 10 x16 32,768 Figure 10 18 ¡ Semiconductor MSM58321 APPLICATION NOTES WRITE and STOP Note that the timing relationship between the STOP and WRITE inputs vary by the related digit when counting is stopped by the STOP input to write data. The time (tSH) between the STOP input leading edge and WRITE input trailing edge for each digit is limited to the minimum value. (See Figure 11) at VDD = 5V±5% STOP WRITE S1 S10 MI1 MI10 H1 1 2 3 4 5 H10 D1(W) D10 6 7 MO1 MO10 8 9 10 Y1 Y10 11 12 tSHS1 tSHS10 tSHY10 Write-inhibited period Figure 11 tSHS1 = 1 µs, tSHS10 = 2 µs, tSHMI1 = 3 µs, tSHM10 = 4 µs, tSHH1 = 5 µs tSHH10 = 6 µs, tSHD1 = 7 µs, tSHW = 7 µs, tSHD10 = 8 µs, tSHM01 = 9 µs tSHMO10 = 10 µs, tSHY1 = 11 µs, tSHY10 = 12 µs. 19 MSM58321 ¡ Semiconductor If a count operation is continued by setting the STOP input to the L level, write operation must be performed, in principle, while the BUSY output is at the H level. While the BUSY output is at the L level, count operations are performed by the digit counters and write operation is inhibited, but there is a marginal period of 244 µs from the BUSY output trailing edge. If the BUSY output goes to the L level during a write operation, the write operation is stopped temporarily within 244 µs and it is restarted when the BUSY output goes to the H level again. Figure 12 shows a time chart of BUSY output, 1 Hz signal inside the IC, and WRITE input. BUSY 1 Hz (inside IC) WRITE input 1 sec Figure 12 Frequency divider and BUSY circuit reset If A0 ~ A3 = H•L•H•H is input to ADDRESS DECODER, the DECODER output (D) goes to the H level. If CS1 = CS2 = H and WRITE = H in this state, the 5 poststage in the 15-stage frequency divider and the BUSY circuit are reset. In this period, the BUSY output remains at the H level and the 1 Hz signal inside the IC remains at the L level, and counting is stopped. If this reset is inactivated while the oscillator operates, the BUSY output goes to the L level after 1000.1221 ±31.25 ms and the 1 Hz signal inside the IC goes to the H level after 1000.3663 ±31.25 ms. These times are not the same because the first ten stages in the 15-stage frequency divider are not reset. (See Figure 13) 15-stage frequency divider circuit 1~10 stage OSC 32,768 kHz Stages 11~15 015 R BUSY R 1 Hz BUSY N RESET STOP STOP Rp WRITE WRITE Rp D CS From ADDRESS DECODER A0 A1 A2 A3 H L H H t3 O15 (inside IC) 1 Hz (inside IC) RESET (inside IC) t1 = 1000.1221 ±31.25 ms t2 = 1000.3663 ±31.25 ms t3 = 1000 ±31.25 ms Figure 13 20 t1 t2 ¡ Semiconductor MSM58321 Selection of leap year This IC is designed to select leap year automatically. Four types of leap years can be selected by writing a select signal in the D2 and D3 bits of the D10 digit (CODE = L•L•L•H). (See table 1 for the functions.) Gregorian calendar or other calendars can be set arbitrarily in the Y1 and Y10 digits of this IC. There is a leap year every four years and the year number varies according to the calendar used. There are four combinations of year numbers and leap years. (See the Table below). No. 1: No. 2: No. 3: No. 4: Gregorian calendar year. The remainder obtained by dividing the leap year number by 4 is 0. The remainder obtained by dividing the leap year number by 4 is 3. The remainder obtained by dividing the leap year number by 4 is 2. The remainder obtained by dividing the leap year number by 4 is 1. D10 digit D2 D3 Remainder obtained by dividing the leap year number by 4 Leap years (examples) L L 0 1980, 1984, 1988, 1992 1996, 2000, 2004 2 H L 3 (83) (87) (91) (95) (99) 55, 59, 63, 67, 71, 75, 79 3 L H 2 82, 86, 90, 94, 98, 102, 106 4 H H 1 81, 85, 89, 93, 97, 101, 105 No.1 1 Calendar Gregorian 21 MSM58321 ¡ Semiconductor APPLICATION EXAMPLE – POWER SUPPLY CIRCUIT VF = 0.69V 1S1588 Ripple +5.7V + 4.7µ 100Ω a) + Operating state 20 mV P-P Backup 0 mV VDD or – C372 GND MSM58321 1.2x3 = 3.6V Ni-Cd battery VF = 0.69 VCE (Sat) = 0.1V Ripple A495 Operating state 100Ω 51K + 10K VDD – b) 20 mV P-P 4.7µ Backup 0 mV + C372 10K GND – MSM58321 RL MC +5V RL 100Ω B + + 4.7µ VDD – c) – GND MSM58321 1.5x2 = 3V Dry cell (Recommended circuit) +V (Power voltage approximately 1.5V higher than 5V) D1 D2 +5V (Peripheral circuit power) d) R2 100Ω 4.7µ VDD + – 3.6V Ni-Cd battery GND MSM58321 Note: Use the same diodes for D1 and D2 to reduce the level difference between +5V and VDD of the MSM58321. 22