Holtek HT827A0 8-bit microcontroller with voice rom Datasheet

HT827A0
8-Bit Microcontroller with Voice ROM
Features
8-bit microcontroller
·
·
·
·
·
·
·
·
Operating voltage: 2.4V~5.2V
8K´16 program ROM
208´8 data RAM
36 bidirectional I/O lines
Interrupt input
16-bit programmable timer/event
counter with overflow interrupts
Watchdog timer
On-chip crystal or RC types of oscillator
·
·
·
·
Halt function and wake-up feature reduces
power consumption
63 powerful instructions
Up to a 1ms instruction cycle with a 4MHz
system clock at VDD=5V
All instructions in 1 or 2 machine cycles
16-bit table read instruction
8-level subroutine nesting
Bit manipulation instruction
·
·
·
·
Current type of D/A switch output
Tone generator counter
Controllable volume
48-pin DIP package
·
·
·
Alert and warning systems
Public address systems
Sound effect generators
·
·
·
Voice and melody synthesizer
·
·
·
·
·
128K´8 voice ROM
3/4 bit ADPCM coding algorithm
26 kinds of voice sampling rates
Tone level of 4 octaves
14 kinds of melody beats
Applications
·
·
·
Intelligent educational toys
High end toy controllers
Talking alarm clocks
General Description
current type D/A output. With such a flexible
structure, the HT827A0 is excellent for versatile voice and sound effect product applications.
It also includes a halt function to reduce power
consumption.
The HT827A0 is 8-bit high performance
microcontroller with a voice synthesizer and
tone generator. They are designed for applications on multiple I/Os with sound effects. The
LSIs provide 26 kinds of voice sampling rates, 4
octaves of tone level as well as a high quality of
1
March 15, 2000
HT827A0
Block Diagram
T M R
IN T
O S C 1
V o ic e R O M
& C o n tr o lle r
8 - b it H ig h P e r fo r m a n c e
M ic r o c o n tr o lle r
O S C 2
R E S
V o ic e
S y n th e s iz e r &
T o n e g e n e ra to r
V D D
V S S
C u rre n t T y p e
D /A O u tp u t
P A 0
A U D
3 6 - b it B id ir e c tio n a l
I/O P o rts
P A 7
P B 0
P B 7
P C 0
P C 7
P D 0
P D 7
P E 0
P E 3
Pin Assignment
P A 3
1
4 8
P B 4
P A 2
2
4 7
P B 5
P A 1
3
4 6
P B 6
N C
4
4 5
P B 7
P A 0
5
4 4
P A 4
P B 3
6
4 3
P A 5
P B 2
7
4 2
P A 6
P B 1
8
4 1
P A 7
P B 0
9
4 0
N C
V S S
1 0
3 9
N C
P E 0
1 1
3 8
N C
P E 1
1 2
3 7
O S C 2
P E 2
1 3
3 6
O S C 1
P E 3
1 4
3 5
V D D
IN T
1 5
3 4
R E S
T M R
1 6
3 3
A U D
P D 0
1 7
3 2
P C 7
P D 1
1 8
3 1
P C 6
P D 2
1 9
3 0
P C 5
P D 3
2 0
2 9
P C 4
P D 4
2 1
2 8
P C 3
P D 5
2 2
2 7
P C 2
P D 6
2 3
2 6
P C 1
P D 7
2 4
2 5
P C 0
0 6 & % ) " & , 12
2
March 15, 2000
HT827A0
Pad Assignment
P A 0
P A 1
P A 2
P A 3
P B 4
P B 5
P B 6
P B 7
P A 4
P A 5
P A 6
P A 7
1
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
2
P B 3
3
P B 2
4
P B 1
5
P B 0
V S S
6
7
P E 0
8
P E 1
P E 2
9
P E 3
1 0
IN T
1 1
T M R
1 2
(0 ,0 )
3 3
O S C 2
3 2
O S C 1
3 1
2 5
2 6
2 7
2 8
P C 7
2 4
A U D
P C 6
2 3
R E S
2 9
P C 5
2 2
P C 4
P D 4
2 1
P C 3
P D 3
2 0
P C 2
P D 2
P D 1
1 9
P C 1
P D 0
1 8
P C 0
1 7
P D 7
1 6
P D 6
1 4 1 5
P D 5
1 3
V D D
3 0
2
Chip size: 3555 ´ 5015 (mm)
* The IC substrate should be connected to VSS in the PCB layout artwork.
* The TMR pad must be bound to VDD or VSS if it is not used.
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March 15, 2000
HT827A0
Pad Coordinates
Unit: mm
Pad No.
X
Y
Pad No.
X
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
-1543.05
-1486.75
-1486.75
-1486.75
-1486.75
-1486.75
-1486.75
-1486.75
-1486.75
-1486.75
-1486.75
-1486.75
-1547.75
-1389.55
-1239.35
-1072.15
-913.45
-744.65
-585.95
-417.15
-258.45
-89.65
2242.95
1675.25
1491.25
1308.95
1126.15
925.35
727.25
538.35
347.85
157.35
-28.35
-219.25
-2211.75
-2211.75
-2211.75
-2211.75
-2211.75
-2211.75
-2211.75
-2211.75
-2211.75
-2211.75
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
69.05
237.85
598.35
890.95
1184.35
1476.95
1507.85
1499.05
1539.95
1585.75
1574.15
1502.55
1227.35
951.35
676.15
396.95
119.35
-159.85
-437.45
-716.65
-991.85
-1267.85
-2211.75
-2211.75
-2291.45
-2291.45
-2291.45
-2291.45
-2091.35
-1925.15
-1757.35
-1465.55
-667.75
2242.95
2242.95
2242.95
2242.95
2242.95
2242.95
2242.95
2242.95
2242.95
2242.95
2242.95
Pad Description
Mask
Option
Description
I/O
Wake-up
Pull-high
or None
Bidirectional 8-bit input/output ports
Each bit can be configured as a wake-up input by mask
option. Software instructions determine the CMOS output or schmitt trigger input with or without a pull-high resistor (mask option).
I/O
Pull-high
or None
Bidirectional 8-bit input/output ports
Software instructions determine the CMOS output or
schmitt trigger input with or without a pull-high resistor
(mask option).
I/O
Pull-high
or None
Bidirectional 8-bit input/output ports
Software instructions determine the CMOS output or
schmitt trigger input with or without a pull-high resistor
(mask option).
Pad No. Pad Name I/O
1, 44~42,
PA0~PA7
37~34
5~2,
41~38
21~28
PB0~PB7
PC0~PC7
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March 15, 2000
HT827A0
Pad No. Pad Name I/O
Mask
Option
Description
Bidirectional 8-bit input/output ports
Software instructions determine the CMOS output or
schmitt trigger input with or without a pull-high resistor
(mask option).
13~20
PD0~PD7
I/O
Pull-high
or None
6
VSS
¾
¾
I/O
Pull-high
or None
Bidirectional 8-bit input/output ports
Software instructions determine the CMOS output or
schmitt trigger input with or without a pull-high resistor
(mask option).
Negative power supply, ground
7~10
PE0~PE3
11
INT
I
¾
External interrupt schmitt trigger input with a
pull-high resistor
Edge triggered is activated on a high to low transition.
12
TMR
I
¾
Schmitt trigger input for a timer/event counter
29
AUD
O
¾
Audio output for driving an external transistor
PMOS open drain output
30
RES
I
¾
Schmitt trigger reset input, active low
31
VDD
¾
¾
Positive power supply
32
33
OSC1
OSC2
I
O
OSC1 and OSC2 connect to an RC network or crystal oscillator (determined by mask option) for an internal sysCrystal or
tem clock. In the case of RC operation, an oscillation
RC
resistor connects to OSC1. OSC2 is the output terminal
of a 1/4 system clock.
Absolute Maximum Ratings
Supply Voltage..............................-0.3V to 5.5V
Storage Temperature.................-50°C to 125°C
Input Voltage .................VSS-0.3V to VDD+0.3V
Operating Temperature ..............-25°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged
exposure to extreme conditions may affect device reliability.
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March 15, 2000
HT827A0
D.C. Characteristics
Symbol
Parameter
VDD
Operating Voltage
IDD1
Operating Current (Crystal OSC)
IDD2
Operating Current (RC OSC)
ISTB1
Standby Current (WDT Enabled)
ISTB2
Standby Current (WDT Disabled)
VIL
Input Low Voltage for I/O Ports
VIH
Input High Voltage for I/O Ports
VIL1
Ta=25°C
Test Conditions
VDD
Conditions
¾
¾
3V
5V
3V
5V
3V
5V
3V
5V
Min.
Typ. Max. Unit
2.4
¾
5.2
V
No load,
fSYS=4MHz
¾
1.5
3
mA
¾
3
5
mA
No load,
fSYS=4MHz
¾
1.5
3
mA
¾
2.5
5
mA
No load,
system Halt
¾
¾
10
mA
¾
¾
20
mA
No load,
system Halt
¾
¾
3
mA
¾
¾
5
mA
3V
¾
0
¾
0.6
V
5V
¾
0
¾
1.0
V
3V
¾
2.4
¾
3
V
5V
¾
4.0
¾
5
V
Input Low Voltage
(RES, TMR, INT)
3V
¾
0
¾
0.6
V
5V
¾
0
¾
1.0
V
VIH1
Input High Voltage
(RES, TMR, INT)
3V
¾
2.4
¾
3
V
5V
¾
4.0
¾
5
V
IOL1
I/O Port Sink Current
(PA, PC, PD, PE)
3V
VOL=0.3V
2
4
¾
mA
5V
VOL=0.5V
6
10
¾
mA
IOH1
I/O Port Source Current
(PA, PC, PD, PE)
3V
VOH=2.7V
-1
-1.5
¾
mA
5V
VOH=4.5V
-2
-4
¾
mA
IOL2
PB Sink Current
3V
VOL=0.3V
6
10
¾
mA
5V
VOL=0.5V
20
25
¾
mA
IOH2
PB Source Current
3V
VOH=2.7V
-0.5
-1
¾
mA
5V
VOH=4.5V
-1
-2
¾
mA
RPH
Pull-high Resistance of I/O Ports
& INT
IO
Max. AUD Output Current
3V
¾
25
50
100
kW
5V
¾
10
30
60
kW
3V
VOH=0.6V
-1.5
-2
¾
mA
5V
VOH=0.6V
-3.5
-4
¾
mA
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March 15, 2000
HT827A0
A.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
Min.
Typ.
Max.
Unit
¾
400
¾
4000
kHz
5V
¾
400
¾
4000
kHz
3V
¾
400
¾
4000
kHz
5V
¾
400
¾
4000
kHz
3V
¾
0
¾
4000
kHz
5V
¾
0
¾
4000
kHz
VDD
Conditions
3V
fSYS1
System Clock (Crystal OSC)
fSYS2
System Clock (RC OSC)
fTIMER
Timer I/P Frequency (TMR)
tWDTOSC
Watchdog Oscillator
5V
¾
31
78
140
ms
tWDT1
Watchdog Timeout Period (RC)
5V
Without WDT
prescaler
8
20
36
ms
tWDT2
Watchdog Timeout Period
(System Clock)
5V
Without WDT
prescaler
¾
1024
¾
tSYS
tRES
External Reset Low Pulse Width
5V
¾
1
¾
¾
ms
tINT
Interrupt Pulse Width
5V
¾
1
¾
¾
ms
Note: tSYS=1/(fSYS)
7
March 15, 2000
HT827A0
Functional Description
gram counter then points to a memory word
containing the next instruction code.
Executive flow
The HT827A0 provides a system clock which is
derived from a crystal or an RC type of oscillator.
The clock is internally divided into four
non-overlapping clocks denoted by P1, P2, P3 and
P4. An instruction cycle consists of T1~T4.
The PC manipulates a program transfer by
loading the address corresponding to each instruction when executing a jump instruction,
conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from
subroutine.
Instruction fetching and execution are
pipelined in such a way that a fetch takes an instruction cycle while decoding and execution
take the next instruction cycle. The pipelining
scheme causes each instruction to execute effectively in a cycle. If an instruction changes
the program counter, two cycles are required to
complete that instruction.
The conditional skip is activated by instructions.
Once the condition is satisfied, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces
it to get a proper instruction. Otherwise, the system will proceed with the next instructions.
The lower byte of the program counter (PCL) is
a readable and writable register (06H). Moving
data into PCL performs a short jump. The destination is within 256 locations.
Program counter - PC
The program counter (PC) controls the sequence in which the instructions stored in the
program ROM are executed.
Once a control transfer takes place, the execution suffers from an additional dummy cycle.
The contents of the program counter are incremented by one after a program memory word is
accessed to fetch an instruction code. The proT 1
S y s te m
O S C 2 (R C
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
C lo c k
o n ly )
P 1
P 2
In te rn a l
P h a s e
C lo c k s
P 3
P 4
P C
P C
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 1
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
P C + 2
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution flow
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March 15, 2000
HT827A0
Program memory - ROM
0 0 0 H
The program memory stores the to-be-executed
program instructions. It also includes data, table and interrupt entries, addressed by the program counter along with the table pointer.
0 0 4 H
D e v ic e in itia liz a tio n p r o g r a m
E x te r n a l in te r r u p t s u b r o u tin e
0 0 8 H
S a m p lin g r a te c o u n te r in te r r u p t s u b r o u tin e
0 0 C H
T im e r /e v e n t c o u n te r in te r r u p t s u b r o u tin e
The program memory size for HT827A0 is
8K´16.
Certain locations in the program memory are
reserved for special usage:
L o o k - u p ta b le ( 2 5 6 w o r d s )
· Location 000H
This area is reserved for program initialization. The program always begins execution at
location 000H each time the system is reset.
L o o k - u p ta b le ( 2 5 6 w o r d s )
1 F F F H
Program memory
· Location 004H
counter overflow, the interrupt is enabled and
the stack is not full.
This area is reserved for an external interrupt
service program. The program begins execution at location 004H if the INT input pin is
activated, the interrupt is enabled and the
stack is not full.
· Location 00CH
This area is reserved for a timer/event counter interrupt service program. The program
begins execution at location 00CH if an interrupt results from a timer/event counter overflow, the interrupt is enabled and the stack is
not full.
· Location 008H
This area is reserved for a voice sampling rate
counter interrupt service program. The program begins execution at location 008H if a
timer interrupt results from a sampling rate
Mode
P ro g ra m
R O M
Program Counter
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial reset
*12 *11 *10
0
0
0
0
0
0
0
0
0
0
0
0
0
External interrupt
0
0
0
0
0
0
0
0
0
0
1
0
0
Sampling rate counter
overflow
0
0
0
0
0
0
0
0
0
1
0
0
0
Timer/event counter
overflow
0
0
0
0
0
0
0
0
0
1
1
0
0
Skip
PC+2
Loading PCL
*12 *11 *10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, call branch
#12 #11 #10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from subroutine
S12 S11 S10 S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program counter
Note:
*12~*0: Bits of program counter
S12~S0: Bits of stack register
#12~#0: Bits of instruction code
@7~@0: Bits of PCL
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March 15, 2000
HT827A0
· Table location
The interrupt request flag will be recorded but
the acknowledgment will be inhibited when the
stack is full and a non-masked interrupt takes
place. After the stack pointer is decremented
(by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow and
allows programmers to use the structure more
easily. In a similar case, if the stack is full and a
²CALL² is subsequently executed, stack overflow occurs and the first entry is lost.
Any location in the program ROM can be used
a s a l ook - up t a b l e. T he i ns t r u c t i o n s
²TABRDC [m]² (the current page, 1 page=256
words) and ²TABRDL [m]² (the last page)
transfer the contents of the lower-order byte
to the specified data memory, and the
higher-order byte to TBLH (08H). Only the
destination of the lower-order byte in the table is well-defined. The other bits of the table
word are transferred to the lower portion of
TBLH. The higher-order byte register
(TBLH) of the table is read only. The table
pointer (TBLP), on the other hand, is a
read/write register (07H) indicating the table
location. This location must be placed in
TBLP before accessing the table. All the table
related instructions require 2 cycles to complete an operation. These areas may function
as a normal program memory depending
upon the user¢s requirements.
Data memory - RAM
The data memory is further divided into two
functional groups, namely, special function registers and general purpose data memories. Although most of them can be read or be written
to, some are read only.
The data memory size for HT827A0 is shown as
follows.
Stack register - Stack
The stack register is a special part of the memory used to save the contents of the program
counter (PC). This stack is organized into 8 levels. It is neither part of the data nor program
space, and cannot be read or written to. Its activated level is indexed by a stack pointer (SP)
and cannot be read or written to. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto
the stack. The program counter is restored to
its previous value from the stack at the end of a
subroutine or interrupt routine, which is signaled by a return instruction (RET or RETI).
After a chip resets, SP will point to the top of
the stack.
Instruction(s)
Pard No.
Special
RAM
General
RAM Address
HT827A0
00H~2FH
30H~FFH
The special function registers include an indirect addressing register (00H), timer/event
counter high byte register (TMRH; 0FH),
timer/event counter low byte register (TMRL;
10H); timer/event counter control register
(TMRC; 11H), program counter lower-order
byte register (PCL; 06H), memory pointer register (MP; 01H), accumulator (ACC; 05H), table
pointer (TBLP; 07H), table higher-order byte
register (TBLH; 08H), status register
(STATUS; 0AH), interrupt control register
(INTC; 0BH), watchdog timer option setting
register (WDTS; 09H), I/O registers (PA; 12H,
PB; 14H, PC; 16H, PD; 18H, PE; 1AH) and I/O
Table Location
*12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P12
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table location
Note:
*12~*0: Bits of table location
P12~P8: Bits of current program counter
@7~@0: Bits of table pointer
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March 15, 2000
HT827A0
0 0 H
In d ir e c t A d d r e s s in g R e g is te r
0 1 H
M P
control registers (PAC; 13H, PBC; 15H, PCC;
17H, PDC; 19H, PEC; 1BH). The 20H to 2FH
are used for sound and tone (melody) synthesis.
The function registers include a lower-order
byte register (DAL; 20H) of D/A data,
higher-order byte register (DAH;21H) of D/A
data , volume control register (VCR; 22H), sampling rate control register (SRC; 23H), beat control register (BEAT; 28H), tempo control
register (TEMPO; 29H), tone control register
(TONE; 2AH) and voice ROM control register
(ROMC; 2CH). The remaining space before 30H
is reserved for future expansion. Reading these
remaining locations will get ²00H². The general
purpose data memory is used for data and control information under instruction commands.
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
A C C
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
0 A H
S T A T U S
0 B H
IN T C
W D T S
0 C H
0 D H
0 E H
0 F H
T M R H
1 0 H
T M R L
1 1 H
T M R C
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
1 8 H
P D
1 9 H
P D C
1 A H
P E
1 B H
P E C
All of the areas of data memory can handle
arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be
set and reset by ²SET [m].i² and ²CLR [m].i²,
and can also be indirectly accessed through a
memory pointer register (MP; 01H).
S p e c ia l P u r p o s e
D A T A M E M O R Y
: U n u s e d
R e a d a s "0 0 "
Indirect addressing register
1 C H
1 D H
Location 00H is an indirect addressing register
that is not physically implemented. Any
read/write operation of [00H] accesses the data
memory pointed to by MP (01H). Indirectly reading location 00H will return the result to 00H
whereas, indirectly writing it will have no effect.
1 E H
1 F H
2 0 H
D A L
2 1 H
D A H
2 2 H
2 3 H
2 4 H
V C R
S R C
2 5 H
Arithmetic and logic unit - ALU
2 6 H
2 7 H
2 8 H
B E A T
2 9 H
T E M P O
2 A H
T O N E
2 B H
2 C H
R O M C
This circuit performs 8-bit arithmetic and logic
operations. ALU provides the following functions:
· Arithmetic operations (ADD, ADC, SUB,
SBC, DAA)
2 D H
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
2 E H
2 F H
3 0 H
· Increment & decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
G e n e ra l P u rp o s e
D A T A M E M O R Y
ALU not only saves the results of a data operation but also change the status register.
F F H
RAM mapping
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March 15, 2000
HT827A0
Status register - STATUS
Interrupt
This 8-bit register (0AH) consists of a zero flag
(Z), carry flag (C), auxiliary carry flag (AC),
overflow flag (OV), power down flag (PD) and
watchdog time-out flag (TO). It also records the
status information and controls the operation
sequence.
Except the TO and PD flags, bits in the status
register can be altered by instructions similar to
other registers. Any data written into the status
register will not change the TO or PD flag. Operations related to the status register may yield different results from those intended. The TO and
PD flags can be altered only by a watchdog timer
overflow, chip power-up, clearing the watchdog
time or executing the ²HALT² instruction.
The Z, OV, AC and C flags generally reflect the
statuses of the latest operations.
The status register will not be pushed onto the
stack automatically on entering the interrupt
sequence or executing the subroutine call. If the
status contents are important and the subroutine may corrupt the status register, the programmer must take precautions and save it
properly.
The HT827A0 provides an external interrupt in
addition to two internal timer/event counter interrupts. The interrupt control register (INTC;
0BH) includes interrupt control bits to set the
enable/disable and the interrupt request flags.
Once an interrupt subroutine is serviced, all
the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any
further interrupt nesting. Other interrupt requests may happen during this interval but
only the interrupt request flag is recorded. If
an interrupt needs servicing within the service routine, the programmer may set the EMI
bit and the corresponding bit of INTC, allowing interrupt nesting. If the stack is full, the
interrupt request will not be acknowledged till
the SP is decremented, whether or not the related interrupt is enabled. If immediate service is desired, the stack has to be prevented
from becoming full.
All these interrupts have a wakeup capability.
As an interrupt is serviced, a control transfer
occurs by pushing the program counter onto the
Labels
Bits
Function
C
0
C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. It
is also affected by a rotate through carry instruction.
AC
1
AC is set if the operation results in a carry out of the low nibbles in addition or if
no borrow from the high nibble into the low nibble in subtraction takes place;
otherwise AC is cleared.
Z
2
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is
cleared.
OV
3
OV is set if an operation results in a carry into the highest-order bit but not a
carry out of the highest-order bit, or vice versa, otherwise OV is cleared.
PD
4
PD is cleared by a system power-up or executing the ²CLR WDT² instruction.
PD is set by executing the ²HALT² instruction.
TO
5
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instructions. TO is set by a WDT time-out.
¾
6
Undefined, read as ²0²
¾
7
Undefined, read as ²0²
STATUS register
12
March 15, 2000
HT827A0
The internal timer/event counter interrupt is
initialized by setting a timer/event counter interrupt request flag (TF; bit 6 of INTC), which
is caused by a timer overflow. When an interrupt is enabled, the stack is not full and the TF
bit is set, a subroutine call to location 0CH will
occur. The related interrupt request flag (TF)
will be reset and the EMI bit will be cleared to
disable further interrupts.
stack and then branching to subroutines at the
specified location(s) in the program memory.
Only the program counter is pushed onto the
stack. The programmer must save the contents
of the register or status register (STATUS) in
advance if they are altered by an interrupt service program which corrupts the desired control sequence.
External interrupts are triggered by a high to
low transition of INT. The related interrupt request flag (EIF; bit 4 of INTC) are also set.
When an interrupt is enabled, the stack is not
full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be
cleared to disable other interrupts.
During the execution of an interrupt subroutine, other interrupt acknowledgments are all
held until the ²RETI² instruction is executed or
the EMI bit and the related interrupt control
bit are set to 1 (if the stack is not full). To return
from an interrupt subroutine, ²RET² or ²RETI²
may be invoked. RETI will set the EMI bit to
enable an interrupt service, but RET will not.
The sampling rate counter interrupt is initialized by setting a sampling rate counter interrupt request flag (SRF; bit 5 of INTC), which is
caused by a timer overflow. When an interrupt
is enabled, the stack is not full and the SRF bit
is set, a subroutine call to location 08H will occur. The related interrupt request flag (SRF)
will be reset and the EMI bit be cleared to disable further interrupts.
Register
INTC
(0BH)
Interrupts occurring in an interval between the
rising edges of two consecutive T2 pulses will be
serviced at the latter of the two T2 pulses if the
corresponding interrupts are enabled. In the
case of simultaneous requests, they can be
masked by resetting the EMI bit. The following
table illustrates the priority of applying the simultaneous requests:
Bit No.
Label
Function
0
EMI
Controls a master (global) interrupt
(1=enabled; 0=disabled)
1
EEI
Controls an external interrupt
(1=enabled; 0=disabled)
2
ESI
Controls a sampling rate counter interrupt
(1=enabled; 0=disabled)
3
ETI
Controls a timer/event counter interrupt
(1=enabled; 0=disabled)
4
EIF
External interrupt request flag
(1=active; 0=inactive)
5
SRF
Sampling rate counter request flag
(1=active; 0=inactive)
6
TF
Internal timer/event counter request flag
(1=active; 0=inactive)
7
¾
Unused bit, read as ²0²
INTC register
13
March 15, 2000
HT827A0
No.
Interrupt
Source
a
External Interrupt
1
04H
b
Sampling Rate
Counter Overflow
2
08H
c
Timer/Event
Counter Overflow
3
0CH
Priority Vector
O S C 1
O S C 1
fS
O S C 2
Y S
/4
O S C 2
R C
C r y s ta l O s c illa to r
O s c illa to r
System oscillator
The timer/event counter interrupt request flag
(TF), external interrupt request flag (EIF), sampling rate counter interrupt request flag (SRF),
enable timer/event counter bit (ETI), enable external interrupt bit (EEI), enable sampling rate
counter bit (ESI) and enable master interrupt bit
(EMI) make up an interrupt control register
(INTC) which is located at 0BH in the data memory. EMI, EEI, ESI and ETI are used to control
the enable/disable status of interrupts. These bits
prevent the requested interrupt from being serviced. Once the interrupt request flags (TF, SRF,
EIF) are all set, they will remain in the INTC register till the interrupts are serviced or cleared by
a software instruction.
frequency of the oscillation may vary with
VDD, temperature and the chip itself due to
process variations. It is, therefore, not suitable
for timing sensitive operations where an accurate oscillator frequency is demanded.
On the other hand, if a crystal type of oscillator
is used instead, a crystal across OSC1 and OSC2
is required, providing feedback and phase shift
for the oscillator. No other external components
are needed. The resonator can replace the crystal and connects between OSC1 and OSC2 so
that a frequency reference can be derived. But
two external capacitors in OSC1 and OSC2 are
required.
The ²CALL subroutine² is preferably not used
within the interrupt subroutine. This is because
interrupts often occur in an unpredictable manner or required to be serviced immediately in certain applications. If only one stack is left and
enabling the interrupt is not well controlled, operation of the ²call² in the interrupt subroutine
will damage the original control sequence.
The WDT oscillator is a free running on-chip RC
oscillator, requiring no external components. The
WDT oscillator still works a period of approximately 78ms even when the system enters the
power down mode and the system clock is terminated. It nonetheless can be disabled by mask option for conserving power.
Oscillator configuration
The clock source of WDT is implemented by a
dedicated RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4), decided by mask option. The watchdog timer is
designed to prevent a software malfunction or
sequence jumping to an unknown location with
unpredictable results. It can be disabled by
mask option. After it is disabled, all executions
related to WDT are ignored.
Watchdog timer - WDT
The HT827A0 provides two kinds of oscillator circuits, namely, RC and crystal oscillators, for system clocks. Selection of the oscillator circuit
type is determined by mask option. When the
device enters the HALT mode, the system oscillator stops to conserve power. The system clock
is later reset with an external signal.
If an RC type of oscillator is used, an external
resistor between OSC1 and GND is required
and the range of the resistance has to be from
51kW to 1MW. The system, divided by 4, is
available on OSC2, which synchronizes external logic. The RC type of oscillator provides the
most cost-effective solution. Nonetheless, the
WDT is first divided by 256 (8 stages) to get a
nominal time-out period of 20 ms once an internal WDT oscillator (RC type of oscillator normally with a period of 78ms) is selected. This
time-out period may vary with temperature,
VDD and process variations. By invoking the
14
March 15, 2000
HT827A0
To clear the contents of WDT (including the
WDT prescaler), three methods are adopted,
namely, external reset (a low level to RES),
software instructions, and ²HALT² instruction.
The software instructions include ²CLR WDT²
and the other sets - ²CLR WDT1² and ²CLR
WDT2². Of these two types of instructions, by
mask option only one can be active at a time ²CLR WDT times selection option². If ²CLR
WDT² is chosen (i.e., CLRWDT times equal
one), any execution of the ²CLR WDT² instruction will clear WDT. In the case that ²CLR
WDT1² and ²CLR WDT2² are selected (i.e.,
CLRWDT times equal two), these two instructions must be executed to clear WDT; otherwise
WDT may reset the chip as a result of time-out.
WDT prescaler, a longer time-out period can be
attained. Writing data to WS2, WS1 and WS0
(bits 2, 1 and 0 of WDTS) can derive different
time-out periods. If WS2, WS1 and WS0 are all
equal to 1, the division ratio is up to 1:128, and
the maximum time-out period is 2.6 seconds.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
Power down operation - HALT
The HALT mode is initialized by the ²HALT²
instruction and results in the following:
WDTS register
If the WDT oscillator is disabled, the WDT clock
may still come from an instruction clock. It operates in the same manner except that WDT may
stop counting and loses its protecting purpose in
the HALT state. In this situation the logic can
only be re-initialized by external logic. The high
nibble and bit 3 of WDTS are reserved for user¢s
defined flags. The programmer may use these
flags to indicate some specified statuses.
· The system oscillator is turned off but the
·
·
·
The on-chip RC oscillator (WDT OSC) is
strongly recommended if the device operates in
a noisy environment, since the HALT function
will stop the system clock.
·
The system can quit the HALT mode by an external reset, interrupt, external falling edge signal
on port A or WDT overflow. An external reset
leads to device initialization and a WDT overflow
performs a ²warm reset². The reason for chip re-
Overflow of the WDT under a normal operation
initializes a ²chip reset² and sets the status bit
²TO². It will initialize a ²warm reset², and only
PC and SP are reset to zero in the HALT mode.
S y s te m
WDT oscillator still keeps running (if the
WDT oscillator is selected).
The contents of the on-chip RAM and registers remain unchanged.
The WDT and WDT prescaler are cleared and
re-counted (if the clock of WDT is from the
WDT oscillator).
All the I/O ports maintain their original
statuses.
The PD flag is set and the TO flag cleared.
C lo c k /4
W D T
O S C
M a s k
O p tio n
S e le c tio n
W D T P r e s c a le r
8 - b it C o u n te r
7 - b it C o u n te r
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog timer
15
March 15, 2000
HT827A0
their original states. Some registers will remain unchanged during reset conditions. Most
registers are reset to the ²initial condition² once
the reset conditions are met. The program can
distinguish between different ²chip resets² by
examining the PD flag and TO flag.
set can then be determined after examining the
TO and PD flags. The PD flag is cleared when the
system powers up or executes the ²CLR WDT² instruction and set when the ²HALT² instruction is
executed. The TO flag is set if the WDT time-out
occurs, and causes a wake-up that resets only the
PC and SP. The others maintain their original
statuses.
TO PD
The port A wake-up and interrupt methods can
be considered as a continuation of normal execution. Each bit in port A can be independently
selected to wake up the device by mask option.
Awakening from an I/O port stimulus, the program resumes execution of the next instruction. However, if it is awakening from an
interrupt, two sequences may happen. The program will resume execution at the next instruction if the related interrupt is disabled or the it
is enabled but the stack is full. Nonetheless, if
the interrupt is enabled and the stack is not
full, a regular interrupt response takes place.
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal
operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal
operation
1
1
WDT wake-up HALT
Note: ²u² means ²unchanged²
To guarantee that the crystal oscillator is
started and stabilized, XST (Crystal Start-up
Timer) provides an extra-delay by an OSC
mask option. The extra-delay delays 1024 system clock pulses when the system awakes from
the HALT state or from system power-up and
the RES transforms low to high. XST is automatically selected if the crystal oscillator is invoked. On the other hand, it is disabled when
the RC oscillator is chosen. The XST delay is
added after XST is chosen and awakening from
the HALT state or the system powers up.
Once the wake-up event occurs, and the system
clock comes from a crystal, it takes 1024 tSYS
(system clock period) to resume a normal operation. In other words, the HT827A0 will insert a
dummy period after the wake-up. If the system
clock, on the other hand, is from an RC type of
oscillator, it will continue operation. The actual
interrupt subroutine execution will be delayed
by one or more cycles if the wake-up results
from an interrupt acknowledgment. On the
other hand, it will be executed immediately after the dummy period is finished if the wake-up
results in the next instruction execution.
The reset duration comes only from RES if an
RC oscillator is selected. An extra delay, on the
other hand, is added during the power-up period and any wakeup from HALT only if a crystal oscillator is chosen instead.
To minimize power consumption, all the I/O
pins should be carefully managed before entering the HALT mode.
The HT827A0 provides another useful feature for
purposes of testing and synchronization. Releasing RES high will start execution if RES
keeps low long enough.
Reset
There are three ways in which a reset can occur:
· RES reset during normal operation
· RES reset during HALT
· WDT time-out reset during a normal operation
The WDT time-out during HALT is different
from other chip reset conditions, since it can
perform a ²warm reset² that resets only the PC
and SP, leaving the other circuits to remain in
16
March 15, 2000
HT827A0
The chip reset status are shown below:
PC
Code
Volume
Code
Volume
0000H
0000 xxxx
1/16
1000 xxxx
9/16
Interrupt
Disabled
Prescaler
Cleared
0001 xxxx
2/16
1001 xxxx
10/16
0010 xxxx
3/16
1010 xxxx
11/16
WDT
Cleared. After a
master reset, WDT
begins counting.
0011 xxxx
4/16
1011 xxxx
12/16
0100 xxxx
5/16
1100 xxxx
13/16
Timer/Event Counter
Off
0101 xxxx
6/16
1101 xxxx
14/16
Input/Output Ports
Input mode
0110 xxxx
7/16
1110 xxxx
15/16
SP
Point to the top of
the stack.
0111 xxxx
8/16
1111 xxxx
16/16
V
Volume level table
D D
Note: ²xx² means don¢t care
R E S
Reset circuit
Audio output and volume control
The HT827A0 provides a current type D/A output for driving external 8W speaker through an
external NPN transistor. The user must write
the voice data to the register DAL (20H) and
DAH (21H). Only 12 bits which include the high
nibble of DAL and the whole byte of DAH are
used. For the current type D/A output the high
nibble data of DAL must be written at first, and
then the DAH data is written.
There are 16 steps of volume controllable level
that are provided for the current type D/A output. The user only writes the volume control
data to the VCR register (22H). Only the high
nibble of VCR are used. Note that writing 0H to
the high nibble of VCR doesn¢t denote mute output. When bit 7 (SRON) of the TEMPO register
(29H) is set as ²1² the change of volume level is
valid. The following is a table of the 16 kinds of
volume level:
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March 15, 2000
HT827A0
The states of the registers are summarized in the following table:
WDT Time-out
(Normal
Operation)
WDT
Time-out
(HALT)*
RES Reset
(Normal
Operation)
RES Reset
(HALT)
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
00-0 1---
00-0 1---
uu-u u---
Register
Reset
(Power On)
TMRH
xxxx xxxx
TMRL
xxxx xxxx
uuuu uuuu
TMRC
00-0 1---
00-0 1---
PC
0000H
0000H
0000H
0000H
0000H
MP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PD
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PDC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PE
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
PEC
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
DAL
0000 ----
0000 ----
0000 ----
0000 ----
0000 ----
DAH
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
VCR
0000 ----
0000 ----
0000 ----
0000 ----
0000 ----
SRC
--xx xxxx
--uu uuuu
--uu uuuu
--uu uuuu
--uu uuuu
BEAT
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TEMPO
00-- xxxx
00-- uuuu
00-- uuuu
00-- uuuu
00-- uuuu
TONE
0-xx xxxx
0-uu uuuu
0-uu uuuu
0-uu uuuu
0-uu uuuu
Note: ²*² means ²warm reset²
²u² means ²unchanged²
²x² means ²unknown²
18
March 15, 2000
HT827A0
Sampling rate counter
Code
The HT827A0 offers a sampling rate counter.
This counter contains a 5 bit programmable
count-up counter. The clock may come from
128kHz or 2kHz by code option and the clock
base on 3.579545MHz system clock.
Code
Freq.
xx00 1010 5.08kHz
xx01 0111 12.43kHz
xx00 1011 5.33kHz
xx01 1000 13.98kHz
xx00 1100 5.59kHz
xx01 1001 15.98kHz
Sampling rate table
Labels
Bit
s
SR0~
SR4
To define a voice sampling
0~4
rate or envelope decaying time
2K/
128K
5
¾
Freq.
Function
Note: ²xx² means don¢t care
On the other hand, when the 2kHz clock is chosen, 32 kinds of time periods of the envelope decay is offered.
To define an input clock
source (0=128K; 1=2K)
The following is a table of the envelope decay:
6~7 Unused bits, read as ²0²
Code
SRC register
Freq.
Code
Freq.
xx10 0000 54.6Hz
xx11 0000
109.3Hz
xx10 0001 56.4Hz
xx11 0001
116.5Hz
D A T A
B U S
xx10 0010 58.3Hz
xx11 0010
124.9Hz
R E L O A D
xx10 0011 60.3Hz
xx11 0011
134.5Hz
xx10 0100 62.4Hz
xx11 0100
145.7Hz
xx10 0101 64.7Hz
xx11 0101
158.9Hz
xx10 0110 67.2Hz
xx11 0110
174.8Hz
xx10 0111 69.9Hz
xx11 0111
194.2Hz
xx10 1000 72.8Hz
xx11 1000
218.5Hz
xx10 1001 76.0Hz
xx11 1001
249.7Hz
xx10 1010 79.5Hz
xx11 1010
291.3Hz
Freq.
xx10 1011 83.2Hz
xx11 1011
349.6Hz
xx00 0000 3.50kHz
xx00 1101 5.89kHz
xx10 1100 87.4Hz
xx11 1100
437.0Hz
xx00 0001 3.61kHz
xx00 1110 6.21kHz
xx10 1101 92.0Hz
xx11 1101
582.7Hz
xx00 0010 3.72kHz
xx00 1111 6.58kHz
xx10 1110 97.1Hz
xx11 1110
874.0Hz
xx00 0011 3.86kHz
xx01 0000 6.99kHz
xx10 1111 102.8Hz xx11 1111
1.75kHz
xx00 0100 3.99kHz
xx01 0001 7.46kHz
Envelope decay table
xx00 0101 4.14kHz
xx01 0010 7.99kHz
xx00 0110 4.30kHz
xx01 0011 8.61kHz
xx00 0111 4.48kHz
xx01 0100 9.32kHz
xx00 1000 4.66kHz
xx01 0101 10.17kHz
xx00 1001 4.86kHz
xx01 0110 11.19kHz
1 2 8 K
S a m p lin g R a te
C o u n te r
P r e lo a d R e g is te r
2 K
2 K /1 2 8 K
S R O N
S a m p lin g R a te
C o u n te r
¸ 1
C o u n te r
O V E R F L O W
to In te rru p t
Sample rate counter
When the 128kHz clock is selected, 26 kinds of
sampling rate are provided for a voice synthesizer. The following is a table of the 26 kinds of
sampling rates:
Code
Freq.
Code
Note: ²xx² means don¢t care
19
March 15, 2000
HT827A0
The clock is blocked to avoid errors once the
sampling rate counter is read. The programmer
should take the counting error into account
since blocking of the clock may result in a
counting error.
One of the relative counter values is preloaded
to the sampling rate counter after a code is
written to the counter (SRC; 23H). Once the
sampling rate counter starts counting, it will
count from its current contents to 1FH. The
counter is reloaded from the sampling rate
counter preload register, and generates an interrupt request flag (SRF; bit 5 of INTC) if overflow of the divide-by-1 counter occurs.
Timer/event counter
The HT827A0 provides a timer/event counter.
This timer contains an 8-bit/16-bit programmable count-up counter. The clock may come from
an external source or from the system clock divided by 4. Only one reference time-base is available when an internal instruction clock is
selected. The external clock input allows the
user to count external events, measure time intervals or pulse widths, or generate an accurate
time base.
To enable a counting operation, the ON bit
(SRON; bit 7 of TEMPO) of the counter should
be set to 1. Overflow of the sampling rate counter is one of the wake-up sources. Writing a ²0²
to ESI will disable the interrupt service.
Writing data to the sampling rate preload register will also reload the data to the sampling
rate counter in the case of 1F condition of the
sampling rate counter. On the other hand, data
written to the sampling rate counter will be
kept only in the counter preload register if the
counter is turned on. The sampling rate counter
still goes on working till an overflow of the divide-by-1 counter occurs.
S y s te m
For the 16-bit timer/event counter, there are
three registers related to the timer/event counter,
namely, TMRH ([0FH]), TMRL ([10H]) and
TMRC ([11H]). Three physical registers are
mapped to the TMR location. Writing TMRL only
writes the data into a low byte buffer, and writing
D A T A B U S
C lo c k /4
T M 1
T M 0
T M R 0
T M R 1
T im e r /e v e n t C o u n te r
P r e lo a d R e g is te r
R E L O A D
T E
T im e r /e v e n t
C o u n te r
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
T M 1
T M 0
T O N
O V E R F L O W
T o In te rru p t
L o w B y te
B u ffe r
16-bit Timer/event counter
S y s te m
C lo c k /4
T M R
D A T A B U S
T M 1
T M 0
T im e r /e v e n t C o u n te r
P r e lo a d R e g is te r
R E L O A D
T E
T M 1
T M 0
T O N
T im e r /e v e n t
C o u n te r
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O V E R F L O W
T o In te rru p t
8-bit Timer/event counter
20
March 15, 2000
HT827A0
cycle can be measured till TON is set. The cycle
measurement will go on functioning as long as
further transient pulses are received. In this
operation mode, the timer/event counter starts
counting not according to the logic level but to
the transient edges. In the case of a counter
overflow, the counter is reloaded from the
timer/event counter preload register and issues
an interrupt request, like the other two modes.
TMRH will write the data and the content of the
low byte buffer into the timer/event counter
preload register (16-bit) simultaneously. The
timer/event counter preload register is changed
by writing TMRH operations and writing TMRL
will keep the timer/event counter preload register
unchanged.
Reading TMRH will also latch the TMRL into
the low byte buffer to avoid the false timing
problem. Reading TMRL returns the content of
the low byte buffer. In other words, the low byte
of the timer/event counter can not be read directly. It must read the TMRH first to make the
low byte content of the timer/event counter
latched into the buffer.
The timer ON bit (TON; bit 4 of TMRC) should
be set to 1 to enable a counting operation. In the
pulse width measurement mode, TON will be
cleared automatically after the measurement
cycle is completed. In the other two modes,
TON can be reset only by instructions. The
overflow of the timer/event counter is one of the
wake-up sources. Writing a ²0² to ETI will disable the interrupt service no matter what kind
of operation mode is chosen.
For the 8-bit timer/event counter, TMRH is undefined. Writing TMRL makes the starting value be
placed in the timer/event counter preload register
and reading it gets the contents of the
timer/event counter. TMRC is a timer/event
counter control register which defines some options.
In the case of the timer/event counter OFF condition, writing data to the timer/event counter
preload register will also reload it to the
timer/event counter. Data written to the
timer/event counter will however be kept in the
timer/event counter preload register if the
timer/event counter is turned on. It will keep on
operating till an overflow occurs.
The TM0 and TM1 bits define the operation
mode. The event counting mode counts external
events, indicating that the source of the clock is
from an external (TMR) pin. The timer mode
functions as a normal timer with the clock
source coming from an instruction clock. The
pulse width measurement mode can be used to
count a high to low level duration of an external
signal (TMR). This counting is based on the instruction clock.
The clock will be blocked to avoid errors when
the timer/event counter (reading TMR) is read.
The programmer should take the counting error into account since clock blocking may result
in a counting error.
In the event counting or timer mode, after the
timer/event counter starts counting, it will count
from its current contents to FFFFH for 16-bit
timer/event counter or FFH for 8-bit timer/event
counter. Once an overflow occurs, the counter is
reloaded from the timer/event counter preload
register and generates an interrupt request flag
(TF; bit 6 of INTC).
In the pulse width measurement mode with the
TON and TE bits equal to one, after TMR transition from low to high (or high to low when the
TE bit is ²0²), it will start counting till it returns
to the original level and resets the TON. The
m e a s ur ed r es ul t s t i l l r em a i ns i n t h e
timer/event counter even when the activated
transition re-occurs. In other words, only one
21
March 15, 2000
HT827A0
Labels (TMRC)
Bits
Function
¾
0~2
TE
3
To define the TMR active edge of a timer/event counter
(0=active on low to high; 1=active on high to low)
TON
4
To enable/disable timer counting (0=disabled; 1=enabled)
¾
5
Unused bits, read as ²0²
6
7
To define the operation mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TM0
TM1
Unused bits, read as ²0²
TMRC register
Tone and melody generator
D A T A B U S
The HT827A0 provides a tone frequency register
(TONE; 2AH), beat frequency register (BEAT;
28H) as well as tempo frequency register
(TEMPO; 29H) for generating melody and sound
effects.
T o n e R e g is te r
T o n e F re q u e n c y
P L A T a b le
The chip can generate four octaves, labeled
from C2# to C6. Desired frequencies can be obtained by first writing the related data into a
tone frequency register (TONE; 2AH) and then
enabling the tone counter. A Tone frequency is
generated and remained if the tone counter
overflows.
Labels
Bits
Function
TN0~
TN3
0~3
To define the tone frequency
(refer to the tone frequency
table)
OCT0
OCT1
4
5
To define the 4 octave tone
frequencies (refer to the
tone frequency table)
¾
6
Unused bit, read as ²0²
7
To enable/disable the tone
counter
(0= disabled; 1= enabled)
TEN
1 2 8 k H z
T E N
T o n e C o u n te r
T o n e F re q u e n c y
TONE counter
The BEAT register counts melody beats. Bit 7
(BTO) of the BEAT register is set when the beat
counter overflows. No interrupt is generated if
the beat counter overflows. So bit 7 (BTO) of the
BEAT register must be polled to generate correct
beat frequencies. After reading the BTO status,
the bit 7 should be cleared by the programmer to
avoid malfunction of the next polling.
Labels Bits
B0~B6
BTO
TONE register
0~6
7
Function
To define the beat frequency
(refer to the beat frequency
table)
BTO is set during beat
counter time-out
BEAT register
22
March 15, 2000
HT827A0
Code
1x00 0000
Frequency
Tone
¾
¾
Code
1x10 0000
#
Frequency
Tone
¾
¾
#
1x10 0001
553.8Hz
C4
D2
1x10 0010
585.7Hz
D4
1x00 0001
138.5Hz
C2
1x00 0010
146.4Hz
#
#
1x00 0011
155.4Hz
D2
1x10 0011
621.5Hz
D4
1x00 0100
164.5Hz
E2
1x10 0100
658.1Hz
E4
1x00 0101
174.8Hz
F2
1x10 0101
699.2Hz
F4
1x00 0110
185.2Hz
F2
1x10 0110
740.9Hz
F4
1x00 0111
195.6Hz
G2
1x10 0111
782.3Hz
G4
207.2Hz
#
G2
1x10 1000
828.7Hz
G4
#
1x00 1000
#
#
#
1x00 1001
220.2Hz
A2
1x10 1001
880.9Hz
A4
1x00 1010
233.1Hz
A2
1x10 1010
932.3Hz
A4
1x00 1011
247.5Hz
B2
1x10 1011
990.0Hz
B4
1x00 1100
261.4Hz
C3
1x10 1100
1045.6Hz
C5
#
1x00 1101
¾
¾
1x10 1101
¾
¾
1x00 1110
¾
¾
1x10 1110
¾
¾
1x00 1111
¾
¾
1x10 1111
¾
¾
¾
¾
1x01 0000
1x11 0000
¾
¾
1x11 0001
1107.7Hz
C5
D3
1x11 0010
1171.5Hz
D5
#
1x01 0001
279.6Hz
C3
1x01 0010
292.9Hz
#
#
#
1x01 0011
310.8Hz
D3
1x11 0011
1243.1Hz
D5
1x01 0100
329.0Hz
E3
1x11 0100
1316.2Hz
E5
1x01 0101
349.6Hz
F3
1x11 0101
1398.4Hz
F5
1x01 0110
370.4Hz
F3
1x11 0110
1481.8Hz
F5
1x01 0111
391.2Hz
G3
1x11 0111
1564.7Hz
G5
414.4Hz
#
G3
1x11 1000
1657.4Hz
G5
#
1x01 1000
#
#
#
1x01 1001
440.5Hz
A3
1x11 1001
1761.8Hz
A5
1x01 1010
466.1Hz
A3
1x11 1010
1864.6Hz
A5
1x01 1011
495.0Hz
B3
1x11 1011
1980.1Hz
B5
1x01 1100
522.8Hz
C4
1x11 1100
2091.1Hz
C6
#
1x01 1101
¾
¾
1x11 1101
¾
¾
1x01 1110
¾
¾
1x11 1110
¾
¾
1x01 1111
¾
¾
1x11 1111
¾
¾
TONE frequency table
Note: ²x² means don¢t care
²¾² means invalid
23
March 15, 2000
HT827A0
Code
Beat
1xxx xxxx
Beat time-out
0000 0000
1/24 Beat
0000 0010
1/8 Beat
0000 0011
1/6 Beat
0000 0101
1/4 Beat
0000 0111
1/3 Beat
0000 1011
1/2 Beat
0000 1111
2/3 Beat
0001 0001
3/4 Beat
0001 0111
1 Beat
0010 0011
3/2 Beat
0010 1111
2 Beats
0100 0100
3 Beats
0101 1111
4 Beats
0111 0111
5 Beats
Other codes
¾
Labels Bits
TN0~
TN3
Function
To define the tempo frequency
0~3 (refer to the tempo frequency
table)
¾
4,5
TMPEN
6
To enable/disable the tempo
counter (0=disabled;
1=enabled)
7
To enable/disable the D/A
output, sampling rate
counter and voice ROM
(0=disabled; 1=enabled)
SRON
Unused bits, read as ²0²
TEMPO register
Code
TEMPO CLK
TEMPO BPM
0000
30.5Hz
68.3
0001
32.55Hz
72.8
0010
34.88Hz
78.0
0011
37.56Hz
84.0
0100
40.69Hz
91.0
0101
44.39Hz
99.3
0110
48.83Hz
109.3
0111
54.25Hz
121.4
1000
61Hz
136.6
1001
65.1Hz
145.7
1010
69.8Hz
156.1
1011
75.12Hz
168.1
1100
81.38Hz
182.1
BEAT counter
1101
88.78Hz
198.6
The TEMPO register counts melodies. A tempo
frequency is generated after tempo data are
loaded and the TEMPO counter is also enabled.
The tempo determines the beat time period.
When the SRON bit of TEMPO register be clear
as ²0², the ²TMPEN¬0² is automatic occur at
the same time. That is to say, if SRON=0,
TMPEN always equals ²0².
1110
97.66Hz
218.5
1111
108.5Hz
242.8
BEAT frequency table
Note: ²¾² means unknown beats
D A T A B U S
B e a t fre q u e n c y
ta b le P L A
2 k H z
T E N
B e a t c o u n te r
S e t th e B T O
TEMPO frequency table
24
March 15, 2000
HT827A0
starting address of the sound data to be read is
0CF0H, the program of reading one byte of
sound or tone (melody) data is as follows:
Voice ROM
The HT827A0 includes a ROM for storing
sound and tone (melody) data. Coded data can
be saved in an internal mask ROM by changing
one layer of the mask after the sound and tone
(melody) sources are coded by Holtek¢s tools.
The voice ROM size for HT827A0 is 128K´8.
Read-New-Data:
SET
MOV A, 00H
MOV [ROMC], A;
The handshaking between the microcontroller
and voice ROM is through a ROM control register
(ROMC; 2CH). To enable the voice ROM, the bit 7
of the TEMPO register should be set as ²1². The
related ROM address has to be saved in the ROM
control register first if the microcontroller attempts to read the sound or tone (melody) data in
the mask ROM. The ROM is comprised by a set of
address counters internally. After the
microcontroller finishes reading a byte of data, its
internal address counter will automatically be increased by one. In this case, reading continuous
data only requires loading the starting address to
the ROM control register.
A d d re s s
C o u n te r
R O M C
A d d re s s
C o u n te r
A d d re s s
C o u n te r
W R
A d d re s s
C o u n te r
R D
Write the first nibble
address
MOV A,0FH
MOV[ROMC], A;
Write the second
nibble address
MOV A, 0CH
MOV [ROMC], A;
Write the third
nibble address
MOV A, 00H
The lower-order nibble is valid whereas the
higher-order nibble is not valid in the ROM control register. Based on this difference, the start
address has to be divided into six nibbles, and
written into the ROM control register six times
with respect to the divided-by-six nibbles. The
lower-order nibble and higher-order nibble data
can then be read back by reading twice after the
sound or tone (melody) starting address is written. Every times of reading must interval at
least fifty instruction cycles after the address is
exchanged or fore reading. For example, if the
A D 0 ~ A D 3
TEMPO.7
MOV [ROMC], A;
Write the fourth nibble
address
MOV A, 00H
MOV [ROMC]
Write the fith nibble
address
MOV A, 00H
MOV [ROMC], A
Writh the sixth nibble
address
CALL DELAY;
Delay 50 instruction cycles
MOV A, [ROMC];
Read the lower-order
nibble data
MOV [DATA], A;
MOV A, [ROMC];
Read the high-order
nibble data
A 1 X ~ A 1 2
A 1 1 ~ A 8
A 7 ~ A 4
V o ic e
R O M
D 4 ~ D 7
D a ta R e g is te r
( h ig h n ib b le )
D 0 ~ D 3
D a ta R e g is te r
( lo w n ib b le )
R D
A 3 ~ A 0
E N
T E M P O .7
¸ 2
X = 4 , 5 o r 6
Voice ROM
25
March 15, 2000
HT827A0
SWAPA [ACC];
ORM A, [DATA];
it is ²0², the contents of the latches will move to
the internal bus. The latter is possible only in
the ²read-modify-write² instruction. For the
output function, CMOS is the only configuration. These control registers are all mapped to
locations 13H, 15H, 17H, 19H, 1BH. The PE
hi-nibble bits are void, this four bits are read as
²0².
Combine the lower-order
data and
higher-order data
Input/Output ports
The HT827A0 includes 36 bidirectional input/output lines, labeled from PA to PC or PE
which are mapped to the data memories of
[12H], [14H], [16H], [18H] and [1AH], respectively. All of these I/O ports can be used as input
and output operations. For input operation,
these ports are non-latched, i.e., the inputs
must be ready at the T2 rising edge of the instruction ²MOV A, [m]² (m=12, 14, 16H, 18H or
1AH). For output operation, all the data are
latched and remain unchanged till the output
latch is re-written.
These input/output lines stay at a high level or
floating (decided by mask option) after a chip
reset. Each bit of the input/output latches can
be set or cleared by the ²SET[m].i² and
²CLR[m].i² (m=12H, 14H, 16H, 18H, 1AH) instructions.
Some instructions will first input data and then
follow the output operations. For instance,
²SET[m].i², ²CLR[m].i², ²CPL[m]², and ²CPLA[m]²
read the entire port state into the CPU, execute
the defined operations (bit-operation), and then
write the results back to the latches or accumulator.
Each I/O line has its own control register (PAC,
PBC, PCC, PDC and PEC) to control the input/output configuration. With a control register, a CMOS output or schmitt trigger input can
be re-configured dynamically (i.e., on-the-fly)
with or without pull-high resistor structures
under a software control. To function as an input, the corresponding latch of a control register must write ²1². The pull-high resistance will
be automatically exhibited if the pull-high option is chosen. The input source also depends on
the control register. If the bit of the control register bit ²1², the input will read the pad state. If
D A T A B U S
W r ite C o n tr o l R e g is te r
D
Each line of port A is capable of waking up the
device. The highest four bits of port E are not
physically implemented. A ²0² will return to
reading the highest four bits, but writing them
will result with no operation.
V
Q
C K
Q
S
V
C h ip R e s e t
D
P A 0
P B 0
P C 0
P D 0
P E 0
Q
C K
S
Q
M
R e a d I/O
S y s te m
W E A K
P u ll- u p
M a s k O p tio n
R e a d C o n tr o l R e g is te r
W r ite I/O
D D
D D
U
~ P A
~ P B
~ P C
~ P D
~ P E
7
7
3
7
7
X
W a k e - u p ( P A o n ly )
M a s k O p tio n
Input/Output ports
26
March 15, 2000
HT827A0
Mask option
The following table illustrates 5 kinds of mask option in the HT827A0. All of them have to be defined
to ensure a proper functioning system.
No.
Mask Option
1
OSC type selection
This option determines the selection of a system clock, whether an RC or crystal type of
oscillator.
2
WDT source selection
Three selections are provided, namely, on-chip RC oscillator, instruction clock and WDT
disable.
3
CLRWDT times selection
This option defines clearing WDT by instructions. ²Once² means ²CLR WDT² can clear
WDT. ²Twice² means WDT can be cleared only if both ²CLR WDT1² and ²CLR WDT2² are
executed.
4
Wake-up selection
This option defines the activity of the wake-up function. All of the external I/O pins (PA
only) are capable of waking up the chip from a HALT mode.
5
Pull-high selection
This option determines whether or not the pull-high resistance exists in the input mode of
the I/O ports. Each bit of the I/O port can be independently selected.
27
March 15, 2000
HT827A0
Application Circuits
RC oscillator for multiple I/O applications
R
fS
Y S
O S C
2 0 p F
O S C 1
O S C 2
/4
V
Crystal oscillator for multiple I/O applications
O S C 1
P A 0 ~ P A 7
1 0 M W
P B 0 ~ P B 7
2 0 p F
P C 0 ~ P C 7
D D
V
O S C 2
P E 0 ~ P E 3
R E S
P D 0 ~ P D 7
V
1 0 k W
D D
V
D D
0 .1 m F
S P K
8 W
A U D
P E 0 ~ P E 3
R E S
0 .1 m F
IN T
P B 0 ~ P B 7
P C 0 ~ P C 7
D D
P D 0 ~ P D 7
1 0 k W
P A 0 ~ P A 7
8 0 5 0
S P K
8 W
IN T
T M R
A U D
8 0 5 0
T M R
0 6 &
% ) 0 6 &
28
% ) March 15, 2000
HT827A0
Instruction Set Summary
Mnemonic
Description
Flag Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to register with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry leaving result in
the data memory
Decimal adjust ACC for addition with result in data memory
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
C
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
Z
Z
Z
Z
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
29
None
None
C
C
None
None
C
C
March 15, 2000
HT827A0
Mnemonic
Description
Flag Affected
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
None
None
None
Clear bit of data memory
Set bit of data memory
None
None
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
None
None
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
No operation
Clear data memory
Set data memory
Clear Watchdog timer
Pre-clear Watchdog timer
Pre-clear Watchdog timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
None
None
None
TO,PD
TO*,PD*
TO*,PD*
None
None
TO,PD
Note: x: 8-bit immediate data
m: 7-bit data memory address
A: Accumulator
i: 0~7 number of bits
addr: 11-bit program memory address
Ö: Flag(s) is affected
-: Flag(s) is unaffected
*: Flag(s) may be affected by the execution status
30
March 15, 2000
HT827A0
Instruction Definition
ADC A,[m]
Add data memory and carry to accumulator
Description
The contents of the specified data memory accumulator and carry flag are
added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add accumulator and carry to data memory
Description
The contents of the specified data memory accumulator and carry flag are
added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to accumulator
Description
The contents of the specified data memory and accumulator are added. The
result is stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to accumulator
Description
The contents of the accumulator and specified data are added, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
31
March 15, 2000
HT827A0
ADDM A,[m]
Add accumulator to data memory
Description
The contents of the specified data memory and accumulator are added. The
result is stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to accumulator
Description
Data in the accumulator and specified data perform a bitwise logical_AND
operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with accumulator
Description
Data in the specified data memory and accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
32
March 15, 2000
HT827A0
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine which is located at the indicated address. The program counter increments once to obtain the address
of the next instruction, and pushes this onto the stack. The indicated address
is then loaded. Program execution continues with the instruction at this address.
Operation
Stack ¬ PC+1
PC ¬ addr
Affected flag(s)
CLR [m]
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
Clear data memory
Description
The contents of the specified data memory are cleared to zero.
Operation
[m] ¬ 00H
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR [m].i
Clear bit of data memory
Description
Bit i of the specified data memory is cleared to zero.
Operation
[m].i ¬ 0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR WDT
Clear watchdog timer
Description
The WDT and WDT Prescaler are cleared (re-count from zero). The power
down bit (PD) and time-out bit (TO) are both cleared.
Operation
WDT & WDT Prescaler ¬ 00H
PD & TO ¬ 0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0
0
¾
¾
¾
¾
33
March 15, 2000
HT827A0
CLR WDT1
Preclear watchdog timer
Description
The PD, TO flags, WDT and the WDT Prescaler are all cleared (re-count
from zero) if the other preclear WDT instruction has been executed. Execution only of this instruction without the other preclear instruction sets the
indicated flag, which implies that this instruction is executed and the PD
and TO flags remain unchanged.
Operation
WDT & WDT Prescaler ¬ 00H*
PD & TO ¬ 0*
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear watchdog timer
Description
The PD, TO flags, WDT and the WDT Prescaler are all cleared (re-count
from zero) if the other preclear WDT instruction has been executed. Execution only of this instruction without the other preclear instruction sets the
indicated flag, which implies that this instruction is executed and the PD
and TO flags remain unchanged.
Operation
WDT & WDT Prescaler ¬ 00H*
PD & TO ¬ 0*
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits which previously contained a one are changed to zero and
vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
34
March 15, 2000
HT827A0
CPLA [m]
Complement data memory place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits which previously contained a one are changed to zero and
vice-versa. The complemented result is stored in the accumulator and the
contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The value of the accumulator is adjusted to a BCD (Binary Code Decimal)
code. If bits 0~3 of the accumulator are greater than 9 or AC is one, six is
added to the low-order nibble of the accumulator, deriving a BCD digit in the
low-order nibble. Similarly, if bits 4~7 of the accumulator are greater than
nine or C is one, six is added to the high-order nibble of the accumulator, generating a BCD digit in the high-order nibble. The result is stored in the data
memory.
Operation
If ACC.3~ACC.0 >9 or AC=1
then ([m].3~[m].0) ¬ (ACC.3~ACC.0)+6
else ([m].3~[m].0) ¬ (ACC.3~ACC.0)
and
If ACC.7~ACC.4 >9 or C=1
then ([m].7~[m].4) ¬ (ACC.7~ACC.4)+6,C=1
else ([m].7~[m].4) ¬ (ACC.7~ACC.4),C=C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory are decremented by one.
Operation
[m] ¬ [m]-1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
35
March 15, 2000
HT827A0
DECA [m]
Decrement data memory place result in the accumulator
Description
Data in the specified data memory are decremented by one, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock.
The contents of the RAM and registers are retained. The WDT and prescaler
are cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is
cleared.
Operation
PC ¬ PC+1
PD ¬ 1
TO ¬ 0
Affected flag(s)
INC [m]
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0
1
¾
¾
¾
¾
Increment data memory
Description
Data in the specified data memory are incremented by one.
Operation
[m] ¬ [m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory-place result in accumulator
Description
Data in the specified data memory are incremented by one, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
36
March 15, 2000
HT827A0
JMP addr
Direct Jump
Description
Bits 0~10 of the program counter are unconditionally replaced with the directly-specified addresses, and the control is passed to this destination.
Operation
PC ¬ addr
Affected flag(s)
MOV A,[m]
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
Move data memory to accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
MOV A,x
Move immediate data to accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
MOV [m],A
Move accumulator to the data memory
Description
The contents of the accumulator are copied to the specified data memory (one
of the data memory).
Operation
[m] ¬ ACC
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
37
March 15, 2000
HT827A0
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
PC ¬ PC+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data
memory) perform a bitwise logical_OR operation. The result is stored in the
accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to accumulator
Description
Data in the accumulator and specified data perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with accumulator
Description
Data in the data memory (one of the data memory) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
38
March 15, 2000
HT827A0
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a two-cycle instruction.
Operation
PC ¬ Stack
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator is
loaded with the specified 8-bit immediate data.
Operation
PC ¬ Stack
ACC ¬ x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts enabled by
setting the EMI bit. EMI is an enable master (global) interrupt bit (bit 0; register INTC).
Operation
PC ¬ Stack
EMI ¬ 1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit to the left with
bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
39
March 15, 2000
HT827A0
RLA [m]
Rotate data memory to the left - then place result in the accumulator
Description
Data in the specified data memory are rotated 1-bit to the left with bit 7 rotated into bit 0, leaving the rotation result in the accumulator. The contents
of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and carry flag are rotated 1-bit to
the left. Bit 7 replaces the carry bit; the original carry flag is rotated to the bit
0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry - then place result in the accumulator
Description
Data in the specified data memory and carry flag are rotated 1-bit left. Bit 7
replaces the carry bit and the original carry flag is rotated to the bit 0 position. The rotation result is stored in the accumulator but the contents of the
data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
40
March 15, 2000
HT827A0
RR [m]
Rotate data memory to the right
Description
The contents of the specified data memory are rotated 1-bit to the right with
bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate to the right - then place result in the accumulator
Description
Data in the specified data memory are rotated 1-bit to the right with bit 0 rotated to bit 7, leaving the rotation result in the accumulator. The contents of
the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory to the right through carry
Description
The contents of the specified data memory and carry flag are rotated 1-bit to
the right. Bit 0 replaces the carry bit; the original carry flag is rotated to the
bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
41
March 15, 2000
HT827A0
RRCA [m]
Rotate to the right through carry - then place result in the accumulator
Description
Data of the specified data memory and carry flag are rotated one bit right. Bit
0 replaces the carry bit and the original carry flag is rotated to the bit 7 position. The rotation result is stored in the accumulator. The contents of the
data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry
flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry
flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
42
March 15, 2000
HT827A0
SDZ [m]
Skip if decrement data memory is zero
Description
The contents of the specified data memory are decremented by one. If the result is zero, the next instruction is skipped and the following instruction,
fetched during the current instruction execution, is discarded and a dummy
cycle is replaced to get a proper instruction. This makes a 2-cycle instruction.
Otherwise proceed to the next instruction.
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory - then place result in ACC, skip if zero
Description
The contents of the specified data memory are decremented by one. If the result is zero, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is zero, the
following instruction, fetched during the current instruction execution, is
discarded and a dummy cycle is replaced to get a proper instruction, making
a 2-cycle instruction. Otherwise proceed to the next instruction.
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1
Operation
[m] ¬ FFH
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SET [m].i
Set bit of data memory
Description
Bit ²i² of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
43
March 15, 2000
HT827A0
SIZ [m]
Skip if increment data memory is zero
Description
The contents of the specified data memory are incremented by one. If the result is zero, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction. This is a 2-cycle instruction. Otherwise proceed to the next instruction.
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory - then place result in ACC, skip if zero
Description
The contents of the specified data memory are incremented by one. If the result is zero, the next instruction is skipped and the result stored in the accumulator. The data memory remains unchanged. If the result is zero, the
following instruction, fetched during the current instruction execution, is
discarded and a dummy cycle is replaced to get a proper instruction. This is a
2-cycle instruction. Otherwise proceed to the next instruction.
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit ²i² of the data memory is not zero
Description
If bit ²i² of the specified data memory is not zero, the following instruction,
fetched during the current instruction execution, is discarded and a dummy
cycle is replaced to get a proper instruction. This is a 2 cycle instruction. Otherwise proceed with the next instruction.
Operation
Skip if [m].i¹0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
44
March 15, 2000
HT827A0
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of
the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (one of the
data memory) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
45
March 15, 2000
HT827A0
SWAPA [m]
Swap data memory - then place result in the accumulator
description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data
memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SZ [m]
Skip if data memory is zero
Description
If the contents of the specified data memory are zero, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get a proper instruction. This is a 2-cycle instruction. Otherwise proceed to the next instruction.
Operation
Skip if [m]=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if zero
Description
The contents of the specified data memory are copied to the accumulator. If
the contents are zero, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get a
proper instruction. This is a 2-cycle instruction. Otherwise proceed to the
next instruction.
Operation
Skip if [m]=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
46
March 15, 2000
HT827A0
SZ [m].i
Skip if bit ²i² of the data memory is zero
Description
If bit ²i² of the specified data memory is zero, the following instruction,
fetched during the current instruction execution, is discarded and a dummy
cycle is replaced to get a proper instruction. This is a 2-cycle instruction. Otherwise proceed to the next instruction.
Operation
Skip if [m].i=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move ROM code (current page) to TBLH and to the data memory
Description
The low byte of the ROM code (current page) addressed by the table pointer
(TBLP) is moved to the specified data memory and the high byte is transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move ROM code (last page) to TBLH and to the data memory
Description
The low byte of the ROM code (last page) addressed by the table pointer
(TBLP) is moved to the data memory and the high byte is transferred to
TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
47
March 15, 2000
HT827A0
XORM A,[m]
Logical XOR data memory with accumulator
Description
Data in the indicated data memory and accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The
zero flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the the accumulator and specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The zero flag
is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
48
March 15, 2000
HT827A0
Holtek Semiconductor Inc. (Headquarters)
No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C.
Tel: 886-3-563-1999
Fax: 886-3-563-1189
Holtek Semiconductor Inc. (Taipei Office)
5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C.
Tel: 886-2-2782-9635
Fax: 886-2-2782-9636
Fax: 886-2-2782-7128 (International sales hotline)
Holtek Semiconductor (Hong Kong) Ltd.
RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657
Copyright Ó 2000 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek
assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are
used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications
will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior
notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
49
March 15, 2000