LINER LTC2630AISC6-LM12TRMPBF Single 12-/10-/8-bit rail-to-rail dacs with integrated reference in sc70 Datasheet

LTC2630
Single 12-/10-/8-Bit Rail-toRail DACs with Integrated
Reference in SC70
DESCRIPTION
FEATURES
■
■
■
■
■
■
■
■
■
■
■
■
Integrated Precision Reference
2.5V Full Scale 10ppm/°C (LTC2630-L)
4.096V Full Scale 10ppm/°C (LTC2630-H)
Maximum INL Error: 1 LSB (LTC2630A-12)
Low Noise: 0.7mVP-P, 0.1Hz to 200kHz
Guaranteed Monotonic over Temperature
Selectable Internal Reference or Supply as Reference
2.7V to 5.5V Supply Range (LTC2630-L)
Low Power Operation: 180µA at 3V
Power Down to 1.5µA Maximum (C and I Grades)
Power-on Reset to Zero or Midscale Options
SPI Serial Interface
Double-Buffered Data Latches
Tiny 6-Lead SC70 Package
■
■
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■
The LTC2630-L has a full-scale output of 2.5V, and
operates from a single 2.7V to 5.5V supply. The
LTC2630-H has a full-scale output of 4.096V, and operates
from a 4.5V to 5.5V supply. Each DAC can also operate in
supply as reference mode, which sets the full-scale output
to the supply voltage.
The parts use a simple SPI/MICROWIRE™ compatible
3-wire serial interface which operates at clock rates up
to 50MHz.
The LTC2630 incorporates a power-on reset circuit. Options are available for reset to zero or reset to midscale
after power-up.
APPLICATIONS
■
The LTC®2630 is a family of 12-, 10-, and 8-bit voltageoutput DACs with an integrated, high-accuracy, low-drift
reference in a 6-lead SC70 package. It has a rail-to-rail
output buffer and is guaranteed monotonic.
Mobile Communications
Process Control and Industrial Automation
Automatic Test Equipment
Portable Equipment
Automotive
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents
including 5396245, 5859606, 6891433 and 6937178.
TYPICAL APPLICATION
Integral Nonlinearity (LTC2630A-LZ12)
VCC
INTERNAL
REFERENCE
1.0
SDI
SCK
0.5
RESISTOR
DIVIDER
INL (LSB)
CONTROL
DECODE LOGIC
VCC = 3V
VFS = 2.5V
24-BIT
SHIFT
REGISTER
0
DACREF
CS/LD
–0.5
INPUT
REGISTER
DAC
REGISTER
DAC
VOUT
–1.0
0
1024
2048
3072
4095
CODE
GND
2630 TA03
2630 BD
2630f
1
LTC2630
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
Supply Voltage (VCC) ................................... –0.3V to 6V
⎯C⎯S/LD, SCK, SDI .......................................... –0.3V to 6V
VOUT .................................. –0.3V to min(VCC + 0.3V, 6V)
Operating Temperature Range
LTC2630C ................................................ 0°C to 70°C
LTC2630I ............................................. –40°C to 85°C
LTC2630H .......................................... –40°C to 125°C
Maximum Junction Temperature .......................... 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
TOP VIEW
CS/LD 1
6 VOUT
SCK 2
5 GND
SDI 3
4 VCC
SC6 PACKAGE
6-LEAD PLASTIC SC70
TJMAX = 150°C (Note 4), θJA = 300°C/W
ORDER INFORMATION
LTC2630 A
C
SC6 –L
M
12
#TRM PBF
LEAD FREE DESIGNATOR
TAPE AND REEL
TR = Tape and Reel
TRM = 500-Piece Tape and Reel
RESOLUTION
12 = 12-Bit
10 = 10-Bit
8 = 8-Bit
POWER-ON RESET
M = Reset to Mid-Scale
Z = Reset to Zero-Scale
FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE
L = 2.5V
H = 4.096V
PACKAGE TYPE
SC6 = 6-Lead SC70
TEMPERATURE GRADE
C = Commercial Temperature Range (0°C to 70°C)
I = Industrial Temperature Range (–40°C to 85°C)
H = Automotive Temperature Range (–40°C to 125°C)
ELECTRICAL GRADE (OPTIONAL)
A = ±1 LSB Maximum INL (12-Bit)
PRODUCT PART NUMBER
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2630f
2
LTC2630
PRODUCT SELECTION GUIDE
PART NUMBER
VFS WITH INTERNAL REFERENCE
POWER-ON RESET TO CODE
RESOLUTION
VCC
LTC2630A-LM12
2.5V • (4095/4096)
Mid-Scale
12-Bit
2.7V–5.5V
MAXIMUM INL
±1LSB
LTC2630A-LZ12
2.5V • (4095/4096)
Zero
12-Bit
2.7V–5.5V
±1LSB
LTC2630A-HM12
4.096V • (4095/4096)
Mid-Scale
12-Bit
4.5V–5.5V
±1LSB
LTC2630A-HZ12
4.096V • (4095/4096)
Zero
12-Bit
4.5V–5.5V
±1LSB
LTC2630-LM12
2.5V • (4095/4096)
Mid-Scale
12-Bit
2.7V–5.5V
±2LSB
LTC2630-LM10
2.5V • (1023/1024)
Mid-Scale
10-Bit
2.7V–5.5V
±1LSB
LTC2630-LM8
2.5V • (255/256)
Mid-Scale
8-Bit
2.7V–5.5V
±0.5LSB
LTC2630-LZ12
2.5V • (4095/4096)
Zero
12-Bit
2.7V–5.5V
±2LSB
LTC2630-LZ10
2.5V • (1023/1024)
Zero
10-Bit
2.7V–5.5V
±1LSB
LTC2630-LZ8
2.5V • (255/256)
Zero
8-Bit
2.7V–5.5V
±0.5LSB
LTC2630-HM12
4.096V • (4095/4096)
Mid-Scale
12-Bit
4.5V–5.5V
±2LSB
LTC2630-HM10
4.096V • (1023/1024)
Mid-Scale
10-Bit
4.5V–5.5V
±1LSB
LTC2630-HM8
4.096V • (255/256)
Mid-Scale
8-Bit
4.5V–5.5V
±0.5LSB
LTC2630-HZ12
4.096V • (4095/4096)
Zero
12-Bit
4.5V–5.5V
±2LSB
LTC2630-HZ10
4.096V • (1023/1024)
Zero
10-Bit
4.5V–5.5V
±1LSB
LTC2630-HZ8
4.096V • (255/256)
Zero
8-Bit
4.5V–5.5V
±0.5LSB
2630f
3
LTC2630
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2630-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2630A-LM12/-LZ12 (VFS = 2.5V)
LTC2630-8
SYMBOL PARAMETER
CONDITIONS
LTC2630-10
LTC2630-12
LTC2630A-12
MAX UNITS
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP
DC Performance
Resolution
●
8
Monotonicity
●
8
VCC = 3V, Internal Ref. (Note 2)
INL
Differential Nonlinearity VCC = 3V, Internal Ref. (Note 2) ●
Integral Nonlinearity
VCC = 3V, Internal Ref. (Note 2) ●
ZSE
Zero Scale Error
VOS
Offset Error
VOSTC
VOS Temperature
Coefficient
FSE
Full Scale Error
VCC = 3V, Internal Ref.
VFSTC
Full Scale Voltage
Temperature
Coefficient
VCC = 3V, Internal Ref. (Note 8)
C-Grade
I-Grade
H-Grade
Load Regulation
VCC = 3V ±10% or 5V ±10%,
Internal Ref., Midscale,
–5mA ≤ IOUT ≤ 5mA
DC Output Impedance VCC = 3V ±10% or 5V ±10%,
Internal Ref., Midscale,
–5mA ≤ IOUT ≤ 5mA
DNL
ROUT
VCC = 3V, Internal Ref., Code = 0 ●
10
12
10
12
±0.5
±0.05 ±0.5
12
Bits
12
±0.5
Bits
±1
±1
LSB
±0.2
±1
±1
±2
±0.5
±1
LSB
0.5
5
0.5
5
0.5
5
mV
±0.5
±5
±0.5
±5
±0.5
±5
0.5
5
VCC = 3V, Internal Ref. (Note 3) ●
±0.5
±5
VCC = 3V, Internal Ref. (Note 3)
±10
±10
±10
±10
±0.2 ±0.8
±0.2 ±0.8
±0.2 ±0.8
±0.2
±10
±10
±10
±10
±10
±10
±10
±10
±10
±10
±10
±10
●
0.008 0.016
0.03 0.064
0.13 0.256
0.13
0.256
LSB/
mA
●
0.08 0.156
0.08 0.156
0.08 0.156
0.08
0.156
Ω
●
SYMBOL PARAMETER
CONDITIONS
VOUT
Supply as Reference
Internal Reference
DAC Output Span
MIN
PSR
Power Supply Rejection
VCC = 3V ±10% or 5V ±10%
ISC
Short Circuit Output Current (Note 4)
Sinking
Sourcing
VFS = VCC = 5.5V
Zero Scale; VOUT Shorted to VCC
Full Scale; VOUT Shorted to GND
●
●
TYP
mV
μV/°C
±0.8
%FSR
ppm/°C
ppm/°C
ppm/°C
MAX
UNITS
0V to VCC
0V to 2.5
V
V
–80
dB
27
–28
50
–50
mA
mA
5.5
V
Power Supply
VCC
Power Supply Voltage
For Specified Performance
●
ICC
Supply Current (Note 5)
Midscale
VCC = 3V, Supply as Reference
VCC = 3V, Internal Reference
VCC = 5V, Supply as Reference
VCC = 5V, Internal Reference
●
●
●
●
160
180
180
190
220
240
250
260
μA
μA
μA
μA
●
●
0.36
0.36
1.5
3
μA
μA
ISD
Supply Current in Shutdown Mode (Note 5) VCC = 5V, C-Grade, I-Grade
VCC = 5V, H-Grade
2.7
Digital I/O
VIH
Digital Input High Voltage
VCC = 3.6V to 5.5V
VCC = 2.7V to 3.6V
●
●
VIL
Digital Input Low Voltage
VCC = 4.5V to 5.5V
VCC = 2.7V to 4.5V
●
●
ILK
Digital Input Leakage
VIN = GND to VCC
CIN
Digital Input Capacitance
(Note 6)
2.4
2.0
V
V
0.8
0.6
V
V
●
±1
μA
●
2.5
pF
2630f
4
LTC2630
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2630-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2630A-LM12/-LZ12 (VFS = 2.5V)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
AC Performance
tS
en
Settling Time
VCC = 3V (Note 7)
±0.39% (±1LSB at 8 Bits)
±0.098% (±1LSB at 10 Bits)
±0.024% (±1LSB at 12 Bits)
3.2
3.9
4.4
μs
μs
μs
Voltage Output Slew Rate
1.0
V/μs
Capacitive Load Driving
500
pF
Glitch Impulse
At Midscale Transition
Output Voltage Noise Density
At f = 1kHz, Supply as Reference
At f = 10kHz, Supply as Reference
At f = 1kHz, Internal Reference
At f = 10kHz, Internal Reference
140
130
160
150
2
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
nV•s
Output Voltage Noise
0.1Hz to 10Hz, Supply as Reference
0.1Hz to 10Hz, Internal Reference
0.1Hz to 200kHz, Supply as Reference
0.1Hz to 200kHz, Internal Reference
20
20
650
700
μVP-P
μVP-P
μVP-P
μVP-P
TIMING CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V. (See Figure 1) (Note 6).
LTC2630-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2630A-LM12/-LZ12 (VFS = 2.5V)
SYMBOL
PARAMETER
t1
SDI Valid to SCK Setup
●
4
ns
t2
SDI Valid to SCK Hold
●
4
ns
t3
SCK High Time
●
9
ns
t4
SCK Low Time
●
9
ns
t5
⎯C⎯S/LD Pulse width
●
10
ns
t6
SCK High to ⎯C⎯S/LD High
●
7
ns
t7
⎯C⎯S/LD Low to SCK High
●
7
ns
t10
⎯C⎯S/LD High to SCK Positive Edge
●
7
ns
SCK Frequency
CONDITIONS
50% Duty Cycle
MIN
●
TYP
MAX
50
UNITS
MHz
2630f
5
LTC2630
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2630-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2630A-HM12/-HZ12 (VFS = 4.096V)
LTC2630-8
SYMBOL PARAMETER
CONDITIONS
LTC2630-10
LTC2630-12
LTC2630A-12
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP
MAX UNITS
DC Performance
●
8
VCC = 5V, Internal Ref. (Note 2) ●
8
Resolution
Monotonicity
INL
Differential Nonlinearity VCC = 5V, Internal Ref. (Note 2) ●
Integral Nonlinearity
VCC = 5V, Internal Ref. (Note 2) ●
ZSE
Zero Scale Error
DNL
10
10
±0.05 ±0.5
0.5
5
±5
VOS
Offset Error
VCC = 5V, Internal Ref. (Note 3) ●
±0.5
VOSTC
VOS Temperature
Coefficient
VCC = 5V, Internal Ref. (Note 3)
±10
FSE
Full Scale Error
VCC = 5V, Internal Ref.
VFSTC
Full Scale Voltage
Temperature
Coefficient
VCC = 5V, Internal Ref. (Note 8)
C-Grade
I-Grade
H-Grade
Load Regulation
●
VCC = 5V ±10%, Internal Ref.,
Midscale, –10mA ≤ IOUT ≤ 10mA
ROUT
●
DC Output Impedance VCC = 5V ±10%, Internal Ref.,
Midscale, –10mA ≤ IOUT ≤ 10mA
12
12
±0.5
VCC = 5V, Internal Ref., Code = 0 ●
●
12
Bits
12
±0.5
Bits
±1
±1
LSB
±0.2
±1
±1
±2
±0.5
±1
LSB
0.5
5
0.5
5
0.5
5
mV
±0.5
±5
±0.5
±5
±0.5
±5
±10
±10
±0.2 ±0.8
±0.2 ±0.8
±0.2 ±0.8
±0.2
±10
±10
±10
±10
±10
±10
±10
±10
±10
±10
±10
±10
0.006 0.01
0.025 0.04
0.10 0.16
0.10
0.16
0.1
0.1
0.1
0.1
0.156
0.156
SYMBOL PARAMETER
CONDITIONS
VOUT
DAC Output Span
Supply as Reference
Internal Reference
PSR
Power Supply Rejection
VCC = 5V ±10%
ISC
Short Circuit Output Current (Note 4)
Sinking
Sourcing
VFS = VCC = 5.5V
Zero Scale; VOUT Shorted to VCC
Full Scale; VOUT Shorted to GND
●
●
0.156
MIN
0.156
TYP
MAX
mV
μV/°C
±10
±0.8
%FSR
ppm/°C
ppm/°C
ppm/°C
LSB/
mA
Ω
UNITS
0V to VCC
0V to 4.096
V
V
–80
dB
27
–28
50
–50
mA
mA
5.5
V
Power Supply
VCC
Power Supply Voltage
For Specified Performance
●
ICC
Supply Current (Note 5)
Midscale
VCC = 5V, Supply as Reference
VCC = 5V, Internal Reference
●
●
180
200
260
280
μA
μA
●
●
0.36
0.36
1.5
3
μA
μA
ISD
Supply Current in Shutdown Mode (Note 5) VCC = 5V, C-Grade, I-Grade
VCC = 5V, H-Grade
4.5
Digital I/O
VIH
Digital Input High Voltage
●
VIL
Digital Input Low Voltage
●
0.8
V
ILK
Digital Input Leakage
VIN = GND to VCC
●
±1
μA
CIN
Digital Input Capacitance
(Note 6)
●
2.5
pF
2.4
V
2630f
6
LTC2630
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2630-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2630A-HM12/-HZ12 (VFS = 4.096V)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
AC Performance
tS
en
Settling Time
VCC = 5V (Note 7)
±0.39% (±1LSB at 8 Bits)
±0.098% (±1LSB at 10 Bits)
±0.024% (±1LSB at 12 Bits)
3.7
4.4
4.8
μs
μs
μs
Voltage Output Slew Rate
1.0
V/μs
Capacitive Load Driving
500
pF
Glitch Impulse
At Midscale Transition
2.4
nV•s
Output Voltage Noise Density
At f = 1kHz, Supply as Reference
At f = 10kHz, Supply as Reference
At f = 1kHz, Internal Reference
At f = 10kHz, Internal Reference
140
130
210
200
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
Output Voltage Noise
0.1Hz to 10Hz, Supply as Reference
0.1Hz to 10Hz, Internal Reference
0.1Hz to 200kHz, Supply as Reference
0.1Hz to 200kHz, Internal Reference
20
20
650
750
μVP-P
μVP-P
μVP-P
μVP-P
TIMING CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V. (See Figure 1) (Note 6).
LTC2630-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2630A-HM12/-HZ12 (VFS = 4.096V)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t1
SDI Valid to SCK Setup
●
4
ns
t2
SDI Valid to SCK Hold
●
4
ns
t3
SCK High Time
●
9
ns
t4
SCK Low Time
●
9
ns
t5
⎯C⎯S/LD Pulse width
●
10
ns
t6
SCK High to ⎯C⎯S/LD High
●
7
ns
t7
⎯C⎯S/LD Low to SCK High
●
7
ns
t10
⎯C⎯S/LD High to SCK Positive Edge
●
7
SCK Frequency
50% Duty Cycle
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Linearity and monotonicity are defined from code kL to code 2N–1,
where N is the resolution and kL is given by kL = 0.016 • (2N/ VFS), rounded
to the nearest whole code. For VFS = 2.5V and N = 12, kL = 26 and linearity
is defined from code 26 to code 4,095. For VFS = 4.096V and
N = 12, kL = 16 and linearity is defined from code 16 to code 4,095.
Note 3: Inferred from measurement at code 16 (LTC2630-12), code 4
(LTC2630-10) or code 1 (LTC2630-8).
●
ns
50
MHz
Note 4: This IC includes current limiting that is intended to protect the
device during momentary overload conditions. Junction temperature can
exceed the rated maximum during current limiting. Continuous operation
above the specified maximum operating junction temperature may impair
device reliability.
Note 5: Digital inputs at 0V or VCC.
Note 6: Guaranteed by design and not production tested.
Note 7: Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale
and 3/4 scale to 1/4 scale. Load is 2kΩ in parallel with 100pF to GND.
Note 8: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
2630f
7
LTC2630
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2630-LM12/-LZ12 (VFS = 2.5V)
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
1.0
1.0
VCC = 3V
VCC = 3V
0.5
DNL (LSB)
INL (LSB)
0.5
0
–0.5
–1.0
0
–0.5
0
1024
2048
3072
–1.0
4095
0
2048
1024
CODE
3072
2630 G01
INL vs Temperature
2630 G02
Full-Scale Output Voltage vs
Temperature
DNL vs Temperature
1.0
1.0
VCC = 3V
2.52
VCC = 3V
VCC = 3V
0.5
FS OUTPUT VOLTAGE (V)
0.5
DNL (LSB)
INL (LSB)
INL (POS)
0
DNL (POS)
0
DNL (NEG)
INL (NEG)
–0.5
–0.5
–1.0
–50 –25
0
4095
CODE
25 50 75 100 125 150
TEMPERATURE (°C)
–1.0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
2630 G03
2.51
2.50
2.49
2.48
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
2630 G04
2630 G05
Settling to ±1LSB
Settling to ±1LSB
CS/LD
2V/DIV
3/4 SCALE TO 1/4 SCALE STEP
VCC = 3V, VFS = 2.5V
RL = 2k, CL = 100pF
AVERAGE OF 256 EVENTS
VOUT
1LSB/DIV
4.4µs
3.6µs
VOUT
1LSB/DIV
1/4 SCALE TO 3/4 SCALE STEP
VCC = 3V, VFS = 2.5V
RL = 2k, CL = 100pF
AVERAGE OF 256 EVENTS
CS/LD
2V/DIV
2µs/DIV
2µs/DIV
2630 G07
2630 G06
2630f
8
LTC2630
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2630-HM12/-HZ12 (VFS = 4.096V)
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
1.0
1.0
VCC = 5V
VCC = 5V
0.5
DNL (LSB)
INL (LSB)
0.5
0
–0.5
–1.0
0
–0.5
0
1024
2048
3072
–1.0
4095
0
1024
CODE
2048
3072
2630 G08
INL vs Temperature
2630 G09
Full-Scale Output Voltage vs
Temperature
DNL vs Temperature
1.0
4.115
1.0
VCC = 5V
VCC = 5V
0.5
FS OUTPUT VOLTAGE (V)
VCC = 5V
0.5
DNL (LSB)
INL (LSB)
INL (POS)
0
DNL (POS)
0
DNL (NEG)
INL (NEG)
–0.5
–0.5
–1.0
–50 –25
0
4095
CODE
25 50 75 100 125 150
TEMPERATURE (°C)
–1.0
–50 –25
2630 G10
0
25 50 75 100 125 150
TEMPERATURE (°C)
4.105
4.095
4.085
4.075
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
2630 G12
2630 G11
Settling to ±1LSB
Settling to ±1LSB
CS/LD
2V/DIV
VOUT
1LSB/DIV
4.8µs
4.0µs
VOUT
1LSB/DIV
1/4 SCALE TO 3/4 SCALE STEP
VCC = 5V, VFS = 4.096V
RL = 2k, CL = 100pF
AVERAGE OF 256 EVENTS
2µs/DIV
CS/LD
2V/DIV
1/4 SCALE TO 3/4 SCALE STEP
VCC = 5V, VFS = 4.096V
RL = 2k, CL = 100pF
AVERAGE OF 256 EVENTS
2µs/DIV
2630 G14
2630 G13
2630f
9
LTC2630
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2630-10
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
1.0
1.0
VCC = 5V
VFS = 4.096V
VCC = 5V
VFS = 4.096V
0.5
DNL (LSB)
INL (LSB)
0.5
0
–0.5
–1.0
0
–0.5
0
256
512
768
–1.0
1023
0
512
256
CODE
768
1023
CODE
2630 G15
2630 G16
LTC2630-8
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
1.0
0.50
VCC = 3V
VFS = 2.5V
VCC = 3V
VFS = 2.5V
0.25
DNL (LSB)
INL (LSB)
0.5
0
–0.5
–1.0
0
–0.25
0
128
64
192
–0.50
255
0
128
64
CODE
192
255
CODE
2630 G17
2630 G18
LTC2630
Load Regulation
8
6
Current Limiting
0.20
VCC = 5V (LTC2630-H)
VCC = 5V (LTC2630-L)
VCC = 3V (LTC2630-L)
0.15
Offset Error vs Temperature
3
VCC = 5V (LTC2630-H)
VCC = 5V (LTC2630-L)
VCC = 3V (LTC2630-L)
2
0.10
OFFSET ERROR (mV)
10
0.05
2
VOUT (V)
∆VOUT (mV)
4
0
–2
0
–0.05
–4
0
–1
–0.10
–6
–0.15
INTERNAL REF.
CODE = MIDSCALE
–8
–10
–30
1
–20
–10
0
10
IOUT (mA)
20
30
2630 G19
–0.20
–30
–2
INTERNAL REF.
CODE = MIDSCALE
–20
–10
0
10
IOUT (mA)
20
30
2630 G20
–3
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
2630 G21
2630f
10
LTC2630
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2630
Power-On Reset Glitch
Midscale-Glitch Impulse
Large-Signal Response
LTC2630-L
INTERNAL REF
VCC
2V/DIV
CS/LD
5V/DIV
LTC2630-H12, VCC = 5V:
2.4nV-s TYP
0.5V/DIV
VOUT
5mV/DIV
ZERO-SCALE
LTC2630-L12, VCC = 3V:
2.0nV-s TYP
VFS = VCC = 5V
1/4 SCALE TO 3/4 SCALE
2µs/DIV
2µs/DIV
200µs/DIV
2630 G23
2630 G22
Headroom at Rails vs Output
Current
500
5V SOURCING
NOISE VOLTAGE (nV/√Hz)
4.0
3V (LTC2630-L) SOURCING
2.5
2.0
1.5
5V SINKING
1.0
0.5
0
0.1Hz to 10Hz Voltage Noise
CODE = MIDSCALE
VCC = 4V, VFS = 2.5V
CODE = MIDSCALE
400
300
LTC2630-H
(VCC = 5V)
200
10µV/DIV
LTC2630-L
(VCC = 4V)
100
3V (LTC2630-L) SINKING
0
1
2
3
4
5
IOUT (mA)
6
7
0
100
8
1k
10k
100k
1s/DIV
1M
2630 G27
FREQUENCY (Hz)
2630 G25
2630 G26
Exiting Power-Down to Midscale
Supply Current vs Logic Voltage
1.0
SWEEP SCK, SDI, CS/LD
BETWEEN 0V AND VCC
CS/LD
2V/DIV
0.8
ICC (mA)
VOUT (V)
3.5
3.0
2630 G24
Noise Voltage vs Frequency
5.0
4.5
VOUT
2mV/DIV
VOUT
0.5V/DIV
VCC = 5V
0.6
0.4
VCC = 3V
(LTC2630-L)
0.2
LTC2630-H
0
4µs/DIV
2630 G28
0
1
2
3
LOGIC VOLTAGE (V)
4
5
2630 G29
2630f
11
LTC2630
PIN FUNCTIONS
⎯C⎯S/LD (Pin 1): Serial Interface Chip Select/Load Input.
When ⎯C⎯S/LD is low, SCK is enabled for shifting data on
SDI into the register. When ⎯C⎯S/LD is taken high, SCK
is disabled and the specified command (see Table 1) is
executed.
VCC (Pin 4): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V
(LTC2630-L) or 4.5V ≤ VCC ≤ 5.5V (LTC2630-H). Also
used as the reference input when the part is programmed
to operate in supply as reference mode. Bypass to GND
with a 0.1μF capacitor.
SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL
compatible.
GND (Pin 5): Ground.
VOUT (Pin 6): DAC Analog Voltage Output.
SDI (Pin 3): Serial Interface Data Input. Data on SDI
is clocked into the DAC on the rising edge of SCK. The
LTC2630 accepts input word lengths of either 24 or 32
bits.
BLOCK DIAGRAM
VCC
INTERNAL
REFERENCE
SDI
CONTROL
DECODE LOGIC
SCK
RESISTOR
DIVIDER
24-BIT
SHIFT
REGISTER
DACREF
CS/LD
INPUT
REGISTER
DAC
REGISTER
DAC
VOUT
GND
2630 BD
2630f
12
LTC2630
TIMING DIAGRAM
t1
t2
SCK
t3
1
t6
t4
2
3
23
24
t10
SDI
t5
t7
CS/LD
2630 F01
Figure 1. Serial Interface Timing
OPERATION
The LTC2630 is a family of single voltage output DACs in
6-lead SC70 packages. Each DAC can operate rail-to-rail
referenced to the input supply, or with its full-scale voltage set by an integrated reference. Twelve combinations
of accuracy (12-, 10-, and 8-bit), power-on reset value
(zero or midscale), and full-scale voltage (2.5V or 4.096V)
are available. The LTC2630 is controlled using a 3-wire
SPI/MICROWIRE compatible interface.
Power-On Reset
The LTC2630-HZ/-LZ clear the output to zero scale when
power is first applied, making system initialization consistent and repeatable.
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2630
contains circuitry to reduce the power-on glitch: the
analog output typically rises less than 5mV above zero
scale during power on if the power supply is ramped
to 5V in 1ms or more. In general, the glitch amplitude
decreases as the power supply ramp time is increased.
See “Power-On Reset Glitch” in the Typical Performance
Characteristics section.
Transfer Function
The digital-to-analog transfer function is
⎛ k ⎞
VOUT(IDEAL) = ⎜ N ⎟ VREF
⎝2 ⎠
where k is the decimal equivalent of the binary DAC
input code, N is the resolution, and VREF is either 2.5V
(LTC2630-L) or 4.096V (LTC2630-H) in internal reference mode, and VCC in Supply as reference mode.
Table 1. Command Codes
Command*
C3 C2 C1 C0
0
0
0
0
Write to Input Register
0
0
0
1
Update (Power up) DAC Register
0
0
1
1
Write to and Update (Power up) DAC Register
0
1
0
0
Power down
0
1
1
0
Select Internal Reference (Power-on Reset Default)
0
1
1
1
Select Supply as Reference (VREF = VCC )
*Command codes not shown are reserved and should not be used.
The LTC2630-HM/-LM provide an alternative reset, setting
the output to midscale when power is first applied.
2630f
13
LTC2630
OPERATION
INPUT WORD (LTC2630-12)
COMMAND
C3
C2
C1
4 DON'T-CARE BITS
C0
X
X
X
X
DATA (12 BITS + 4 DON'T-CARE BITS)
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
MSB
D0
X
X
X
X
X
X
X
X
X
X
X
X
X
LSB
INPUT WORD (LTC2630-10)
COMMAND
C3
C2
C1
4 DON'T-CARE BITS
C0
X
X
X
X
DATA (10 BITS + 6 DON'T-CARE BITS)
D9
D8
D7
D6
D5
D4
D3
D2
D1
MSB
D0
X
LSB
INPUT WORD (LTC2630-8)
COMMAND
C3
C2
C1
4 DON'T-CARE BITS
C0
X
X
X
X
DATA (8 BITS + 8 DON'T-CARE BITS)
D7
D6
D5
MSB
D4
D3
D2
D1
D0
X
LSB
X
X
X
2630 F02
Figure 2. Command and Data Input Format
Serial Interface
The ⎯C⎯S/LD input is level triggered. When this input is taken
low, it acts as a chip-select signal, enabling the SDI and
SCK buffers and the input shift register. Data (SDI input)
is transferred at the next 24 rising SCK edges. The 4-bit
command, C3-C0, is loaded first; then 4 don’t-care bits;
and finally the 16-bit data word. The data word comprises
the 12-, 10- or 8-bit input code, ordered MSB-to-LSB, followed by 4, 6 or 8 don’t-care bits (LTC2630-12, -10 and
-8 respectively; see Figure 2). Data can only be transferred
to the device when the ⎯C⎯S/LD signal is low, beginning on
the first rising edge of SCK. SCK may be high or low at
the falling edge of ⎯C⎯S/LD. The rising edge of ⎯C⎯S/LD ends
the data transfer and causes the device to execute the
command specified in the 24-bit input sequence. The
complete sequence is shown in Figure 3a.
The command (C3-C0) assignments are shown in Table 1.
The first three commands in the table consist of write and
update operations. A Write operation loads a 16-bit data
word from the 24-bit shift register into the input register.
In an Update operation, the input register is copied to the
DAC register and converted to an analog voltage at the
DAC output. Write to and Update combines the first two
commands. The Update operation also powers up the
DAC if it had been in power-down mode. The data path
and registers are shown in the Block Diagram.
While the minimum input sequence is 24 bits, it may
optionally be extended to 32 bits to accommodate microprocessors that have a minimum word width of 16 bits
(2 bytes). To use the 32-bit width, 8 don’t-care bits are transferred to the device first, followed by the 24-bit sequence
described. Figure 3b shows the 32-bit sequence.
The 16-bit data word is ignored for all commands that do
not include a Write operation.
Power-Down Mode
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever the
DAC output is not needed. When in power-down, the buffer
amplifier, bias circuit, and reference circuit are disabled and
draw essentially zero current. The DAC output is put into
a high-impedance state, and the output pin is passively
pulled to ground through a 200kΩ resistor. Input and DAC
register contents are not disturbed during power-down.
The DAC can be put into power-down mode by using
command 0100. The supply current is reduced to 1.5µA
maximum when the DAC is powered down.
Normal operation resumes after executing any command
that includes a DAC update, as shown in Table 1. The DAC
is powered up and its voltage output is updated. Normal
settling is delayed while the bias, reference, and amplifier
circuits are re-enabled. The power up delay time is 18μs
for settling to 12 bits.
2630f
14
LTC2630
OPERATION
Reference Modes
For applications where an accurate external reference is
not available, the LTC2630 has a user-selectable, integrated
reference. The LTC2630-LM and LTC2630-LZ provide a
full-scale output of 2.5V. The LTC2630-HM and LTC2630HZ provide a full-scale output of 4.096V.
The internal reference can be useful in applications where
the supply voltage is poorly regulated. Internal Reference
mode can be selected by using command 0110, and is
the power-on default.
The DAC can also operate in supply as reference mode using command 0111. In this mode, VCC supplies the DAC’s
reference voltage and the supply current is reduced.
Voltage Output
The LTC2630’s integrated rail-to-rail amplifier has guaranteed load regulation when sourcing or sinking up to 10mA
at 5V, and 5mA at 3V.
Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
load current. The measured change in output voltage per
change in forced load current is expressed in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to ohms. The amplifier’s DC output
impedance is 0.1Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 50Ω typical channel resistance of the output devices
(e.g., when sinking 1mA, the minimum output voltage is
50Ω • 1mA, or 50mV). See the graph “Headroom at Rails
vs. Output Current” in the Typical Performance Characteristics section.
The amplifier is stable driving capacitive loads of up to
500pF.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is
limited to voltages within the supply range.
Since the analog output of the DAC cannot go below ground,
it may limit for the lowest codes as shown in Figure 4b.
Similarly, limiting can occur near full scale when using the
supply as reference. If VFS = VCC and the DAC full-scale
error (FSE) is positive, the output for the highest codes
limits at VCC, as shown in Figure 4. No full-scale limiting
can occur if VFS is less than VCC–FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
Board Layout
The PC board should have separate areas for the analog and
digital sections of the circuit. A single, solid ground plane
should be used, with analog and digital signals carefully
routed over separate areas of the plane. This keeps digital
signals away from sensitive analog signals and minimizes
the interaction between digital ground currents and the
analog section of the ground plane. The resistance from
the LTC2630 GND pin to the ground plane should be as
low as possible. Resistance here will add directly to the
effective DC output impedance of the device (typically
0.1Ω). Note that the LTC2630 is no more susceptible to
this effect than any other parts of this type; on the contrary, it allows layout-based performance improvements
to shine rather than limiting attainable performance with
excessive internal resistance.
Another technique for minimizing errors is to use a separate power ground return trace on another board layer.
The trace should run between the point where the power
supply is connected to the board and the DAC ground pin.
Thus the DAC ground pin becomes the common point for
analog ground, digital ground, and power ground. When
the LTC2630 is sinking large currents, this current flows
out the ground pin and directly to the power ground trace
without affecting the analog ground plane voltage.
It is sometimes necessary to interrupt the ground plane
to confine digital ground currents to the digital portion of
the plane. When doing this, make the gap in the plane only
as long as it needs to be to serve its purpose and ensure
that no traces cross over the gap.
2630f
15
LTC2630
OPERATION
additional current through Q1. Note that at the maximum
loop voltage of 80V, Q1 will dissipate 1.6W when IOUT =
20mA and must have an appropriate heat sink.
Optoisolated 4mA to 20mA Process Controller
Figure 5 shows how to use an LTC2630HZ to make an
optoisolated, digitally-controlled 4mA to 20mA transmitter. The transmitter circuitry, including optoisolation, is
powered by the loop voltage which has a wide range of
5.4V to 80V. The 5V output of the LT®3010-5 is used to
set the 4mA offset current and VOUT is used to digitally
control the 0mA to 16mA signal current. The supply current for the regulator, DAC, and op amp is well below
the 4mA budget at zero scale. RS senses the total loop
current, which includes the quiescent supply current and
ROFFSET and RGAIN are the closest 0.1% values to ideal
for controlling a 4mA to 20mA output as the digital input
varies from zero scale to full scale. Alternatively, ROFFSET
can be a 365k, 1% resistor in series with a 20k trim pot
and RGAIN can be a 75.0k, 1% resistor in series with a 5k
trim pot. The optoisolators shown will limit the speed of
the serial bus; the 6N139 is an alternative that will allow
higher data rates.
CS/LD
SCK
1
C3
SDI
3
2
C2
5
4
C1
C0
X
6
X
8
7
X
X
9
D11
11
10
D10
D9
12
D8
13
D7
15
14
D6
D5
16
D4
17
D3
18
D2
19
D1
20
D0
22
21
X
X
23
X
24
X
2630 F03a
COMMAND WORD
4 DON’T-CARE BITS
DATA WORD
24-BIT INPUT WORD
Figure 3a. 24-Bit Load Sequence (Minimum Input Word)
LTC2630-12 SDI Data Word: 12-Bit Input Code + 4 Don’t-Care Bits (Shown);
LTC2630-10 SDI Data Word: 10-Bit Input Code + 6 Don’t-Care Bits;
LTC2630-8 SDI Data Word: 8-Bit Input Code + 8 Don’t-Care Bits
CS/LD
SCK
SDI
1
X
3
2
X
X
5
4
X
X
6
X
8 DON’T-CARE BITS
8
7
X
X
9
C3
10
C2
11
C1
COMMAND WORD
12
C0
13
X
14
X
15
X
16
X
4 DON’T-CARE BITS
17
D11
18
D10
19
D9
20
D8
21
D7
22
D6
23
D5
24
D4
25
D3
26
D2
27
D1
28
D0
29
X
30
X
31
X
32
X
DATA WORD
2630 F03b
32-BIT INPUT WORD
Figure 3b. 32-Bit Load Sequence
LTC2630-12 SDI Data Word: 12-Bit Input Code + 4 Don’t-Care Bits (Shown);
LTC2630-10 SDI Data Word: 10-Bit Input Code + 6 Don’t-Care Bits;
LTC2630-8 SDI Data Word: 8-Bit Input Code + 8 Don’t-Care Bits
2630f
16
NEGATIVE
OFFSET
0V
OUTPUT
VOLTAGE
(b)
INPUT CODE
0
2,048
INPUT CODE
(a)
4,095
Figure 4. Effects of Rail-to-Rail Operation on a DAC Transfer Curve (Shown for 12 Bits).
(a) Overall Transfer Function
(b) Effect of Negative Offset for Codes Near Zero
(c) Effect of Positive Full-Scale Error for Codes Near Full Scale
0V
OUTPUT
VOLTAGE
VREF = VCC
INPUT CODE
(c)
VREF = VCC
2630 F04
OUTPUT
VOLTAGE
POSITIVE
FSE
LTC2630
OPERATION
2630f
17
LTC2630
TYPICAL APPLICATION
12-Bit, 2.7V to 5.5V Single Supply, Voltage Output DAC
2.7V TO 5.5V
0.1µF
SDI
µP
SCK
VCC
LTC2630-LZ12 V
OUT
CS/LD
OUTPUT
0V TO 2.5V OR
0V TO VCC
GND
2630 TA01
2630f
18
LTC2630
PACKAGE DESCRIPTION
SC6 Package
6-Lead Plastic SC70
(Reference LTC DWG # 05-08-1638 Rev B)
0.47
MAX
0.65
REF
1.80 – 2.20
(NOTE 4)
1.00 REF
INDEX AREA
(NOTE 6)
1.80 – 2.40 1.15 – 1.35
(NOTE 4)
2.8 BSC 1.8 REF
PIN 1
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.10 – 0.40
0.65 BSC
0.15 – 0.30
6 PLCS (NOTE 3)
0.80 – 1.00
0.00 – 0.10
REF
1.00 MAX
GAUGE PLANE
0.15 BSC
0.26 – 0.46
0.10 – 0.18
(NOTE 3)
SC6 SC70 1205 REV B
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. DETAILS OF THE PIN 1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE INDEX AREA
7. EIAJ PACKAGE REFERENCE IS EIAJ SC-70
8. JEDEC PACKAGE REFERENCE IS MO-203 VARIATION AB
2630f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC2630
TYPICAL APPLICATION
VLOOP
5.4V TO 80V
ROFFSET
374k
0.1%
LT3010-5
IN
OUT
+
SHDN SENSE
1µF
1µF
GND
FROM
OPTOISOLATED
INPUTS
SDI
RGAIN
76.8k
0.1%
VCC
LTC2630-HZ
SCK
+
VOUT
CS/LD
1k
LTC2054
3.01k
Q1
2N3440
–
1000PF
10k
RS
10Ω
5V
OPTO-ISOLATORS
SDI
SCK
CS/LD
500Ω
10k
4N28
IOUT
SDI
SCK
CS/LD
2630 F05
Figure 5. An Optoisolated 4mA to 20mA Process Controller
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1660/LTC1665
Octal 10-/8-Bit VOUT DACs in 16-Pin Narrow SSOP
VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output
LTC1663
Single 10-Bit VOUT DAC in SOT-23
VCC = 2.7V to 5.5V, 60μA, Internal reference, SMBus Interface
LTC1664
Quad 10-Bit VOUT DAC in 16-Pin Narrow SSOP
VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output
LTC1669
Single 10-Bit VOUT DAC in SOT-23
VCC = 2.7V to 5.5V, 60μA, Internal reference, I2C Interface
LTC1821
Parallel 16-Bit Voltage Output DAC
Precision 16-Bit Settling in 2μs for 10V Step
LTC2600/LTC2610/LTC2620
Octal 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP
250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
LTC2601/LTC2611/LTC2621
Single 16-/14-/12-Bit VOUT DACs in 10-Lead DFN
300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
LTC2602/LTC2612/LTC2622
Dual 16-/14-/12-Bit VOUT DACs in 8-Lead MSOP
300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
LTC2604/LTC2614/LTC2624
Quad 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP
250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
LTC2605/LTC2615/LTC2625
Octal 16-/14-/12-Bit VOUT DACs with I2C Interface
250μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output,
I2C Interface
LTC2606/LTC2616/LTC2626
Single 16-/14-/12-Bit VOUT DACs with I2C Interface 270μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output,
I2C Interface
LTC2609/LTC2619/LTC2629
Quad 16-/14-/12-Bit VOUT DACs with I2C Interface
250μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output
with Separate VREF Pins for Each DAC
2630f
20 Linear Technology Corporation
LT 0407 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2007
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