TI MSP430F2370TRHAT Mixed signal microcontroller Datasheet

MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED JANUARY 2010
D
D
D
D
D
D
D
D
D
Low Supply-Voltage Range, 1.8 V to 3.6 V
Ultralow Power Consumption:
- Active Mode: 270 µA at 1 MHz, 2.2 V
- Standby Mode: 0.7 µA
- Off Mode (RAM Retention): 0.1 µA
Ultrafast Wake-Up From Standby Mode in
Less Than 1 µs
16-Bit RISC Architecture,
62.5-ns Instruction Cycle Time
Hardware Multiplier
Basic Clock Module Configurations:
- Internal Frequencies up to 16 MHz With
Four Calibrated Frequencies to ±1%
- Internal Very Low Power Low-Frequency
(LF) Oscillator
- 32-kHz Crystal
- High-Frequency (HF) Crystal up to
16 MHz
- Resonator
- External Digital Clock Source
- External Resistor
16-Bit Timer_A With Three
Capture/Compare Registers
16-Bit Timer_B With Three
Capture/Compare Registers
On-Chip Comparator for Analog Signal
Compare Function or Slope
Analog-to-Digital (A/D) Conversion
D
D
D
D
D
D
D
D
Universal Serial Communication Interface
- Enhanced UART Supporting Auto
Baudrate Detection (LIN)
- IrDA Encoder and Decoder
- Synchronous SPI
- I2Ct
Brownout Detector
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by
Security Fuse
Bootstrap Loader in Flash Devices
On-Chip Emulation Module
Family Members Include
MSP430F2330
8KB + 256B Flash Memory
1KB RAM
MSP430F2350
16KB + 256B Flash Memory
2KB RAM
MSP430F2370
32KB + 256B Flash Memory
2KB RAM
Available in 40-Pin QFN Package and
49-Pin Die-Sized BGA Package
For Complete Module Descriptions,
See the MSP430x2xx Family User’s Guide
(SLAU144)
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes is optimized to achieve extended battery life in portable measurement applications. The devices feature
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 1 µs.
The MSP430F23x0 series is an ultralow-power microcontroller with two built-in 16-bit timers, one universal
serial communication interface (USCI), a versatile analog comparator, and 32 I/O pins.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2010, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
AVAILABLE OPTIONS{
PACKAGED DEVICES}
TA
PLASTIC 49-PIN DSBGA
PLASTIC 40-PIN QFN
(YFF)
(RHA)
MSP430F2330IYFF
MSP430F2330IRHA
MSP430F2350IYFF
MSP430F2350IRHA
- 40°C to 85°C
MSP430F2370IYFF
MSP430F2370IRHA
MSP430F2330TRHA
MSP430F2350TRHA
- 40°C to 105°C
MSP430F2370TRHA
† For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at www.ti.com.
‡ Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
DEVELOPMENT TOOL SUPPORT
All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging
and programming through easy to use development tools. Recommended hardware options include the
following:
D Debugging and Programming Interface
-- MSP--FET430UIF (USB)
-- MSP--FET430PIF (Parallel Port)
D Debugging and Programming Interface With Target Board
-- MSP--FET430U23X0 (RHA package)
D Production Programmer
-- MSP--GANG430
2
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MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
AVCC
D/AVSS
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
P4.7/TBCLK
P4.6/TBOUTH/ACLK
P4.5/TB2
MSP430F23x0IRHA and MSP430F23x0TRHA
40 39 38 37 36 35 34 33 32 31
1
30
P4.4/TB1
XIN/P2.6/CA6
2
29
P4.3/TB0
XOUT/P2.7/CA7
P1.0/TACLK
3
4
28
27
P4.2/TB2
P4.1/TB1
26
P4.0/TB0
25
24
P3.7
P3.6
DVCC
P1.1/TA0
5
P1.2/TA1
P1.3/TA2
6
7
P1.4/SMCLK
8
23
P3.5/UCA0RXD/UCA0SOMI
P1.5/TA0
9
22
P3.4/UCA0TXD/UCA0SIMO
P1.6/TA1
10
21
11 12 13 14 15 16 17 18 19 20
P3.3/UCB0CLK/UCA0STE
P3.2/UCB0SOMI/UCB0SCL
RHA PACKAGE
(TOP VIEW)
P1.7/TA2
P2.0/ACLK/CA2
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/ROSC/CA5
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
pin designation,
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3
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
pin designation,
MSP430F23x0IYFF
A1
A2
A3
A4
A5
A6
A7
B1
B2
B3
B4
B5
B6
B7
C1
C2
C3
C4
C5
C6
C7
TOP VIEW
D1
D2
D3
D4
D5
D6
D7
E1
E2
E3
E4
E5
E6
E7
F1
F2
F3
F4
F5
F6
F7
G1
G2
G3
G4
G5
G6
G7
Package Dimensions
The package dimensions for this YFF package are shown in the following table. See the package drawing at
the end of this data sheet for more details.
PACKAGED DEVICES
MSP430F2370IYFF
4
YFF Package Dimensions
D
3.20 ± 0.05 mm
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
E
3.20 ± 0.05 mm
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
functional block diagram
XIN
XOUT
DVCC
D/AVSS
AVCC
P1.x/P2.x
2x8
P3.x/P4.x
2x8
ACLK
Basic Clock
System+ SMCLK
Flash
RAM
32kB
16kB
8kB
2kB
2kB
1kB
MCLK
16MHz
CPU
MAB
incl. 16
Registers
MDB
Hardware
Multiplier
Emulation
JTAG
Interface
Brownout
Protection
MPY,
MPYS,
MAC,
MACS
Ports
P1/P2
2x8 I/O
Interrupt
capability
Watchdog
WDT+
15-Bit
Ports
P3/P4
2x8 I/O
Timer_A3
Timer_B3
Comp_A+
3 CC
Registers
3 CC
Registers
8
Channels
USCI A0:
UART
IrDA, SPI
USCI B0:
SPI, I2C
RST/NMI
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MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
Terminal Functions
NAME
TERMINAL
DS-- QFN I/O
BGA
DESCRIPTION
DVCC
XIN/P2.6/CA6
XOUT/P2.7/CA7
P1.0/TACLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
P1.5/TA0
P1.6/TA1
P1.7/TA2
P2.0/ACLK/CA2
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/C
A4
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/ROSC/CA5
B3
A2
A3
B4
C4
A5
B5
A6
B6
A7
B7
C5
C7
C6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D7
D6
E7
15
16
17
I/O
I/O
I/O
P3.0/UCB0STE/
UCA0CLK
P3.1/UCB0SIMO/UC
B0SDA
P3.2/UCB0SOMI/
UCB0SCL
P3.3/UCB0CLK/UCA
0STE
P3.4/UCA0TXD/
UCA0SIMO
P3.5/UCA0RXD/
UCA0SOMI
P3.6
P3.7
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB0
P4.4/TB1
P4.5/TB2
P4.6/TBOUTH/ACLK
E6
18
I/O
F7
19
F6
20
G7
21
I/O General-purpose digital I/O pin/USCIB0 slave in/master out in SPI mode, SDA I 2C data in I2C
mode
I/O General-purpose digital I/O pin/USCIB0 slave out/master in in SPI mode, SCL I 2C clock in I2C
mode
I/O General-purpose digital I/O/USCIB0 clock input/output, USCIA0 slave transmit enable
G6
22
G5
23
F5
G4
F4
G3
G2
F3
G1
F1
F2
24
25
26
27
28
29
30
31
32
E2
E1
D1
D2
33
34
35
36
P4.7/TBCLK
TDO/TDI
TDI/TCLK
TMS
6
Digital supply voltage, positive terminal. Supplies all digital parts.
Input terminal of crystal oscillator/general-purpose digital I/O pin/Comparator_A input
Output terminal of crystal oscillator/general-purpose digital I/O pin/Comparator_A input
General-purpose digital I/O pin/Timer_A, clock signal TACLK input
General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output
General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output
General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output
General-purpose digital I/O pin/SMCLK signal output
General-purpose digital I/O pin/Timer_A, compare: Out0 output
General-purpose digital I/O pin/Timer_A, compare: Out1 output
General-purpose digital I/O pin/Timer_A, compare: Out2 output
General-purpose digital I/O pin/ACLK output/Comparator_A input
General-purpose digital I/O pin/Timer_A, clock signal at INCLK/Comparator_A input
General-purpose digital I/O pin/Comparator_A output/Timer_A, capture: CCI0B
input/Comparator_A input
General-purpose digital I/O pin/Comparator_A input/Timer_A, compare: Out1 output
General-purpose digital I/O pin/Comparator_A input/Timer_A, compare: Out2 output
General-purpose digital I/O pin/input for external resistor defining the DCO nominal
frequency/Comparator_A input
General-purpose digital I/O pin/USCIB0 slave transmit enable/USCIA clock input/output
I/O General-purpose digital I/O pin/USCIA0 transmit data output in UART mode, slave data in/master
out in SPI mode
I/O General-purpose digital I/O pin/USCIA0 receive data input in UART mode, slave data out/master
in in SPI mode
I/O General-purpose digital I/O pin
I/O General-purpose digital I/O pin
I/O General-purpose digital I/O pin/Timer_B, capture: CCI0A input, compare: Out0 output
I/O General-purpose digital I/O pin/Timer_B, capture: CCI1A input, compare: Out1 output
I/O General-purpose digital I/O pin/Timer_B, capture: CCI2A input, compare: Out2 output
I/O General-purpose digital I/O pin/Timer_B, capture: CCI0B input, compare: Out0 output
I/O General-purpose digital I/O pin/Timer_B, capture: CCI1B input, compare: Out1 output
I/O General-purpose digital I/O pin/Timer_B, compare: Out2 output
I/O General-purpose digital I/O pin/switch all PWM digital outputs to high impedance - Timer_B3: TB0
to TB2/ACLK output
I/O General-purpose digital I/O pin/input clock TBCLK - Timer_B3
I/O Test data output port. TDO/TDI data output or programming data input terminal
I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
I Test mode select. TMS is used as an input port for device programming and test.
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MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
Terminal Functions (Continued)
NAME
TCK
RST/NMI
D/AVSS
AVCC
QFN Pad
Reserved
TERMINAL
DESCRIPTION
BGA QFN I/O
C1 37
I Test clock. TCK is the clock input port for device programming and test.
C2 38
I Reset input, nonmaskable interrupt input port.
B1 39
Digital/Analog supply voltage, negative terminal.
A1 40
Analog supply voltage, positive terminal.
NA NA QFN package pad connection to D/AVSS recommended.
A4
NA BGA package GND balls. Connection to DVSS/AVSS is recommended.
B2
C3
D3
D4
D5
E3
E4
E5
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MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
short-form description
CPU
ISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in conjunction with seven addressing modes for source
operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
The MSP430 CPU has a 16-bit R
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
Constant Generator
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; Table 2 shows the address
modes.
SR/CG1/R2
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
Single operands, destination only
Relative jump, un/conditional
e.g., ADD R4,R5
e.g., CALL R8
e.g., JNE
R4 + R5 - - - > R5
PC - - >(TOS), R8-- - > PC
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE S D
SYNTAX
Register
F F
MOV Rs,Rd
Indexed
F F MOV X(Rn),Y(Rm)
Symbolic (PC relative) F F
MOV EDE,TONI
Absolute
F F MOV &MEM,&TCDAT
Indirect
F
MOV @Rn,Y(Rm)
Indirect
F
MOV @Rn+,Rm
autoincrement
Immediate
F
MOV #X,TONI
NOTE : S = source
D = destination
8
EXAMPLE
MOV R10,R11
MOV 2(R5),6(R6)
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
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OPERATION
R10 - - > R11
M(2+R5)-- - > M(6+R6)
M(EDE) - - > M(TONI)
M(MEM) - - > M(TCDAT)
M(R10) - - > M(Tab+R6)
M(R10) - - > R11
R10 + 2-- - > R10
#45 - - > M(TONI)
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D Active mode (AM)
-- All clocks are active
D Low-power mode 0 (LPM0)
-- CPU is disabled
-- ACLK and SMCLK remain active
-- MCLK is disabled
D Low-power mode 1 (LPM1)
-- CPU is disabled
-- ACLK and SMCLK remain active
-- MCLK is disabled
-- DCO’s dc generator is disabled if DCO not used in active mode
D Low-power mode 2 (LPM2)
-- CPU is disabled
-- MCLK and SMCLK are disabled
-- DCO’s dc generator remains enabled
-- ACLK remains active
D Low-power mode 3 (LPM3)
-- CPU is disabled
-- MCLK and SMCLK are disabled
-- DCO’s dc generator is disabled
-- ACLK remains active
D Low-power mode 4 (LPM4)
-- CPU is disabled
-- ACLK is disabled
-- MCLK and SMCLK are disabled
-- DCO’s dc generator is disabled
-- Crystal oscillator is stopped
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MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0xFFFF to 0xFFC0.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE
Power-up
External Reset
Watchdog
Flash key violation
PC out of range (see Note 1)
NMI
Oscillator Fault
Flash memory access violation
Timer_B3
Timer_B3
Comparator_A+
Watchdog timer
Timer_A3
Timer_A3
USCI_A0/USCI_B0 Receive
USCI_B0 I2C Status
USCI_A0/USCI_B0 Transmit
USCI_B0 I2C Receive / Transmit
I/O port P2 (eight flags)
I/O port P1 (eight flags)
INTERRUPT FLAG
PORIFG
RSTIFG
WDTIFG
KEYV
(see Note 2)
NMIIFG
OFIFG
ACCVIFG
(see Notes 2 and 6)
TBCCR0 CCIFG (see Note 3)
TBCCR1 and TBCCR2,
CCIFGs, TBIFG
(see Notes 2 and 3)
CAIFG
WDTIFG
TACCR0 CCIFG (see Note 3)
TACCR1 CCIFG,
TACCR2 CCIFG,
TAIFG (see Notes 2 and 3)
UCA0RXIFG, UCB0RXIFG
(see Notes 2 and 4)
UCA0TXIFG, UCB0TXIFG
(see Notes 2 and 5)
SYSTEM INTERRUPT
Reset
WORD ADDRESS
0xFFFE
PRIORITY
31, highest
(non)-maskable
(non)-maskable
(non)-maskable
0xFFFC
30
maskable
0xFFFA
29
maskable
0xFFF8
28
maskable
maskable
maskable
0xFFF6
0xFFF4
0xFFF2
27
26
25
maskable
0xFFF0
24
maskable
0xFFEE
23
maskable
0xFFEC
22
P2IFG.0 to P2IFG.7
(see Notes 2 and 3)
P1IFG.0 to P1IFG.7
(see Notes 2 and 3)
maskable
0xFFEA
0xFFE8
0xFFE6
21
20
19
maskable
0xFFE4
18
0xFFE2
17
0xFFE0
16
(see Note 7)
0xFFDE
15
(see Note 8)
0xFFDC-- 0xFFC0
14-- 0, lowest
NOTES: 1. A reset is executed if the CPU tries to fetch instructions from within the module register memory address range (0x0000 to 0x01FF).
2. Multiple source flags.
3. Interrupt flags are located in the module.
4. In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
5. In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
6. Non-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot.
Non-maskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.
7. This location is used as bootstrap loader security key (BSLSKEY).
A 0xAA55 at this location disables the BSL completely.
A zero (0h) disables the erasure of the flash if an invalid password is supplied.
8. The interrupt vectors at addresses 0xFFDC to 0xFFC0 are not used in this device and can be used for regular program code if
necessary.
10
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MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
special function registers
Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits
not allocated to a functional purpose are not physically present in the device. This arrangement provides simple
software access.
interrupt enable 1 and 2
Address
00h
WDTIE
OFIE
NMIIE
ACCVIE
7
6
5
ACCVIE
rw-- 0
4
NMIIE
rw-- 0
3
2
1
OFIE
rw-- 0
0
WDTIE
rw-- 0
Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog
Timer is configured in interval timer mode.
Oscillator fault enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
Address
01h
7
6
5
UCA0RXIE
UCA0TXIE
UCB0RXIE
UCB0TXIE
USCI_A0 receive interrupt enable
USCI_A0 transmit interrupt enable
USCI_B0 receive interrupt enable
USCI_B0 transmit interrupt enable
4
3
2
1
0
UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE
rw-- 0
rw-- 0
rw-- 0
rw-- 0
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MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
interrupt flag register 1 and 2
Address
02h
7
WDTIFG
6
5
4
NMIIFG
rw-- 0
1
OFIFG
rw-- 1
0
WDTIFG
rw-- (0)
CC
CC
PORIFG
NMIIFG
CC
Address
7
6
5
03h
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
4
3
UCB0TX
IFG
rw-- 0
USCI_A0 receive interrupt flag
USCI_A0 transmit interrupt flag
USCI_B0 receive interrupt flag
USCI_B0 transmit interrupt flag
rw:
rw-0,1:
rw-(0,1):
Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device
12
2
PORIFG
rw-- (1)
Set on watchdog timer overflow or security key violation.
Reset on V power-up or a reset condition at RST/NMI pin in reset mode.
Flag set on oscillator fault
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on
V power up
Power-on interrupt flag. Set on V power up.
Set via RST/NMI pin
OFIFG
RSTIFG
Legend
3
RSTIFG
rw-- (0)
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2
UCB0RX
IFG
rw-- 0
1
UCA0TX
IFG
rw-- 0
0
UCA0RX
IFG
rw-- 0
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
memory organization
Memory
Main: interrupt vector
Main: code memory
Information memory
Boot memory
RAM
Peripherals
Size
Flash
Flash
Size
Flash
Size
ROM
Size
16-bit
8-bit
8-bit SFR
MSP430F2330
8KB Flash
0xFFFF - 0xFFC0
0xFFFF - 0xE000
256 Byte
0x10FF - 0x1000
1KB
0x0FFF - 0x0C00
1KB Byte
0x5FF - 0x0200
0x01FF - 0x0100
0x00FF - 0x0010
0x000F - 0x0000
MSP430F2350
16KB Flash
0xFFFF - 0xFFC0
0xFFFF - 0xC000
256 Byte
0x10FF - 0x1000
1KB
0x0FFF - 0x0C00
2KB Byte
0x9FF - 0x0200
0x01FF - 0x0100
0x00FF - 0x0010
0x000F - 0x0000
MSP430F2370
32KB
0xFFFF - 0xFFC0
0xFFFF - 0x8000
256 Byte
0x10FF - 0x1000
1KB
0x0FFF - 0x0C00
2KB
0x09FF - 0x0200
0x01FF - 0x0100
0x00FF - 0x0010
0x000F - 0x0000
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the MSP430 Memory Programming User’s
Guide, literature number SLAU265.
BSL FUNCTION
Data transmit
Data receive
YFF PACKAGE PINS
C4 - P1.1
C6 - P2.2
RHA PACKAGE PINS
5 - P1.1
14 - P2.2
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A to D can be erased individually, or as a group with segments 0 to n.
Segments A to D are also called information memory.
D Segment A contains calibration data. After reset segment A is protected against programming or erasing.
It can be unlocked but care should be taken not to erase this segment if the calibration data is required.
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13
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User’s Guide, literature number
SLAU144.
oscillator and system clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very low power, low frequency oscillator, an internal digitally-controlled oscillator (DCO),
and a high-frequency crystal oscillator. The basic clock module is designed to meet the requirements of both
low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and
stabilizes in less than 1 µs. The basic clock module provides the following clock signals:
D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, or the internal very
low power LF oscillator.
D Main clock (MCLK), the system clock used by the CPU.
D Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules.
The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.
DCO CALIBRATION DATA
(PROVIDED FROM FACTORY IN FLASH INFO MEMORY SEGMENT A)
DCO FREQUENCY
CALIBRATION
SIZE
ADDRESS
REGISTER
1 MHz
8 MHz
12 MHz
16 MHz
CALBC1_1MHZ
CALDCO_1MHZ
CALBC1_8MHZ
CALDCO_8MHZ
CALBC1_12MHZ
CALDCO_12MHZ
CALBC1_16MHZ
CALDCO_16MHZ
byte
byte
byte
byte
byte
byte
byte
byte
0x10FF
0x10FE
0x10FD
0x10FC
0x10FB
0x10FA
0x10F9
0x10F8
brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off.
digital I/O
There are four 8-bit I/O ports implemented—ports P1 through P4:
D All individual I/O bits are independently programmable.
D Any combination of input, output, and interrupt conditions is possible.
D Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
D Read/write access to port-control registers is supported by all instructions.
D Each I/O has an individually programmable pullup/pulldown resistor.
The MSP430F23x0 devices provide 32 total port I/O pins available externally. See the device pinout for more
information.
14
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MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
watchdog timer (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.
hardware multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs 16×16,
16×8, 8×16, and 8×8 bit operations. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
Comparator_A+
The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_A3 SIGNAL CONNECTIONS
INPUT PIN NUMBER
YFF
RHA
B4 - P1.0
4 - P1.0
C7 - P2.1
C4 - P1.1
C6 - P2.2
13 - P2.1
5 - P1.1
14 - P2.2
A5 - P1.2
6 - P1.2
B5 - P1.3
7 - P1.3
DEVICE INPUT
SIGNAL
TACLK
ACLK
SMCLK
TAINCLK
TA0
TA0
VSS
VCC
TA1
CAOUT (internal)
VSS
VCC
TA2
ACLK (internal)
VSS
VCC
MODULE
MODULE
INPUT NAME BLOCK
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
VCC
CCI1A
CCI1B
GND
VCC
CCI2A
CCI2B
GND
VCC
Timer
CCR0
CCR1
CCR2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MODULE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
YFF
RHA
NA
TA0
TA1
TA2
C4 - P1.1
B6 - P1.5
5 - P1.1
9 - P1.5
A5 - P1.2
A7 - P1.6
D7 - P2.3
6 - P1.2
10 - P1.6
15 - P2.3
B5 - P1.3
B7 - P1.7
D6 - P2.4
7 - P1.3
11 - P1.7
16 - P2.4
15
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
timer_B3
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
INPUT PIN NUMBER
YFF
RHA
E2 - P4.7
33 - P4.7
F4 - P4.0
F3 - P4.3
26 - P4.0
29 - P4.3
G3 - P4.1
G1 - P4.4
27 - P4.1
30 - P4.4
G2 - P4.2
28 - P4.2
TIMER_B3 SIGNAL CONNECTIONS
MODULE
MODULE
DEVICE INPUT
MODULE
INPUT
OUTPUT
SIGNAL
BLOCK
NAME
SIGNAL
TBCLK
TACLK
ACLK
ACLK
Timer
NA
SMCLK
SMCLK
TBCLK
INCLK
TB0
CCI0A
TB0
CCI0B
CCR0
TB0
VSS
GND
VCC
VCC
TA1
CCI1A
TB1
CCI1B
CCR1
TB1
VSS
GND
VCC
VCC
TB2
CCI2A
ACLK (internal)
CCI2B
CCR2
TB2
VSS
GND
VCC
VCC
OUTPUT PIN NUMBER
YFF
RHA
F4 - P4.0
F3 - P4.3
26 - P4.0
29 - P4.3
G3 - P4.1
G1 - P4.4
27 - P4.1
30 - P4.4
G2 - P4.2
F1 - P4.5
28 - P4.2
31 - P4.5
universal serial communications interface (USCI)
The USCI module is used for serial data communication. The USCI module supports synchronous
communication protocols like SPI (3 pin or 4 pin) or I2C and asynchronous communication protocols like UART,
enhanced UART with automatic baudrate detection (LIN), and IrDA.
USCI A0 provides support for SPI (3 pin or 4 pin), UART, enhanced UART and IrDA.
USCI B0 provides support for SPI (3 pin or 4 pin) and I2C.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
peripheral file map
Timer_B3
Timer_A3
Flash Memory
Hardware Multiplier
Watchdog Timer+
USCI_B0
USCI_A0
PERIPHERALS WITH WORD ACCESS
Capture/compare register
Capture/compare register
Capture/compare register
Timer_B register
Capture/compare control
Capture/compare control
Capture/compare control
Timer_B control
Timer_B interrupt vector
Capture/compare register
Capture/compare register
Capture/compare register
Timer_A register
Capture/compare control
Capture/compare control
Capture/compare control
Timer_A control
Timer_A interrupt vector
Flash control 3
Flash control 2
Flash control 1
Sum extend
Result high word
Result low word
Second operand
Multiply signed +accumulate/operand1
Multiply+accumulate/operand1
Multiply signed/operand1
Multiply unsigned/operand1
Watchdog/timer control
TBCCR2
TBCCR1
TBCCR0
TBR
TBCCTL2
TBCCTL1
TBCCTL0
TBCTL
TBIV
TACCR2
TACCR1
TACCR0
TAR
TACCTL2
TACCTL1
TACCTL0
TACTL
TAIV
FCTL3
FCTL2
FCTL1
SUMEXT
RESHI
RESLO
OP2
MACS
MAC
MPYS
MPY
WDTCTL
0x0196
0x0194
0x0192
0x0190
0x0186
0x0184
0x0182
0x0180
0x011E
0x0176
0x0174
0x0172
0x0170
0x0166
0x0164
0x0162
0x0160
0x012E
0x012C
0x012A
0x0128
0x013E
0x013C
0x013A
0x0138
0x0136
0x0134
0x0132
0x0130
0x0120
USCI_B0 transmit buffer
USCI_B0 receive buffer
USCI_B0 status
USCI_B0 bit rate control 1
USCI_B0 bit rate control 0
USCI_B0 control 1
USCI_B0 control 0
USCI_B0 I2C slave address
USCI_B0 I2C own address
USCI_A0 transmit buffer
USCI_A0 receive buffer
USCI_A0 status
USCI_A0 modulation control
USCI_A0 baud rate control 1
USCI_A0 baud rate control 0
USCI_A0 control 1
USCI_A0 control 0
USCI_A0 IrDA receive control
USCI_A0 IrDA transmit control
USCI_A0 auto baud rate control
UCB0TXBUF
UCB0RXBUF
UCB0STAT
UCB0BR1
UCB0BR0
UCB0CTL1
UCB0CTL0
UCB0SA
UCB0OA
UCA0TXBUF
UCA0RXBUF
UCA0STAT
UCA0MCTL
UCA0BR1
UCA0BR0
UCA0CTL1
UCA0CTL0
UCA0IRRCTL
UCA0IRTCTL
UCA0ABCTL
0x06F
0x06E
0x06D
0x06B
0x06A
0x069
0x068
0x011A
0x0118
0x0067
0x0066
0x0065
0x0064
0x0063
0x0062
0x0061
0x0060
0x005F
0x005E
0x005D
PERIPHERALS WITH BYTE ACCESS
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17
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
Basic Clock System+
Port P4
Port P3
Port P2
Port P1
Special Function
18
PERIPHERALS WITH BYTE ACCESS (continued)
Basic clock system control 3
Basic clock system control 2
Basic clock system control 1
DCO clock frequency control
Port P4 resistor enable
Port P4 selection
Port P4 direction
Port P4 output
Port P4 input
Port P3 resistor enable
Port P3 selection
Port P3 direction
Port P3 output
Port P3 input
Port P2 resistor enable
Port P2 selection
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt flag
Port P2 direction
Port P2 output
Port P2 input
Port P1 resistor enable
Port P1 selection
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt flag
Port P1 direction
Port P1 output
Port P1 input
SFR interrupt flag 2
SFR interrupt flag 1
SFR interrupt enable 2
SFR interrupt enable 1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
BCSCTL3
BCSCTL2
BCSCTL1
DCOCTL
P4REN
P4SEL
P4DIR
P4OUT
P4IN
P3REN
P3SEL
P3DIR
P3OUT
P3IN
P2REN
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
P1REN
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
IFG2
IFG1
IE2
IE1
0x0053
0x0058
0x0057
0x0056
0x0011
0x001F
0x001E
0x001D
0x001C
0x0010
0x001B
0x001A
0x0019
0x0018
0x002F
0x002E
0x002D
0x002C
0x002B
0x002A
0x0029
0x0028
0x0027
0x0026
0x0025
0x0024
0x0023
0x0022
0x0021
0x0020
0x0003
0x0002
0x0001
0x0000
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
absolute maximum ratings (see Note 1)
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to + 4.1 V
Voltage applied to any pin (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to VCC+0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature: Unprogrammed device (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . --55°C to 150°C
Programmed device (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . --40°C to 105°C
NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
2. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage
is applied to the TDI/TCLK pin when blowing the JTAG fuse.
3. Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with
peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
recommended operating conditions
PARAMETER
MIN
1.8
2.2
0.0
- 40
- 40
Supply voltage during program execution, VCC
Supply voltage during flash memory programming, V CC
Supply voltage, VSS
MAX UNITS
3.6
V
3.6
V
0.0
V
85 °C
105 °C
AVCC = DVCC = VCC (see Note 1)
AVCC = DVCC = VCC (see Note 1)
AVSS = DVSS = VSS
I version
Operating free-air
free air temperature range,
range TA
T version
VCC = 1.8 V,
dc
4.15
Duty cycle = 50% ±10%
VCC = 2.7 V,
Processor frequency fSYSYTEM (Maximum MCLK frequency)
dc
12 MHz
Duty cycle = 50% ±10%
(see Notes 2 and 3 and Figure
g 1)
VCC ≥ 3.3 V,
dc
16
Duty cycle = 50% ±10%
NOTES: 1. It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AV CC and DVCC can
be tolerated during power-up.
2. The MSP430 CPU is clocked directly with MCLK.
Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency.
3. Modules might have a different maximum input clock specification. See the specification of the respective module in this datasheet.
Legend:
16 MHz
z
H
M
- 12 MHz
yc
ne
uq
er
F 7.5 MHz
m
et
sy
S 4.15 MHz
Supply voltage range
during flash memory
programming
Supply voltage range
during program execution
1.8 V
2.2 V
2.7 V
3.3 V 3.6 V
Supply Voltage - V
NOTE : Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum V CC of 2.2 V.
Figure 1. Operating Area
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
19
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
active mode supply current (into VCC) excluding external current (see Notes 1 and 2)
PARAMETER
IAM, 1MHz
IAM, 1MHz
IAM, 4kHz
IAM,100kHz
Active mode (AM)
current (1MHz)
Active mode (AM)
current (1MHz)
Active mode (AM)
current (4kHz)
Active mode (AM)
current (100kHz)
TEST CONDITIONS
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 32,768 Hz,
Program executes from flash,
BCSCTL1 = CALBC1_1MHZ,
CALBC1 1MHZ
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 32,768 Hz,
Program executes in RAM,
BCSCTL1 = CALBC1_1MHZ,
CALBC1 1MHZ
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
fMCLK = fSMCLK =
fACLK = 32,768 Hz/8 = 4,096 Hz,
fDCO = 0Hz,
Program executes in flash,
SELMx = 11, SELS = 1,
DIVMx = DIVSx = DIVAx = 11,
CPUOFF = 0, SCG0 = 1, SCG1 = 0,
OSCOFF = 0
fMCLK = fSMCLK = fDCO(0, 0) ≈ 100kHz,
fACLK = 0Hz,
0Hz
Program executes in flash,
RSELx = 0, DCOx = 0,
CPUOFF = 0,
0 SCG0 = 0,
0 SCG1 = 0,
0
OSCOFF = 1
TA
VCC
2.2 V
MIN
TYP
270
370
µA
3V
390
2.2 V
226
550
µA
3V
318
- 40_C to 85_C
2.2 V
2
105_C
2.2 V
- 40_C to 85_C
3V
105_C
3V
- 40_C to 85_C
105_C
- 40_C to 85_C
105_C
2.2 V
2.2 V
3V
3V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6
14
3
9
µA
17
60
72
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
2. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF.
The internal and external load capacitance is chosen to closely match the required 9 pF.
20
MAX UNIT
85
95
95
105
µA
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
typical characteristics - active mode supply current (into DVCC + AVCC)
8.0
5.0
DCO = 16 MHz
f
7.0
A
m
-t
ne
rr
uC
ed
o
M
ev
it
cA
6.0
DCO
f
5.0
4.0
= 12 MHz
DCO = 8 MHz
f
3.0
2.0
A = 85 °C
T
A 4.0
m
-t
ne
rr 3.0
uC
ed
o
M 2.0
ev
it
cA
A = 25 °C
T
CC = 3 V
V
A = 85 °C
T
A = 25 °C
T
1.0
1.0
0.0
1.5
CC = 2.2 V
V
DCO = 1 MHz
f
2.0
2.5
3.0
3.5
VCC - Supply Voltage - V
4.0
Figure 2. Active mode current vs VCC, TA = 25°C
0.0
0.0
4.0
DCO
f
8.0
12.0
16.0
-- DCO Frequency -- MHz
Figure 3. Active mode current vs DCO frequency
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
21
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
low power mode supply currents (into VCC) excluding external current (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
MCLK = 0MHz,
f
Low-power mode
0 (LPM0) current,
current
see Note 3
fSMCLK == ffDCO == 11 MHz,
f
MHz
fACLK = 32,768 Hz,
BCSCTL1 = CALBC1_1MHZ,
CALBC1 1MHZ
DCOCTL = CALDCO_1MHZ,
_
CPUOFF = 1,
1 SCG0 = 0,
0 SCG1 = 0,
0
OSCOFF = 0
fMCLK = 0MHz,
fSMCLK = fDCO(0, 0) ≈ 100kHz
100kHz,
fACLK = 0Hz,
RSELx = 0, DCOx = 0,
CPUOFF = 1,
1 SCG0 = 0,
0 SCG1 = 0,
0
OSCOFF = 1
fMCLK = fSMCLK = 0MHz, fDCO = 1 MHz,
fACLK = 32,768
32 768 Hz,
Hz
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1,
1 SCG0 = 0,
0 SCG1 = 1,
1
OSCOFF = 0
TA
--40°C to 85
VCC
_C
22V
2.2
TYP
68
MAX UNIT
84 µA
90
µA
88
110
µA
105_C
- 40°C to 85_C
36
22V
2.2
Low-power mode
105_C
ILPM0, 100kHz 0 (LPM0) current,
current
- 40°C to 85_C
40
see Note 3
3V
105_C
- 40°C to 85_C
20
22V
2.2
Low-power mode
105_C
ILPM2
2 (LPM2) current,
current
- 40°C to 85_C
23
see Note 4
3V
105_C
- 40°C to 25°C
0.7
85°C
2.2 V
= fSMCLK = 0MHz,
0MHz
Low-power mode ffDCO ==fMCLK
105°C
32,768
Hz,
ACLK
ILPM3,LFXT1 3 (LPM3) current,
current CPUOFF = 1, SCG0 = 1, SCG1 = 1,
- 40°C to 25°C
0.85
see Note 4
OSCOFF = 0
85°C
3V
105°C
- 40°C to 25°C
0.25
85°C
2.2 V
fMCLK = fSMCLK = 0MHz,
0MHz
Low-power mode ffDCO =from
105°C
internal LF oscillator (VLO),
ACLK
ILPM3,VLOO
3 current,
current (LPM3) CPUOFF
=
1,
SCG0
=
1,
SCG1
=
1,
40
°
C to 25°C
0.35
see Note 4
OSCOFF = 0
85°C
3V
105°C
- 40°C
25°C
2 2V
2.2V
85°C
1.7
f
=
f
=
f
=
0MHz
0MHz,
SMCLK
Low-power mode fDCO = MCLK
105
°
C
ACLK 0Hz,
4 (LPM4) current,
current CPUOFF
ILPM4
= 1, SCG0 = 1, SCG1 = 1,
- 40°C
see Note 5
OSCOFF = 1
25°C
3V
85°C
1.9
105°C
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
2. The currents are characterized with a Micro Crystal CC4V-- T1A SMD crystal with a load capacitance of 9 pF.
The internal and external load capacitance is chosen to closely match the required 9pF.
3. Current for brownout and WDT clocked by SMCLK included.
4. Current for brownout and WDT clocked by ACLK included.
5. Current for brownout included.
115
45
50
50
54
28
32
32
37
1.0
3.3
10
1.2
3.8
12
0.8
2.9
9
1.0
3.5
11
0.5
0.5
2.7
8.6
0.5
0.5
3
9
µA
ILPM0, 1MHz
22
105_C
MIN
- 40°C to 85_C
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3V
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
Schmitt-trigger inputs - Ports P1, P2, P3, P4, JTAG, RST/NMI, and XIN (see Note)
PARAMETER
TEST CONDITIONS
VCC
V
PPositive-going
iti
i input
i t threshold
th h ld
voltage
2.2 V
3V
V
Negative-going
N
ti
i input
i t threshold
th h ld
voltage
V
Input voltage hysteresis
(V - V )
2.2 V
3V
2.2 V
3V
IT+
IT--
hys
R
Pull
IT+
IT--
For pullup: V = V ,
For pulldown: V = V
V = V or V
Pullup/pulldown resistor
IN
C
Input capacitance
NOTE : XIN only in bypass mode.
I
IN
SS
20
SS
IN
MIN TYP
0.45
1.00
1.35
0.25
0.55
0.75
0.2
0.3
CC
35
5
CC
MAX UNIT
0.75 VCC
1.65
V
2.25
0.55 V
1.20
V
1.65
1.0
V
1.0
CC
50
kΩ
pF
inputs - Ports P1, P2
PARAMETER
TEST CONDITIONS
VCC
MIN TYP MAX UNIT
Port P1, P2: P1.x to P2.x, External
trigger puls width to set interrupt
t
External interrupt timing
2.2 V/3 V
20
ns
flag, (see Note)
NOTE : An external signal sets the interrupt flag every time the minimum interrupt puls width t is met. It may be set even with trigger signals
shorter than t .
(int)
(int)
(int)
leakage current - Ports P1, P2, P3 and P4
PARAMETER
TEST CONDITIONS
VCC
MIN TYP MAX UNIT
I
High-impedance leakage current
see Notes 1 and 2
2.2 V/3 V
±50
nA
NOTES: 1. The leakage current is measured with V SS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pull-- up/pull-- down resistor
is disabled.
lkg(Px.x)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
23
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
outputs -- Ports P1, P2, P3 and P4
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
I(OHmax) = - 1.5 mA (see Notes 1)
2.2 V
VCC - 0.25
VCC
2.2 V
VCC - 0.6
VCC
I(OHmax) = - 6 mA (see Notes 2)
High-level
High
level output
VOH
V
voltage
g
3V
VCC - 0.25
VCC
I(OHmax) = - 1.5 mA (see Notes 1)
I(OHmax) = - 6 mA (see Notes 2)
3V
VCC - 0.6
VCC
I(OLmax) = 1.5 mA (see Notes 1)
2.2 V
VSS
VSS+0.25
2.2 V
VSS
VSS+0.6
I(OLmax) = 6 mA (see Notes 2)
Low-level
Low
level output
VOL
V
voltage
I(OLmax) = 1.5 mA (see Notes 1)
3V
VSS
VSS+0.25
I(OLmax) = 6 mA (see Notes 2)
3V
VSS
VSS+0.6
NOTES: 1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±12 mA to hold the maximum
voltage drop specified.
2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±48 mA to hold the maximum
voltage drop specified.
output frequency -- Ports P1, P2, P3 and P4
PARAMETER
Port output frequency
(with load)
TEST CONDITIONS
VCC
MIN TYP
MAX UNIT
2.2
V
7.5 MHz
P1.4/SMCLK, CL = 20 pF, RL = 1 kΩ
fPx.y
(see Note 1 and 2)
3V
12 MHz
2.2 V
7.5 MHz
P1.4/SMCLK, CL = 20 pF
fPort_CLK
Clock output frequency P2.0/ACLK,
(see Note 2)
3V
16 MHz
NOTES: 1. A resistive divider with 2 times 0.5 k Ω between VCC and VSS is used as load. The output is connected to the center tap of the divider.
2. The output voltage reaches at least 10% and 90% V CC at the specified toggle frequency.
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- outputs
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
A
m
-t
ne
rr
uC
tu
tpu
O
le
ve
Lw
oL
la
ci
py
-T
L
IO
25.0
A
m
-t
ne
rr
uC
tu
pt
u
O
le
ve
Lw
oL
la
ci
py
T
L
IO
A = 25°C
CC = 2.2 V
T
V
P2.4
A = 85°C
20.0
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
T
15.0
10.0
5.0
0.0
50.0
CC = 3 V
V
A = 25°C
P2.4
T
40.0
A = 85°C
T
30.0
20.0
10.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
OL -- Low-Level Output Voltage -- V
1.0
0.0
P2.4
A = 85°C
T
A = 25°C
T
0.5
1.0
1.5
2.0
OH -- High-Level Output Voltage -- V
V
Figure 6
NOTE : One output loaded at a time.
3.0
3.5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
A 0.0
m
-t
ne
rr --10.0
uC
tu
tpu
O
le --20.0
ve
Lhg --30.0
iH
la
ci
py
T --40.0
H
IO
CC = 2.2 V
V
0.0
2.5
Figure 5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
--25.0
2.0
V
Figure 4
A
m
-t
ne --5.0
rr
uC
tu
tpu--10.0
O
le
ve
Lhg--15.0
iH
la
ci
py --20.0
T
H
IO
1.5
OL -- Low-Level Output Voltage -- V
V
2.5
CC = 3 V
V
P2.4
A = 85°C
T
A = 25°C
T
--50.0
0.0
0.5
OH
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1.0
1.5
2.0
2.5
3.0
3.5
-- High-Level Output Voltage -- V
Figure 7
25
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
POR/brownout reset (BOR) (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP MAX UNIT
(see Figure 8)
dVCC/dt ≤ 3 V/s
0.7 × V(B_IT--)
V
V(B_IT--)
(see Figure 8 through Figure 10)
dVCC/dt ≤ 3 V/s
1.71 V
Vhys(B_IT--)
(see Figure 8)
dVCC/dt ≤ 3 V/s
70
130 210 mV
td(BOR)
(see Figure 8)
2000 µs
Pulse length needed at RST/NMI pin to
t(reset)
2.2 V/3 V
2
µs
accepted reset internally
NOTES: 1. The current consumption of the brownout module is already included in the I CC current consumption data. The voltage level
V(B_IT--) + Vhys(B_IT--) is ≤ 1.8 V.
2. During power up, the CPU begins code execution following a period of t d(BOR) after VCC = V(B_IT--) + Vhys(B_IT--). The default DCO
settingsmustnotbechangeduntilVCC ≥ VCC(min), whereVCC(min) isthe minimumsupply voltagefor thedesired operatingfrequency.
VCC(start)
V
CC
V
hys(B_IT--)
V
(B_IT--)
CC(start)
V
1
0
t d(BOR)
Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- POR/brownout reset (BOR)
V
CC
2
CC
V
t
pw
3 V
= 3 V
Typical Conditions
V
)
p
o
r
d
(
C
C
V
1.5
1
V
CC(drop)
0.5
0
0.001
1
1000
1 ns
pw -- Pulse Width -- µs
t
1 ns
pw -- Pulse Width -- µs
t
Figure 9. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
V
CC
2
t
pw
3 V
CC = 3 V
V
V
)
p
o
r
d
(
C
C
V
1.5
Typical Conditions
1
V
CC(drop)
0.5
f
t = t
0
0.001
1
1000
pw -- Pulse Width -- µs
t
r
tr
f
tpw -- Pulse Width -- µs
t
Figure 10. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
27
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
main DCO characteristics
D All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
D DCO control bits DCOx have a step size as defined by parameter SDCO.
D Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency f
to:
DCO(RSEL,DCO)
f
average
is used for the remaining cycles. The frequency is an average equal
×f
= MOD × 32
f
×f
+(32−MOD) × f
DCO(RSEL,DCO)
DCO(RSEL,DCO)
DCO frequency
PARAMETER
VCC
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
S
DCO(0,0)
DCO(0,3)
DCO(1,3)
DCO(2,3)
DCO(3,3)
DCO(4,3)
DCO(5,3)
DCO(6,3)
DCO(7,3)
DCO(8,3)
DCO(9,3)
DCO(10,3)
DCO(11,3)
DCO(12,3)
DCO(13,3)
DCO(14,3)
DCO(15,3)
DCO(15,7)
RSEL
S
Duty cycle
DCO
28
TEST CONDITIONS
RSELx < 14
RSELx = 14
Supply voltage
RSELx = 15
DCO frequency (0, 0)
RSELx = 0, DCOx = 0, MODx = 0
DCO frequency (0, 3)
RSELx = 0, DCOx = 3, MODx = 0
DCO frequency (1, 3)
RSELx = 1, DCOx = 3, MODx = 0
DCO frequency (2, 3)
RSELx = 2, DCOx = 3, MODx = 0
DCO frequency (3, 3)
RSELx = 3, DCOx = 3, MODx = 0
DCO frequency (4, 3)
RSELx = 4, DCOx = 3, MODx = 0
DCO frequency (5, 3)
RSELx = 5, DCOx = 3, MODx = 0
DCO frequency (6, 3)
RSELx = 6, DCOx = 3, MODx = 0
DCO frequency (7, 3)
RSELx = 7, DCOx = 3, MODx = 0
DCO frequency (8, 3)
RSELx = 8, DCOx = 3, MODx = 0
DCO frequency (9, 3)
RSELx = 9, DCOx = 3, MODx = 0
DCO frequency (10, 3) RSELx = 10, DCOx = 3, MODx = 0
DCO frequency (11, 3) RSELx = 11, DCOx = 3, MODx = 0
DCO frequency (12, 3) RSELx = 12, DCOx = 3, MODx = 0
DCO frequency (13, 3) RSELx = 13, DCOx = 3, MODx = 0
DCO frequency (14, 3) RSELx = 14, DCOx = 3, MODx = 0
DCO frequency (15, 3) RSELx = 15, DCOx = 3, MODx = 0
DCO frequency (15, 7) RSELx = 15, DCOx = 7, MODx = 0
Frequency step between S = f
/f
range RSEL and RSEL+1
Frequency step between S = f
/f
tap DCO and DCO+1
Measured at P1.4/SMCLK
RSEL
DCO
DCO(RSEL+1,DCO)
DCO(RSEL,DCO+1)
+
DCO(RSEL,DCO
DCO(RSEL,DCO)
DCO(RSEL,DCO)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1)
+
DCO(RSEL,DCO
VCC
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
3V
3V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
1)
MIN
1.8
2.2
3.0
0.06
0.07
0.10
0.14
0.20
0.28
0.39
0.54
0.80
1.10
1.60
2.50
3.00
4.30
6.00
8.60
12.0
16.0
TYP
MAX
3.6
3.6
3.6
0.14
0.17
0.20
0.28
0.40
0.54
0.77
1.06
1.50
2.10
3.00
4.30
5.50
7.30
9.60
13.9
18.5
26.0
1.55
1.05 1.08 1.12
40 50 60
UNIT
V
V
V
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ratio
%
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
electrical
characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
calibrated DCO frequencies - tolerance at calibration
PARAMETER
Frequency tolerance at calibration
fCAL(1MHz)
fCAL(8MHz)
fCAL(12MHz)
fCAL(16MHz)
TEST CONDITIONS
BCSCTL1= CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
BCSCTL1= CALBC1_8MHZ,
8-MHz calibration value DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
BCSCTL1= CALBC1_12MHZ,
12-MHz calibration value DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
BCSCTL1= CALBC1_16MHZ,
16-MHz calibration value DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
1-MHz calibration value
TA
25°C
VCC
3V
MIN TYP MAX UNIT
- 1 ±0.2
+1 %
25°C
3V
0.990
1 1.010 MHz
25°C
3V
7.920
8 8.080 MHz
25°C
3V
11.88
12 12.12 MHz
25°C
3V
15.84
16 16.16 MHz
VCC
3.0 V
3.0 V
3.0 V
3.0 V
2.2 V
3.0 V
3.6 V
2.2 V
3.0 V
3.6 V
2.2 V
3.0 V
3.6 V
3.0 V
MIN TYP
- 2.5 ±0.5
- 2.5
±1
- 2.5
±1
-3
±2
0.970
1
0.975
1
0.970
1
7.760
8
7.800
8
7.600
8
11.64
12
11.64
12
11.64
12
15.52
16
15.00
16
calibrated DCO frequencies - tolerance over temperature 0°C to 85°C
PARAMETER
1-MHz tolerance over temperature
8-MHz tolerance over temperature
12-MHz tolerance over temperature
16-MHz tolerance over temperature
TEST CONDITIONS
TA
0°C to 85°C
0°C to 85°C
0°C to 85°C
0°C to 85°C
fCAL(1MHz)
11-MHz
MHz calibration value
BCSCTL1= CALBC1_1MHZ,
CALBC1 1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
0°C to 85°C
fCAL(8MHz)
88-MHz
MHz calibration value
BCSCTL1= CALBC1_8MHZ,
CALBC1 8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
0°C to 85°C
BCSCTL1= CALBC1_12MHZ,
CALBC1 12MHZ,
fCAL(12MHz) 12
12-MHz
MHz calibration value DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
0°C to 85°C
BCSCTL1= CALBC1_16MHZ,
CALDCO 16MHZ
fCAL(16MHz) 16-MHz
16 MHz calibration value DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
0°C to 85°C
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3.6 V
MAX
+2.5
+2.5
+2.5
+3
1.030
1.025
1.030
8.400
8.200
8.240
12.36
12.36
12.36
16.48
16.48
UNIT
%
%
%
%
MHz
MHz
MHz
MHz
29
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
CC
TA
25°C
25°C
25°C
25°C
VCC
1.8 V to 3.6 V
1.8 V to 3.6 V
2.2 V to 3.6 V
3.0 V to 3.6 V
MIN TYP MAX UNIT
-3
±2
+3 %
-3
±2
+3 %
-3
±2
+3 %
-6
±2
+3 %
25°C
1.8 V to 3.6 V
0.970
1 1.030 MHz
25°C
1.8 V to 3.6 V
7.760
8 8.240 MHz
25°C
2.2 V to 3.6 V
11.64
12 12.36 MHz
25°C
3.0 V to 3.6 V
15.00
16 16.48 MHz
TA
- 40°C to 105°C
- 40°C to 105°C
- 40°C to 105°C
- 40°C to 105°C
VCC
1.8 V to 3.6 V
1.8 V to 3.6 V
2.2 V to 3.6 V
3.0 V to 3.6 V
MIN TYP MAX UNIT
-5
±2
+5 %
-5
±2
+5 %
-5
±2
+5 %
-6
±3
+6 %
calibrated DCO frequencies -- tolerance over supply voltage V
PARAMETER
1 MHz tolerance over VCC
8 MHz tolerance over VCC
12 MHz tolerance over VCC
16 MHz tolerance over VCC
fCAL(1MHz)
1MHz calibration
value
fCAL(8MHz)
8MHz calibration
value
calibration
fCAL(12MHz) 12MHz
value
calibration
fCAL(16MHz) 16MHz
value
TEST CONDITIONS
BCSCTL1= CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
BCSCTL1= CALBC1_8MHZ ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
BCSCTL1= CALBC1_12MHZ ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
BCSCTL1= CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
calibrated DCO frequencies -- overall tolerance
PARAMETER
1-MHz tolerance overall
8-MHz tolerance overall
12-MHz tolerance overall
16-MHz tolerance overall
fCAL(1MHz)
1-MHz calibration
value
fCAL(8MHz)
8-MHz calibration
value
calibration
fCAL(12MHz) 12-MHz
value
calibration
fCAL(16MHz) 16-MHz
value
30
TEST CONDITIONS
BCSCTL1= CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time: 5 ms
BCSCTL1= CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time: 5 ms
BCSCTL1= CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time: 5 ms
BCSCTL1= CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time: 2 ms
- 40°C to 105°C 1.8 V to 3.6 V
0.950
1 1.050 MHz
- 40°C to 105°C 1.8 V to 3.6 V
7.600
8 8.400 MHz
- 40°C to 105°C 2.2 V to 3.6 V
11.40
12 12.60 MHz
- 40°C to 105°C 3.0 V to 3.6 V
15.00
16 17.00 MHz
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
1.03
1.02
z
H
M
y
c
n
e
u
q
e
r
F
A = 105 °C
T
1.01
A = 85 °C
T
1.00
A = 25 °C
T
0.99
A = --40 °C
T
0.98
0.97
1.5
2.0
2.5
3.0
3.5
4.0
CC -- Supply Voltage -- V
V
Figure 11. Calibrated 1-MHz Frequency vs VCC
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
31
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
,electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
wake-up from lower power modes (LPM3/4)
PARAMETER
t
DCO,LPM3/4
TEST CONDITIONS
BCSCTL1= CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ
BCSCTL1= CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ
BCSCTL1= CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ
BCSCTL1= CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ
DCO clock wake
wake-up
up time from
LPM3/4 (see Note 1)
VCC
MIN
TYP
MAX UNIT
2.2 V/3 V
2
2.2 V/3 V
1.5
2.2 V/3 V
1
3V
1
µs
CPU wake-up time from LPM3/4
1/f
+
(see Note 2)
t
NOTES: 1. The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g., port interrupt) to the first clock edge
observable externally on a clock pin (MCLK or SMCLK).
2. Parameter applicable only if DCOCLK is used for MCLK.
t
MCLK
CPU,LPM3/4
Clock,LPM3/4
typical characteristics - DCO clock wake-up time from LPM3/4
10.00
su
e
im
T
ek
a
W 1.00
O
CD
RSELx = 0...11
RSELx = 12...15
0.10
0.10
1.00
10.00
DCO Frequency -- MHz
Figure 12. Clock Wake-Up Time From LPM3 vs DCO Frequency
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
OSC (see Note)
PARAMETER
TEST CONDITIONS
VCC
DCOR
=
1,
2.2 V
DCO output frequency RSELx = 4,
fDCO,ROSC
4 DCOx = 3,
3 MODx = 0,
0
with ROSC
3V
TA = 25°C
DCOR
=
1,
Dt
Temperature drift
2.2 V/3 V
RSELx = 4, DCOx = 3, MODx = 0
DCOR = 1,
DV
Drift with VCC
2.2 V/3 V
RSELx = 4, DCOx = 3, MODx = 0
NOTE : ROSC = 100kΩ. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and T K = ±50ppm/°C.
DCO with external resistor R
MIN
TYP
1.8
1.95
MAX UNIT
±0.1
%/°C
10
%/V
MHz
OSC
typical characteristics -- DCO with external resistor R
10.00
10.00
z
H
M
y
c
n
e
u
q
e
r
z
H
M
-
1.00
y
c
n
e
u
q
e
r
F
O
C
D
F
0.10
RSELx = 4
O
C
D
O
C
D
0.10
RSELx = 4
0.01
10.00
0.01
10.00
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
- 50
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
2.0
100.00
1000.00
10000.00
ROSC - External Resistor - kΩ
Figure 14. DCO Frequency vs ROSC,
VCC = 3.0 V, TA = 25°C
100.00
1000.00
10000.00
ROSC - External Resistor - kΩ
Figure 13. DCO Frequency vs ROSC,
VCC = 2.2 V, TA = 25°C
z
H
M
y
c
n
e
u
q
e
r
F
1.00
ROSC = 100k
z
H
M
y
c
n
e
u
q
e
r
F
ROSC = 270k
O
C
D
ROSC = 1M
- 25
0
25
50
75
TA - Temperature - °C
100
Figure 15. DCO Frequency vs Temperature,
VCC = 3.0 V
ROSC = 100k
ROSC = 270k
ROSC = 1M
2.5
3.0
3.5
VCC - Supply Voltage - V
4.0
Figure 16. DCO Frequency vs VCC,
TA = 25°C
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
33
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
crystal oscillator, LFXT1, low frequency modes (see Note 4)
f
LFXT1,LF
f
LFXT1,LF,logic
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
LFXT1 oscillator crystal
XTS = 0, LFXT1Sx = 0 or 1
1.8 V to 3.6 V
32768
Hz
frequency, LF mode 0, 1
LFXT1 oscillator logic level
= 0, XCAPx = 0,
square wave input frequency, XTS
1.8 V to 3.6 V 10000 32768 50000 Hz
LFXT1Sx
=3
LF mode
XTS = 0, LFXT1Sx = 0,
f
= 32,768 kHz,
500
kΩ
C = 6 pF
Oscillation allowance for
LF crystals
XTS = 0, LFXT1Sx = 0,
f
= 32,768 kHz,
200
kΩ
C = 12 pF
XTS = 0, XCAPx = 0
1
pF
Integrated effective load
XTS = 0, XCAPx = 1
5.5
pF
capacitance LF mode
capacitance,
XTS = 0, XCAPx = 2
8.5
pF
(see Note 1)
XTS = 0, XCAPx = 3
11
pF
XTS
=
0,
Measured
at
P1.4/ACLK,
LF mode
2.2 V/3 V
30
50
70 %
f
= 32,768 Hz
Oscillator fault frequency,
XTS = 0, XCAPx = 0.
2.2 V/3 V
10
10000 Hz
LF mode (see Note 3)
LFXT1Sx = 3 (see Note 2)
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
Measured with logic level input frequency but also applies to operation with crystals.
Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag.
Frequencies in between might set the flag.
To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
-- Keep the trace between the device and the crystal as short as possible.
-- Design a good ground plane around the oscillator pins.
-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
-- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
-- Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
-- If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
-- Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
LFXT1,LF
OA
L,eff
LF
LFXT1,LF
L,eff
C
L,eff
Duty cycle
f
Fault,LF
NOTES: 1.
2.
3.
4.
LFXT1,LF
internal very low power, low frequency oscillator (VLO)
PARAMETER
TEST CONDITIONS
VCC
MIN
f
VLO frequency
2.2 V/3 V
4
df /dT
VLO frequency temperature drift
See Note 1
2.2 V/3 V
df /dV
VLO frequency supply voltage drift
See Note 2
1.8 V to 3.6 V
NOTES: 1. Calculated using the box method:
I Version: (MAX(-- 40...85_C) - MIN(-- 40...85_C))/MIN(-- 40...85_C)/(85_C - (-- 40_C))
T Version: (MAX(-- 40...105_C) - MIN(-- 40...105_C))/MIN(-- 40...105_C)/(105_C - (-- 40_C))
2. Calculated using the box method: (MAX(1.8...3.6V) - MIN(1.8...3.6V))/MIN(1.8...3.6V)/(3.6V - 1.8V)
VLO
VLO
VLO
34
CC
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYP
12
0.5
4
MAX UNIT
20 kHz
%/°C
%/V
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
crystal oscillator, LFXT1, high frequency modes (see Note 5)
f
LFXT1,HF0
f
LFXT1,HF1
f
LFXT1,HF2
f
PARAMETER
TEST CONDITIONS
VCC
MIN TYP MAX UNIT
LFXT1 oscillator crystal frequency, XTS = 1, XCAPx = 0, LFXT1Sx = 0 1.8 V to 3.6 V
0.4
1 MHz
HF mode 0
LFXT1 oscillator crystal frequency, XTS = 1, XCAPx = 0, LFXT1Sx = 1 1.8 V to 3.6 V
1
4 MHz
HF mode 1
1.8 V to 3.6 V
2
10
LFXT1 oscillator
ill t crystal
t l frequency,
f
2.2
V
to
3.6
V
2
12 MHz
XTS
=
1,
XCAPx
=
0,
LFXT1Sx
=
2
HF mode 2
3.0 V to 3.6 V
2
16
1.8 V to 3.6 V
0.4
10
LFXT1 oscillator
ill t logic
l i level
l l square
2.2
V
to
3.6
V
0.4
12 MHz
XTS
=
1,
XCAPx
=
0,
LFXT1Sx
=
3
wave input frequency,
frequency HF mode
3.0 V to 3.6 V
0.4
16
XTS = 1, XCAPx = 0, LFXT1Sx = 0,
2700
f
= 1 MHz, C = 15 pF
Oscillation allowance for HF
XTS = 1, XCAPx = 0, LFXT1Sx = 1
800
Ω
crystals
f
= 4 MHz, C = 15 pF
(see Figure 17 and Figure 18)
XTS = 1, XCAPx = 0, LFXT1Sx = 2
300
f
= 16 MHz, C = 15 pF
Integrated effective load
capacitance, HF mode
XTS = 1, XCAPx = 0 (see Note 2)
1
pF
(see Note 1)
XTS = 1, XCAPx = 0,
Measured at P1.4/ACLK,
2.2 V/3 V
40
50
60 %
f
= 10 MHz
HF mode
XTS = 1, XCAPx = 0,
Measured at P1.4/ACLK,
2.2 V/3 V
40
50
60 %
f
= 16 MHz
Oscillator fault frequency, HF mode XTS = 1, XCAPx = 0, LFXT1Sx = 3
2.2 V/3 V
30
300 kHz
(see Note 4)
(see Notes 3)
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Measured with logic level input frequency but also applies to operation with crystals.
Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag.
Frequencies in between might set the flag.
To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
-- Keep the trace between the device and the crystal as short as possible.
-- Design a good ground plane around the oscillator pins.
-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
-- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
-- Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
-- If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
-- Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
LFXT1,HF,logic
LFXT1,HF
,logic
OA
HF
LFXT1,HF
L,eff
LFXT1,HF
L,eff
LFXT1,HF
C
L,eff
Duty cycle
L,eff
LFXT1,HF
LFXT1,HF
f
Fault,HF
NOTES: 1.
2.
3.
4.
5.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
35
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics - LFXT1 oscillator in HF mode (XTS = 1)
100000.00
s
m
h 10000.00
O
ec
na
w
ol 1000.00
A
no
it
lai
cs 100.00
O
10.00
0.10
LFXT1Sx = 2
LFXT1Sx = 0
LFXT1Sx = 1
1.00
10.00
Crystal Frequency - MHz
100.00
Figure 17. Oscillation Allowance vs Crystal Frequency, CL,eff = 15 pF, TA = 25°C
800.0
Au
tn
er
ru
C
lyp
pu
Sr
ot
al
ic
s
O
TX
LFXT1Sx = 2
700.0
600.0
500.0
400.0
300.0
LFXT1Sx = 1
200.0
100.0
0.0
0.0
LFXT1Sx = 0
4.0
8.0
12.0
16.0
Crystal Frequency - MHz
20.0
Figure 18. XT Oscillator Supply Current vs Crystal Frequency, CL,eff = 15 pF, TA = 25°C
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Timer_A
PARAMETER
fTA
Timer A clock frequency
Timer_A
tTA,cap
Timer_A, capture timing
Timer_B
PARAMETER
fTB
Timer B clock frequency
Timer_B
tTB,cap
Timer_B, capture timing
TEST CONDITIONS
Internal: SMCLK, ACLK,
External: TACLK,
TACLK INCLK,
INCLK
Duty cycle = 50% ±10%
TA0, TA1, TA2
VCC
2.2 V
3V
2.2 V/3 V
MIN
TEST CONDITIONS
Internal: SMCLK, ACLK,
External: TBCLK,
TBCLK
Duty cycle = 50% ±10%
TB0, TB1, TB2
VCC
2.2 V
MIN
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3V
2.2 V/3 V
20
20
MAX UNIT
10
MHz
16
ns
MAX UNIT
10
MHz
16
ns
37
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (UART mode)
PARAMETER
fUSCI
TEST CONDITIONS
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
USCI input clock frequency
VCC
MIN
TYP
MAX UNIT
fSYSTEM MHz
Maximum BITCLK clock frequency
(equals baud rate in MBaud)
2.2V /3 V
2
MHz
(see Note 6)
2.2 V
50 150
ns
UART receive deglitch time
tτ
(see Note 7)
3V
50 100
ns
NOTES: 6. The DCO wake-up time must be considered in LPM3/4 for baudrates above 1 MHz.
7. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
fmax,BITCLK
USCI (SPI master mode) (see Figure 19 and Figure 20)
PARAMETER
fUSCI
USCI input clock frequency
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time
NOTE :
f UCxCLK
= 2t 1
LOፒHI
with t LOፒHI
TEST CONDITIONS
SMCLK, ACLK
Duty cycle = 50% ± 10%
≥ max(t
UCLK edge to SIMO valid,
CL = 20 pF
+t
VALID,MO(USCI)
t
SU,SI(Slave), SU,MI(USCI)
VCC
MIN
TYP
MAX UNIT
fSYSTEM MHz
+t
2.2 V
3V
2.2 V
3V
2.2 V
3V
110
75
30
20
ns
ns
ns
ns
ns
ns
).
VALID,SO(Slave)
For the slave’s parameters tSU,SI(Slave) and tVALID,SO(Slave) refer to the SPI parameters of the attached slave.
USCI (SPI slave mode) (see Figure 21 and Figure 22)
tSTE,DIS
PARAMETER
STE lead time
STE low to clock
STE lag time
Last clock to STE high
STE access time
STE low to SOMI data out
STE disable time
STE high to SOMI high impedance
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time
tSTE,LEAD
tSTE,LAG
tSTE,ACC
NOTE :
f UCxCLK
= 2t 1
LOፒHI
with t LOፒHI
≥ max(t
TEST CONDITIONS
VCC
MIN
2.2 V/3 V
VALID,MO(Master)
+t
t
SU,SI(USCI), SU,MI(Master)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ns
10
ns
2.2 V/3 V
50
ns
2.2 V/3 V
50
ns
75
50
ns
ns
ns
ns
ns
ns
+t
2.2 V
3V
2.2 V
3V
2.2 V
3V
20
15
10
10
).
VALID,SO(USCI)
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
38
MAX UNIT
50
2.2 V/3 V
UCLK edge to SOMI valid,
CL = 20 pF
TYP
110
75
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)8
1/fUCxCLK
UCLK
CKPL=0
CKPL=1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 19. SPI Master Mode, CKPH = 0
1/fUCxCLK
UCLK
CKPL=0
CKPL=1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 20. SPI Master Mode, CKPH = 1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
39
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)9
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,SI
tHD,SI
SIMO
tSTE,ACC
tVALID,SO
tSTE,DIS
SOMI
Figure 21. SPI Slave Mode, CKPH = 0
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,SI
tHD,SI
SIMO
tSTE,ACC
tVALID,SO
SOMI
Figure 22. SPI Slave Mode, CKPH = 1
40
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
tSTE,DIS
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (I2C mode) (see Figure 23)
PARAMETER
TEST CONDITIONS
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
tSU,DAT
tSU,STO
Data hold time
Data setup time
Setup time for STOP
Pulse width of spikes suppressed by
input filter
tSP
fSCL ≤ 100kHz
fSCL > 100kHz
fSCL ≤ 100kHz
fSCL > 100kHz
tHD,STA
VCC
MIN
TYP
MAX UNIT
fSYSTEM MHz
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V
3V
0
4.0
0.6
4.7
0.6
0
250
4.0
50
50
400
kHz
µs
µs
150
100
600
600
ns
ns
µs
ns
tSU,STA tHD,STA
SDA
1/fSCL
tSP
SCL
tHD,DAT
tSU,DAT
tSU,STO
Figure 23. I2C Mode Timing
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
41
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Comparator_A+ (see Note 1)
PARAMETER
I(DD)
CAON=1 CARSEL=0,
CAON=1,
CARSEL=0 CAREF=0
I(Refladder/RefDiode)
V(IC)
V(Ref025)
TEST CONDITIONS
Common-mode input voltage
Voltage @ 0.25 V CC node
VCC
Voltage @ 0.5V CC node
VCC
CAON=1, CARSEL=0,
CAREF 1/2/3
CAREF=1/2/3,
no load at P1.0/CA0 and P1.1/CA1
CAON=1
PCA0=1, CARSEL=1, CAREF=1,
no load at P2.3/CA0 and P2.4/CA1
VCC
2.2 V
3V
2.2 V
MIN
3V
2.2 V/3 V
0
2.2 V/3 V
0.23
TYP
25
45
30
45
0.24
MAX
40
60
50
71
VCC - 1
UNIT
µA
µA
V
0.25
PCA0=1, CARSEL=1, CAREF=2,
2.2 V/3 V
0.47 0.48
0.5
no load at P2.3/CA0 and P2.4/CA1
PCA0=1, CARSEL=1, CAREF=3,
2.2 V
390 480 540
V(RefVT)
(see Figure 27 and Figure 28)
mV
no load at P2.3/CA0
P2 3/CA0 and P2.4/CA1,
P2 4/CA1
3V
400 490 550
TA = 85°C
V(offset)
Offset voltage
See Note 2
2.2 V/3 V
- 30
30 mV
Vhys
Input hysteresis
CAON=1
2.2 V/3 V
0
0.7
1.4 mV
TA = 25°C, Overdrive 10 mV,
2.2 V
80 165 300
Without filter: CAF=0
ns
(see Note 3, Figure 24 and
3
V
70
120
240
Figure 25)
Response time
t(response)
(low-high and high-low)
TA = 25°C, Overdrive 10 mV,
2.2 V
1.4
1.9
2.8
With filter: CAF=1
µs
(see Note 3, Figure 24 and
3
V
0.9
1.5
2.2
Figure 25)
NOTES: 1. The leakage current for the Comparator_A+ terminals is identical to I lkg(Px.x) specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements.
The two successive measurements are then summed together.
3. Response time measured at P1.3/CAOUT.
V(Ref050)
42
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
0 V VCC
0 1
CAF
CAON
To Internal
Modules
Low Pass Filter
+
_
V+
V--
0
0
1
1
CAOUT
Set CAIFG
Flag
τ≈
2.0 µs
Figure 24. Block Diagram of Comparator_A+ Module
VCAOUT
Overdrive
V--
400 mV
t(response)
V+
Figure 25. Overdrive Definition
CA0
CASHORT
CA1
1
VIN
+
-
Comparator_A+
CASHORT = 1
IOUT = 10µA
Figure 26. Comparator_A+ Short Resistance Test Condition
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
43
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics - Comparator_A+
650
650
VCC = 3 V
V 600
m
tsl
oV
ec 550
ne
re
fe
R 500
-)
TV
FE
R
V( 450
400
- 45
V 600
m
slt
oV
ec 550
ne
re
fe
R- 500
)T
VF
ER
V( 450
Typical
- 25
-5
15
35
55
75
TA - Free-Air Temperature - °C
VCC = 2.2 V
95
Figure 27. V(RefVT) vs Temperature, VCC = 3 V
400
- 45
Typical
- 25
-5
15
35
55
75
TA - Free-Air Temperature - °C
Figure 28. V(RefVT) vs Temperature, VCC = 2.2 V
100.00
s
m
h
O
k
ec
na 10.00
ts
is
eR
tr
oh
S
VCC = 2.2V
VCC = 3.0V
VCC = 1.8V
VCC = 3.6V
1.00
0.0
0.2
0.4
0.6
0.8
1.0
VIN/VCC - Normalized Input Voltage - V/V
Figure 29. Short Resistance vs VIN/VCC
44
95
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
flash memory
VCC(PGM/
ERASE)
PARAMETER
TEST CONDITIONS
VCC
Program and erase supply voltage
MIN
TYP
2.2
MAX UNIT
3.6
V
fFTG
IPGM
IERASE
tCPT
tCMErase
Flash Timing Generator frequency
257
476 kHz
Supply current from VCC during program
2.2 V/3.6 V
1
5 mA
Supply current from VCC during erase
2.2 V/3.6 V
1
7 mA
Cumulative program time (see Note 1)
2.2 V/3.6 V
10 ms
Cumulative mass erase time
2.2 V/3.6 V
20
ms
4
5
Program/erase endurance
10
10
cycles
tRetention
Data retention duration
TJ = 25°C
100
years
tWord
Word or byte program time
See Note 2
30
tFTG
tBlock, 0
Block program time for first byte or word
See Note 2
25
tFTG
tBlock, 1-63
Block program time for each additional byte or word See Note 2
18
tFTG
tBlock, End
Block program end-sequence wait time
See Note 2
6
tFTG
tMass Erase
Mass erase time
See Note 2
10593
tFTG
tSeg Erase
Segment erase time
See Note 2
4819
tFTG
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. These values are hardwired into the Flash Controller’s state machine (t FTG = 1/fFTG).
RAM
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
V(RAMh)
RAM retention supply voltage (see Note)
CPU halted
1.6
V
NOTE : ThisparameterdefinestheminimumsupplyvoltageV CC whenthedatainRAMremains unchanged.No programexecution shouldhappen
during this supply voltage condition.
JTAG interface
PARAMETER
fTCK
TCK input frequency
TEST
CONDITIONS
See Note 1
RInternal
Internal pullup resistance on TMS, TCK, TDI/TCLK See Note 2
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG fuse (see Note)
PARAMETER
TEST
CONDITIONS
TA = 25°C
VCC
MIN
TYP
MAX
UNIT
2.2 V
3V
2.2 V/ 3 V
0
0
20
35
5
10
55
MHz
MHz
kΩ
VCC
MIN
TYP
MAX
UNIT
VCC(FB) Supply voltage during fuse-blow condition
2.5
V
VFB
Voltage level on TDI/TCLK for fuse-blow: F versions
6
7
V
IFB
Supply current into TDI/TCLK during fuse blow
100 mA
tFB
Time to blow fuse
1 ms
NOTE : Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
45
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
APPLICATION INFORMATION
Port P1 pin schematic: P1.0 to P1.7, input/output with Schmitt trigger
Pad Logic
P1REN.x
P1DIR.x
0
0
Module X OUT
1
0
DVCC
1
P1.0/TACLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
P1.5/TA0
P1.6/TA1
P1.7/TA2
P1SEL.x
P1IN.x
EN
Module X IN
D
P1IE.x
P1IRQ.x
EN
Q
Set
P1IFG.x
P1SEL.x
P1IES.x
46
1
Direction
0: Input
1: Output
1
P1OUT.x
DVSS
Interrupt
Edge Select
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
Port P1.0 to P1.7 pin functions
PIN NAME (P1.X)
(P1 X)
P1.0/TACLK
/
P1.1/TA0
/
P1.2/TA1
/
P1.3/TA2
/
P1.4/SMCLK
/
P1.5/TA0
/
P1.6/TA1
/
P1.7/TA2
/
X
FUNCTION
0 P1.0 (I/O)
Timer_A3.TACLK
DVSS
1 P1.1 (I/O)
Timer_A3.CCI0A
Timer_A3.TA0
2 P1.2 (I/O)
Timer_A3.CCI0A
Timer_A3.TA0
3 P1.3 (I/O)
Timer_A3.CCI0A
Timer_A3.TA0
4 P1.4 (I/O)
SMCLK
5 P1.5 (I/O)
Timer_A3.CCI0A
Timer_A3.TA0
6 P1.6 (I/O)
Timer_A3.CCI0A
Timer_A3.TA1
7 P1.7 (I/O)
Timer_A3.CCI0A
Timer_A3.TA2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CONTROL BITS / SIGNALS
P1DIR.x
P1SEL.x
I: 0, O: 1
0
0
1
1
1
I: 0, O: 1
0
0
1
1
1
I: 0, O: 1
0
0
1
1
1
I: 0, O: 1
0
0
1
1
1
I: 0, O: 1
0
1
1
I: 0, O: 1
0
0
1
1
1
I: 0, O: 1
0
0
1
1
1
I: 0, O: 1
0
0
1
1
1
47
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
Port P2 pin schematic: P2.0 to P2.4, input/output with Schmitt trigger
Pad Logic
To
Comparator_A
From
Comparator_A
CAPD.x
P2REN.x
P2DIR.x
0
0
Module X OUT
1
0
DVCC
1
Bus
Keeper
EN
P2SEL.x
P2IN.x
EN
Module X IN
D
P2IE.x
P2IRQ.x
EN
Q
Set
P2IFG.x
P2SEL.x
P2IES.x
48
1
Direction
0: Input
1: Output
1
P2OUT.x
DVSS
Interrupt
Edge Select
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
P2.0/ACLK/CA2
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/CA0/TA1
P2.4/CA1/TA2
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
Port P2.0 to P2.4 pin functions
PIN NAME (P2.X)
(P2 X)
X
FUNCTION
P2.0/ACLK/CA2
/
/
CONTROL BITS / SIGNALS
CAPD.x
P2DIR.x
P2SEL.x
0
I: 0, O: 1
0
0
1
1
1
X
X
0
I: 0, O: 1
0
0
0
1
0
1
1
1
X
X
0
I: 0, O: 1
0
0
1
1
0
0
1
1
X
X
0
I: 0, O: 1
0
1
X
X
0
1
1
0
I: 0, O: 1
0
1
X
X
0
1
1
0 P2.0 (I/O)
ACLK
CA2 (see Note 4)
P2.1/TAINCLK/CA3
/
/
1 P2.1 (I/O)
Timer_A3.TAINCLK
DVSS
CA3 (see Note 4)
P2.2/CAOUT/TA0/
/
/ /
2 P2.2 (I/O)
CA4
CAOUT
TA0
CA4 (see Note 4)
P2.3/CA0/TA1
/ /
3 P2.3 (I/O)
CA0 (see Note 4)
Timer_A3.TA1
P2.4/CA1/TA2
/ /
4 P2.4 (I/O)
CA1 (see Note 4)
Timer_A3.TA2
NOTES: 3. X: Don’t care.
4. SettingtheCAPD.xbitdisablestheoutputdriveraswellastheinputtopreventparasiticcrosscurrentswhenapplying analogsignals.
Selecting the CAx input to the comparator multiplexer with the P2CAx bits automatically disables the input buffer for that pin,
regardless of the state of the associated CAPD.x bit.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
49
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
Port P2 pin schematic: P2.5, input/output with Schmitt trigger
Pad Logic
To Comparator
From Comparator
CAPD.5
To DCO
in DCO
DCOR
P2REN.5
P2DIR.5
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.5
DVSS
P2.5/ROSC/CA5
Bus
Keeper
EN
P2SEL.x
P2IN.5
EN
Module X IN
D
P2IE.5
EN
P2IRQ.5
Q
Set
P2IFG.5
P2SEL.5
P2IES.5
Interrupt
Edge Select
Port P2.5 pin functions
PIN NAME (P2.X)
(P2 X)
P2.5/R
/ OSC//CA5
X
FUNCTION
CAPD.5
0
0
0
1
CONTROL BITS / SIGNALS
DCOR
P2DIR.5
0
I: 0, O: 1
1
X
0
1
0
X
P2SEL.5
0
X
1
X
5 P2.5 (I/O)
ROSC
DVSS
CA5 (see Note 6)
NOTES: 5. X: Don’t care.
6. SettingtheCAPD.xbitdisablestheoutputdriveraswellastheinputtopreventparasiticcrosscurrentswhenapplying analogsignals.
Selecting the CAx input to the comparator multiplexer with the P2CAx bits automatically disables the input buffer for that pin,
regardless of the state of the associated CAPD.x bit.
50
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
Port P2 pin schematic: P2.6, input/output with Schmitt trigger
BCSCTL3.LFXT1Sx = 11
P2.7/XOUT/CA7
LFXT1 off
0
LFXT1CLK
1
Pad Logic
To Comparator
From
Comparator
CAPD.6
P2SEL.7
P2REN.6
P2DIR.6
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.6
DVSS
P2.6/XIN/CA6
Bus
Keeper
EN
P2SEL.6
P2IN.6
EN
Module X IN
D
P2IE.6
P2IRQ.6
EN
Q
Set
P2IFG.6
P2SEL.6
P2IES.6
Interrupt
Edge Select
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
51
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
Port P2.6 pin functions
PIN NAME (P2.X)
(P2 X)
X
FUNCTION
P2.6/XIN/CA6
/ /
CONTROL BITS / SIGNALS
CAPD.6
P2DIR.6
P2SEL.6
0
I: 0, O: 1
0
X
1
1
1
X
0
6 P2.6 (I/O)
XIN (default)
CA6 (see Note 8)
NOTES: 7. X: Don’t care.
8. SettingtheCAPD.xbitdisablestheoutputdriveraswellastheinputtopreventparasiticcrosscurrentswhenapplying analogsignals.
Selecting the CAx input to the comparator multiplexer with the P2CAx bits automatically disables the input buffer for that pin,
regardless of the state of the associated CAPD.x bit.
52
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
Port P2 pin schematic: P2.7, input/output with Schmitt trigger
BCSCTL3.LFXT1Sx = 11
P2.6/XIN/TA1
LFXT1 off
0
LFXT1CLK
From P2.6/XIN
1
Pad Logic
To Comparator
From
Comparator
CAPD.7
P2SEL.6
P2REN.7
P2DIR.7
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.7
DVSS
P2.7/XOUT
Bus
Keeper
EN
P2SEL.7
P2IN.7
EN
Module X IN
D
P2IE.7
P2IRQ.7
EN
Q
Set
P2IFG.7
P2SEL.7
P2IES.7
Interrupt
Edge Select
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
53
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
Port P2.7 pin functions
PIN NAME (P2.X)
(P2 X)
X
FUNCTION
P2.7/XOUT/CA7
/
/
CONTROL BITS / SIGNALS
CAPD.7
P2DIR.7
P2SEL.7
0
I: 0, O: 1
0
X
1
1
1
X
0
7 P2.7 (I/O)
XOUT (default)
CA7 (see Note 10)
NOTES: 9. X: Don’t care.
10. SettingtheCAPD.xbitdisablestheoutputdriveraswellastheinputtopreventparasiticcrosscurrentswhenapplying analogsignals.
Selecting the CAx input to the comparator multiplexer with the P2CAx bits automatically disables the input buffer for that pin,
regardless of the state of the associated CAPD.x bit.
54
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
Port P3 pin schematic: P3.0 to P3.5, input/output with Schmitt trigger
Pad Logic
P3REN.x
P3DIR.x
0
Module
direction
1
P3OUT.x
0
Module X OUT
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
1
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3SEL.x
P3IN.x
EN
Module X IN
D
Port P3.0 to P3.5 pin functions
PIN NAME (P3.X)
(P3 X)
X
FUNCTION
P3.0/UCB0STE/
/
/
UCA0CLK
0 P3.0 (I/O)
UCB0STE/UCA0CLK (see Notes 1 and 2)
P3.1/UCB0SIMO/
/
/
1 P3.1 (I/O)
UCB0SDA
UCB0SIMO/UCB0SDA (see Notes 1, 2 and 3)
P3.2/UCB0SOMI/
/
/
2 P3.2 (I/O)
UCB0SCL
UCB0SOMI/UCB0SCL (see Notes 1, 2 and 3)
P3.3/UCB0CLK/
/
/
3 P3.3 (I/O)
UCA0STE
UCB0CLK/UCA0STE (see Notes 1 and 2)
P3.4/UCA0TXD/
/
/
4 P3.4 (I/O)
UCA0SIMO
UCA0TXD/UCA0SIMO (see Notes 1 and 2)
P3.5/UCA0RXD/
/
/
5 P3.5 (I/O)
UCA0SOMI
UCA0RXD/UCA0SOMI (see Notes 1 and 2)
NOTES: 1. X: Don’t care.
2. The pin direction is controlled by the USCI module.
3. In case the I2C functionality is selected the output drives only the logical 0 to V SS level.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CONTROL BITS / SIGNALS
P3DIR.x
P3SEL.x
I: 0, O: 1
0
X
1
I: 0, O: 1
0
X
1
I: 0, O: 1
0
X
1
I: 0, O: 1
0
X
1
I: 0, O: 1
0
X
1
I: 0, O: 1
0
X
1
55
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
Port P3 pin schematic: P3.6 to P3.7, input/output with Schmitt trigger
Pad Logic
P3REN.x
P3DIR.x
0
0
1
P3OUT.x
0
Module X OUT
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
1
P3.6
P3.7
P3SEL.x
P3IN.x
EN
Module X IN
D
Port P3.6 to P3.7 pin functions
PIN NAME (P3.X)
P3.6
P3.7
56
X
6 P3.6 (I/O)
7 P3.7 (I/O)
FUNCTION
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
P3DIR.x
I: 0, O: 1
I: 0, O: 1
P3SEL.x
0
0
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
Port P4 pin schematic: P4.0 to P4.7, input/output with Schmitt trigger
Pad Logic
P4REN.x
P4DIR.x
0
0
Module X OUT
1
0
DVCC
1
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB0
P4.4/TB1
P4.5/TB2
P4.6/TBOUTH/ACLK
P4.7/TBCLK/
TBINCLK
P4SEL.x
P4IN.x
EN
Module X IN
D
Port P4.0 to P4.7 pin functions
PIN NAME (P4.X)
(P4 X)
P4.0/TB0
/
P4.1/TB1
/
P4.2/TB2
/
P4.3/TB0
/
P4.4/TB1
/
P4.5/TB2
/
P4.6/TBOUTH/ACLK
/
/
P4.7/TBCLK
/
1
Direction
0: Input
1: Output
1
P4OUT.x
DVSS
X
FUNCTION
0 P4.0 (I/O)
Timer_B3.CCI0A
Timer_B3.OUT0
1 P4.1 (I/O)
Timer_B3.CCI1A
Timer_B3.OUT1
2 P4.2 (I/O)
Timer_B3.CCI2A
Timer_B3.OUT2
3 P4.3 (I/O)
Timer_B3.CCI0B
Timer_B3.OUT0
4 P4.4 (I/O)
Timer_B3.CCI1B
Timer_B3.OUT1
5 P4.5 (I/O)
N/A
Timer_B3.OUT2
6 P4.6 (I/O)
Timer_B3.TBOUTH
ACLK
7 P4.7 (I/O)
Timer_B3.TBCLK
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CONTROL BITS / SIGNALS
P4DIR.x
P4SEL.x
I: 0, O: 1
0
0
1
1
1
I: 0, O: 1
0
0
1
1
1
I: 0, O: 1
0
0
1
1
1
I: 0, O: 1
0
0
1
1
1
I: 0, O: 1
0
0
1
1
1
I: 0, O: 1
0
0
1
1
1
I: 0, O: 1
0
0
1
1
1
I: 0, O: 1
0
0
1
57
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
APPLICATION INFORMATION
JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger
TDO
Controlled by JTAG
Controlled by JTAG
JTAG
Controlled
by JTAG
TDI
TDO/TDI
DVCC DVCC
Fuse
Test
&
Emulation
Module
Burn & Test
Fuse
TDI/TCLK
DVCC
TMS
TMS
DVCC
TCK
TCK
58
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
During Programming Activity and
During Blowing of the Fuse, Pin
TDO/TDI Is Used to Apply the Test
Input Data for JTAG Circuitry
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
APPLICATION INFORMATION
JTAG fuse check mode
MSP430F23x0 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the
continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated,
a fuse check current, ITF, of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TDI/TCLK pin to ground if the fuse
is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall
system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see
Figure 30). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
I
I
TF
TDI/TCLK
Figure 3
0. Fuse Check Mode Current
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
59
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518C -- AUGUST 2006 -- REVISED OCTOBER 2009
Data Sheet Revision History
LITERATURE
NUMBER
SLAS518
SLAS518A
SLAS518B
SLAS518C
60
SUMMARY
PRODUCT PREVIEW data sheet release
PRODUCTION DATA data sheet release
The USCI parameter section was revised, pages 36 to 39.
Corrected the port schematics of port P2.6 and P2.7
Added in the DSBGA package version.
Corrected WDTIFG description in IFG1 register.
register
Corrected labels in Figure 17 and 18.
Corrected test conditions of Comparator_A+ from P1.0, P1.1 to P2.3 and P2.4.
Corrected the UART parameters.
Release of MSP430F2330IYFF and MSP430F2350IYFF
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
13-Jan-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
MSP430F2330IRHAR
ACTIVE
VQFN
RHA
40
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2330IRHAT
ACTIVE
VQFN
RHA
40
250
CU NIPDAU
Level-3-260C-168 HR
MSP430F2330IYFFR
ACTIVE
DSBGA
YFF
49
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
MSP430F2330IYFFT
ACTIVE
DSBGA
YFF
49
250
SNAGCU
Level-1-260C-UNLIM
MSP430F2330TRHAR
ACTIVE
VQFN
RHA
40
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2330TRHAT
ACTIVE
VQFN
RHA
40
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2350IRHAR
ACTIVE
VQFN
RHA
40
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2350IRHAT
ACTIVE
VQFN
RHA
40
250
CU NIPDAU
Level-3-260C-168 HR
MSP430F2350IYFFR
ACTIVE
DSBGA
YFF
49
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
MSP430F2350IYFFT
ACTIVE
DSBGA
YFF
49
250
SNAGCU
Level-1-260C-UNLIM
MSP430F2350TRHAR
ACTIVE
VQFN
RHA
40
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2350TRHAT
ACTIVE
VQFN
RHA
40
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2370IRHAR
ACTIVE
VQFN
RHA
40
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2370IRHAT
ACTIVE
VQFN
RHA
40
250
CU NIPDAU
Level-3-260C-168 HR
MSP430F2370IYFFR
ACTIVE
DSBGA
YFF
49
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
MSP430F2370IYFFT
ACTIVE
DSBGA
YFF
49
250
SNAGCU
Level-1-260C-UNLIM
MSP430F2370TRHAR
ACTIVE
VQFN
RHA
40
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2370TRHAT
ACTIVE
VQFN
RHA
40
250
CU NIPDAU
Level-3-260C-168 HR
Green (RoHS &
no Sb/Br)
Green (RoHS &
no Sb/Br)
Green (RoHS &
no Sb/Br)
Green (RoHS &
no Sb/Br)
Green (RoHS &
no Sb/Br)
Green (RoHS &
no Sb/Br)
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
13-Jan-2010
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Mar-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
MSP430F2370IRHAR
Package Package Pins
Type Drawing
VQFN
RHA
40
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
16.4
Pack Materials-Page 1
6.3
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
6.3
1.1
12.0
16.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Mar-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430F2370IRHAR
VQFN
RHA
40
2500
346.0
346.0
33.0
Pack Materials-Page 2
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