AD AD5432BRM 8-/10-/12-bit high bandwidth multiplying dacs with serial interface Datasheet

8-/10-/12-Bit High Bandwidth
Multiplying DACs with Serial Interface
AD5426/AD5432/AD5443*
FEATURES
3.0 V to 5.5 V Supply Operation
50 MHz Serial Interface
10 MHz Multiplying Bandwidth
ⴞ10 V Reference Input
Low Glitch Energy < 2 nV-s
Extended Temperature Range –40ⴗC to +125ⴗC
10-Lead MSOP Package
Pin Compatible 8-, 10-, and 12-Bit Current
Output DACs
Guaranteed Monotonic
4-Quadrant Multiplication
Power-On Reset with Brownout Detection
Daisy-chain Mode
Readback Function
0.4 ␮A Typical Power Consumption
FUNCTIONAL BLOCK DIAGRAM
VDD
AD5426/
AD5432/
AD5443
VREF
R
8-/10-/12-BIT
R-2R DAC
RFB
IOUT1
IOUT2
DAC REGISTER
POWER-ON
RESET
SYNC
SCLK
SDIN
INPUT LATCH
CONTROL LOGIC AND
INPUT SHIFT REGISTER
SDO
GND
APPLICATIONS
Portable Battery-Powered Applications
Waveform Generators
Analog Processing
Instrumentation Applications
Programmable Amplifiers and Attenuators
Digitally Controlled Calibration
Programmable Filters and Oscillators
Composite Video
Ultrasound
Gain, Offset, and Voltage Trimming
GENERAL DESCRIPTION
The AD5426/AD5432/AD5443 are CMOS 8-, 10-, and 12-bit
current output digital-to-analog converters, respectively.
These devices operate from a 3.0 V to 5.5 V power supply,
making them suited to battery-powered applications and many
other applications.
The applied external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback resistor (RFB)
provides temperature tracking and full-scale voltage output when
combined with an external current to voltage precision amplifier.
The AD5426/AD5432/AD5443 DACs are available in small
10-lead MSOP packages.
These DACs utilize double buffered 3-wire serial interface that
is compatible with SPI®, QSPI™, MICROWIRE™, and most
DSP interface standards. In addition, a serial data out pin (SDO)
allows for daisy-chaining when multiple packages are used. Data
readback allows the user to read the contents of the DAC register
via the SDO pin. On power-up, the internal shift register and
latches are filled with 0s and the DAC outputs are at zero scale.
As a result of manufacture on a CMOS submicron process, they
offer excellent 4-quadrant multiplication characteristics, with
large signal multiplying bandwidths of 10 MHz.
*U.S. Patent No. 5,689,257
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2004 Analog Devices, Inc. All rights reserved.
AD5426/AD5432/AD5443–SPECIFICATIONS1
(VDD = 3 V to 5.5 V, VREF = 10 V, IOUTx = O V. All specifications TMIN to TMAX, unless otherwise noted. DC performance measured with OP177, AC
performance with AD8038, unless otherwise noted.)
Parameter
Min
STATIC PERFORMANCE
AD5426
Resolution
Relative Accuracy
Differential Nonlinearity
AD5432
Resolution
Relative Accuracy
Differential Nonlinearity
AD5443
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Error Temperature Coefficient 2
Output Leakage Current
REFERENCE INPUT2
Reference Input Range
VREF Input Resistance
RFB Resistance
Input Capacitance
Code All 0s
Code All 1s
DIGITAL INPUTS/OUTPUT 2
Input High Voltage, VIH
Input Low Voltage, VIL
Input Leakage Current, I IL
Input Capacitance
VDD = 4.5 V to 5.5 V
Output Low Voltage, VOL
Output High Voltage, VOH
VDD = 3 V to 3.6 V
Output Low Voltage, VOL
Output High Voltage, VOH
DYNAMIC PERFORMANCE 2
Reference Multiplying Bandwidth
Output Voltage Settling Time
AD5426
AD5432
AD5443
Digital Delay
10% to 90% Rise/Fall Time
Digital-to-Analog Glitch Impulse
Multiplying Feedthrough Error
Typ
Max
Unit
Conditions
8
± 0.25
± 0.5
Bits
LSB
LSB
Guaranteed monotonic
10
± 0.5
±1
Bits
LSB
LSB
Guaranteed monotonic
12
±1
–1/+2
± 10
±5
± 25
Bits
LSB
LSB
mV
ppm FSR/°C
nA
nA
± 10
10
10
12
12
V
kΩ
kΩ
3
5
6
8
pF
pF
4
0.6
2
10
V
V
␮A
pF
±5
8
8
1.7
ISINK = 200 ␮A
ISOURCE = 200 ␮A
0.4
V
V
ISINK = 200 ␮A
ISOURCE = 200 ␮A
MHz
VREF = ± 3.5 V; DAC loaded all 1s
VREF = 10 V; RLOAD = 100 Ω, CLOAD = 15 pF
Measured to ±16 mV of full scale
Measured to ± 4 mV of full scale
Measured to ± 1 mV of full scale
Interface Delay Time
Rise and fall time, VREF = 10 V, RLOAD = 100 Ω
1 LSB change around major carry, V REF = 0 V
DAC latch loaded with all 0s. V REF = ±3.5 V
1 MHz
10 MHz
VDD – 0.5
10
IOUT1
Digital Feedthrough
Total Harmonic Distortion
Digital THD Clock = 1 MHz
50 kHz fOUT
Output Noise Spectral Density
22
10
12
25
0.1
Input resistance TC = –50 ppm/°C
Input resistance TC = –50 ppm/°C
V
V
100
110
160
75
30
70
48
Output Capacitance
IOUT2
Data = 0x0000, TA = 25°C, IOUT
Data = 0x0000, IOUT
0.4
VDD – 1
50
55
90
40
15
2
Guaranteed monotonic
ns
ns
ns
ns
ns
nV-s
dB
dB
25
12
17
30
pF
pF
pF
pF
nV-s
–81
dB
All 0s loaded
All 1s loaded
All 0s loaded
All 1s loaded
Feedthrough to DAC output with SYNC high and
alternate loading of all 0s and all 1s
VREF = 3.5 V pk-pk; all 1s loaded, f = 1 kHz
73
25
dB
nV/√Hz
@ 1 kHz
–2–
REV. 0
AD5426/AD5432/AD5443
Parameter
Min
SFDR Performance (Wide Band)
Clock = 10 MHz
50 kHz fOUT
20 kHz fOUT
SFDR Performance (Narrow Band)
Clock = 1 MHz
50 kHz fOUT
20 kHz fOUT
Intermodulation Distortion
Clock = 1 MHz
f1 = 20 kHz, f2 = 25 kHz
POWER REQUIREMENTS
Power Supply Range
IDD
Typ
Max
Unit
AD5443, 4096 codes VREF = 3.5 V
75
76
dB
dB
87
87
dB
dB
78
dB
3.0
0.4
5.5
5
0.6
V
␮A
␮A
NOTES
1
Temperature range is as follows: Y version: –40°C to +125°C.
2
Guaranteed by design and characterization, not subject to production test.
Specifications subject to change without notice.
REV. 0
Conditions
–3–
Logic inputs = 0 V or VDD
TA = 25°C, logic inputs = 0 V or V DD
AD5426/AD5432/AD5443
TIMING CHARACTERISTICS1 (V
DD
= 3 V to 5.5 V, VREF = 10 V, IOUT2 = O V. All specifications TMIN to TMAX, unless otherwise noted.)
Parameter
3.0 V to 5.5 V
4.5 V to 5.5 V
Unit
Conditions/Comments
fSCLK
t1
t2
t3
t4 2
t5
t6
t7
t8
t9 3
50
20
8
8
13
5
3
5
30
80
120
50
20
8
8
13
5
3
5
30
45
65
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns max
Max clock frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK active edge setup time
Data setup time
Data hold time
SYNC rising edge to SCLK active edge
Minimum SYNC high time
SCLK active edge to SDO valid
NOTES
1
See Figures 1 and 2. Temperature range is as follows: Y version: –40°C to +125°C. Guaranteed by design and characterization, not subject to production test.
All input signals are specified with tr = tf = 1 ns (10% to 90% of V DD) and timed from a voltage level of (V IL + VIH)/2.
2
Falling or rising edge as determined by control bits of serial word.
3
Daisy-chain and readback modes cannot operate at max clock frequency. SDO timing specifications measured with load circuit as shown in Figure 3.
Specifications subject to change without notice.
t1
SCLK
t2
t3
t8
t7
t4
SYNC
t6
t5
DIN
DB15
DB0
ALTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF
SCLK AS DETERMINED BY CONTROL BITS. TIMING AS PER ABOVE, WITH SCLK INVERTED.
Figure 1. Standalone Mode Timing Diagram
t1
SCLK
t2
t3
t7
t8
t4
SYNC
t6
t5
SDIN
DB15 (N)
DB0 (N)
DB15
(N+1)
DB0 (N+1)
DB15(N)
DB0(N)
t9
SDO
ALTERNATiVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING
EDGE OF SCLK. TIMING AS PER ABOVE, WITH SCLK INVERTED.
Figure 2. Daisy-chain and Readback Modes Timing Diagram
–4–
REV. 0
AD5426/AD5432/AD5443
ABSOLUTE MAXIMUM RATINGS 1, 2
200␮A
(TA = 25°C, unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VREF, RFB to GND . . . . . . . . . . . . . . . . . . . . . . –12 V to +12 V
IOUT1, IOUT2 to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Logic Inputs and Output3 . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Extended Industrial (Y Version) . . . . . . . . –40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
10-lead MSOP θJA Thermal Impedance . . . . . . . . . . . 206°C/W
Lead Temperature, Soldering (10 seconds) . . . . . . . . . . 300°C
IR Reflow, Peak Temperature (<20 seconds) . . . . . . . . 235°C
TO
OUTPUT
PIN
IOL
VOH (MIN) + VOL (MAX)
2
CL
20pF
200␮A
IOH
Figure 3. Load Circuit for SDO Timing Specifications
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Transient currents of up to 100 mA will not cause SCR latchup.
3
Overvoltages at SCLK, SYNC, and DIN, will be clamped by internal diodes.
ORDERING GUIDE
Model
AD5426YRM
AD5426YRM-REEL
AD5426YRM-REEL7
AD5432YRM
AD5432YRM-REEL
AD5432YRM-REEL7
AD5443YRM
AD5443YRM-REEL
AD5443YRM-REEL7
EVAL-AD5426EB
EVAL-AD5432EB
EVAL-AD5443EB
Resolution
(Bit)
INL
(LSB)
Temperature Range
8
8
8
10
10
10
12
12
12
± 0.25
± 0.25
± 0.25
± 0.5
± 0.5
± 0.5
±1
±1
±1
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Package
Description
MSOP
MSOP
MSOP
MSOP
MSOP
MSOP
MSOP
MSOP
MSOP
Evaluation Kit
Evaluation Kit
Evaluation Kit
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5426/AD5432/AD5443 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
REV. 0
–5–
Branding
Package
Option
D1Q
D1Q
D1Q
D1R
D1R
D1R
D1S
D1S
D1S
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
AD5426/AD5432/AD5443
PIN CONFIGURATION
IOUT1 1
IOUT2 2
GND 3
10 RFB
AD5426/
AD5432/
AD5443
SCLK 4
SDIN 5
9
VREF
8
VDD
7 SDO
(Not to Scale)
6 SYNC
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic
Function
1
IOUT1
DAC Current Output.
2
IOUT2
DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
3
GND
Ground Pin.
4
SCLK
Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial
clock input. Alternatively, by means of the serial control bits, the device may be configured such that data is
clocked into the shift register on the rising edge of SCLK.
5
SDIN
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input.
By default, on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits
allow the user to change the active edge to rising edge.
6
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes
low, it powers on the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded to the
shift register on the active edge of the following clocks (power-on default is falling clock edge). In standalone
mode, the serial interface counts clocks and data is latched to the shift register on the 16th active clock edge.
7
SDO
Serial Data Output. This allows a number of parts to be daisy-chained. By default, data is clocked into the
shift register on the falling edge and out via SDO on the rising edge of SCLK. Data will always be clocked
out on the alternate edge to loading data to the shift register. Writing the Readback control word to the
shift register makes the DAC register contents available for readback on the SDO pin, clocked out on the
opposite edges to the active clock edge.
8
VDD
Positive Power Supply Input. These parts can be operated from a supply of 3 V to 5.5 V.
9
VREF
DAC Reference Voltage Input.
10
RFB
DAC Feedback Resistor pin. Establish voltage output for the DAC by connecting to external amplifier output.
–6–
REV. 0
Typical Performance Characteristics–AD5426/AD5432/AD5443
0.20
1.0
0.5
TA = 25ⴗC
VREF = 10V
VDD = 5V
0.15
TA = 25ⴗC
VREF = 10V
VDD = 5V
0.4
0.3
TA = 25ⴗC
VREF = 10V
VDD = 5V
0.8
0.6
0
–0.05
0.2
0.4
0.1
0.2
INL (LSB)
0.05
INL (LSB)
INL (LSB)
0.10
0
–0.1
0
–0.2
–0.2
–0.4
–0.3
–0.6
–0.4
–0.8
–0.10
–0.15
–0.20
0
50
100
150
CODE
200
–0.5
250
TPC 1. INL vs. Code (8-Bit DAC)
0
200
400
600
CODE
800
–1.0
1000
TPC 2. INL vs. Code (10-Bit DAC)
0.20
0.15
500 1000 1500 2000 2500 3000 3500 4000
CODE
TPC 3. INL vs. Code (12-Bit DAC)
1.0
0.5
TA = 25ⴗC
VREF = 10V
VDD = 5V
0
TA = 25ⴗC
VREF = 10V
VDD = 5V
0.4
0.3
TA = 25ⴗC
VREF = 10V
VDD = 5V
0.8
0.6
0
–0.05
0.2
0.4
0.1
0.2
DNL (LSB)
0.05
DNL (LSB)
DNL (LSB)
0.10
0
–0.1
0
–0.2
–0.2
–0.4
–0.3
–0.6
–0.15
–0.4
–0.8
–0.20
–0.5
–0.10
0
50
100
150
200
–1.0
0
250
200
400
CODE
TPC 4. DNL vs. Code (8-Bit DAC)
800
1000
TPC 5. DNL vs. Code (10-Bit DAC)
0.6
0.4
MAX INL
4
3
0.1
0
ERROR (mV)
DNL (LSB)
TA = 25ⴗC
VREF = 10V
VDD = 5V
AD5443
–0.55
–0.60
1
0
–1
MIN INL
MIN DNL
–3
–0.65
–0.2
–4
2
3
4
5
6
7
8
REFERENCE VOLTAGE
9
10
TPC 7. INL vs. Reference Voltage
REV. 0
VDD = 3V
–2
–0.1
–0.3
VDD = 5V
2
–0.50
0.2
500 1000 1500 2000 2500 3000 3500 4000
CODE
5
TA = 25ⴗC
VREF = 10V
VDD = 5V
AD5443
–0.45
0.3
0
TPC 6. DNL vs. Code (12-Bit DAC)
–0.40
0.5
INL (LSB)
600
CODE
–0.70
2
3
4
5
6
7
8
REFERENCE VOLTAGE
9
10
TPC 8. DNL vs. Reference Voltage
–7–
–5
VREF = 10V
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (ⴗC)
TPC 9. Gain Error vs. Temperature
AD5426/AD5432/AD5443
2.0
TA = 25ⴗC
VREF = 2.5V
VDD = 3V
AD5443
3
1.5
TA = 25ⴗC
VREF = 0V
VDD = 3V
AD5443
MAX INL
0.5
2
0.3
MAX INL
LSB
MAX DNL
0
MIN DNL
–1
–0.5
–2
–3
MIN DNL
–1.5
–4
–2.0
–5
0
TPC 10. Linearity vs. VBIAS
Voltage Applied to IOUT2
4
MAX INL
3
2
2
GAIN ERROR
TA = 25ⴗC
VREF = 0V
VDD = 5V
AD5443
0
–0.1
OFFSET ERROR
MAX DNL
0
0
MAX INL
MIN DNL
–2
MIN INL
–3
–0.3
TA = 25ⴗC
VREF = 2.5V
VDD = 3V AND 5V
–0.4
0
–2
–4
MIN DNL
–3
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VBIAS (V)
0.5
1.0
MIN INL
1.5
–5
0.5
2.5
2.0
1.0
1.6
0.6
1.4
0.50
TA = 25ⴗC
0.45
VDD = 5V
VDD = 5V
0.4
0.3
TA = 25ⴗC
1.2
IOUT1 VDD 5V
1.0
0.8
0.6
0.4
IOUT1 VDD 3V
1
2
3
INPUT VOLTAGE (V)
4
TPC 16. Supply Current vs.
Logic Input Voltage, SYNC
(SCLK, DATA = 0)
5
0.20
VDD = 3V
0.10
0.2
0
ALL 1s
0.25
ALL 1s
0
–40 –20
ALL 0s
0.05
VDD = 3V
0
ALL 0s
0.30
0.15
0.2
0.1
0.35
CURRENT (␮A)
IOUT LEAKAGE (nA)
0.40
0.5
2.0
TPC 15. Linearity vs. VBIAS
Voltage Applied to IOUT2
TPC 14. Linearity vs. VBIAS
Voltage Applied to IOUT2
0.7
1.5
VBIAS (V)
VBIAS (V)
TPC 13. Gain and Offset Errors
vs. VBIAS Voltage Applied to IOUT2
CURRENT (mA)
MAX DNL
–1
–1
–0.2
TA = 25ⴗC
VREF = 2.5V
VDD = 5V
AD5443
1
LSB
1
0.1
LSB
VOLTAGE (mV)
TPC 12. Gain and Offset Errors vs.
VBIAS Voltage Applied to IOUT2
3
0.2
–0.5
–0.5
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VBIAS (V)
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VBIAS (V)
0.4
0.3
OFFSET ERROR
–0.4
TPC 11. Linearity vs. VBIAS
Voltage Applied to IOUT2
0.5
0
–0.1
–0.3
MIN INL
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VBIAS (V)
0.1
–0.2
MIN INL
–1.0
GAIN ERROR
0.2
1
0
TA = 25ⴗC
VREF = 0V
VDD = 3V AND 5V
0.4
MAX DNL
VOLTAGE (mV)
1.0
LSB
0.5
4
0
20 40 60 80
TEMPERATURE (ⴗC)
100 120
TPC 17. IOUT1 Leakage Current
vs. Temperature
–8–
0
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (ⴗC)
TPC 18. Supply Current vs.
Temperature
REV. 0
AD5426/AD5432/AD5443
6
0
–6
–12
–18
–24
–30
–36
–42
–48
–54
–60
–66
–72
–78
–84
–90
–96
–102
TA = 25ⴗC
AD5443
LOADING 010101010101
GAIN (dB)
2.0
1.5
VCC = 5V
1.0
VCC = 3V
0.5
0
1
10
100
TPC 19. Supply Current vs.
Update Rate
3.00
OUTPUT VOLTAGE (V)
GAIN (dB)
DB5
DB4
DB3
DB2
VREF = ⴞ2V, AD8038 CC 1.47pF
VREF = ⴞ2V, AD8038 CC 1pF
VREF = ⴞ0.15V, AD8038 CC 1pF
VREF = ⴞ0.15V, AD8038 CC 1.47pF
VREF = ⴞ3.51V, AD8038 CC 1.8pF
TA = 25ⴗC
VDD = 5V
VREF = ⴞ3.5V
INPUT
CCOMP = 1.8pF
AD8038 AMPLIFIER
ALL OFF
10
100M
TA = 25ⴗC
VREF = 0V
AD8038 AMP
CCOMP = 1.8pF
AD5443
VDD 3V, 0V REF
NRG = 0.088nVs
800H TO 7FFH
0.020
VDD 3V, 0V REF
NRG = 1.877nVs
7FFH TO 800H
0.010
0.000
VDD 5V, 0V REF
NRG = 0.119nVs,
800H TO 7FFH
0
50
100
150
200
TIME (ns)
–0.8
–1.700
10
100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
VDD 5V, 3.5V REF
NRG = 1.184nVs
7FFH TO 800H
–1.710
TA = 25ⴗC
VREF = 3.5V
AD8038 AMP
CCOMP = 1.8pF
AD5443
–1.720
VDD 3V, 3.5V REF
NRG = 1.433nVs
7FFH TO 800H
–1.730
VDD 3V, 3.5V REF
NRG = 0.647nVs
800H TO 7FFH
–1.740
–1.750
250
300
VDD 5V, 3.5V REF, NRG = 0.364nVs,
800H TO 7FFH
–1.760
0
50
100
250
150
200
TIME (ns)
300
TPC 24. Midscale Transition
VREF = 3.5 V
0.7
–60
TA = 25ⴗC
VDD = 3V
V
REF = 3.5V p-p
–65
TA = 25ⴗC
VDD = 3V
0 AMP = AD8038
1
TPC 21. Reference Multiplying
Bandwidth—All Ones Loaded
TPC 23. Midscale Transition
VREF = 0 V
20
TA = 25ⴗC
VDD = 5V
VREF = ⴞ3.5V
CCOMP = 1.8pF
AD8038 AMPLIFIER
–0.6
100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
VDD 5V, 0V REF
NRG = 2.049nVs
7FFH TO 800H
–0.010
100k
1M
10M
FREQUENCY (Hz)
–0.4
DB0
0.030
–0.020
–0.2
DB1
0.040
TPC 22. Reference Multiplying
Bandwidth vs. Frequency and
Compensation Capacitor
ALL 1s
ALL 0s
0.6
0.5
THD + N (dB)
–20
PSRR (dB)
DB6
0.050
–3.00
–40
–60
FULL SCALE
–80
–70
–75
–80
–85
–90
1
10
100
1k
10k 100k
FREQUENCY (Hz)
1M
10M
TPC 25. Power Supply Rejection vs.
Frequency
REV. 0
0.4
VDD = 5V
0.3
0.2
ZERO SCALE
–100
–120
DB7
0.060
0.00
–9.00
10k
0
DB8
TPC 20. Reference Multiplying
Bandwidth vs. Frequency and Code
TA = 25ⴗC
VDD = 5V
AD8038 AMPLIFIER
–6.00
DB10
DB9
1
1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
DB11
CURRENT (␮A)
IDD (A)
2.5
0.2
ALL ON
OUTPUT VOLTAGE (V)
3.0
TA = 25ⴗC
LOADING
ZS TO FS
GAIN (dB)
3.5
0.1
1
10
100
1k
10k
FREQUENCY (Hz)
100k
TPC 26. THD and Noise vs.
Frequency
–9–
1M
0
–40 –20
VDD = 3V
0
20 40 60 80
TEMPERATURE (ⴗC)
TPC 27. Supply Current
vs. Temperature
100 120
AD5426/AD5432/AD5443
100
1.8
80
TA = 25ⴗC
MCLK = 500kHz
MCLK = 200kHz
80
1.4
VIH
MCLK = 1MHz
MCLK = 500kHz
VIL
0.8
SFDR (dB)
1.0
60
40
0.6
TA = 25ⴗC
VREF = 3.5V
AD8038 AMP
AD5443
20
0.4
0.2
0
0
2.5
3.0
3.5
4.0
4.5
VOLTAGE (V)
5.0
5.5
0
10
30
40
0
50
–20
–10
–20
–30
–40
–40
–40
–60
SFDR (dB)
–30
SFDR (dB)
–30
–50
–50
–60
–70
–80
–80
–80
–90
–90
–100
–100
–10
TA = 25ⴗC
VREF = 3.5V
–20
AD8038 AMP
AD5443
–30
–30
–40
–40
–50
–100
25 30
35 40 45 50 55 60
FREQUENCY (Hz)
65 70 75
TPC 33. Narrowband (± 50%)
SFDR fOUT = 50 kHz,
Update = 1 MHz
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
10 12
TA = 25ⴗC
VREF = 3.5V
AD8038 AMP
AD5443
0
TA = 25ⴗC
VREF = 3.5V
AD8038 AMP
AD5443
dB
SFDR (dB)
–20
50 100 150 200 250 300 350 400 450 500
FREQUENCY (Hz)
TPC 32. Wideband SFDR
fOUT = 20 kHz, Update = 1 MHz
0
–10
50
–90
0
TPC 31. Wideband SFDR
fOUT = 50 kHz, Update = 1 MHz
40
–60
–70
50 100 150 200 250 300 350 400 450 500
FREQUENCY (Hz)
30
–50
–70
0
20
0
TA = 25ⴗC
VREF = 3.5V
AD8038 AMP
AD5443
–10
10
TPC 30. Wideband SFDR vs.
fOUT Frequency (AD5426)
0
TA = 25ⴗC
VREF = 3.5V
AD8038 AMP
AD5443
–20
0
fOUT (kHz)
TPC 29. Wideband SFDR vs.
fOUT Frequency (AD5443)
0
–10
TA = 25ⴗC
VREF = 3.5V
AD8038 AMP
AD5426
20
20
MCLK = 200kHz
40
fOUT (kHz)
TPC 28. Threshold Voltages
vs. Supply Voltage
SFDR (dB)
60
MCLK = 1MHz
1.2
SFDR (dB)
THRESHOLD VOLTAGE (V)
1.6
–100
14 16 18 20 22 24
FREQUENCY (Hz)
26 28 30
TPC 34. Narrowband (± 50%)
SFDR fOUT = 20 kHz,
Update = 1 MHz
10
15
20
25
FREQUENCY (Hz)
30
35
TPC 35. Narrowband (± 50%)
IMD, fOUT = 20 kHz, 25 kHz,
Update = 1 MHz
–10–
REV. 0
AD5426/AD5432/AD5443
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for 0 and full scale and is normally expressed in LSBs
or as a percentage of full-scale reading.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of –1 LSB max over
the operating temperature range ensures monotonicity.
Gain Error
Gain error or full-scale error is a measure of the output error
between an ideal DAC and the actual device output. For these
DACs, ideal maximum output is VREF – 1 LSB. Gain error of
the DACs is adjustable to 0 with external resistance.
Digital Feedthrough
When the device is not selected, high frequency logic activity on
the device digital inputs may be capacitively coupled through the
device to show up as noise on the IOUT pins and subsequently
into the following circuitry. This noise is digital feedthrough.
Multiplying Feedthrough Error
This is the error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT1 terminal, when all 0s are
loaded to the DAC.
Total Harmonic Distortion (THD)
The DAC is driven by an ac reference. The ratio of the rms
sum of the harmonics of the DAC output to the fundamental
value is the THD. Usually only the lower order harmonics are
included, such as second to fifth.
THD = 20 log
(V
2
2
2
2
2
+ V3 + V4 + V5
Output Leakage Current
)
V1
Output leakage current is current that flows in the DAC ladder
switches when these are turned off. For the IOUT1 terminal, it
can be measured by loading all 0s to the DAC and measuring
the IOUT1 current. Minimum current will flow in the IOUT2 line
when the DAC is loaded with all 1s.
Digital Intermodulation Distortion
Output Capacitance
Spurious-Free Dynamic Range (SFDR)
Capacitance from IOUT1 or IOUT2 to AGND.
It is the usable dynamic range of a DAC before spurious noise
interferes or distorts the fundamental signal. SFDR is the measure of difference in amplitude between the fundamental and
the largest harmonically or nonharmonically related spur from
dc to full Nyquist bandwidth (half the DAC sampling rate, or
fS/2). Narrow band SFDR is a measure of SFDR over an arbitrary window size, in this case 50% of the fundamental. Digital
SFDR is a measure of the usable dynamic range of the DAC
when the signal is digitally generated sine wave.
Output Current Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full scale input change. For these devices, it
is specified with a 100 Ω resistor to ground.
The settling time specification includes the digital delay from
SYNC rising edge to the full-scale output charge.
Digital to Analog Glitch Impulse
Second-order intermodulation distortion (IMD) measurements
are the relative magnitude of the fa and fb tones generated digitally by the DAC and the second-order products at 2fa – fb and
2fb – fa.
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-secs or nV-secs
depending upon whether the glitch is measured as a current or
voltage signal.
REV. 0
–11–
AD5426/AD5432/AD5443
DAC SECTION
Low Power Serial Interface
The AD5426, AD5432, and AD5443 are 8-, 10-, and 12-bit current output DACs consisting of a standard inverting R-2R ladder
configuration. A simplified diagram for the 8-bit AD54246 is
shown in Figure 4. The feedback resistor RFB has a value of R.
The value of R is typically 10 kΩ (minimum 8 kΩ and maximum
12 kΩ). If IOUT1 and IOUT2 are kept at the same potential, a constant current flows in each ladder leg, regardless of digital input
code. Therefore, the input resistance presented at VREF is always
constant and nominally of value R. The DAC output (IOUT) is
code-dependent, producing various resistances and capacitances.
External amplifier choice should take into account the variation
in impedance generated by the DAC on the amplifiers inverting
input node.
To minimize the power consumption of the device, the interface
powers up fully only when the device is being written to, i.e., on
the falling edge of SYNC. The SCLK and DIN input buffers are
powered down on the rising edge of SYNC.
R
R
R
VREF
2R
2R
2R
2R
S1
S2
S3
S8
2R
R
RFB A
IOUT1
DAC Control Bits C3 to C0
Control Bits C3 to C0 allow control of various functions of the
DAC as seen in Table I. Default settings of the DAC on power
on are as follows:
Data clocked into shift register on falling clock edges; daisy-chain
mode is enabled. Device powers on with zero-scale load to the
DAC register and IOUT lines.
The DAC control bits allow the user to adjust certain features
on power-on, for example, daisy-chaining may be disabled if not
in use, active clock edge may be changed to rising edge, and DAC
output may be cleared to either zero or midscale. The user may
also initiate a readback of the DAC register contents for verification purposes.
IOUT 2
DAC DATA LATCHES
AND DRIVERS
Table I. DAC Control Bits
C3 C2 C1 C0 Function Implemented
Figure 4. Simplified Ladder
Access is provided to the VREF, RFB, IOUT1, and IOUT2 terminals
of the DAC, making the device extremely versatile and allowing
it to be configured in several different operating modes, for
example, to provide a unipolar output, 4-quadrant multiplication in bipolar mode, or in single-supply modes of operation.
Note that a matching switch is used in series with the internal
RFB feedback resistor. If users attempt to measure RFB, power
must be applied to VDD to achieve continuity.
SERIAL INTERFACE
The AD5426/AD5432/AD5443 have an easy to use 3-wire interface that is compatible with SPI/QSPI/MICROWIRE and DSP
interface standards. Data is written to the device in 16 bit words.
This 16-bit word consists of 4 control bits and either 8, 10, or
12 data bits as shown in Figure 5. The AD5443 uses all 12 bits of
DAC data. The AD5432 uses 10 bits and ignores the 2 LSBs,
while the AD5426 uses 8 bits and ignores the last 4 bits.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
No Operation (Power-On Default)
Load and Update
Initiate Readback
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Daisy-chain Disable
Clock Data to Shift Register On Rising Edge
Clear DAC Output to Zero
Clear DAC Output to Midscale
Reserved
Reserved
Reserved
DB15 (MSB)
C3
C2
DB0 (LSB)
C1
C0
DB7 DB6 DB5 DB4
DB3 DB2 DB1 DB0
CONTROL BITS
X
X
X
X
DATA BITS
Figure 5a. AD5426 8-Bit Input Shift Register Contents
DB15 (MSB)
C3
C2
DB0 (LSB)
C1
C0
DB9 DB8 DB7 DB6 DB5 DB4
CONTROL BITS
DB3 DB2 DB1 DB0
X
X
DATA BITS
Figure 5b. AD5432 10-Bit Input Shift Register Contents
DB15 (MSB)
C3
C2
DB0 (LSB)
C1
C0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
CONTROL BITS
DATA BITS
Figure 5c. AD5443 12-Bit Input Shift Register Contents
–12–
REV. 0
AD5426/AD5432/AD5443
SYNC Function
SYNC is an edge-triggered input that acts as a frame synchronization signal and chip enable. Data can be transferred into the
device only while SYNC is low. To start the serial data transfer,
SYNC should be taken low observing the minimum SYNC
falling to SCLK falling edge setup time, t4.
These DACs are designed to operate with either negative or
positive reference voltages. The VDD power pin is used by
only the internal digital logic to drive the DAC switches’ on
and off states.
These DACs are also designed to accommodate ac reference
input signals in the range of –10 V to +10 V.
Daisy-Chain Mode
VDD
Daisy-chain is the default power-on mode. To disable the daisychain function, write 1001 to control word. In daisy-chain mode
the internal gating on SCLK is disabled. The SCLK is continuously
applied to the input shift register when SYNC is low. If more
than 16 clock pulses are applied, the data ripples out of the shift
register and appears on the SDO line. This data is clocked out on
the rising edge of SCLK (this is the default, use the control word
to change the active edge) and is valid for the next device on the
falling edge (default). By connecting this line to the DIN input on
the next device in the chain, a multidevice interface is constructed.
16 clock pulses are required for each device in the system. Therefore, the total number of clock cycles must equal 16N where N is
the total number of devices in the chain. See the timing diagram
in Figure 3.
When the serial transfer to all devices is complete, SYNC should
be taken high. This prevents any further data being clocked into
the input shift register. A burst clock containing the exact number
of clock cycles may be used and SYNC taken high some time
later. After the rising edge of SYNC, data is automatically transferred from each device’s input shift register to the addressed DAC.
When control bits = 0000, the device is in No Operation mode.
This may be useful in daisy-chain applications where the user
does not want to change the settings of a particular DAC in the
chain. Simply write 0000 to the control bits for that DAC and
the following data bits will be ignored.
C1
VDD
VREF
R1
After the falling edge of the 16th SCLK pulse, data will automatically be transferred from the input shift register to the DAC. For
another serial transfer to take place, the counter must be reset by
the falling edge of SYNC.
When an output amplifier is connected in unipolar mode, the
output voltage is given by
D
VOUT = –VREF × n
2
where D is the fractional representation of the digital word
loaded to the DAC, and n is the number of bits.
D = 0 to 255 (8-bit AD5426)
= 0 to 1023 (10-bit AD5432)
= 0 to 4095 (12-bit AD5443)
Note that the output voltage polarity is opposite to the VREF
polarity for dc reference voltages.
REV. 0
IOUT1
AD5426/
AD5432/AD5443 I 2
A1
VOUT =
0 TO –VREF
OUT
GND
MICROCONTROLLER
AGND
NOTES
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2. C1 PHASE COMPENSATION (1pF – 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 6. Unipolar Operation
With a fixed 10 V reference, the circuit shown in Figure 6 will
give a unipolar 0 V to –10 V output voltage swing. When VIN
is an ac signal, the circuit performs 2-quadrant multiplication.
Table II shows the relationship between digital code and expected
output voltage for unipolar operation (AD5426, 8-bit device).
Table II. Unipolar Code Table
After power-on, write 1001 to control word to disable daisy-chain
mode. The first falling edge of SYNC resets a counter that counts
the number of serial clocks to ensure the correct number of bits
are shifted in and out of the serial shift registers. A rising edge on
SYNC during a write causes the write cycle to be aborted.
Using a single op amp, these devices can easily be configured to
provide 2-quadrant multiplying operation or a unipolar output
voltage swing as shown in Figure 6.
VREF
RFB
SYNC SCLK SDIN
Standalone Mode
CIRCUIT OPERATION
Unipolar Mode
R2
Digital Input
Analog Output (V)
1111 1111
1000 0000
0000 0001
0000 0000
–VREF (255/256)
–VREF (128/256) = –VREF/2
–VREF (1/256)
–VREF (0/256) = 0
Bipolar Operation
In some applications, it may be necessary to generate full
4-quadrant multiplying operation or a bipolar output swing.
This can be easily accomplished by using another external
amplifier and some external resistors as shown in Figure 7. In
this circuit, the second amplifier A2 provides a gain of 2. Biasing the external amplifier with an offset from the reference
voltage results in full 4-quadrant multiplying operation. The
transfer function of this circuit shows that both negative and
positive output voltages are created as the input data (D) is
incremented from code zero (VOUT = –VREF) to midscale
(VOUT = 0 V ) to full scale (VOUT = +VREF).
D 

VOUT = VREF × n –1  – VREF

2 
where D is the fractional representation of the digital word
loaded to the DAC and n is the resolution of the DAC.
D = 0 to 255 (8-bit AD5426)
= 0 to 1023 (10-bit AD5432)
= 0 to 4095 (12-bit AD5443)
When VIN is an ac signal, the circuit performs 4-quadrant
multiplication.
–13–
AD5426/AD5432/AD5443
R3
10k⍀
VDD
R2
VDD
R1
VREF
ⴞ10V
VREF
AD5426/
AD5432/AD5443
SYNC SCLK SDIN
RFB
R5
20k⍀
C1
R4
10k⍀
IOUT1
A1
IOUT 2
A2
VOUT =
–VREF to +VREF
GND
AGND
MICROCONTROLLER
NOTES
1. R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
ADJUST R1 FOR VOUT = 0 V WITH CODE 10000000 LOADED TO DAC.
2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4.
3. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED IF A1/A2 IS
A HIGH SPEED AMPLIFIER.
Figure 7. Bipolar Operation
Table III shows the relationship between digital code and the
expected output voltage for bipolar operation (AD5426, 8-bit
device).
VDD
C1
VDD
Table III. Bipolar Code Table
Digital Input
Analog Output (V)
1111 1111
1000 0000
0000 0001
0000 0000
+VREF (127/128)
0
–VREF (127/128)
–VREF (128/128)
VIN
RFB
IOUT1
VREF
A1
IOUT2
VOUT
GND
A2
VBIAS
Stability
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY
2. C1 PHASE COMPENSATION (1pF– 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
In the I-to-V configuration, the IOUT of the DAC and the inverting node of the op amp must be connected as close as possible,
and proper PCB layout techniques must be employed. Since
every code change corresponds to a step function, gain peaking
may occur if the op amp has limited GBP and there is excessive
parasitic capacitance at the inverting node. This parasitic capacitance introduces a pole into the open-loop response which can
cause ringing or instability in closed-loop applications.
Figure 8. Single-Supply Current Mode Operation
In this configuration, the output voltage is given by
{
}
VOUT = D × ( RFB RDAC ) × (VBIAS − VIN ) + VBIAS
An optional compensation capacitor, C1 can be added in parallel with
RFB for stability as shown in Figures 6 and 7. Too small a value of
C1 can produce ringing at the output, while too large a value can
adversely affect the settling time. C1 should be found empirically
but 1 pF to 2 pF is generally adequate for compensation.
SINGLE-SUPPLY APPLICATIONS
Current Mode Operation
These DACs are specified and tested to guarantee operation in
single-supply applications. Figure 8 shows a typical circuit for
operation with a single 3.0 V to 5 V supply. In the current mode
circuit of Figure 8, IOUT2 and hence IOUT1 is biased positive by
an amount applied to VBIAS.
As D varies from 0 to 255 (AD5426), 1023 (AD5432) or 4095
(AD5443), the output voltage varies from
VOUT = VBIAS to VOUT = 2 VBIAS − VIN
VBIAS should be a low impedance source capable of sinking and
sourcing all possible variations in current at the IOUT2 terminal
without any problems.
It is important to note that VIN is limited to low voltages because
the switches in the DAC ladder no longer have the same sourcedrain drive voltage. As a result, their on resistance differs, which
degrades the linearity of the DAC. See TPCs 10 to 15.
–14–
REV. 0
AD5426/AD5432/AD5443
resistors of the DAC. Simply placing a resistor in series with the
RFB resistor will causing mismatches in the temperature coefficients,
resulting in larger gain temperature coefficient errors. Instead, the
circuit of Figure 11 is a recommended method of increasing the
gain of the circuit. R1, R2, and R3 should all have similar temperature coefficients, but they need not match the temperature
coefficients of the DAC. This approach is recommended in circuits
where gains of great than 1 are required.
Voltage Switching Mode of Operation
Figure 9 shows these DACs operating in the voltage-switching
mode. The reference voltage, VIN, is applied to the IOUT1 pin,
IOUT2 is connected to AGND, and the output voltage is available
at the VREF terminal. In this configuration, a positive reference
voltage results in a positive output voltage making single-supply
operation possible. The output from the DAC is voltage at a
constant impedance (the DAC ladder resistance), thus an
op amp is necessary to buffer the output voltage. The reference
input no longer sees a constant input impedance, but one that
varies with code. So, the voltage input should be driven from a
low impedance source.
VDD
C1
VDD
RFB
R2
VDD
R1
VIN
R2
IOUT1
VREF
R3
GND
RFB
VIN
VDD
IOUT1
R2
A1
VREF
VOUT
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY
2. C1 PHASE COMPENSATION (1pF– 2pF) MAY BE
REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.
IOUT2
GND
Also, VIN must not go negative by more than 0.3 V or an internal
diode will turn on, exceeding the max ratings of the device. In
this type of application, the full range of multiplying capability
of the DAC is lost.
Current steering DACs are very flexible and lend themselves to
many different applications. If this type of DAC is connected as
the feedback element of an op amp and RFB is used as the input
resistor as shown in Figure 12, then the output voltage is
inversely proportional to the digital input fraction D.
For D = 1–2n the output voltage is
(
VOUT = −VIN D = −VIN 1 − 2− n
POSITIVE OUTPUT VOLTAGE
Note that the output voltage polarity is opposite to the VREF
polarity for dc reference voltages. To achieve a positive voltage
output, an applied negative reference to the input of the DAC is
preferred over the output inversion through an inverting amplifier
because of the resistor tolerance errors. To generate a negative
reference, the reference can be level shifted by an op amp such
that the VOUT and GND pins of the reference become the virtual
ground and –2.5 V, respectively, as shown in Figure 10.
ADR03
VOUT VIN
GND
VDD
VREF
VDD
RFB
IOUT1
–2.5V
VIN
A1
IOUT2
1/2 AD8552
VOUT =
0 to +2.5V
GND
–5V
)
As D is reduced, the output voltage increases. For small values
of the digital fraction D, it is important to ensure that the
amplifier does not saturate and also that the required accuracy
is met. For example, an 8-bit DAC driven with the binary code
0x10 (00010000), i.e., 16 decimal, in the circuit of Figure 12
should cause the output voltage to be 16 ⫻ VIN. However, if the
DAC has a linearity specification of ± 0.5 LSB then D can in
fact have the weight anywhere in the range 15.5/256 to 16.5/256
so that the possible output voltage will be in the range 15.5 VIN
to 16.5 VIN—an error of +3% even though the DAC itself has a
maximum error of 0.2%.
C1
+ 5V
R1 = R2R3
R2 + R3
USED AS A DIVIDER OR PROGRAMMABLE GAIN
ELEMENT
Figure 9. Single-Supply Voltage Switching
Mode Operation
VDD = 5V
GAIN = R2 + R3
R2
Figure 11. Increasing Gain of Current Output DAC
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY
2. C1 PHASE COMPENSATION (1pF– 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
A2
VOUT
A1
IOUT2
RFB
VDD
IOUT1
1/2 AD8552
VREF
IOUT2
GND
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY
2. C1 PHASE COMPENSATION (1pF– 2pF) MAY BE
REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 10. Positive Voltage Output with Minimum
of Components
VOUT
NOTE
ADDITIONAL PINS OMITTED FOR CLARITY
ADDING GAIN
In applications where the output voltage is required to be greater
than VIN, gain can be added with an additional external amplifier
or it can also be achieved in a single stage. It is important to
consider the effect of temperature coefficients of the thin film
REV. 0
Figure 12. Current Steering DAC Used as a Divider
or Programmable Gain Element
–15–
AD5426/AD5432/AD5443
DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Since only a fraction D of the current into the VREF terminal is
routed to the IOUT1 terminal, the output voltage has to change
as follows:
AMPLIFIER SELECTION
Output Error Voltage Due to DAC Leakage = (Leakage ⫻ R)/D
where R is the DAC resistance at the VREF terminal. For a DAC
leakage current of 10 nA, R = 10 kΩ and a gain (i.e., 1/D) of 16
the error voltage is 1.6 mV.
REFERENCE SELECTION
When selecting a reference for use with the AD5426 series of
current output DACs, pay attention to the references output
voltage temperature coefficient specification. This parameter not
only affects the full-scale error, but can also affect the linearity
(INL and DNL) performance. The reference temperature coefficient should be consistent with the system accuracy specifications.
For example, an 8-bit system required to hold its overall specification to within 1 LSB over the temperature range 0°C to 50°C
dictates that the maximum system drift with temperature should be
less than 78 ppm/°C. A 12-bit system with the same temperature
range to overall specification within 2 LSBs requires a maximum
drift of 10 ppm/°C. By choosing a precision reference with low
output temperature coefficient, this error source can be minimized.
Table IV suggests some references available from Analog Devices
that are suitable for use with this range of current output DACs.
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset voltage. The input offset voltage of an op amp is multiplied by the
variable gain (due to the code dependent output resistance of
the DAC) of the circuit. A change in this noise gain between
two adjacent digital fractions produces a step change in the
output voltage due to the amplifier’s input offset voltage. This
output voltage change is superimposed on the desired change in
output between the two codes and gives rise to a differential
linearity error, which, if large enough, could cause the DAC to
be nonmonotonic. In general, the input offset voltage should be
a fraction (~ <1/4) of an LSB to ensure monotonic behavior
when stepping through codes.
The input bias current of an op amp also generates an offset at
the voltage output as a result of the bias current flowing in the
feedback resistor RFB. Most op amps have input bias currents low
enough to prevent any significant errors in 12-bit applications.
Common-mode rejection of the op amp is important in voltage
switching circuits since it produces a code dependent error at
the voltage output of the circuit. Most op amps have adequate
common-mode rejection for use at 8-, 10-, and 12-bit resolution.
Provided the DAC switches are driven from true wideband low
impedance sources (VIN and AGND), they settle quickly. Consequently, the slew rate and settling time of a voltage switching DAC
circuit is determined largely by the output op amp. To obtain
minimum settling time in this configuration, it is important to
minimize capacitance at the VREF node (voltage output node in
this application) of the DAC. This is done by using low inputs
capacitance buffer amplifiers and careful board design.
Table IV. Suitable ADI Precision References Recommended for Use with AD5426/AD5432/AD5443 DACs
Part No.
Output Voltage
Initial Tolerance
Temperature Drift
0.1 Hz to 10 Hz Noise
Package
ADR01
ADR02
ADR03
ADR425
10 V
5V
2.5 V
5V
0.1%
0.1%
0.2%
0.04%
3 ppm/°C
3 ppm/°C
3 ppm/°C
3 ppm/°C
20 ␮V p-p
10 ␮V p-p
10 ␮V p-p
3.4 ␮V p-p
SC70, TSOT, SOIC
SC70, TSOT, SOIC
SC70, TSOT, SOIC
MSOP, SOIC
Table V. Some Precision ADI Op Amps Suitable for Use with AD5426/AD5432/AD5443 DACs
Part No.
Max Supply Voltage (V)
VOS(max) (␮V)
IB(max) (nA)
GBP (MHz)
Slew Rate (V/␮s)
OP97
OP1177
AD8551
± 20
± 18
+6
25
60
5
0.1
2
0.05
0.9
1.3
1.5
0.2
0.7
0.4
Table VI. Listing of Some High Speed ADI Op Amps Suitable for Use with AD5426/AD5432/AD5443 DACs
Part No.
Max Supply Voltage
(V)
BW @ ACL
(MHz)
Slew Rate
(V/␮s)
VOS(max)
(␮V)
IB(max)
(nA)
AD8065
AD8021
AD8038
AD9631
± 12
± 12
±5
±5
145
200
350
320
180
100
425
1300
1500
1000
3000
10000
0.01
1000
0.75
7000
–16–
REV. 0
AD5426/AD5432/AD5443
Most single-supply circuits include ground as part of the analog
signal range, which in turns requires an amplifier that can handle
rail-to-rail signals, there is a large range of single-supply amplifiers
available from Analog Devices.
MICROPROCESSOR INTERFACING
Microprocessor interfacing to this family of DACs is via a serial bus
that uses standard protocol compatible with microcontrollers and
DSP processors. The communications channel is a 3-wire interface
consisting of a clock signal, a data signal, and a synchronization
signal. The AD5426/AD5432/AD5443 requires a 16-bit word
with the default being data valid on the falling edge of SCLK,
but this is changeable via the control bits in the data-word.
Communication between two devices at a given clock speed is
possible when the following specs are compatible: frame sync delay
and frame sync setup and hold, data delay and data setup and
hold, and SCLK width. The DAC interface expects a t4 (SYNC
falling edge to SCLK falling edge setup time) of 13 ns minimum.
Consult the ADSP-21xx User Manual for information on clock
and frame sync frequencies for the SPORT register.
The SPORT control register should be set up as follows:
TFSW = 1, Alternate Framing
INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
ISCLK = 1, Internal Serial Clock
TFSR = 1, Frame Every Word
ITFS = 1, Internal Framing Signal
SLEN = 1111, 16-Bit Data-Word
ADSP-21xx to AD5426/AD5432/AD5443 Interface
The ADSP-21xx family of DSPs are easily interface to this family
of DACs without extra glue logic. Figure 13 shows an example of
an SPI interface between the DAC and the ADSP-2191M. SCK
of the DSP drives the serial data line, DIN. SYNC is driven from
one of the port lines, in this case SPIxSEL.
ADSP-2191*
SPIxSEL
SYNC
MOSI
SDIN
SCK
SCLK
AD5426/
AD5432/
AD5443*
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 13. ADSP-2191 SPI to AD5426/AD5432/AD5443
Interface
A serial interface between the DAC and DSP SPORT is shown
in Figure 14. In this interface example, SPORT0 is used to
transfer data to the DAC shift register. Transmission is initiated
by writing a word to the Tx register after the SPORT has been
enabled. In a write sequence, data is clocked out on each rising
edge of the DSPs serial clock and clocked into the DAC input
shift register on the falling edge of its SCLK. The update of the
DAC output takes place on the rising edge of the SYNC signal.
ADSP-2101/
ADSP-2103/
ADSP-2191*
TFS
SYNC
DT
SDIN
SCLK
SCLK
80C51/80L51 to AD5426/AD5432/AD5443 Interface
A serial interface between the DAC and the 8051 is shown in
Figure 15. TxD of the 8051 drives SCLK of the DAC serial
interface, while RxD drives the serial data line, DIN. P3.3 is a
bit-programmable pin on the serial port and is used to drive
SYNC. When data is to be transmitted to the switch, P3.3 is
taken low. The 80C51/80L51 transmits data only in 8-bit bytes;
thus, only eight falling clock edges occur in the transmit cycle.
To load data correctly to the DAC, P3.3 is left low after the first
eight bits are transmitted, and a second write cycle is initiated to
transmit the second byte of data. Data on RxD is clocked out of
the microcontroller on the rising edge of TxD and is valid on the
falling edge. As a result, no glue logic is required between the
DAC and microcontroller interface. P3.3 is taken high following
the completion of this cycle. The 8051 provides the LSB of its
SBUF register as the first bit in the data stream. The DAC input
register requires its data with the MSB as the first bit received.
The transmit routine should take this into account.
8051*
AD5426/
AD5432/
AD5443*
SCLK
RxD
SDIN
P1.1
SYNC
AD5426/
AD5432/
AD5443*
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 15. 80C51/80L51 to AD5426/AD5432/AD5443
Interface
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 14. ADSP-2101/ADSP-2103/ADSP-2191 SPORT
to AD5426/AD5432/AD5443 Interface
REV. 0
TxD
–17–
AD5426/AD5432/AD5443
MC68HC11 Interface to AD5426/AD5432/AD5443 Interface
PIC16C6x/7x to AD5426/AD5432/AD5443
Figure 16 shows an example of a serial interface between the
DAC and the MC68HC11 microcontroller. The serial peripheral
interface (SPI) on the MC68HC11 is configured for master
mode (MSTR = 1), clock polarity bit (CPOL) = 0, and the clock
phase bit (CPHA) = 1. The SPI is configured by writing to the
SPI control register (SPCR)—see the 68HC11 User Manual.
SCK of the 68HC11 drives the SCLK of the DAC interface, the
MOSI output drives the serial data line (DIN) of the AD5516.
The SYNC signal is derived from a port line (PC7). When data is
being transmitted to the AD5516, the SYNC line is taken low
(PC7). Data appearing on the MOSI output is valid on the falling
edge of SCK. Serial data from the 68HC11 is transmitted in 8-bit
bytes with only eight falling clock edges occurring in the transmit
cycle. Data is transmitted MSB first. To load data to the DAC,
PC7 is left low after the first eight bits are transferred, and a second
serial write operation is performed to the DAC. PC7 is taken high
at the end of this procedure.
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit (CKP) = 0. This is
done by writing to the synchronous serial port control register
(SSPCON). See the PIC16/17 Microcontroller User Manual. In
this example, I/O port RA1 is being used to provide a SYNC signal
and to enable the serial port of the DAC. This microcontroller
transfers only eight bits of data during each serial transfer operation;
therefore, two consecutive write operations are required. Figure 18
shows the connection diagram.
If the user wants to verify the data previously written to the input
shift register, the SDO line could be connected to MISO of the
MC68HC11, and with SYNC low, the shift register would clock
data out on the rising edges of SCLK.
MC68HC11*
PC7
SYNC
SCK
SCLK
MOSI
SDIN
AD5426/
AD5432/
AD5443*
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 16. 68HC11/68L11 to AD5426/AD5432/AD5443
Interface
MICROWIRE to AD5426/AD5432/AD5443 Interface
Figure 17 shows an interface between the DAC and any
MICROWIRE compatible device. Serial data is shifted out on
the falling edge of the serial clock, SK, and is clocked into the
DAC input shift register on the rising edge of SK, which corresponds to the falling edge of the DACs SCLK.
MICROWIRE*
SK
SCLK
SO
SDIN
CS
SYNC
AD5426/
AD5432/
AD5443*
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 17. MICROWIRE to AD5426/AD5432/AD5443
Interface
PIC16C6x/7x*
SCK/RC3
SCLK
SDI/RC4
SDIN
RA1
AD5426/
AD5432/
AD5443*
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 18. PIC16C6x/7x to AD5426/AD5432/AD5443
Interface
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5426/AD5432/AD5443 is mounted should be designed so
that the analog and digital sections are separated, and confined
to certain areas of the board. If the DAC is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
These DACs should have ample supply bypassing of 10 ␮F in
parallel with 0.1 ␮F on the supply located as close to the package as possible, ideally right up against the device. The 0.1 ␮F
capacitor should have low effective series resistance (ESR) and
effective series inductance (ESI), such as the common ceramic
types that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching. Low ESR 1 ␮F to 10 ␮F tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
Fast switching signals such as clocks should be shielded with
digital ground to avoid radiating noise to other parts of the board,
and should never be run near the reference inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a
double-sided board. In this technique, the component side of the
board is dedicated to ground plane while signal traces are placed
on the solder side.
It is good practice to employ compact, minimum lead length
PCB layout design. Leads to the input should be as short as
possible to minimize IR drops and stray inductance.
The PCB metal traces between VREF and RFB should also be
matched to minimize gain error. To maximize on high frequency
performance, the I-to-V amplifier should be located as close to
the device as possible.
–18–
REV. 0
AD5426/AD5432/AD5443
EVALUATION BOARD FOR THE AD5426/AD5432/AD5443
SERIES OF DACS
OPERATING THE EVALUATION BOARD
Power Supplies
The board consists of a 12-bit AD5443 and a current to voltage
amplifier AD8065. Included on the evaluation board is a 10 V
reference ADR01. An external reference may also be applied via
an SMB input.
The board requires ± 12 V, and +5 V supplies. The +12 V VDD
and VSS are used to power the output amplifier, while the +5 V
is used to power the DAC (VDD1) and transceivers (VCC).
The evaluation kit consists of a CD-ROM with self-installing
PC software to control the DAC. The software simply allows
the user to write a code to the device.
Both supplies are decoupled to their respective ground plane
with 10 ␮F tantalum and 0.1 ␮F ceramic capacitors.
Link1 (LK1) is provided to allow selection between the on-board
reference (ADR01) or an external reference applied through J2.
For the AD5426/AD5432/AD5443 use Link2 in the SDO position.
VDD1
J3
P1–3
P1–2
P1–4
P1–5
SCLK
SCLK
4
J4
5
VDD
SDIN
6
IOUT1
SYNC
SDO/LDAC
IOUT2
7
LDAC
SDO/LDAC
GND
A
LK2
P1–13
B
SDO
P1–19
P1–20
P1–21
P1–22
P1–23
P1–24
P1–25
P1–26
P1–27
P1–28
P1–29
P1–30
VREF
AD5426/
AD5432/
AD5443
+
C1
0.1␮F
8
R1 = 0⍀
C2
10␮F
C7
C6
4.7pF
10
RFB
SYNC
SYNC
J6
SCLK
SDIN
SDIN
J5
U1
AD8065AR
2
1
2
3
3
U3
VREF
VREF
VDD
J2
9
VDD
2
+VIN
VOUT
6
U2
ADR01AR
C4
0.1␮F
5
TRIM
GND
VDD
C5
0.1␮F
4
P2–3
C11
0.1␮F
+ C12
10␮F
P2–2
C13
0.1␮F
+ C14
AGND
10␮F
P2–1
VSS
VDD1
P2–4
C15
0.1␮F
+ C16
10␮F
Figure 19. Schematic of AD5426/AD5432/AD5443 Evaluation Board
REV. 0
TP1
4
V–
V+
LK1
C3
10␮F
C8
VSS
10␮F
+
0.1␮F
–19–
6
VOUT
J1
7
C9 10␮F
+
C10 0.1␮F
AD5426/AD5432/AD5443
P1
SCLK
J3
C11
U3
SDIN
J4
SDIN
SYNC
U1
R1 C6
C1
C2
SYNC
TP1
J1
VOUT
C8
SCLK
C4
VREF LK1
U2
SDO
J5 SDO/LDAC
SDO/LDAC
C9
C16
J6
LK2
C3
VREF
J2
C14
C10
C13
LDAC
C15
VSS
AGND
VDD1
VDD
P2
EVAL–AD5426/
AD5432/AD5443EB
Figure 20. Silkscreen—Component Side View (Top Layer)
7C
21C
Figure 21. Silkscreen—Component Side View (Bottom Layer)
–20–
REV. 0
AD5426/AD5432/AD5443
Overview of AD54xx Devices
Part No.
Resolution
No. DACs
INL
tS max
Interface Package
AD5403*
8
2
± 0.25
60 ns
Parallel
AD5410*
8
1
± 0.25
100 ns
Serial
AD5413*
8
2
± 0.25
100 ns
Serial
AD5424
8
1
± 0.25
60 ns
Parallel
AD5425
8
1
± 0.25
100 ns
Serial
AD5426
AD5428
8
8
1
2
± 0.25
± 0.25
100 ns
60 ns
Serial
Parallel
AD5429
AD5450
AD5404*
8
8
10
2
1
2
± 0.25
± 0.25
± 0.5
100 ns
100 ns
70 ns
Serial
Serial
Parallel
AD5411*
10
1
± 0.5
110 ns
Serial
AD5414*
10
2
± 0.5
110 ns
Serial
AD5432
AD5433
10
10
1
1
± 0.5
± 0.5
110 ns
70 ns
Serial
Parallel
AD5439
10
2
± 0.5
110 ns
Serial
10 MHz Bandwidth,
10 ns CS Pulse Width,
4-Quadrant Multiplying Resistors
RU-16
10 MHz Bandwidth, 50 MHz Serial,
4-Quadrant Multiplying Resistors
RU-24
10 MHz Bandwidth, 50 MHz Serial,
4-Quadrant Multiplying Resistors
RU-16, CP-20 10 MHz Bandwidth,
17 ns CS Pulse Width
RM-10
Byte Load, 10 MHz Bandwidth,
50 MHz Serial
RM-10
10 MHz Bandwidth, 50 MHz Serial
RU-20
10 MHz Bandwidth,
17 ns CS Pulse Width
RU-10
10 MHz Bandwidth, 50 MHz Serial
RJ-8
10 MHz Bandwidth, 50 MHz Serial
CP-40
10 MHz Bandwidth,
17 ns CS Pulse Width,
4-Quadrant Multiplying Resistors
RU-16
10 MHz Bandwidth, 50 MHz Serial,
4-Quadrant Multiplying Resistors
RU-24
10 MHz Bandwidth, 50 MHz Serial,
4-Quadrant Multiplying Resistors
RM-10
10 MHz Bandwidth, 50 MHz Serial
RU-20, CP-20 10 MHz Bandwidth,
17 ns CS Pulse Width
RU-16
10 MHz Bandwidth, 50 MHz Serial
AD5440
10
2
± 0.5
70 ns
Parallel
RU-24
AD5451
AD5405
10
12
1
2
± 0.25
±1
110 ns
120 ns
Serial
Parallel
AD5412*
12
1
±1
160 ns
Serial
AD5415
12
2
±1
160 ns
Serial
AD5443
AD5444
AD5445
12
12
12
1
1
1
±1
± 0.5
±1
160 ns
160 ns
120 ns
Serial
Serial
Parallel
AD5446
AD5447
14
12
1
2
±2
±1
180 ns
120 ns
Serial
Parallel
AD5449
12
2
±1
160 ns
Serial
AD5452
AD5453
12
14
1
1
± 0.5
±2
160 ns
180 ns
Serial
Serial
*Future parts, contact factory for availability
REV. 0
–21–
Features
CP-40
10 MHz Bandwidth,
17 ns CS Pulse Width
RJ-8
10 MHz Bandwidth, 50 MHz Serial
CP-40
10 MHz Bandwidth,
17 ns CS Pulse Width,
4-Quadrant Multiplying Resistors
RU-16
10 MHz Bandwidth, 50 MHz Serial,
4-Quadrant Multiplying Resistors
RU-24
10 MHz Bandwidth, 50 MHz Serial,
4-Quadrant Multiplying Resistors
RM-10
10 MHz Bandwidth, 50 MHz Serial
RM-10
10 MHz Bandwidth, 50 MHz Serial
RU-20, CP-20 10 MHz Bandwidth,
17 ns CS Pulse Width
RM-10
10 MHz Bandwidth, 50 MHz Serial
RU-24
10 MHz Bandwidth,
17 ns CS Pulse Width
RU-16
10 MHz Bandwidth,
17 ns CS Pulse Width
RJ-8, RM-8
10 MHz Bandwidth, 50 MHz Serial
RJ-8, RM-8
10 MHz Bandwidth, 50 MHz Serial
AD5426/AD5432/AD5443
OUTLINE DIMENSIONS
10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
3.00 BSC
10
6
4.90 BSC
3.00 BSC
1
5
PIN 1
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.15
0.00
0.27
0.17
SEATING
PLANE
0.23
0.08
8ⴗ
0ⴗ
0.80
0.60
0.40
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA
–22–
REV. 0
–23–
–24–
D03162–0–1/04(0)