TI MSP50C614 Mixed-signal processor Datasheet

MSP50C614
MIXED-SIGNAL PROCESSOR
SPSS023C – DECEMBER 1999 – REVISED FEBRUARY 2001
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Advanced, Integrated Speech Synthesizer
for High-Quality Sound.
Operates up to 12.32 MHz (Performs up to
12 MIPS)
Single-Chip Solution for up to 6.8 Minutes
of Speech
External ROM Interface for up to 18.8 Hours
of Speech
Supports High-Quality Synthesis
Algorithms Such as MELP, CELP, LPC,
ADPCM, and Polyphonic Music
Simultaneous Speech Plus Music
Capability
Very Low-Power Operation, Ideal for
Hand-Held Devices.
Low-Voltage Operation, Sustainable by
Three Batteries
Reduced Power Stand-By Modes, Less
Than 10 µA in Deep-Sleep Mode
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Contains 64K Byte Words Onboard ROM
(2K Words Reserved)
640-Word RAM
64 I/O Pins Consisting of
– 40 General-Purpose Bit Configurable I/O
– 8 Inputs With Programmable Pullup
Resistor and Dedicated Interrupt
(Key-Scan)
– 16 Dedicated Output Pins
Direct Speaker Driver, 32 Ω (PDM)
One-bit Comparator With Edge-Detection
Interrupt Service
Resistor-Trimmed Oscillator or 32.768 kHz
Crystal Reference Oscillator
Serial Scan Port for In-Circuit Emulation
and Diagnostics
The MSP50C614 Is Sold in Die Form, or
100-pin PJM Package
An Emulator Device Is Available in a
Ceramic Package for Development
description
The MSP50C614 is a low-cost, mixed-signal processor that combines a speech synthesizer, general-purpose
I/O, onboard ROM, and direct speaker-drive in a single package. The computational unit utilizes a powerful new
DSP which gives the MSP50C614 unprecedented speed and computational flexibility compared with previous
devices of its type. The MSP50C614 supports a variety of speech and audio coding algorithms, providing a
range of options with respect to speech duration and sound quality.
The device consists of a micro-DSP core, embedded program, and data memory, and a self-contained clock
generation system. General-purpose periphery is comprised of 64 bits of partially configurable I/O.
The core processor is a general-purpose 16-bit microcontroller with DSP capability. The basic core block
includes computational unit (CU), data address unit, program address unit, two timers, eight level interrupt
processor, and several system and control registers. The core processor gives the MSP50C614 break-point
capability in emulation.
The processor is Harvard type for efficient DSP algorithm execution. It requires separate program and data
memory blocks to permit simultaneous access. It is configured in 32K 17-bit words.
The total ROM space is divided into two areas: 1) The lower 2K words are reserved by Texas Instruments for
the purposes of a built-in self-test 2) The upper 30K is for user program/data.
The data memory is internal static RAM. The RAM is configured in 640 17-bit words. Both memories are
designed to consume minimum power at a given system clock and algorithm acquisition frequency.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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MSP50C614
MIXED-SIGNAL PROCESSOR
SPSS023C – DECEMBER 1999 – REVISED FEBRUARY 2001
description (continued)
A flexible clock generation system enables the software to control the clock over a wide frequency range. The
implementation uses a phase-locked loop (PLL) circuit that drives the processor clock at a selectable frequency
between the minimum and maximum achievable. Selectable frequencies for the processor clock are spaced
apart in 65.536 kHz steps. The PLL clock-reference is also selectable; either a resistor-trimmed oscillator or a
crystal-referenced oscillator may be used. Internal and external clock sources are controlled separately to
provide different levels of power management.
The periphery consists of five 8-bit wide general-purpose I/O ports, one 8-bit wide dedicated input port, and one
16-bit wide dedicated output port. The bidirectional I/O can be configured under software control as either
high-impedance inputs or as totem-pole outputs. They are controlled via addressable I/O registers. The
input-only port has a programmable pullup option (70-kΩ minimum resistance) and a dedicated service
interrupt. These features make the input port especially useful as a key-scan interface.
A simple one-bit comparator is also included in the periphery. The comparator is enabled by a control register,
and its pin access is shared with two pins in one of the general-purpose I/O ports. Rounding out the MSP50C614
periphery is a built-in pulse-density-modulated DAC (digital-to-analog converter) with direct speaker-drive
capability. The functional block diagram gives an overview of the MSP50C614 functionality.
functional block diagram
SCANIN
SCANOUT
SCANCLK
VSS
VDD
5
5
Power
Scan Interface
(P614 only)
(EP)ROM
Break Point
Emulation
OTP Program
Serial Comm.
SYNC
TEST
32k x (16 + 1) bit
Test-Area
(reserved)
0x0000 to
0x07FF
User ROM
0x0800 to
0x7FEF
INT vectors
0x7FF0 to
0x7FFF
DAC
DACM
32 Ω PDM
0x30
Instr. Decoder
PCU
RESET
CU
Initialization
Logic
TIMER1
OSC Reference
TIMER2
Resistor
Trimmed
32 kHz nominal
OSCIN
or
or
OSCOUT
Crystal
Referenced
32.768 kHz
PLL
2
PLL Filter
Prog. Counter Unit
Computational Unit
PRD1
0x3A
TIM1
0x3B
PRD2
0x3E
TIM2
0x3F
0x08
0x0C
PC0–7
+
Data
Control
Data
Control
PD0–7
0x18
0x1C
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8
PE0–7
0x20
0x24
F port INPUT
8
PF0–7
Data
0x28
8
G port OUTPUT
0x000 to
0x027F
8
–
D port I/O
E port I/O
RAM 640 x 17 bit
(data)
0x10
0x14
Comparator
1 bit: PD5 vs PD4
0x38
Data Mem. Addr.
8
C port I/O
Gen. Control
Interrupt Processor
FLAG
MASK
0x39
0x38
8
PB0–7
Data
Control
0x3D
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0x00
0x04
B port I/O
Clock Control
DMAU
PA0–7
Data
Control
Data
Control
Core
DACP
A port I/O
Data
PG0–15
0x2C
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MSP50C614
MIXED-SIGNAL PROCESSOR
SPSS023C – DECEMBER 1999 – REVISED FEBRUARY 2001
pin assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
NC
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
VDD1
VSS1
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PLL
OSCIN
OSCOUT
NC
NC
NC
VSS
PE0
PG6
PG5
PG4
PG3
PG2
PG1
PG0
SCANOUT
TEST
SYNC
SCANCLK
SCANIN
RESET
PE7
PE6
PE5
PE4
PE3
PE2
PE1
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS3 /DA
NC
NC
NC
DACM
VDD3 /DA
DACP
VDD
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
NC
PG15
PG14
PG13
PG12
PG11
PG10
PG9
PG8
VSS4
VDD4
NC
NC
PG7
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
VDD2
VSS2
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
NC
NC
PJM PACKAGE
(TOP VIEW)
NC – No internal connection
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MSP50C614
MIXED-SIGNAL PROCESSOR
SPSS023C – DECEMBER 1999 – REVISED FEBRUARY 2001
Terminal Functions
NAME
PIN NO.
PAD NO.
I/O
DESCRIPTION
PA0 – PA7
66 – 59
75 – 68
I/O
Port A general-purpose I/O
(1 Byte)
PB0 – PB7
76 – 69
85 – 78
I/O
Port B general-purpose I/O
(1 Byte)
PC0 – PC7
90 – 83
8–1
I/O
Port C general-purpose I/O
(1 Byte)
PD0 – PD7
100 – 93
18 – 11
I/O
Port D general-purpose I/O
(1 Byte)
PE0 – PE7
51 – 44
63 – 56
I/O
Port E general-purpose I/O
(1 Byte)
PF0 – PF7
16 – 9
31 – 24
I
Port F key-scan input
(1 Byte)
PG0 – PG7
37 – 30
49 – 42
PG8 – PG15
25 – 18
39 – 32
O
Port G dedicated output
(2 Bytes)
Pins PD4 and PD5 may be dedicated to the comparator function, if the comparator enable bit is set.
Refer to Section 3.3, Comparator, for details.
Scan Port Control Signals
SCANIN
42
54
I
Scan port data input
SCANOUT
38
50
O
Scan port data output
SCANCLK
41
53
I
Scan port clock
SYNC
40
52
I
Scan port synchronization
TEST
39
51
I
MSP50C614: test modes
The scan port pins must be bonded out on any MSP50C614 production board.
Consult the Important Note regarding Scan Port Bond Out, see Chapter 7 in the MSP50C614 User’s Guide (SPSU014).
Reference Oscillator Signals
OSCOUT
56
65
O
Resistor/crystal reference out
OSCIN
57
66
I
Resistor/crystal reference in
PLL
58
67
O
Phase-lock-loop filter
DACP
7
22
O
Digital-to-analog plus output (+)
DACM
5
20
O
Digital-to-analog minus output (–)
RESET
43
55
I
Initialization
VSS
1†, 26, 52,
67, 91
9, 19†, 40,
64, 76
Ground
VDD
6†, 8, 27,
68, 92
10, 21†,
23, 41, 77
Processor power (+)
Digital-to-Analog Sound Output
Initialization
Power Signals
† The VSS and VDD connections service the DAC circuitry. Their pins tend to sustain a higher current draw. A dedicated decoupling capacitor across
these pins is therefore required.
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MSP50C614
MIXED-SIGNAL PROCESSOR
SPSS023C – DECEMBER 1999 – REVISED FEBRUARY 2001
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 to 7 V
Supply current, IDD (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 to VDD + 0.3 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 to VDD + 0.3 V
Storage temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30°C to 125°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Unless otherwise noted, all voltages are measured with respect to VSS .
2. The total supply current includes the current out of all the I/O pins as well as the operating current of the device.
recommended operating conditions
MIN
Supply voltage (with respect to VSS), VDD
MAX
3
5.2
CPU clock rate (as programmed), f(CPU)
64
12,320
Load resistance between DACP and DACM, R(DAC)
32
Operating free-air temperature, TA
Device functionality
0
UNIT
V
kHz
Ω
°C
70
timing requirements
MIN
MAX
UNIT
t(RESET)
Reset low pulse width, while VDD is within specified limits
100
t1(WIDTH)
Pulse width required prior to a negative transition at pin...PD3, PD5, or PF0...PF7‡
2
1/FCPU
Pulse width required prior to a positive transition at pin...PD2 or PD4†
2
1/FCPU
t2(WIDTH)
‡ While these pins are being used as interrupt inputs.
ns
t(RESET)
t(RESET)
Figure 1. Initialization Timing Diagram
t1(WIDTH (PD3, PD5, or F port))
t1(WIDTH)
t2(WIDTH (PD2, or PD4))
t2(WIDTH)
Figure 2. MSP50C614 External Interrupt Pin Pulse Width Requirements t1WIDTH and t2WIDTH
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MSP50C614
MIXED-SIGNAL PROCESSOR
SPSS023C – DECEMBER 1999 – REVISED FEBRUARY 2001
dc electrical characteristics, TA = 0 to 70°C
PARAMETER
TEST CONDITIONS
VDD = 3 V
RESET
Threshold changes
VDD = 5.2 V
VIH
VIL
High level input
High-level
voltage
Low-level
Low
level input
voltage
MIN
TYP§
Positive going threshold
2.4
Negative going threshold
1.8
Hysteresis
0.6
Positive going threshold
3.3
Negative going threshold
2.9
Hysteresis
0.4
MAX
V
V
VDD = 3 V
VDD = 4.5 V
2
3
3
4.5
VDD = 5.2 V
VDD = 3 V
3.5
5.2
0
1
VDD = 4.5 V
VDD = 5.2 V
0
1.5
0
1.7
IOH¶
High-level output
current per pin of I/O
port
IOL¶
Low-level output
current per pin of I/O
port
IOH (DAC)
High-level output
DAC current
VOH = 4 V
IOL (DAC)
Low-level output
DAC current
VOL = 0.5 V
Ilkg
Input leakage
current
Excludes OSCIN
Standby current
RESET is low
Operating current
VDD = 4.5 V,
VDD = 4.5 V,
FCLOCK = 12.32 MHz
DAC off,
ARM set,
OSC disabled
0.05
VDD = 4.5 V,
VDD = 4.5 V,
DAC off,
ARM set,
OSC enabled
40
60
DAC off,
ARM clear,
OSC enabled
60
100
Vref = 1 to 4.25 V
25
50
I(STANDBY)
IDD†
I(SLEEP-deep)
I(SLEEP-mid)
Supply current
VOH = 4 V
VDD = 4.5 V
I(SLEEP-light)
VIO
Input offset voltage
VDD = 4.5 V,
R(PULLUP)
F port pullup
resistance
VDD = 5 V
∆f(RTO
ti )
(RTO-trim)
Trim deviation
∆f(RTO
lt)
(RTO-volt)
Voltage deviation
∆f(RTO
t
)
(RTO-temp)
Temperature
deviation
∆f(RTO
(RTO-res))
Resistance deviation
VOL = 0.5 V
0.05
RRTO = 470 kΩ,
VDD = 4.5 V, TA = 25°C,
fRTO = 8.192 MHz (PLL setting = 7 Ch)‡
RRTO = 470 kΩ, VDD = 3.5 to 5.2 V,
fRTO = 8.192 MHz (PLL setting = 7 Ch)‡
TA = 25°C,
RRTO = 470 kΩ, VDD = 4.5 V, TA = 0 to 70°C,
fRTO = 8.192 MHz (PLL setting = 7 Ch)‡
VDD = 4.5 V,
TA = 25°C,
R(OSC) = 470 kΩ at ± 1%,
fRTO = 8.192 MHz (PLL setting = 7 Ch)‡
V
mA
5
mA
–10
mA
20
mA
1
µA
10
µA
mA
10
150
± 1%
V
–2
15
70
UNIT
µA
mV
kΩ
± 3%
1 5%
± 1.5%
± 0.03
0 03
%/°C
± 1%
† Operating current assumes all inputs are tied to either VSS or VDD with no input currents due to programmed pullup resistors. The DAC output
and other outputs are open circuited.
‡ The best trim value is selected at nominal temperature and voltage but the deviation due to the trim error is ignored.
§ Typical voltage and current measurement taken at 25°C
¶ Cannot exceed 15 mA total per internal VDD pin. Port A, B share 1 internal VDD pin; Port C, D share 1 internal VDD.
6
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MSP50C614
MIXED-SIGNAL PROCESSOR
SPSS023C – DECEMBER 1999 – REVISED FEBRUARY 2001
external component absolute values
PARAMETER
R(RTO)
RTO external resistance
C(PLL)
PLL external capacitance
TEST CONDITIONS
TA = 25°C,
TA = 25°C,
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MAX
UNIT
1% tolerance
MIN
470
kΩ
10% tolerance
3300
pF
7
MSP50C614
MIXED-SIGNAL PROCESSOR
SPSS023C – DECEMBER 1999 – REVISED FEBRUARY 2001
MECHANICAL DATA
PJM (R-PQFP-G100)
PLASTIC QUAD FLATPACK
0,38
0,22
0,65
80
0,13 M
51
50
81
12,35 TYP
100
14,20
13,80
17,45
16,95
31
1
30
0,16 NOM
18,85 TYP
20,20
19,80
23,45
22,95
2,90
2,50
Gage Plane
0,25
0,25 MIN
0°– 7°
1,03
0,73
Seating Plane
0,10
3,40 MAX
4040022 / B 03/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-022
8
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