Holtek HT86A36 A/d type voice 8-bit mcu Datasheet

HT86Axx/HT86ARxx
A/D Type Voice 8-Bit MCU
Technical Document
· Application Note
- HA0075E MCU Reset and Oscillator Circuits Application Note
Features
· HT86Axx Operating voltage: 2.0V~5.5V
· Four 8-bit programmable Timer with overflow
HT86ARxx Operating voltage: 2.2V~5.5V
interrupt and 7-stage prescaler
· System clock: 4MHz~8MHz
· One optional 32768Hz crystal oscillator for RTC
time base
· Crystal and RC system oscillator
· 40 I/O pins
· 8-bit counter with 3-bit prescaler
· 8K´16-bit Program Memory
· Watchdog timer function
· 8-level subroutine nesting
· 384´8-bit Data Memory
· Low voltage reset and low voltage detect function
· 768/1536K-bit voice ROM size
· Integrated voice ROM with various capacities
· 36/72 sec voice length
· Power-down function and wake-up feature reduce
· External interrupt input
power consumption
· 12-bit high quality voltage type D/A output
· Up to 0.5ms instruction cycle with 8MHz system
· 4 channels 12-bit resolution A/D Converter
clock at VDD= 5V
· SPI series protocol interface
· 63 powerful instructions
· Integrated 1W power amplifier to drive 8W Speaker
· 44-pin LQFP and 64-pin LQFP packages
General Description
The devices are Voice type series 8-bit high performance microcontrollers which include a voice
synthesiser and tone generator. They are specifically
designed for applications which require multiple I/Os
and sound effects, such as voice and melodies. They
can provide various sampling rates and beats, tone
levels, tempos for speech synthesisers and melody
generators. They also include an integrated high
quality, voltage type DAC output, an integrated series
Rev. 1.10
protocol interface, multi-channel A/D Converter and
integrated power amplifier for speaker driving. The external interrupt can be triggered with falling edges or
both falling and rising edges.
The devices are fully supported by the Holtek range of
fully functional development and programming tools,
providing a means for fast and efficient product development cycles.
1
December 12, 2012
HT86Axx/HT86ARxx
Selection Table
The devices include a comprehensive range of features, with most features common to all devices. The main features
distinguishing them are Voice ROM capacity and power supply voltage. The functional differences between the devices are shown in the following table. Devices which include an ²A² in their part number are Mask type while devices
which contain an ²R² in their part number are OTP type.
Part No.
VDD
HT86A36
2.0V~
5.5V
HT86A72
Program
Data
Memory Memory
8K´16
Voice
ROM
Voice
Capacity
96´8
36sec
192´8
72sec
384´8
2.2V~
HT86AR72
5.5V
I/O
Timer
D/A
Stack
Package
Types
40
8-bit´4
12-bit´1
8
44/64LQFP
Note: Voice length is estimated by 21K-bit data rate
Block Diagram
W a tc h d o g
T im e r
S ta c k
P ro g ra m
M e m o ry
V o ic e
R O M
8 - b it
R IS C
M C U
C o re
R A M D a ta
M e m o ry
L o w
V o lta g e
D e te c t
L o w
V o lta g e
R e s e t
W a tc h d o g
T im e r O s c illa to r
R e s e t
C ir c u it
In te rru p t
C o n tr o lle r
R C /C ry s ta l
O s c illa to r
A /D
C o n v e rte r
I/O
P o rts
R T C
8 - b it
T im e r
S e r ia l
In te rfa c e
D /A
C o n v e rte rs
P o w e r
A m p lifie r
Rev. 1.10
2
December 12, 2012
HT86Axx/HT86ARxx
Pin Assignment
4 4 4 3 4 2 4 1
1
0
3
4 0 3 9 3 8 3 7 3 6 3 5 3 4
2
R E S
P D 6
P D 5
P D 4
P A 7
P A 6
P A 5
P A 4
P A 3
P A 2
P A 1
R E S
P D 6
P D 5
P D 4
P A 7
P A 6
P A 5
P A 4
P A 3
P A 2
P A 1
P A
P C
P C
P C
P C
P D
P D
P D
P D
3 3
X IN
X O
V D
P E
P E
V S
IN T
P E
O S
O S
P C
3 2
2
3
1
4
0
5
0
6
1
7
2
8
2 6
3
9
V D D A 1
V S S A 1
1 0
2 5
3 1
3 0
2 9
H T 8 6 A 3 6
4 4 L Q F P -A
1 1
2 8
2 7
2 4
1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2
2 3
P A
P C
P C
P C
P C
P D
P D
P D
P D
U T
3 2
2
3
3 1
1
4
0
5
0
6
1
7
2
8
2 6
3
9
V D D A 1
V S S A 1
1 0
2 5
5
S
6
C 2
2 3
S
6
C 2
C 1
5
M
M
1 1
1 2
1 3
1 4
1 5
1 6
1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2
M
H T 8 6 A 3 6
6 4 L Q F P -A
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
S
_ IN
_ O U T
A
6
P A
N
N
P A
P A
P A
P A
P A
P A
P C
P C
P C
P C
P D
P D
P D
P E 3
R E S
X IN
X O U T
V D D
P E 4
P E 5
V S S
IN T
P E 6
O S C 2
O S C 1
P E 7
P C 7
P C 6
P C 5
6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9
0
C
1
C
2
3
1
4
2
5
3
6
4
7
5
H T 8 6 A 7 2
H T 8 6 A R 7 2
6 4 L Q F P -A
8
7
3
9
1 0
2
1 1
1
1 2
0
1 3
0
1 4
2
1
1 5
1 6
1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
P E 3
R E S
X IN
X O U T
V D D
P E 4
P E 5
V S S
IN T
P E 6
O S C 2
O S C 1
P E 7
P C 7
P C 6
P C 5
S P V S S
V D D
V D D
V S S
S P +
V B IA
A U D
A U D
V D D
V S S
P C 4
V R E
V D D
V S S
P D 3
M
M
M
M
S
_ IN
_ O U T
A
M
M
S
_ IN
_ O U T
A
3
A
M
M
A
F
A 1
A 1
F
A 1
A 1
S P V S S
V D D
V D D
V S S
S P +
V B IA
A U D
A U D
V D D
V S S
P C 4
V R E
V D D
V S S
P D 3
Rev. 1.10
1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2
A
5
1 0
2 4
5
F
4
9
2 7
4
P E 2
P E 1
P E 0
P D 7
P D 6
P D 5
P D 4
P B 7
P B 6
P B 5
P B 4
P B 3
P B 2
P B 1
P B 0
P A 6
3
8
2 8
U T
D
M
S
_ IN
_ O U T
A
2
7
2 9
X IN
X O
V D
P E
P E
V S
IN T
P E
O S
O S
P C
S P V S S
V D D
V S S
S P +
V B IA
A U D
A U D
V D D
V S S
V R E
M
M
A
F
6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9
1
3 0
H T 8 6 A 7 2
H T 8 6 A R 7 2
4 4 L Q F P -A
1 1
S P V S S
V D D
V S S
S P +
V B IA
A U D
A U D
V D D
V S S
V R E
P E 2
P E 1
P E 0
P D 7
P D 6
P D 5
P D 4
P B 7
P B 6
P B 5
P B 4
P B 3
P B 2
P B 1
P B 0
P A 6
P A 0
N C
N C
P A 1
P A 2
P A 3
P A 4
P A 5
P A 7
P C 3
P C 2
P C 1
P C 0
P D 0
P D 1
P D 2
3 3
2
4
5
4 0 3 9 3 8 3 7 3 6 3 5 3 4
3
D
C 1
4 4 4 3 4 2 4 1
1
0
December 12, 2012
HT86Axx/HT86ARxx
Pad Assignment
HT86A36
1
6 7 6 6
6 5
6 4
6 3 6 2
6 1 6 0
5 7
5 9 5 8
5 6
5 5 5 4
5 2
5 3
5 1 5 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
(0 ,0 )
3 9
3 8
3 7
3 6
2
3 5
3
3 4
4
5
6
3 3
7
8
9
1 0
1 4 1 5 1 6 1 7 1 8
1 1
1 2
1 3
1 9
2 0
2 2
2 1
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 2
3 1
3 0
Chip Size: 2655 ´ 2725 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 1.10
4
December 12, 2012
HT86Axx/HT86ARxx
Pad Coordinates
Unit: mm
Pad No.
Pad Name
X
Y
Pad No.
Pad Name
X
Y
1
PA0
-1141.487
1211.389
35
OSC2
1175.250
-400.731
2
PC3
-1177.862
-380.061
36
PE6
1175.250
-296.331
3
PC2
-1177.862
-483.061
37
INT
1175.250
-201.331
4
PC1
-1177.862
-578.061
38
VSS
1174.567
-90.426
5
PC0
-1177.862
-681.061
39
PE5
1174.567
19.807
6
PD0
-1150.059
-789.182
40
PE4
1174.567
122.807
7
PD1
-1150.059
-892.182
41
VDD
1174.567
226.177
8
PD2
-1150.059
-987.182
42
XOUT
1174.450
794.097
9
PD3
-1150.059
-1090.182
43
XIN
1174.450
897.097
10
VSSA1
-1215.319
-1257.457
44
RES
1174.450
992.097
11
VDDA1
-1008.914
-1225.000
45
PE3
1166.013
1211.389
12
VREF
-906.508
-1213.900
46
PE2
1063.013
1211.389
13
PC4
-803.508
-1213.900
47
PE1
941.513
1211.389
14
NC
-672.868
-1082.529
48
PE0
838.513
1211.389
15
NC
-596.868
-1082.529
49
PD7
743.513
1211.389
16
NC
-520.868
-1082.529
50
PD6
640.513
1211.389
17
NC
-444.868
-1082.529
51
PD5
545.513
1211.389
18
NC
-368.868
-1082.529
52
PD4
442.513
1211.389
19
VSSA
-220.317
-1116.909
53
PB7
347.513
1211.389
20
VDDA
-113.217
-1121.909
54
PB6
244.513
1211.389
21
AUD_OUT
8.383
-1151.309
55
PB5
149.513
1211.389
22
AUD_IN
156.311
-1146.077
56
PB4
46.513
1211.389
23
VBIAS
289.311
-1146.077
57
PB3
-48.487
1211.389
24
SP+
391.136
-1101.247
58
PB2
-151.487
1211.389
25
VSSM
498.085
-1101.247
59
PB1
-246.487
1211.389
26
VDDM
605.036
-1101.247
60
PB0
-349.487
1211.389
27
VDDM
733.086
-1101.247
61
PA7
-444.487
1211.389
28
VSSM
840.037
-1101.247
62
PA6
-547.487
1211.389
29
SP-
946.986
-1101.247
63
PA5
-642.487
1211.389
30
PC5
1174.567
-1158.350
64
PA4
-745.487
1211.389
31
PC6
1174.567
-1055.350
65
PA3
-840.487
1211.389
32
PC7
1174.567
-960.350
66
PA2
-943.487
1211.389
33
PE7
1174.567
-857.350
67
PA1
-1038.487
1211.389
34
OSC1
1175.250
-499.731
Rev. 1.10
5
December 12, 2012
HT86Axx/HT86ARxx
HT86A72
1
6 7 6 6
6 5
6 4
6 3 6 2
6 1 6 0
5 7 5 6
5 9 5 8
5 5
5 4
5 3 5 2
5 1 5 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
(0 ,0 )
3 8
3 7
3 6
2
3
4
3 5
5
3 4
6
3 3
7
8
1 4 1 5 1 6 1 7 1 8
9
1 0
1 1
1 2
1 3
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 2
3 1
3 0
Chip Size: 2651 ´ 3078 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 1.10
6
December 12, 2012
HT86Axx/HT86ARxx
Pad Coordinates
Unit: mm
Pad No.
Pad Name
X
Y
Pad No.
Pad Name
X
Y
1
PA0
-1139.487
1389.643
35
OSC2
1177.250
-817.231
2
PC3
-1175.862
-556.476
36
PE6
1177.250
-232.827
3
PC2
-1175.862
-659.476
37
INT
1177.250
-137.827
4
PC1
-1175.862
-754.476
38
VSS
1176.567
-27.172
5
PC0
-1175.862
-857.476
39
PE5
1176.567
82.881
6
PD0
-1148.059
-965.628
40
PE4
1176.567
185.881
7
PD1
-1148.059
1068.682
41
VDD
1176.567
289.431
8
PD2
-1148.059
-1163.682
42
XOUT
1176.450
892.351
9
PD3
-1148.059
-1266.682
43
XIN
1176.450
995.351
10
VSSA1
-1213.319
-1433.997
44
RES
1176.450
1090.351
11
VDDA1
-1009.034
-1401.500
45
PE3
1141.513
1389.643
12
VREF
-906.613
-1390.400
46
PE2
1038.513
1389.643
13
PC4
-803.613
-1390.400
47
PE1
943.513
1389.643
14
NC
-671.507
-1258.234
48
PE0
840.513
1389.643
15
NC
-595.507
-1258.234
49
PD7
745.513
1389.643
16
NC
-519.507
-1258.234
50
PD6
642.513
1389.643
17
NC
-443.507
-1258.234
51
PD5
547.513
1389.643
18
NC
-367.507
-1258.234
52
PD4
444.513
1389.643
19
VSSA
-218.317
-1293.409
53
PB7
349.513
1389.643
20
VDDA
-111.217
-1298.409
54
PB6
246.513
1389.643
21
AUD_OUT
10.383
-1327.809
55
PB5
151.513
1389.643
22
AUD_IN
158.311
-1322.577
56
PB4
48.513
1389.643
23
VBIAS
261.311
-1322.577
57
PB3
-46.487
1389.643
24
SP+
393.136
-1277.747
58
PB2
-149.487
1389.643
25
VSSM
500.085
-1277.747
59
PB1
-244.487
1389.643
26
VDDM
607.036
-1277.747
60
PB0
-347.487
1389.643
27
VDDM
735.086
-1277.747
61
PA7
-442.487
1389.643
28
VSSM
842.037
-1277.747
62
PA6
-545.487
1389.643
29
SP-
948.986
-1277.747
63
PA5
-640.487
1389.643
30
PC5
1176.567
-1334.850
64
PA4
-743.487
1389.643
31
PC6
1176.567
-1231.850
65
PA3
-838.487
1389.643
32
PC7
1176.567
-1136.850
66
PA2
-941.487
1389.643
33
PE7
1176.567
-1033.850
67
PA1
-1036.487
1389.643
34
OSC1
1177.250
-916.231
Rev. 1.10
7
December 12, 2012
HT86Axx/HT86ARxx
HT86AR72
1
6 7 6 6
6 5 6 4 6 3
6 2
6 1 6 0 5 9
5 8
5 7
5 6
5 5 5 4
5 3 5 2
5 1 5 0
4 9 4 8
4 7 4 6
4 5
(0 ,0 )
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
2
3
4
3 5
5
3 4
6
3 3
7
3 2
8
9
1 0
1 1
1 2 1 3
1 4 1 5 1 6 1 7 1 8
1 9
2 0
2 2
2 1
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 1
3 0
Chip Size: 2580 ´ 5870 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 1.10
8
December 12, 2012
HT86Axx/HT86ARxx
Pad Coordinates
Unit: mm
Pad No.
Pad Name
X
Y
Pad No.
Pad Name
X
Y
1
PA0
-1138.054
2785.633
35
OSC2
1138.850
-2171.224
2
PC3
-1138.629
-1952.576
36
PE6
1138.668
-1669.854
3
PC2
-1138.629
-2055.576
37
INT
1138.668
-1574.854
4
PC1
-1138.629
-2150.576
38
VSS
1138.985
-1432.154
5
PC0
-1138.629
-2253.576
39
PE5
1138.985
-1321.921
6
PD0
-1110.826
-2361.132
40
PE4
1138.985
-1218.921
7
PD1
-1110.826
-2464.132
41
VDD
1138.900
-1110.526
8
PD2
-1110.826
-2559.132
42
XOUT
1138.908
-994.167
9
PD3
-1110.826
-2662.132
43
XIN
1138.908
-891.167
10
VSSA1
-1176.086
-2827.757
44
RES
1138.906
-761.007
11
VDDA1
-968.465
-2785.850
45
PE3
1142.946
2785.633
12
VREF
-873.465
-2785.850
46
PE2
1039.946
2785.633
13
PC4
-770.465
-2785.850
47
PE1
944.946
2785.633
14
NC
-638.243
-2804.019
48
PE0
841.946
2785.633
15
NC
-562.243
-2804.019
49
PD7
746.946
2785.633
16
NC
-486.243
-2804.019
50
PD6
643.946
2785.633
17
NC
-410.243
-2804.019
51
PD5
548.946
2785.633
18
NC
-334.243
-2804.019
52
PD4
445.946
2785.633
19
VSSA
-232.480
-2738.114
53
PB7
350.946
2785.633
20
VDDA
-131.115
-2739.664
54
PB6
247.946
2785.633
21
AUD_OUT
-28.525
-2739.664
55
PB5
152.946
2785.633
22
AUD_IN
120.644
-2718.027
56
PB4
49.946
2785.633
23
VBIAS
223.644
-2718.027
57
PB3
-45.054
2785.633
24
SP+
355.469
-2673.197
58
PB2
-148.054
2785.633
25
VSSM
462.418
-2673.197
59
PB1
-243.054
2785.633
26
VDDM
569.369
-2673.197
60
PB0
-346.054
2785.633
27
VDDM
697.419
-2673.197
61
PA7
-441.054
2785.633
28
VSSM
804.370
-2673.197
62
PA6
-544.054
2785.633
29
SP-
911.319
-2673.197
63
PA5
-639.054
2785.633
30
PC5
1138.900
-2696.357
64
PA4
-742.054
2785.633
31
PC6
1138.900
-2593.357
65
PA3
-837.054
2785.633
32
PC7
1138.900
-2498.357
66
PA2
-940.054
2785.633
33
PE7
1138.900
-2395.357
67
PA1
-1035.054
2785.633
34
OSC1
1138.900
-2274.826
Rev. 1.10
9
December 12, 2012
HT86Axx/HT86ARxx
Pin Description
Pin Name
I/O
Options
Description
PA0~PA7
I/O
Wake-up,
Pull-high
Bidirectional 8-bit I/O port. Each pin on this port can be configured as a wake-up
input by a configuration option. Software instructions determine if the pin is a
CMOS output or Schmitt trigger input. Configuration options determine which pins
on the port have a pull-high resistor.
PB0~PB7
I/O
Pull-high
Bidirectional 8-bit I/O port. Software instructions determine if the pin is a CMOS
output or Schmitt trigger input. Configuration options determine which pins on the
port have a pull-high resistor.
Pull-high
Bidirectional 8-bit I/O port. Software instructions determine if the pin is a CMOS
output or Schmitt trigger input. Configuration options determine which pins on the
port have a pull-high resistor. Pins PC0~PC3 are pin-shared with A/D converter
input pins AD0~AD3.
PC0/AD0
PC1/AD1
PC2/AD2
PC3/AD3
PC4~PC7
I/O
PD0/SCS
PD1/SCK
PD2/SDI
PD3/SDO
PD4~PD7
I/O
Pull-high
Bidirectional 8-bit I/O port. Software instructions determine if the pin is a CMOS
output or Schmitt trigger input. Configuration options determine which pin on the
port have a pull-high resistor. Pins PD0~PD3 are pin-shared with SPI interface
pins SCS, SCK, SDI, SDO.
PE0~PE7
I/O
Pull-high
Bidirectional 8-bit I/O port. Software instructions determine if the pin is a CMOS
output or Schmitt trigger input. Configuration options determine which pins on the
port have a pull-high resistor.
AUD_OUT
O
¾
AUD_IN
I
SP-, SP+
VBIAS
O
RES
I
INT
I
Audio output for driving an external transistor or for driving HT82V739
¾
Power amplifier input pin
¾
Power amplifier output pins
¾
Voltage bias pin
¾
Schmitt trigger reset input. Active low.
Falling Edge
External interrupt Schmitt trigger input without pull-high resistor. A configuration
Trigger or
option determines if the interrupt active edge is a falling edge only or both a falling
Falling/Rising
and rising edge.
Edge Trigger
¾
Crystal
or RC
OSC1, OSC2 are connected to an external RC network or external crystal, determined by configuration option, for the internal system clock. If the RC system
clock option is selected, pin OSC2 can be used to measure the system clock at
1/4 frequency.
XIN
XOUT
¾
Crystal
Connected to an external 32kHz crystal
VREF
I
¾
A/D circuit reference voltage
VDD
¾
¾
Positive digital power supply
VSS
¾
¾
Negative digital power supply, ground.
VDDA
¾
¾
Positive DAC circuit power supply
VSSA
¾
¾
Negative DAC circuit power supply, ground
VDDA1
¾
¾
Positive A/D circuit power supply
VSSA1
¾
¾
Negative A/D circuit power supply, ground
VDDM
¾
¾
Positive Power Amp. power supply
VSSM
¾
¾
Negative Power Amp. power supply, ground
OSC1
OSC2
Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function.
2. Individual pins can be selected to have pull-high resistors.
Rev. 1.10
10
December 12, 2012
HT86Axx/HT86ARxx
Absolute Maximum Ratings
Supply Voltage ...........................VSS+2.0V to VSS+5.5V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................150mA
Total Power Dissipation .....................................500mW
Operating Temperature...........................-40°C to 85°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
Min.
Typ.
Max.
Unit
Conditions
VDD
HT86Axx Operating Voltage
¾ fSYS=4MHz/8MHz
2.0
¾
5.5
V
VDD
HT86ARxx Operating Voltage
¾ fSYS=4MHz/8MHz
2.2
¾
5.5
V
3V No load, f
SYS=4MHz,
5V RTC enable, DAC disable
¾
¾
1.5
mA
¾
¾
5.0
mA
3V No load, f
SYS=8MHz,
5V RTC enable, DAC disable
¾
¾
3.0
mA
¾
¾
7.0
mA
3V No load, f
SYS=4MHz,
5V RTC enable, DAC enable
¾
¾
10
mA
¾
¾
18
mA
3V No load, f
SYS=8MHz,
5V RTC enable, DAC enable
¾
¾
20
mA
¾
¾
36
mA
3V No load, f
SYS=4MHz,
5V RTC disable, DAC disable
¾
¾
1.5
mA
¾
¾
5.0
mA
3V No load, f
SYS=8MHz,
5V RTC disable, DAC disable
¾
¾
3.0
mA
¾
¾
7.0
mA
3V No load, f
SYS=4MHz,
5V RTC disable, DAC enable
¾
¾
10
mA
¾
¾
18
mA
3V No load, f
SYS=8MHz,
5V RTC disable, DAC enable
¾
¾
20
mA
¾
¾
36
mA
3V No load, system HALT,
5V WDT enable, RTC enable
¾
¾
5
mA
¾
¾
10
mA
3V No load, system HALT,
5V WDT disable, RTC enable
¾
¾
2
mA
¾
¾
4
mA
3V No load, system HALT,
5V WDT enable, RTC disable
¾
¾
4
mA
¾
¾
8
mA
3V No load, system HALT,
5V WDT disable, RTC disable
¾
¾
1.0
mA
¾
¾
2.0
mA
IDD1
IDD2
IDD3
IDD4
ISTB1
ISTB2
ISTB3
ISTB4
Operating Current
Operating Current
Operating Current
Operating Current
Standby Current
Standby Current
Standby Current
Standby Current
VIL1
Input Low Voltage for I/O Ports
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports ¾
¾
0.7VDD
¾
VDD
V
Rev. 1.10
11
December 12, 2012
HT86Axx/HT86ARxx
Test Conditions
Symbol
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
VLVR
Low Voltage Reset
¾ LVR 2.1V option
2.0
2.1
2.2
V
VLVD1
Low Voltage Detect
¾ LVD 2.2V
1.9
¾
2.5
V
VLVD2
Low Voltage Detect
¾ LVD 2.3V
2.0
¾
2.6
V
VLVD3
Low Voltage Detect
¾ LVD 2.4V
2.1
¾
2.7
V
VLVD4
Low Voltage Detect
¾ LVD 2.5V
2.2
¾
2.8
V
I/O Port Sink Current
(For PA0~PA7, PB0~PB7,
PC0~PC7, PD4~PD7,
PE0~PE7)
4
¾
¾
mA
IOL1
10
¾
¾
mA
-2
¾
¾
mA
-5
¾
¾
mA
8
¾
¾
mA
20
¾
¾
mA
-2
¾
¾
mA
-5
¾
¾
mA
-1.5
¾
¾
mA
-3
¾
¾
mA
20
60
100
kW
10
30
50
kW
0
¾
VREF
V
IOH1
IOL2
IOH2
IAUD
I/O Port Source Current
(For PA0~PA7, PB0~PB7,
PC0~PC7, PD4~PD7,
PE0~PE7)
I/O Port Sink Current
(For PD0~PD3)
I/O Port Source Current
(For PD0~PD3)
3V
VOL=0.1VDD
5V
3V
VOH=0.9VDD
5V
3V
VOL=0.1VDD
5V
3V
VOH=0.9VDD
5V
3V
AUD Source Current
VOH=0.9VDD
5V
RPH
3V
¾
Pull-high Resistance
5V
VAD
A/D Input/Output
¾
VREF
ADC Input Reference Voltage
Range
3V AVDD=3V
1.3
¾
AVDD
V
5V AVDD=5V
1.5
¾
AVDD
V
DNL
ADC Differential Non-Linear
¾
AVDD=5V, VREF=AVDD,
tAD=1ms
¾
¾
±2.0
LSB
INL
ADC Integral Non-Linear
¾
AVDD=5V, VREF=AVDD,
tAD=1ms
¾
±2.5
±4.0
LSB
¾
¾
12
bits
¾
0.5
1.0
mA
¾
1.5
3.0
mA
RESOLU Resolution
IADC
Rev. 1.10
Additional Power Consumption
if A/D Converter is Used
¾
¾
¾
3V
5V
No load, tAD=1ms
12
December 12, 2012
HT86Axx/HT86ARxx
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
fSYS
System Clock
(RC OSC, Crystal OSC)
tWDTOSC
Watchdog Oscillator Period
tRES
External Reset Low Pulse Width
Min.
Typ.
Max.
Unit
HT86Axx:2.0V~5.5V
HT86ARxx:2.2V~5.5V
4
¾
8
MHz
3V
¾
45
90
180
ms
5V
¾
32
65
130
ms
¾
¾
1
¾
¾
ms
¾
1024
¾
*tSYS
VDD
Conditions
¾
tSST
System Start-up Timer Period
¾
Power-up or Wake-up
from HALT
tLVR
Low Voltage Reset Time
¾
¾
2
¾
¾
ms
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tAD
A/D Clock Period
¾
¾
1.0
¾
¾
ms
tADC
A/D Conversion Time
¾
¾
¾
80
¾
tAD
tADC
A/D Sampling Time
¾
¾
¾
32
¾
tAD
tMAT
Circumscribe Memory Access Time
¾
HT86Axx:2.0V~5.5V
HT86ARxx:2.2V~5.5V
¾
¾
400
ns
Note: *tSYS=1/fSYS
Characteristics Curves
HT86Axx
· R vs. F Chart Characteristics Curves
R v s . F C h a rt
F re q u e n c y (M H z )
1 0
8
6
3 .0 V
4 .5 V
4
2
1 4 6
1 8 8
3 5 7
2 7 6
R
4 0 9
(k W )
· T vs. F Chart Characteristics Curves
T v s . F C h a rt
1 .1 5
1 .1 1
S C
(2 5 °C )
0 .9 9
V
V
fO
fO
1 .0 3
S C
1 .0 7
0 .9 5
0 .9 1
D D
-4 0
= 3 V
V
D D
= 5 V
= 3 V
V
-6 0
D D
D D
= 5 V
-2 0
0
2 0
4 0
6 0
8 0
1 0 0
T (° C )
Rev. 1.10
13
December 12, 2012
HT86Axx/HT86ARxx
· V vs. F Chart Characteristics Curves - 3.0V
V v s . F C h a r t (F o r 3 .0 V )
1 0
8 M H z /1 4 6 k W
F re q u e n c y (M H z )
8
6 M H z /1 8 8 k W
6
4 M H z /2 7 6 k W
4
2
2 .6
2 .2
3 .3
3 .0
3 .8
4 .2
V
D D
4 .5
4 .9
5 .2
5 .5
4 .9
5 .2
5 .5
(V )
· V vs. F Chart Characteristics Curves - 4.5V
V v s . F C h a r t (F o r 4 .5 V )
1 0
8 M H z /1 4 0 k W
F re q u e n c y (M H z )
8
6 M H z /1 8 7 k W
6
4 M H z /2 6 9 k W
4
2
2 .2
2 .6
3 .0
3 .3
3 .8
V
D D
(V )
4 .2
4 .5
HT86ARxx
· R vs. F Chart Characteristics Curves
R v s . F C h a rt
F re q u e n c y (M H z )
1 0
8
6
3 .0 V
4 .5 V
2
4
4 9
6 1
8 6
R
Rev. 1.10
14
1 1 1
1 3 2
(k W )
December 12, 2012
HT86Axx/HT86ARxx
· T vs. F Chart Characteristics Curves
T v s . F C h a rt
1 .1 0
1 .0 8
S C
fO
S C
fO
(2 5 °C )
1 .0 6
1 .0 4
V
1 .0 2
D D
= 3 V
V
1 .0 0
V
0 .9 8
D D
D D
= 5 V
= 5 V
V
0 .9 6
D D
= 3 V
0 .9 4
-6 0
-4 0
-2 0
0
2 0
4 0
6 0
8 0
1 0 0
4 .9
5 .2
5 .5
4 .9
5 .2
5 .5
T (° C )
· V vs. F Chart Characteristics Curves - 3.0V
V v s . F C h a r t (F o r 3 .0 V )
1 0
8 M H z /4 9 k W
F re q u e n c y (M H z )
8
6 M H z /6 1 k W
6
4 M H z /8 6 k W
4
2
2 .2
2 .6
3 .3
3 .0
3 .8
4 .2
V
D D
4 .5
(V )
· V vs. F Chart Characteristics Curves - 4.5V
V v s . F C h a r t (F o r 4 .5 V )
1 0
8 M H z /4 3 k W
F re q u e n c y (M H z )
8
6 M H z /5 5 k W
6
4 M H z /7 9 k W
2
4
2 .2
2 .6
3 .0
3 .3
3 .8
V
Rev. 1.10
15
D D
(V )
4 .2
4 .5
December 12, 2012
HT86Axx/HT86ARxx
System Architecture
Program Counter is incremented at the beginning of the
T1 clock during which time a new instruction is fetched.
The remaining T2~T4 clocks carry out the decoding and
execution functions. In this way, one T1~T4 clock cycle
forms one instruction cycle. Although the fetching and
execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the
microcontroller ensures that instructions are effectively
executed in one instruction cycle. The exception to this
are instructions where the contents of the Program
Counter are changed, such as subroutine calls or
jumps, in which case the instruction will take one more
instruction cycle to execute.
A key factor in the high-performance features of the
Holtek range of Voice microcontrollers is attributed to
the internal system architecture. The range of devices
take advantage of the usual features found within RISC
microcontrollers providing increased speed of operation
and enhanced performance. The pipelining scheme is
implemented in such a way that instruction fetching and
instruction execution are overlapped, hence instructions
are effectively executed in one cycle, with the exception
of branch or call instructions. An 8-bit wide ALU is used
in practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation,
increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the
Accumulator and the ALU. Certain internal registers are
implemented in the Data Memory and can be directly or
indirectly addressed. The simple addressing methods of
these registers along with additional architectural features ensure that a minimum of external components is
required to provide a functional I/O, voltage type DAC,
capacitor/resistor sensor input and external RC oscillator converter with maximum reliability and flexibility.
When the RC oscillator is used, OSC2 is freed for use as
a T1 phase clock synchronizing pin. This T1 phase clock
has a frequency of fSYS/4 with a 1:3 high/low duty cycle.
For instructions involving branches, such as jump or call
instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as
the program takes one cycle to first obtain the actual
jump or call address and then another cycle to actually
execute the branch. The requirement for this extra cycle
should be taken into account by programmers in timing
sensitive applications.
Clocking and Pipelining
The main system clock, derived from either a Crystal/
Resonator or RC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The
O s c illa to r C lo c k
( S y s te m C lo c k )
P h a s e C lo c k T 1
P h a s e C lo c k T 2
P h a s e C lo c k T 3
P h a s e C lo c k T 4
P ro g ra m
C o u n te r
P ip e lin in g
P C
P C + 1
F e tc h In s t. (P C )
E x e c u te In s t. (P C -1 )
F e tc h In s t. (P C + 1 )
E x e c u te In s t. (P C )
P C + 2
F e tc h In s t. (P C + 2 )
E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
M O V A ,[1 2 H ]
2
C A L L D E L A Y
3
C P L [1 2 H ]
4
:
5
:
6
1
D E L A Y :
F e tc h In s t. 1
E x e c u te In s t. 1
F e tc h In s t. 2
E x e c u te In s t. 2
F e tc h In s t. 3
F lu s h P ip e lin e
F e tc h In s t. 6
E x e c u te In s t. 6
F e tc h In s t. 7
N O P
Instruction Fetching
Rev. 1.10
16
December 12, 2012
HT86Axx/HT86ARxx
Program Counter
The lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL might
cause program branching, so an extra cycle is needed
to pre-fetch. Further information on the PCL register can
be found in the Special Function Register section.
During program execution, the Program Counter is used
to keep track of the address of the next instruction to be
executed. It is automatically incremented by one each
time an instruction is executed except for instructions,
such as ²JMP² or ²CALL², that demand a jump to a
non-consecutive Program Memory address. Note that
the Program Counter width varies with the Program
Memory capacity depending upon which device is selected. However, it must be noted that only the lower 8
bits, known as the Program Counter Low Register, are
directly addressable by user.
Stack
This is a special part of the memory which is used to
save the contents of the Program Counter only. The
stack has 8 levels and is neither part of the data nor part
of the program space, and is neither readable nor
writable. The activated level is indexed by the Stack
Pointer, SP, and is neither readable nor writable. At a
subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack.
At the end of a subroutine or an interrupt routine, signaled by a return instruction, ²RET² or ²RETI², the Program Counter is restored to its previous value from the
stack. After a device reset, the Stack Pointer will point to
the top of the stack.
When executing instructions requiring jumps to
non-consecutive addresses such as a jump instruction,
a subroutine call, interrupt or reset, etc., the
microcontroller manages program control by loading the
required address into the Program Counter. For conditional skip instructions, once the condition has been
met, the next instruction, which has already been
fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained.
P ro g ra m
The lower byte of the Program Counter, known as the
Program Counter Low register or PCL, is available for
program control and is a readable and writable register.
By transferring data directly into this register, a short
program jump can be executed directly, however, as
only this low byte is available for manipulation, the
jumps are limited to the present page of memory, that is
256 locations. When such program jumps are executed
it should also be noted that a dummy cycle will be inserted.
C o u n te r
S ta c k L e v e l 1
T o p o f S ta c k
S ta c k L e v e l 2
S ta c k
P o in te r
B o tto m
P ro g ra m
M e m o ry
S ta c k L e v e l 3
o f S ta c k
S ta c k L e v e l 8
Program Counter
Mode
*12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
0
0
0
1
0
0
Timer 0 Overflow
0
0
0
0
0
0
0
0
0
1
0
0
0
Timer 1 Overflow
0
0
0
0
0
0
0
0
0
1
1
0
0
Timer 2 Overflow
0
0
0
0
0
0
0
0
1
0
0
0
0
Timer 3 Overflow
0
0
0
0
0
0
0
0
1
0
1
0
0
A/D Converter Interrupt
0
0
0
0
0
0
0
0
1
1
0
0
0
Skip
Program Counter + 2
Loading PCL
*12
*11
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#12
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S12 S11 S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
*12~*0: Program counter bits
#12~#0: Instruction code bits
Rev. 1.10
S12~S0: Stack register bits
@7~@0: PCL bits
17
December 12, 2012
HT86Axx/HT86ARxx
If the stack is full and an enabled interrupt takes place,
the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack
Pointer is decremented, by RET or RETI, the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack
overflow. Precautions should be taken to avoid such
cases which might cause unpredictable program
branching.
· Location 004H
This vector is used by the external interrupt. If the external interrupt pin on the device goes low, the program will jump to this location and begin execution if
the external interrupt is enabled and the stack is not
full.
· Location 008H
This internal vector is used by the 8-bit Timer 0. If a
overflow occurs, the program will jump to this location
and begin execution if the timer interrupt is enabled
and the stack is not full.
· Location 00CH
Arithmetic and Logic Unit - ALU
This internal vector is used by the 8-bit Timer1. If a
overflow occurs, the program will jump to this location
and begin execution if the timer interrupt is enabled
and the stack is not full.
The arithmetic-logic unit or ALU is a critical area of the
microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main
microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or
logical operations after which the result will be placed in
the specified register. As these ALU calculation or operations may result in carry, borrow or other status
changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the
following functions:
· Location 010H
This internal vector is used by the 8-bit Timer2. If a
overflow occurs, the program will jump to this location
and begin execution if the timer interrupt is enabled
and the stack is not full.
· Location 014H
This internal vector is used by the 8-bit Timer3. If a
overflow occurs, the program will jump to this location
and begin execution if the timer interrupt is enabled
and the stack is not full.
· Arithmetic operations ADD, ADDM, ADC, ADCM,
SUB, SUBM, SBC, SBCM, DAA
· Logic operations AND, OR, XOR, ANDM, ORM,
· Location 018H
XORM, CPL, CPLA
This internal vector is used by the A/D Converter. If an
A/D converter conversion completes, the program will
jump to this location and begin execution if the A/D
converter interrupt is enabled and the stack is not full.
· Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
RLC
· Increment and Decrement INCA, INC, DECA, DEC
· Branch decision JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA,
0 0 0 H
SDZA, CALL, RET, RETI
0 0 4 H
Program Memory
0 0 8 H
The Program Memory is the location where the user
code or program is stored.
0 0 C H
Structure
0 1 0 H
The program memory stores the program instructions
that are to be executed. It also includes data, table and
interrupt entries, addressed by the Program Counter
along with the table pointer. The program memory size
is 8192´16 bits. Certain locations in the program memory are reserved for special usage.
0 1 4 H
0 1 8 H
In itia lis a tio n
V e c to r
E x te rn a l
In te rru p t V e c to r
T im e r 0
In te rru p t V e c to r
T im e r 1
In te rru p t V e c to r
T im e r 2
In te rru p t V e c to r
T im e r 3
In te rru p t V e c to r
A /D C o n v e rte r
In te rru p t V e c to r
0 1 9 H
Special Vectors
1 F F F H
1 6 b its
Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts.
Program Memory Structure
· Location 000H
This vector is reserved for use by the device reset for
program initialisation. After a device reset is initiated, the
program will jump to this location and begin execution.
Rev. 1.10
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December 12, 2012
HT86Axx/HT86ARxx
Look-up Table
The following diagram illustrates the addressing/data
flow of the look-up table for the devices:
Any location within the Program Memory can be defined
as a look-up table where programmers can store fixed
data. To use the look-up table, table pointers are used to
setup the address of the data that is to be accessed from
the Program Memory. However, as some devices possess
only a low byte table pointer and other devices possess
both a high and low byte pointer it should be noted that depending upon which device is used, accessing look-up table data is implemented in slightly different ways.
T B H P
T B L P
T B L H
H ig h B y te o f T a b le C o n te n ts
S p e c ifie d b y [m ]
L o w
B y te o f T a b le C o n te n ts
Look-up Table
For the devices, there are two Table Pointer Registers
known as TBLP and TBHP in which the lower order and
higher order address of the look-up data to be retrieved
must be respectively first written. Unlike the other devices in which only the low address byte is defined using
the TBLP register, the additional TBHP register allows
the complete address of the look-up table to be defined
and consequently allow table data from any address
and any page to be directly accessed. For these devices, after setting up both the low and high byte table
pointers, the table data can then be retrieved from any
area of Program Memory using the ²TABRDC [m]² instruction or from the last page of the Program Memory
using the ²TABRDL [m]² instruction. When either of
these instructions are executed, the lower order table
byte from the Program Memory will be transferred to the
user defined Data Memory register [m] as specified in
the instruction. The higher order table data byte from the
Program Memory will be transferred to the TBLH special
register. Any unused bits in this transferred higher order
byte will be read as ²0².
?
?
P ro g ra m
M e m o ry
Table Program Example
The following example shows how the table pointer and
table data is defined and retrieved from the devices. This
example uses raw table data located in the last page
which is stored there using the ORG statement. The
value at this ORG statement is ²1F00H² which refers to
the start address of the last page within the Program
Memory of the microcontroller. The table pointer is setup
here to have an initial value of ²06H². This will ensure that
the first data read from the data table will be at the Program Memory address ²1F06H² or 6 locations after the
start of the last page. Note that the value for the table
pointer is referenced to the first address of the present
page if the ²TABRDC [m]² instruction is being used. The
high byte of the table data which in this case is equal to
zero will be transferred to the TBLH register automatically
when the ²TABRDL [m]² instruction is executed.
tempreg1
tempreg2
db
db
:
:
; temporary register #1
; temporary register #2
mov
a,06h
; initialise table pointer - note that this address
; is referenced
mov
tblp,a
:
:
; to the last page or present page
tabrdl
tempreg1
;
;
;
;
dec
tblp
; reduce value of table pointer by one
tabrdl
tempreg2
;
;
;
;
;
;
;
;
transfers value in table referenced by table pointer
to tempregl
data at prog. memory address ²1F06H² transferred to
tempreg1 and TBLH
transfers value in table referenced by table pointer
to tempreg2
data at prog.memory address ²1F05H² transferred to
tempreg2 and TBLH
in this example the data ²1AH² is transferred to
tempreg1 and data ²0FH² to register tempreg2
the value ²00H² will be transferred to the high byte
register TBLH
:
:
org
1F00h
dc
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
Rev. 1.10
; sets initial address of HT86A72 last page
19
December 12, 2012
HT86Axx/HT86ARxx
Because the TBLH register is a read-only register and
cannot be restored, care should be taken to ensure its
protection if both the main routine and Interrupt Service
Routine use table read instructions. If using the table
read instructions, the Interrupt Service Routines may
change the value of the TBLH and subsequently cause
errors if used again by the main routine. As a rule it is
recommended that simultaneous use of the table read
instructions should be avoided. However, in situations
where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any
main routine table-read instructions. Note that all table
related instructions require two instruction cycles to
complete their operation.
Table Location
Instruction
*12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P12
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
*12~*0: Current Program ROM table
@7~@0: Write @7~@0 to TBLP pointer register
P12~P8: Write P12~P8 to TBHP pointer register
Data Memory
and the last Data Memory address is ²FFH². Registers
which are common to all microcontrollers, such as ACC,
PCL, etc., have the same Data Memory address.
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into two sections, the first of
these is an area of RAM where special function registers
are located. These registers have fixed locations and
are necessary for correct operation of the device. Many
of these registers can be read from and written to directly under program control, however, some remain
protected from user manipulation. The second area of
RAM Data Memory is reserved for general purpose use.
All locations within this area are read and write accessible under program control.
Note: Most of the RAM Data Memory bits can be directly
manipulated using the ²SET [m].i² and ²CLR [m].i² instructions with the exception of a few dedicated bits.
The RAM Data Memory can also be accessed through
the Memory Pointer registers MP0 and MP1.
General Purpose Data Memory
All microcontroller programs require an area of
read/write memory where temporary data can be stored
and retrieved for use later. It is this area of RAM memory
that is known as General Purpose Data Memory. This
area of Data Memory is fully accessible by the user program for both read and write operations. By using the
²SET [m].i² and ²CLR [m].i² instructions individual bits
can be set or reset under program control giving the
user a large range of flexibility for bit manipulation in the
Data Memory.
Structure
The Data Memory is subdivided into two banks, known
as Bank 0 and Bank 1, all of which are implemented in
8-bit wide RAM. Most of the RAM Data Memory is located in Bank 0 which is also subdivided into two sections, the Special Purpose Data Memory and the
General Purpose Data Memory. The start address of the
RAM Data Memory for all devices is the address ²00H²,
0 0 H
S p e c ia l P u r p o s e
D a ta M e m o ry
3 E H
4 0 H
F F H
G e n e ra l P u rp o s e
D a ta M e m o ry
(1 9 2 B y te s )
B a n k 0
4 0 H
F F H
G e n e ra l P u rp o s e
D a ta M e m o ry
(1 9 2 B y te s )
B a n k 1
: U n k n o w
RAM Data Memory Structure - Bank 0 and Bank 1
Rev. 1.10
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December 12, 2012
HT86Axx/HT86ARxx
Special Purpose Data Memory
the relevant Special Function Register section. Note
that for locations that are unused, any read instruction to
these addresses will return the value ²00H². Although
the Special Purpose Data Memory registers are located
in Bank 0, they will still be accessible even if the Bank
Pointer has selected Bank 1.
This area of Data Memory, is located in Bank 0, where
registers, necessary for the correct operation of the
microcontroller, are stored. Most of the registers are
both readable and writeable but some are protected and
are readable only, the details of which are located under
0 0 H
0 1 H
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
1 4 H
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
2 0 H
2 1 H
2 2 H
2 3 H
2 4 H
2 5 H
2 6 H
2 7 H
2 8 H
2 9 H
2 A H
2 B H
2 C H
2 D H
2 E H
2 F H
3 0 H
3 1 H
3 2 H
3 3 H
3 4 H
3 5 H
3 6 H
3 7 H
3 8 H
3 9 H
3 A H
3 B H
3 C H
3 D H
IA R 0
M P 0
IA R 1
M P 1
B P
A C C
P C L
T B L P
T B L H
W D T S
S T A T U S
IN T C
Special Function Registers
To ensure successful operation of the microcontroller,
certain internal registers are implemented in the RAM
Data Memory area. These registers ensure correct operation of internal functions such as timers, interrupts,
watchdog, etc., as well as external functions such as I/O
data control. The location of these registers within the
RAM Data Memory begins at the address ²00H². Any
unused Data Memory locations between these special
function registers and the point where the General Purpose Memory begins is reserved for future expansion
purposes, attempting to read data from these locations
will return a value of ²00H².
T M R 0
T M R 0 C
L
L
L
L
L
L
T M R 1
T M R 1 C
P A
P A C
P B
P B C
P C
P C C
A T C H 0
A T C H 0
A T C H 0
A T C H 1
A T C H 1
A T C H 1
IN T C H
T B H P
Indirect Addressing Register - IAR0, IAR1
The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register
space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data
manipulation uses these Indirect Addressing Registers
and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in
no actual read or write operation to these registers but
rather to the memory location specified by their corresponding Memory Pointer, MP0 or MP1. Acting as a
pair, IAR0 and MP0 can together only access data from
Bank 0, while the IAR1 and MP1 register pair can access data from both Bank 0 and Bank 1. As the Indirect
Addressing Registers are not physically implemented,
reading the Indirect Addressing Registers indirectly will
return a result of ²00H² and writing to the registers indirectly will result in no operation.
H
M
M
L
H
L
T M R 2
T M R 2 C
T M R 3
T M R 3 C
V O IC E C
D A L
D A H
V O L
L A T C H D
Memory Pointer - MP0, MP1
P D
P D C
A D R L
A D R H
A D C R
A C S R
L V D C
P
P E
S B
S B
For all devices, two Memory Pointers, known as MP0
and MP1 are provided. These Memory Pointers are
physically implemented in the Data Memory and can be
manipulated in the same way as normal registers providing a convenient way with which to address and track
data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that
the microcontroller is directed to, is the address specified by the related Memory Pointer. MP0, together with
Indirect Addressing Register, IAR0, are used to access
data from Bank 0 only, while MP1 and IAR1 are used to
access data from both Bank 0 and Bank 1.
E
C
C R
D R
: U n k n o w
Special Purpose Data Memory Structure
Rev. 1.10
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December 12, 2012
HT86Axx/HT86ARxx
The following example shows how to clear a section of four RAM locations already defined as locations adres1 to
adres4.
data .section ¢data¢
adres1
db ?
adres2
db ?
adres3
db ?
adres4
db ?
block
db ?
code .section at 0 ¢code¢
org 00h
start:
mov
mov
mov
mov
a,04h
; setup size of block
block,a
a,offset adres1; Accumulator loaded with first RAM address
mp0,a
; setup memory pointer with first RAM address
clr
inc
sdz
jmp
IAR0
mp0
block
loop
loop:
; clear the data at address defined by MP0
; increment memory pointer
; check if last memory location has been cleared
continue:
The important point to note here is that in the example shown above, no reference is made to specific RAM addresses.
Bank Pointer - BP
carried out by the ALU. The Accumulator is the place
where all intermediate results from the ALU are stored.
Without the Accumulator it would be necessary to write
the result of each calculation or logical operation such
as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads.
Data transfer operations usually involve the temporary
storage function of the Accumulator; for example, when
transferring data between one user defined register and
another, it is necessary to do this by passing the data
through the Accumulator as no direct transfer between
two registers is permitted.
The RAM Data Memory is divided into two Banks,
known as Bank 0 and Bank 1. With the exception of the
BP register, all of the Special Purpose Registers and
General Purpose Registers are contained in Bank 0. If
data in Bank 0 is to be accessed, then the BP register
must be loaded with the value "00", while if data in Bank
1 is to be accessed, then the BP register must be loaded
with the value ²01².
Using Memory Pointer MP0 and Indirect Addressing
Register IAR0 will always access data from Bank 0, irrespective of the value of the Bank Pointer.
Program Counter Low Register - PCL
The Data Memory is initialised to Bank 0 after a reset,
except for the WDT time-out reset in the Power Down
Mode, in which case, the Data Memory bank remains
unaffected. It should be noted that Special Function
Data Memory is not affected by the bank selection,
which means that the Special Function Registers can be
accessed from within either Bank 0 or Bank 1. Directly
addressing the Data Memory will always result in Bank 0
being accessed irrespective of the value of the Bank
Pointer.
To provide additional program control functions, the low
byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area
of the Data Memory. By manipulating this register, direct
jumps to other program locations are easily implemented. Loading a value directly into this PCL register
will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only
jumps within the current Program Memory page are permitted. When such operations are used, note that a
dummy cycle will be inserted.
Accumulator - ACC
The Accumulator is central to the operation of any
microcontroller and is closely related with operations
b 7
b 0
B P 0
B a n k P o in te r
B P 0
0
1
D a ta M e m o ry
B a n k 0
B a n k 1
N o t u s e d , m u s t b e re s e t to "0 "
Bank Pointer - BP
Rev. 1.10
22
December 12, 2012
HT86Axx/HT86ARxx
Look-up Table Registers - TBLP, TBHP, TBLH
time-out or by executing the ²CLR WDT² or ²HALT² instruction. The PDF flag is affected only by executing the
²HALT² or ²CLR WDT² instruction or during a system
power-up.
These two special function registers are used to control
operation of the look-up table which is stored in the Program Memory. TBLP is the table pointer and indicates
the location where the table data is located. Its value
must be setup before any table read commands are executed. Its value can be changed, for example using the
²INC² or ²DEC² instructions, allowing for easy table data
pointing and reading. TBLH is the location where the
high order byte of the table data is stored after a table
read data instruction has been executed. Note that the
lower order table data byte is transferred to a user defined location.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
· C is set if an operation results in a carry during an ad-
dition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
· AC is set if an operation results in a carry out of the
low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is
cleared.
Watchdog Timer Register - WDTS
· Z is set if the result of an arithmetic or logical operation
The Watchdog feature of the microcontroller provides
an automatic reset function giving the microcontroller a
means of protection against spurious jumps to incorrect
Program Memory addresses. To implement this, a timer
is provided within the microcontroller which will issue a
reset command when its value overflows. To provide
variable Watchdog Timer reset times, the Watchdog
Timer clock source can be divided by various division ratios, the value of which is set using the WDTS register.
By writing directly to this register, the appropriate division ratio for the Watchdog Timer clock source can be
setup. Note that only the lower 3 bits are used to set division ratios between 1 and 128.
is zero; otherwise Z is cleared.
· OV is set if an operation results in a carry into the high-
est-order bit but not a carry out of the highest-order bit,
or vice versa; otherwise OV is cleared.
· PDF is cleared by a system power-up or executing the
²CLR WDT² instruction. PDF is set by executing the
²HALT² instruction.
· TO is cleared by a system power-up or executing the
²CLR WDT² or ²HALT² instruction. TO is set by a
WDT time-out.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status registers are important and if the subroutine
can corrupt the status register, precautions must be
taken to correctly save it.
Status Register - STATUS
This 8-bit register contains the zero flag (Z), carry flag
(C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO).
These arithmetic/logical operation and system management flags are used to record the status and operation of
the microcontroller.
Interrupt Control Register - INTC, INTCH
Two 8-bit register, known as the INTC and INTCH registers, controls the operation of both external and internal
timer interrupts. By setting various bits within these registers using standard bit manipulation instructions, the
enable/disable function of the external and timer interrupts can be independently controlled. A master interrupt bit within this register, the EMI bit, acts like a global
enable/disable and is used to set all of the interrupt enable bits on or off. This bit is cleared when an interrupt
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO
flag can be affected only by a system power-up, a WDT
b 7
b 0
T O
P D F
O V
Z
A C
C
S T A T U S R e g is te r
A r
C a
A u
Z e
ith m e
r r y fla
x ilia r y
r o fla g
O v e r flo w
g
tic /L o g ic O p e r a tio n F la g s
c a r r y fla g
fla g
S y s te m M
P o w e r d o w
W a tc h d o g
N o t im p le m
a n
n
tim
e
a g e m e n t F la g s
fla g
e - o u t fla g
n te d , re a d a s "0 "
Status Register
Rev. 1.10
23
December 12, 2012
HT86Axx/HT86ARxx
routine is entered to disable further interrupt and is set
by executing the ²RETI² instruction.
least 4ms at least, will be required to latch the voice ROM
data, after which the microcontroller can read the voice
data from LATCHD.
Note: In situations where other interrupts may require
servicing within present interrupt service routines, the EMI bit can be manually set by the program after the present interrupt service routine
has been entered.
Voice Control and Audio output Registers VOICEC, DAL, DAH, VOL
The device includes a single 12-bit current type DAC
function for driving an external 8W speaker through an
external NPN transistor. The programmer must write the
voice data to the DAL/DAH registers.
Timer Registers
All devices contain four 8-bit Timers whose associated
registers are known as TMR0, TMR1, TMR2 and TMR3,
which are the locations where the associated timer's
8-bit value is located. Their associated control registers,
known as TMR0C, TMR1C, TMR2C and TMR3C, contain the setup information for these timers. Note that all
timer registers can be directly written to in order to
preload their contents with fixed data to allow different
time intervals to be setup.
A/D Converter Registers ADRL, ADRH, ADCR, ACSR
The device contains a 4-channel 12-bit A/D converter.
The correct operation of the A/D requires the use of two
data registers, a control register and a clock source register. It contain a 12-bit A/D converter, there are two data
registers, a high byte data register known as ADRH, and
a low byte data register known as ADRL. These are the
register locations where the digital value is placed after
the completion of an analog to digital conversion cycle.
The channel selection and configuration of the A/D converter is setup via the control register ADCR while the
A/D clock frequency is defined by the clock source register, ACSR.
Input/Output Ports and Control Registers
Within the area of Special Function Registers, the I/O
registers and their associated control registers play a
prominent role. All I/O ports have a designated register
correspondingly labeled as PA, PB, PC, PD, PE, etc.
These labeled I/O registers are mapped to specific addresses within the Data Memory as shown in the Data
Memory table, which are used to transfer the appropriate output or input data on that port. With each I/O port
there is an associated control register labeled PAC,
PBC, PCC, PDC, PEC, etc., also mapped to specific addresses with the Data Memory. The control register
specifies which pins of that port are set as inputs and
which are set as outputs. To setup a pin as an input, the
corresponding bit of the control register must be set
high, for an output it must be set low. During program initialisation, it is important to first setup the control registers to specify which pins are outputs and which are
inputs before reading data from or writing data to the I/O
ports. One flexible feature of these registers is the ability
to directly program single bits using the ²SET [m].i² and
²CLR [m].i² instructions. The ability to change I/O pins
from output to input and vice-versa by manipulating specific bits of the I/O control registers during normal program operation is a useful feature of these devices.
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on
their I/O ports. With the input or output designation of every pin fully under user program control, pull-high options for all ports and wake-up options on certain pins,
the user is provided with an I/O structure to meet the
needs of a wide range of application possibilities.
Depending upon which device or package is chosen,
the microcontroller range provides 40 bidirectional input/output lines labeled with port names PA, PB, PC,
PD, PE, etc. These I/O ports are mapped to the RAM
Data Memory with specific addresses as shown in the
Special Purpose Data Memory table. All of these I/O
ports can be used for input and output operations. For
input operation, these ports are non-latching, which
means the inputs must be ready at the T2 rising edge of
instruction ²MOV A,[m]², where m denotes the port address. For output operation, all the data is latched and
remains unchanged until the output latch is rewritten.
Voice ROM Data Address Latch Counter Registers
These are the LATCH0H/LATCH0M/LATCH0L,
LATCH1H/LATCH1M/LATCH1L and the Voice ROM
data registers. The voice ROM data address latch count e r p ro vi d e s t h e h a n d s hak i ng b e t w e e n t h e
microcontroller and the voice ROM, where the voice
codes are stored. Eight bits of voice ROM data will be
addressed by using the 21-bit address latch counter,
which is composed of LATCH0H/LATCH0M/LATCH0L
or LATCH1H/LATCH1M/LATCH1L. After the 8-bit voice
ROM data is addressed, several instruction cycles of at
Rev. 1.10
Pull-high Resistors
Many product applications require pull-high resistors for
their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have
the capability of being connected to an internal pull-high
resistor. These pull-high resistors are selectable via
configuration options and are implemented using a
weak PMOS transistor. Note that if the pull-high option is
24
December 12, 2012
HT86Axx/HT86ARxx
There are no configuration options associated with
the A/D function. If used as I/O pins, then full pull-high
resistor selections remain, however if used as A/D inputs then any pull-high resistor selections associated
with these pins will be automatically disconnected.
selected, then all I/O pins on that port will be connected
to pull-high resistors, individual pins can be selected for
pull-high resistor options.
Port A Wake-up
· Serial Interface
Each device has a HALT instruction enabling the
microcontroller to enter a Power Down Mode and preserve power, a feature that is important for battery and
other low-power applications. Various methods exist to
wake-up the microcontroller, one of which is to change
the logic condition on one of the Port A pins from high to
low. After a ²HALT² instruction forces the microcontroller
into entering a HALT condition, the processor will remain idle or in a low-power state until the logic condition
of the selected wake-up pin on Port A changes from high
to low. This function is especially suitable for applications that can be woken up via external switches. Note
that each pin on Port A can be selected individually to
have this wake-up feature.
The Serial Interface are pin-shared with PD0 to PD3.
If there are to be used as Serial Interface inputs and
not as normal I/O pins then the corresponding bits in
the Serial Interface Control Register that must be
properly set. There are a configuration option associated with the Serial Interface function. If used as I/O
pins, then full pull-high resistor selections remain,
however if used as the Serial Interface inputs then any
pull-high resistor selections associated with these
pins will be automatically disconnected.
· I/O Pin Structures
The following diagrams illustrate the I/O pin internal
structures. As the exact logical construction of the I/O
pin may differ from these drawings, they are supplied
as a guide only to assist with the functional understanding of the I/O pins. Note also that the specified
pins refer to the largest device package, therefore not
all pins specified will exist on all devices.
I/O Port Control Registers
Each I/O port has its own control register PAC, PBC,
PCC, PDC, PEC, etc., to control the input/output configuration. With this control register, each CMOS output or
input with or without pull-high resistor structures can be
reconfigured dynamically under software control. Each
pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as
an input, the corresponding bit of the control register
must be written as a ²1². This will then allow the logic
state of the input pin to be directly read by instructions.
When the corresponding bit of the control register is
written as a ²0², the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions
can still be used to read the output register. However, it
should be noted that the program will in fact only read
the status of the output data latch and not the actual
logic status of the output pin.
Programming Considerations
Within the user program, one of the first things to consider is port initialization. After a reset, all of the I/O data
and port control registers will be set high. This means
that all I/O pins will default to an input state, the level of
which depends on the other connected circuitry and
whether pull-high options have been selected. If the port
control registers, PAC, PBC, PCC, PDC, PEC etc., are
then programmed to setup some pins as outputs, these
output pins will have an initial high output value unless
the associated port data registers, PA, PB, PC, PD, PE,
etc., are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide
by loading the correct values into the appropriate port
control register or by programming individual bits in the
port control register using the ²SET [m].i² and ²CLR
[m].i² instructions. Note that when using these bit control
instructions, a read-modify-write operation takes place.
The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then
rewrite this data back to the output ports.
Pin-shared Functions
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design
constraints on designers but by supplying pins with
multi-functions, many of these difficulties can be overcome. For some pins, the chosen function of the
multi-function I/O pins is set by configuration options
while for others the function is set by application program control.
T 1
S y s te m
T 3
T 4
T 1
T 2
T 3
T 4
P o rt D a ta
· A/D Inputs
W r ite to P o r t
The device have 4 A/D converter channel inputs. All of
these analog inputs are pin-shared with PC0 to PC3. If
these pins are to be used as A/D inputs and not as
normal I/O pins then the corresponding bits in the A/D
Converter Control Register that must be properly set.
Rev. 1.10
T 2
C lo c k
R e a d fro m
P o rt
Read/Write Timing
25
December 12, 2012
HT86Axx/HT86ARxx
V
P u ll- H ig h
O p tio n
C o n tr o l B it
D a ta B u s
Q
D
W r ite C o n tr o l R e g is te r
C K
D D
W e a k
P u ll- u p
Q
S
C h ip R e s e t
P A 0 ~ P A 7
R e a d C o n tr o l R e g is te r
D a ta B it
Q
D
W r ite D a ta R e g is te r
C K
Q
S
M
U
X
R e a d D a ta R e g is te r
S y s te m
W a k e -u p
W a k e - u p O p tio n
PA Input/Output Port
V
P u ll- H ig h
O p tio n
C o n tr o l B it
D a ta B u s
Q
D
W r ite C o n tr o l R e g is te r
C K
D D
W e a k
P u ll- u p
Q
S
C h ip R e s e t
P B 0 ~ P B 7
P E 0 ~ P E 7
R e a d C o n tr o l R e g is te r
D a ta B it
Q
D
W r ite D a ta R e g is te r
C K
Q
S
M
R e a d D a ta R e g is te r
U
X
PB/PE Input/Output Ports
V
P u ll- H ig h
O p tio n
C o n tr o l B it
D a ta B u s
Q
D
W r ite C o n tr o l R e g is te r
C K
D D
W e a k
P u ll- u p
Q
S
C h ip R e s e t
P C 0 ~ P C 7
A D 0 ~ A D 3
R e a d C o n tr o l R e g is te r
D a ta B it
Q
D
W r ite D a ta R e g is te r
C K
S
Q
M
P C 0 D a ta B it
A D 0 ~ A D 3
M
R e a d D a ta R e g is te r
U
U
X
A /D
C o n v e rte r
X
PC Input/Output Port
Rev. 1.10
26
December 12, 2012
HT86Axx/HT86ARxx
V
P u ll- H ig h
O p tio n
C o n tr o l B it
D a ta B u s
Q
D
W r ite C o n tr o l R e g is te r
C K
D D
W e a k
P u ll- u p
Q
S
C h ip R e s e t
P D 0 ~ P D 7
S C S , S C K , S D I, S D O
R e a d C o n tr o l R e g is te r
D a ta B it
Q
D
W r ite D a ta R e g is te r
C K
S
Q
M
P D 0 D a ta B it
S C S , S C K , S D I, S D O
M
R e a d D a ta R e g is te r
U
U
X
S e r ia l In te r fa c e
X
PD Input/Output Port
the system clock divided by four or the RTC clock which
is derived from a external 32kHz crystal. A configuration
option determines which clock is selected. If the RTC
clock is selected then note that it will continue to run
when the device is powered down using the HALT instruction. The 8-bit timer clock source is also first divided by a prescaler, the division ratio of which is
conditioned by the three lower bits of the associated
timer control register.
Port A has the additional capability of providing wake-up
functions. When the device is in the Power Down Mode,
various methods are available to wake the device up.
One of these is a high to low transition of any of the Port
A pins. Single or multiple pins on Port A can be setup to
have this function.
Timers
The provision of timers form an important part of any
microcontroller, giving the designer a means of carrying
out time related functions. The devices in the Voice Type
MCU series contain four count up timers of 8-bit capacity. Each timer has only one operating mode, which is to
act as a general timer. The provision of an internal
prescaler to the clock circuitry of the timers gives added
range to the timer.
Timer Registers - TMR0, TMR1, TMR2, TMR3
The timer registers are special function registers located
in the special purpose Data Memory and is the place
where the actual timer value is stored. The value in the
timer registers increases by one each time an internal
clock pulse is received. The timer will count from the initial value loaded by the preload register to the full count
of FFH at which point the timer overflows and an internal
interrupt signal is generated. The timer value will then
be reset with the initial preload register value and continue counting.
Configuring the Timer Input Clock Source
The clock source of Timer0/Timer1/Tmier2 is the system
clock divided by four and the clock source of Timer3 is
D a ta B u s
T 2 P S C 2 ~ T 2 P S C 0
T 1 P S C 2 ~ T 1 P S C 0
T 0 P S C 2 ~ T 0 P S C 0
fS
Y S
/4
P r e s c a le r
(1 /2 ~ 1 /2 5 6 )
T 2 T M 1
T 1 T M 1
T 0 T M 1
P r e lo a d R e g is te r
T 2 T M 0
T 1 T M 0
T 0 T M 0
T im e r
T im e r M o d e C o n tr o l
T 0 O N
T 1 O N
T 2 O N
R e lo a d
O v e r flo w
to In te rru p t
8 - B it T im e r
8-bit Timer Structure - TMR0, TMR1, TMR2
Rev. 1.10
27
December 12, 2012
HT86Axx/HT86ARxx
D a ta B u s
P r e lo a d R e g is te r
C o n fig u r a tio n
O p tio n
fS
Y S /4
R T C
M U X
T 3 P S C 2 ~ T 3 P S C 0
P r e s c a le r
T 3 T M 1
R e lo a d
T 3 T M 0
O v e r flo w
to In te rru p t
T im e r
T im e r M o d e C o n tr o l
(1 /2 ~ 1 /2 5 6 )
T 3 O N
8 - B it T im e r
8-bit Timer Structure - TMR3
timer-on bit, which is bit 4 of the Timer Control Register
and known as TON, provides the basic on/off control of
the respective timer. setting the bit high allows the timer
to run, clearing the bit stops the timer. Bits 0~2 of the
Timer Control Register determine the division ratio of
the input clock prescaler.
Note that to achieve a maximum full range count of FFH
for the 8-bit timer, the preload registers must first be
cleared to all zeros. It should be noted that after
power-on, the preload registers will be in an unknown
condition. Note that if the Timer Counters are in an OFF
condition and data is written to their preload registers,
this data will be immediately written into the actual counter. However, if the counter is enabled and counting, any
new data written into the preload data register during
this period will remain in the preload register and will
only be written into the actual counter the next time an
overflow occurs. Note also that when the timer registers
are read, the timer clock will be blocked to avoid errors,
however, as this may result in certain timing errors, programmers must take this into account.
Configuring the Timer
The Timer is used to measure fixed time intervals, providing an internal interrupt signal each time the Timer
overflows. To do this the Operating Mode Select bit pair
in the Timer Control Register must be set to the correct
value as shown.
The Timer clock source is further divided by a prescaler,
the value of which is determined by the Prescaler Rate
Select bits, which are bits 0~2 in the Timer Control Register. After the other bits in the Timer Control Register
have been setup, the enable bit, which is bit 4 of the
Timer Control Register, can be set high to enable the
Timer to run. Each time an internal clock cycle occurs,
the Timer increments by one. When it is full and overflows, an interrupt signal is generated and the Timer will
reload the value already loaded into the preload register
and continue counting. The interrupt can be disabled by
ensuring that the Timer Interrupt Enable bit in the Interrupt Control Register, INTC, is reset to zero.
Timer Control Registers TMR0C, TMR1C, TMR2C, TMR3C
The timers are setup using their respective control register. These registers are known as TMR0C, TMR1C,
TMR2C and TMR3C. It is the timer control register together with its corresponding timer registers that control
the full operation of the Timer. Before the timers can be
used, it is essential that the appropriate timer control
register is fully programmed with the right data to ensure
its correct operation, a process that is normally carried
out during program initialization.
Bits 7 and 6 of the Timer Control Register, which are
known as the bit pair TM1/TM0, must be set to 10 respectively to ensure correct Timer operation. The
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o n tr o lle r
T im e r + 1
T im e r + 2
T im e r + N
T im e r + N
+ 1
Timer Mode Timing Diagram
Rev. 1.10
28
December 12, 2012
HT86Axx/HT86ARxx
b 7
T M 1
b 0
T M 0
T O N
P S C 2
P S C 1
P S C 0
T M R 0 C /T M R 1 C /T M R 2 C /T M R 3 C
T im
T 0
T 1
T 2
T 3
e r
P S C
P S C
P S C
P S C
0
0
0
0
1
1
1
1
P re s
2 T
2 T
2 T
2 T
c a
0
1
2
3
le r
P S C
P S C
P S C
P S C
0
0
1
1
0
0
1
1
R a te
T
1
T
1
T
1
T
1
S e
0 P
1 P
2 P
3 P
le c
S C
S C
S C
S C
0
1
0
1
0
1
0
1
R e g is te r
t
0
0
0
0
T im e r R a te
1 :2
1 :4
1 :8
1 :1
1 :3
1 :6
1 :1
1 :2
6
2
4
2 8
5 6
N o t im p le m e n t e d , r e a d a s " d o n 't c a r e "
T im e r o n /o ff c o n tr o l
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "
O p
T 0
T 1
T 2
T 3
e r
T M
T M
T M
T M
0
0
1
1
a tin g M
T
1
T
1
T
1
T
1
o d
0 T
1 T
2 T
3 T
1
0
1
0
e S e le c t
M 0
M 0
M 0
M 0
n o
n o
tim
n o
m o d
m o d
e r m
m o d
e a v a ila b le
e a v a ila b le
o d e
e a v a ila b le
Timer Control Register - All Devices
Prescaler
must be properly set otherwise the internal interrupt associated with the timer will remain inactive. It is also important to ensure that an initial value is first loaded into
the timer registers before the timer is switched on; this is
because after power-on the initial values of the timer
registers are unknown. After the timer has been initialised the timer can be turned on and off by controlling the
enable bit in the timer control register.
All of the 8-bit timers possess a prescaler. Bits 0~2 of
their associated timer control register, define the
pre-scaling stages of the internal clock source of the
Timer. The Timer overflow signal can be used to generate signals for the Timer interrupt.
Programming Considerations
The internal system clock is used as the timer clock
source and is therefore synchronized with the overall
operation of the microcontroller. In this mode, when the
appropriate timer register is full, the microcontroller will
generate an internal interrupt signal directing the program flow to the respective internal interrupt vector.
Timer Program Example
The following example program section is based on the
devices, which contain a single internal 8-bit timer. Programming the timer for other devices is conducted in a
very similar way. The program shows how the timer registers are setup along with how the interrupts are enabled and managed. Also note how the timer is turned
on by setting bit 4 of the respective timer control register.
The timer can be turned off in a similar way by clearing
the same bit. This example program sets the timer to be
in the timer mode which uses the internal system clock
as their clock source.
When the Timer is read, the clock is blocked to avoid errors, however as this may result in a counting error, this
should be taken into account by the programmer. Care
must be taken to ensure that the timers are properly initialised before using them for the first time. The associated timer enable bits in the interrupt control register
Rev. 1.10
29
December 12, 2012
HT86Axx/HT86ARxx
include HT86A72.inc
jmp begin
:
org 04h
; external interrupt vectors
reti
org 08h
reti
org 0Ch
reti
org 10h
; timer 2 interrupt vector
jmp tmr2int
; jump here when timer 2 overflows
org 14h
reti
org 18h
reti
:
; internal timer 2 interrupt routine
tmr2int:
:
; timer 2 main program placed here
:
reti
:
begin:
; setup timer 2 registers
mov a,09bh
; setup timer 2
mov tmr2,a
mov a,0097h
; setup timer 2
mov tmr2c,a
; setup timer 2
; setup interrupt register
mov a,01h
; enable master interrupt
mov intc,a
mov a,01h
; enable timer 2 interrupt
mov intch,a
:
Rev. 1.10
30
December 12, 2012
HT86Axx/HT86ARxx
Interrupts
Interrupts are an important part of any microcontroller
system. When an external event or an internal function
such as a Timer requires microcontroller attention, their
corresponding interrupt will enforce a temporary susp e n s io n o f t h e m a i n pr o g r am al l ow i n g t h e
microcontroller to direct attention to their respective
needs.
next instruction from this interrupt vector. The instruction at this vector will usually be a JMP statement which
will take program execution to another section of program which is known as the interrupt service routine.
Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated
with a RETI statement, which retrieves the original Program Counter address from the stack and allows the
microcontroller to continue with normal execution at the
point where the interrupt occurred.
Interrupt Register
Overall interrupt control, which means interrupt enabling
and flag setting, is controlled using two registers, known
as INTC and INTCH, which are located in the Data
Memory. By controlling the appropriate enable bits in
these registers each individual interrupt can be enabled
or disabled. Also when an interrupt occurs, the corresponding request flag will be set by the microcontroller.
The global enable flag if cleared to zero will disable all
interrupts.
The various interrupt enable bits, together with their associated request flags, are shown in the accompanying
diagram with their order of priority.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be cleared automatically. This will prevent any further interrupt nesting
from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing
while the program is already in another interrupt service
routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the
related interrupt is enabled, until the Stack Pointer is
decremented. If immediate service is desired, the stack
must be prevented from becoming full.
Interrupt Operation
A timer overflow or the external interrupt line being
pulled low will all generate an interrupt request by setting their corresponding request flag, if their appropriate
interrupt enable bit is set. When this happens, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the
stack. The Program Counter will then be loaded with a
new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its
b 7
b 0
T 1 F
T 0 F
E IF
E T 1 I
E T 0 I
E E I
E M I
IN T C R e g is te r
M a s te r In te r r u p t G lo b a l E n a b le
1 : g lo b a l e n a b le
0 : g lo b a l d is a b le
E x te r n a l In te r r u p t E n a b le
1 : e n a b le
0 : d is a b le
T im e r 0 In te r r u p t E n a b le
1 : e n a b le
0 : d is a b le
T im e r 1 In te r r u p t E n a b le
1 : e n a b le
0 : d is a b le
E x te r n a l In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
T im e r 0 In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
T im e r 1 In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
N o im p le m e n te d , r e a d a s " 0 "
Interrupt Control Register
Rev. 1.10
31
December 12, 2012
HT86Axx/HT86ARxx
b 7
b 0
A D F
T 3 F
T 2 F
E A D I
E T 3 I E T 2 I
IN T C H
R e g is te r
T im e r 2 In te r r u p t E n a b le
1 : e n a b le
0 : d is a b le
T im e r 3 In te r r u p t E n a b le
1 : e n a b le
0 : d is a b le
A /D
C o n v e r te r In te r r u p t E n a b le
N o im p le m e n te d , r e a d a s " 0 "
T im e r 2 In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
T im e r 3 In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
A /D C o n v e r te r In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
N o im p le m e n te d , r e a d a s " 0 "
INTCH Register
A u to m a tic a lly D is a b le d b y IS R
C a n b e E n a b le d M a n u a lly
A u to m a tic a lly C le a r e d b y IS R
M a n u a lly S e t o r C le a r e d b y S o ftw a r e
P r io r ity
E x te rn a l In te rru p t
R e q u e s t F la g E IF
E E I
T im e r 0
In te r r u p t R e q u e s t F la g T 0 F
E T 0 I
T im e r 1
In te r r u p t R e q u e s t F la g T 1 F
E T 1 I
T im e r 2
In te r r u p t R e q u e s t F la g T 2 F
E T 2 I
T im e r 3
In te r r u p t R e q u e s t F la g T 3 F
E T 3 I
A /D C o n v e rte r
In te r r u p t R e q u e s t F la g A D F
E A D I
E M I
H ig h
In te rru p t
P o llin g
L o w
Interrupt Structure
Rev. 1.10
32
December 12, 2012
HT86Axx/HT86ARxx
Interrupt Priority
External Interrupt
04H
1
Timer 0 Overflow
08H
2
Timer 1 Overflow
0CH
3
Timer 2 Overflow
10H
4
Each timer also has a corresponding timer interrupt request flag, which are known as T0F, T1F, T2F and T3F,
also located in the INTC and INTCH registers. When the
master interrupt and corresponding timer interrupt enable bits are enabled, the stack is not full, and when the
corresponding timer overflows a subroutine call to the
corresponding timer interrupt vector will occur. The corresponding Program Memory vector locations for Timer
0, Timer1, Timer 2 and Timer 3 are 08H, 0CH, 10H and
14H. After entering the interrupt execution routine, the
corresponding interrupt request flags, T0F, T1F, T2F or
T3F will be reset and the EMI bit will be cleared to disable other interrupts.
Timer 3 Overflow
14H
5
A/D Converter Interrupt
A/D Converter Overflow
18H
6
The internal A/D Converter interrupt is initialised by setting the A/D interrupt request flag (ADF:bit6 of INTCH).
When the interrupt is enabled, and the stack is not full
and the ADF bit is set, a subroutine call to location ²18H²
will occur. The related interrupt request flag, ADF, will be
reset and the EMI bit cleared to disable further interrupts.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of simultaneous requests, the
accompanying table shows the priority that is applied.
Interrupt Source
Interrupt Vector Priority
In cases where both external the timer interrupts are enabled and where an external and timer interrupt occur
simultaneously, the external interrupt will always have
priority and will therefore be serviced first. Suitable
masking of the individual interrupts using the INTC and
INTCH registers can prevent simultaneous occurrences.
Programming Considerations
By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however,
once an interrupt request flag is set, it will remain in this
condition in the INTC or INTCH register until the corresponding interrupt is serviced or until the request flag is
cleared by a software instruction.
External Interrupt
Each device contains a single external interrupt function
controlled by the external pin, INT. For an external interrupt to occur, the corresponding external interrupt enable bit must be first set. This is bit 1 of the INTC register
and known as EEI. An external interrupt is triggered by
an external edge transition on the external interrupt pin
INT, after which the related interrupt request flag, EIF,
which is bit 4 of INTC, will be set. A configuration option
exists for the external interrupt pin to determine the type
of external edge transition which will trigger an external
interrupt. There are two options available, a low going
edge or both high and low going edges. When the master interrupt and external interrupt bits are enabled, the
stack is not full and an active edge transition, as setup in
the configuration options, occurs on the INT pin, a subroutine call to the corresponding external interrupt vector, which is located at 04H, will occur. After entering the
interrupt execution routine, the corresponding interrupt
request flag, EIF, will be reset and the EMI bit will be
cleared to disable other interrupts.
It is recommended that programs do not use the ²CALL
subroutine² instruction within the interrupt subroutine.
Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications. If
only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged
once a ²CALL subroutine² is executed in the interrupt
subroutine.
All of these interrupts have the capability of waking up
the MCU when in the Power Down Mode. Only the Program Counter is pushed onto the stack. If the contents of
the register or status register are altered by the interrupt
service program, which may corrupt the desired control
sequence, then the contents should be saved in advance.
Timer Interrupt
For a timer generated interrupt to occur, the corresponding timer interrupt enable bit must be first set. Each device contains four 8-bit timers whose corresponding
interrupt enable bits are known as ET0I, ET1I, ET2I and
ET3I and are located in the INTC and INTCH registers.
Rev. 1.10
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HT86Axx/HT86ARxx
Reset and Initialisation
inhibited. After the RES line reaches a certain voltage
value, the reset delay time tRSTD is invoked to provide
an extra delay time after which the microcontroller will
begin normal operation. The abbreviation SST in the
figures stands for System Start-up Timer.
A reset function is a fundamental part of any
microcontroller ensuring that the device can be set to
some predetermined condition irrespective of outside
parameters. The most important reset condition is after
power is first applied to the microcontroller. In this case,
internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready
to execute the first program instruction. After this
power-on reset, certain important internal registers will
be set to defined states before the program commences. One of these registers is the Program Counter,
which will be reset to zero forcing the microcontroller to
begin program execution from the lowest Program
Memory address.
V D D
0 .9 V
R E S
tR
D D
S T D
S S T T im e - o u t
In te rn a l R e s e t
Power-On Reset Timing Chart
For most applications a resistor connected between
VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES
pin should be kept as short as possible to minimise
any stray noise interference.
In addition to the power-on reset, situations may arise
where it is necessary to forcefully apply a reset condition
when the microcontroller is running. One example of this
is where after power has been applied and the
microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain
unchanged allowing the microcontroller to proceed with
normal operation after the reset line is allowed to return
high. Another type of reset is when the Watchdog Timer
overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup.
V D D
1 0 0 k W
R E S
0 .1 m F
V S S
Basic Reset Circuit
For applications that operate within an environment
where more noise is present the Enhanced Reset Circuit shown is recommended.
Another reset exists in the form of a Low Voltage Reset,
LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage
falls below a certain threshold.
0 .0 1 m F
V D D
1 0 0 k W
Reset Functions
R E S
There are five ways in which a microcontroller reset can
occur, through events occurring both internally and externally:
1 0 k W
0 .1 m F
V S S
· Power-on Reset
Enhanced Reset Circuit
The most fundamental and unavoidable reset is the
one that occurs after power is first applied to the
microcontroller. As well as ensuring that the Program
Memory begins execution from the first memory address, a power-on reset also ensures that certain
other registers are preset to known conditions. All the
I/O port and port control registers will power up in a
high condition ensuring that all pins will be first set to
inputs.
Although the microcontroller has an internal RC reset
function, if the VDD power supply rise time is not fast
enough or does not stabilise quickly at power-on, the
internal reset function may be incapable of providing
proper reset operation. For this reason it is recommended that an external RC network is connected to
the RES pin, whose additional time delay will ensure
that the RES pin remains low for an extended period
to allow the power supply to stabilise. During this time
delay, normal operation of the microcontroller will be
More information regarding external reset circuits is
located in Application Note HA0075E on the Holtek
website.
· RES Pin Reset
This type of reset occurs when the microcontroller is
already running and the RES pin is forcefully pulled
low by external hardware such as an external switch.
In this case as in the case of other reset, the Program
Counter will reset to zero and program execution initiated from this point.
R E S
0 .4 V
0 .9 V
D D
D D
tR
S T D
S S T T im e - o u t
In te rn a l R e s e t
RES Reset Timing Chart
Rev. 1.10
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December 12, 2012
HT86Axx/HT86ARxx
· Low Voltage Reset - LVR
Reset Initial Conditions
The microcontroller contains a low voltage reset circuit
in order to monitor the supply voltage of the device,
which is selected via a configuration option. If the supply
voltage of the device drops to within a range of
0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally. The LVR includes the following specifications: For
a valid LVR signal, a low voltage, i.e., a voltage in the
range between 0.9V~VLVR must exist for greater than the
value tLVR specified in the A.C. characteristics. If the low
voltage state does not exceed 1ms, the LVR will ignore it
and will not perform a reset function.
The different types of reset described affect the reset
flags in different ways. These flags, known as PDF and
TO are located in the status register and are controlled
by various microcontroller operations, such as the
Power Down function or Watchdog Timer. The reset
flags are shown in the table:
TO PDF
L V R
tR
S T D
S S T T im e - o u t
RESET Conditions
0
0
RES reset during power-on
u
u
RES or LVR reset during normal operation
1
u
WDT time-out reset during normal operation
1
1
WDT time-out reset during Power Down
Note: ²u² stands for unchanged
In te rn a l R e s e t
The following table indicates the way in which the various components of the microcontroller are affected after
a power-on reset occurs.
Low Voltage Reset Timing Chart
· Watchdog Time-out Reset during Normal Operation
Item
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except
that the Watchdog time-out flag TO will be set to ²1².
W D T T im e - o u t
tR
S T D
S S T T im e - o u t
Program Counter
Reset to zero
Interrupts
All interrupts will be disabled
WDT
Clear after reset, WDT begins
counting
Timer
All Timer will be turned off
Prescaler
The Timer Prescaler will be
cleared
In te rn a l R e s e t
WDT Time-out Reset during Normal Operation
Timing Chart
Condition After RESET
Input/Output Ports I/O ports will be setup as inputs
Stack Pointer
· Watchdog Time-out Reset during Power Down
Stack Pointer will point to the top
of the stack
The Watchdog time-out Reset during Power Down is
a little different from other kinds of reset. Most of the
conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to
²0² and the TO flag will be set to ²1². Refer to the A.C.
Characteristics for tSST details.
W D T T im e - o u t
tS
S T
S S T T im e - o u t
WDT Time-out Reset during Power Down
Timing Chart
Rev. 1.10
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December 12, 2012
HT86Axx/HT86ARxx
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable
continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller
is in after a particular reset occurs. The following table describes how each type of reset affects each of the
microcontroller internal registers. Note that where more than one package type exists the table will reflect the situation
for the larger package type.
Register
Reset
(Power-on)
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
from HALT
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
BP
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
PCL
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
STATUS
--00 xxxx
-- 1u uuuu
--uu uuuu
-- 01 uuuu
--11 uuuu
INTC
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR0
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
TMR1
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TMR1C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PD
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PDC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PE
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PEC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
TMR2
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TMR2C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
TMR3
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TMR3C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
INTCH
-000 -000
-000 -000
-000 -000
-000 -000
-uuu -uuu
TBHP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
DAL
xxxx ----
uuuu ----
uuuu ----
uuuu ----
uuuu ----
DAH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
VOL
xxx- ----
xxx- ----
xxx- ----
xxx- ----
uuu- ----
VOICEC
0000 -00-
0000 -00-
0000 -00-
0000 -00-
uuuu -uu-
Rev. 1.10
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December 12, 2012
HT86Axx/HT86ARxx
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
from HALT
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
LATCH1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
LATCH1M
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
LATCH1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
LATCHD
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ADRL
xxxx ----
xxxx ----
xxxx ----
xxxx ----
uuuu ----
ADRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR
0100 0000
0100 0000
0100 0000
0100 0000
uuuu uuuu
ACSR
---- --00
---- --00
---- --00
---- --00
---- --uu
Register
Reset
(Power-on)
LATCH0H
xxxx xxxx
uuuu uuuu
LATCH0M
xxxx xxxx
LATCH0L
LVDC
000x 0-00
000x 0-00
000x 0-00
000x 0-00
uuux u-uu
SBCR
0110 0000
0110 0000
0110 0000
0110 0000
uuuu uuuu
SBDR
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
Note: ²u² stands for unchanged
²x² stands for unknown
²-² stands for undefined
Rev. 1.10
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December 12, 2012
HT86Axx/HT86ARxx
Oscillator
OSC1 and VSS. A clock signal, with a frequency of the
generated system clock divided by 4, will be provided on
OSC2 as an output which can be used for external synchronisation purposes. Note that as the OSC2 output is
an NMOS open-drain type, a pull high resistor should be
connected if it to be used to monitor the internal frequency. Although this is a cost effective oscillator configuration, the oscillation frequency can vary with VDD,
temperature and process variations and is therefore not
suitable for applications where timing is critical or where
accurate oscillator frequencies are required. Note that it
is the only microcontroller internal circuitry together with
the external resistor, that determines the frequency of
the oscillator.
Various oscillator options offer the user a wide range of
functions according to their various application requirements. Two types of system clocks can be selected
while various clock source options for the Watchdog
Timer are provided for maximum flexibility. All oscillator
options are selected through the configuration options.
The two methods of generating the system clock are:
· External crystal/resonator oscillator
· External RC oscillator
One of these two methods must be selected using the
configuration options.
More information regarding the oscillator is located in
Application Note HA0075E on the Holtek website.
O S C 1
External Crystal/Resonator Oscillator
R
The simple connection of a crystal across OSC1 and
OSC2 will create the necessary phase shift and feedback for oscillation, and will normally not require external capacitors. However, for some crystals and most
resonator types, to ensure oscillation and accurate frequency generation, it may be necessary to add two
small value external capacitors, C1 and C2. The exact
values of C1 and C2 should be selected in consultation
C 1
R f
C a
C b
C 2
RTC Oscillator
A 32KHz crystal can be connected to pins XIN and
XOUT to implement an RTC oscillator. The RTC oscillator is used as a clock source for Timer/Event Counter 3
but must be first enabled using a configuration option. If
the configuration option enables the RTC oscillator then
it will automatically become the clock source for the
Timer/Event Counter 3. The RTC oscillator will continue
to operate even if the HALT instruction is executed and
the device is powered down. It may be necessary to
connect two small capacitors between XIN, XOUT and
ground for correct operation of the RTC.
Crystal/Resonator Oscillator
with the crystal or resonator manufacturer¢s specification. The external parallel feedback resistor, Rp, is normally not required but in some cases may be needed to
assist with oscillation start up.
Internal Ca, Cb, Rf Typical Values @ 5V, 25°C
Cb
Rf
11~13pF
13~15pF
800kW
3 2 7 6 8 H z
Oscillator Internal Component Values
External RC Oscillator
X IN
X O U T
Using the external system RC oscillator requires that an
external resistor is connected. For the Mask version device a value of between 120kW and 280kW is required
For the OPT device a value of between 40kW and 90kW
is required. This external resistor is connected between
Rev. 1.10
O S C 2
The WDT oscillator is a fully self-contained free running
on-chip RC oscillator with a typical period of 65ms at 5V
requiring no external components. When the device enters the Power Down Mode, the system clock will stop
running but the WDT oscillator continues to free-run and
to keep the watchdog active. However, to preserve
power in certain applications the WDT oscillator can be
disabled via a configuration option.
N o te : 1 . R p is n o r m a lly n o t r e q u ir e d .
2 . A lth o u g h n o t s h o w n O S C 1 /O S C 2 p in s h a v e a p a r a s itic
c a p a c ita n c e o f a r o u n d 7 p F .
Ca
/4 N M O S O p e n D r a in
Watchdog Timer Oscillator
T o in te r n a l
c ir c u its
O S C 2
Y S
External RC Oscillator
In te r n a l
O s c illa to r
C ir c u it
O S C 1
R p
fS
O S C
RTC Oscillator
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December 12, 2012
HT86Axx/HT86ARxx
Power Down Mode and Wake-up
Power Down Mode
Wake-up
All of the Holtek microcontrollers have the ability to enter
a Power Down Mode, also known as the HALT Mode or
Sleep Mode. When the device enters this mode, the normal operating current, will be reduced to an extremely
low standby current level. This occurs because when
the device enters the Power Down Mode, the system
oscillator is stopped which reduces the power consumption to extremely low levels, however, as the device
maintains its present internal condition, it can be woken
up at a later stage and continue running, without requiring a full reset. This feature is extremely important in application areas where the MCU must have its power
supply constantly maintained to keep the device in a
known condition but where the power supply capacity is
limited such as in battery applications.
After the system enters the Power Down Mode, it can be
woken up from one of various sources listed as follows:
· An external reset
· An external falling edge on Port A
· A system interrupt
· A WDT overflow
If the system is woken up by an external reset, the device will experience a full system reset, however, if the
device is woken up by a WDT overflow, a Watchdog
Timer reset will be initiated. Although both of these
wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a
system power-up or executing the clear Watchdog
Timer instructions and is set when executing the ²HALT²
instruction. The TO flag is set if a WDT time-out occurs,
and causes a wake-up that only resets the Program
Counter and Stack Pointer, the other flags remain in
their original status.
Entering the Power Down Mode
There is only one way for the device to enter the Power
Down Mode and that is to execute the ²HALT² instruction in the application program. When this instruction is
executed, the following will occur:
· The system oscillator will stop running and the appli-
Each pin on Port A can be setup via an individual configuration option to permit a negative transition on the pin
to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the ²HALT² instruction.
cation program will stop at the ²HALT² instruction.
· The Data Memory contents and registers will maintain
their present condition.
· The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the WDT
oscillator. The WDT will stop if its clock source originates from the system clock.
If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related
interrupt is disabled or the interrupt is enabled but the
stack is full, in which case the program will resume execution at the instruction following the ²HALT² instruction.
In this situation, the interrupt which woke-up the device
will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or
when a stack level becomes free. The other situation is
where the related interrupt is enabled and the stack is
not full, in which case the regular interrupt response
takes place. If an interrupt request flag is set to ²1² before entering the Power Down Mode, the wake-up function of the related interrupt will be disabled.
· The I/O ports will maintain their present condition.
· In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be
cleared.
Standby Current Considerations
As the main reason for entering the Power Down Mode
is to keep the current consumption of the MCU to as low
a value as possible, perhaps only in the order of several
micro-amps, there are other considerations which must
also be taken into account by the circuit designer if the
power consumption is to be minimized. Special attention must be made to the I/O pins on the device. All
high-impedance input pins must be connected to either
a fixed high or low level as any floating input pins could
create internal oscillations and result in increased current consumption. Care must also be taken with the
loads, which are connected to I/Os, which are setup as
outputs. These should be placed in a condition in which
minimum current is drawn or connected only to external
circuits that do not draw current, such as other CMOS
inputs. Also note that additional standby current will also
be required if the configuration options have enabled the
Watchdog Timer internal oscillator.
Rev. 1.10
No matter what the source of the wake-up event is, once
a wake-up situation occurs, a time period equal to 1024
system clock periods will be required before normal system operation resumes. However, if the wake-up has
originated due to an interrupt, the actual interrupt subroutine execution will be delayed by an additional one or
more cycles. If the wake-up results in the execution of
the next instruction following the ²HALT² instruction, this
will be executed immediately after the 1024 system
clock period delay has ended.
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December 12, 2012
HT86Axx/HT86ARxx
Watchdog Timer
The Watchdog Timer is provided to prevent program
malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events
such as electrical noise. It operates by providing a device reset when the WDT counter overflows. The WDT
clock is supplied by one of two sources selected by configuration option: its own self-contained dedicated internal WDT oscillator, or the instruction clock which is the
system clock divided by 4. Note that if the WDT configuration option has been disabled, then any instruction relating to its operation will result in no operation.
Under normal program operation, a WDT time-out will
initialise a device reset and set the status bit TO. However, if the system is in the Power Down Mode, when a
WDT time-out occurs, only the Program Counter and
Stack Pointer will be reset. Three methods can be
adopted to clear the contents of the WDT and the WDT
prescaler. The first is an external hardware reset, which
means a low level on the RES pin, the second is using
the watchdog software instructions and the third is via a
²HALT² instruction.
There are two methods of using software instructions to
clear the Watchdog Timer, one of which must be chosen
by configuration option. The first option is to use the single ²CLR WDT² instruction while the second is to use
the two commands ²CLR WDT1² and ²CLR WDT2². For
the first option, a simple execution of ²CLR WDT² will
clear the WDT while for the second option, both ²CLR
WDT1² and ²CLR WDT2² must both be executed to
successfully clear the WDT. Note that for this second
option, if ²CLR WDT1² is used to clear the WDT, successive executions of this instruction will have no effect,
only the execution of a ²CLR WDT2² instruction will
clear the WDT. Similarly, after the ²CLR WDT2² instruction has been executed, only a successive ²CLR WDT1²
instruction can clear the Watchdog Timer.
The internal WDT oscillator has an approximate period
of 65ms at a supply voltage of 5V. If selected, it is first divided by 256 via an 8-stage counter to give a nominal
period of 17ms. Note that this period can vary with VDD,
temperature and process variations. For longer WDT
time-out periods the WDT prescaler can be utilized. By
writing the required value to bits 0, 1 and 2 of the WDTS
register, known as WS0, WS1 and WS2, longer time-out
periods can be achieved. With WS0, WS1 and WS2 all
equal to 1, the division ratio is 1:128 which gives a maximum time-out period of about 2.1s.
A configuration option can select the instruction clock,
which is the system clock divided by 4, as the WDT clock
source instead of the internal WDT oscillator. If the instruction clock is used as the clock source, it must be
noted that when the system enters the Power Down
Mode, as the system clock is stopped, then the WDT
clock source will also be stopped. Therefore the WDT
will lose its protecting purposes. In such cases the system cannot be restarted by the WDT and can only be restarted using external signals. For systems that operate
in noisy environments, using the internal WDT oscillator
is therefore the recommended choice.
b 7
b 0
W S 2
W S 1
W S 0
W D T S R e g is te r
W D T p r e s c a le r r a te s e le c t
W D T R
W S 0
W S 1
W S 2
1 :1
0
0
0
1 :2
1
0
0
1 :4
0
1
0
1 :8
1
1
0
1 :1
0
0
1
1 :3
1
0
1
1 :6
0
1
1
1 :1
1
1
1
a te
6
2
4
2 8
N o t u s e d
Watchdog Timer Register
Rev. 1.10
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December 12, 2012
HT86Axx/HT86ARxx
C L R W D T 1 F la g
C L R W D T 2 F la g
C le a r W D T T y p e
C o n fig u r a tio n O p tio n
1 o r 2 In s tr u c tio n s
fS
Y S
/4
W D T O s c illa to r
C L R
W D T C lo c k S o u r c e
C o n fig u r a tio n O p tio n
C L R
8 - b it C o u n te r
(¸ 2 5 6 )
7 - b it P r e s c a le r
W D T C lo c k S o u r c e
W S 0 ~ W S 2
8 -to -1 M U X
W D T T im e - o u t
Watchdog Timer
Voice Output
There are 8 levels of volume which are setup using the
VOL register. Only the highest 3-bits of this register are
used for volume control, the other bits are not used and
read as zero.
Voice Control
The voice control register controls the voice ROM circuit
and the DAC circuit and selects the Voice ROM latch
counter. If the DAC circuit is not enabled, any DAH/DAL
outputs will be invalid. Writing a ²1² to the DAC bit will
enable the DAC circuit, while writing a ²0² to the DAC bit
will disable the DAC circuit. If the voice ROM circuit is
not enabled, then voice ROM data cannot be accessed.
Writing a ²1² to the VROMC bit will enable the voice
ROM circuit, while writing a ²0² to the VROMC bit will
disable the voice ROM circuit. The LATCH bit determines which voice ROM address latch counter will be
used as the voice ROM address latch counter.
b 7
b 0
D 3
D 2
D 1
D A L R e g is te r
N o t u s e d , re a d a s "0 "
D ig ita l to A n a lo g D a ta L o w
b 7
A u d io o u tp u t
R e g is te r
b 0
D 1 1
D 1 0
D 9
D 8
D 7
D 6
D 5
D 4
D A H R e g is te r
A u d io o u tp u t
D ig ita l to A n a lo g D a ta H ig h R e g is te r
b 7
Audio Output and Volume Control - DAL, DAH, VOL
b 0
V O L R e g is te r
V O L 2 V O L 1 V O L 0
The audio output is 12-bits wide whose highest 8-bits
are written into the DAH register and whose lowest four
bits are written into the highest four bits of the DAL register. Bits 0~3 of the DAL register are always read as zero.
N o t u s e d , re a d a s "0 "
D A v o lu m e c o n tr o l d a ta
V o lu m e C o n tr o l R e g is te r
b 7
F A S T
D 0
b 0
P 0 A E M
P 0 A E N
L A T C H C
V R O M C
D A C
V O IC E C R e g is te r
N o t im p le m e n te d , r e a d a s z e r o
D A C E n a b le
1 : e n a b le
0 : d is a b le
V o ic e c R O M
1 : e n a b le
0 : d is a b le
E n a b le
N o t im p le m e n te d , r e a d a s z e r o
V o ic e R O M C o u n te r S e le c t
1 : A d d re s s L a tc h 1
0 : A d d re s s L a tc h 0
P o w e r A m p lifie r E n a b le
1 : e n a b le
0 : d is a b le
P o w e r A m p lifie r M u te E n a b le
1 : e n a b le
0 : d is a b le
S p e e d - U p 3 2 k H z C r y s ta l E n a b le
1 : e n a b le
0 : d is a b le
VOICE Control Register
Rev. 1.10
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December 12, 2012
HT86Axx/HT86ARxx
Voice ROM Data Address Latch Counter
The Voice ROM address is 21-bits wide and therefore requires three registers to store the address. There are two sets
of three registers to store this address, which are LATCH0H/LATCH0M/LATCH0L and LATCH1H/
LATCH1M/LATCH1L. The 21-bit address stored in one set of these three registers is used to access the 8-bit voice
code data in the Voice ROM. After the 8-bit Voice ROM data is addressed, a few instruction cycles, of at least 4us duration, are needed to latch the Voice ROM data. After this the microcontroller can read the voice data from the LATCHD
register.
Example: Read an 8-bit voice ROM data which is located at address 000007H by address latch 0
Set
[26H].2
; Enable voice ROM circuit
mov
A, 07H
;
mov
LATCH0L, A
; Set LATCH0L to 07H
mov
A, 00H
;
mov
LATCH0M, A
; Set LATCH0M to 00H
mov
A, 00H
;
mov
LATCH0H, A
; Set LATCH0H to 00H
call
Delay
; Delay a short period of time
mov
A, LATCHD
; Get voice data at 000007H
Power Amplifier
Each device contains an audio power amplifier which is
an integrated class AB monophonic type speaker driver.
It has the properties of high S/N ratio, high slew rate,
low distortion, large output voltage swing, excellent
power supply ripple rejection, low power consumption,
low standby current and power off control etc.
VBIAS: Speaker non-inverting input voltage reference
SP+:Audio Positive output
SP-: Audio Negative output
OUTP Rising Time (tR)
S P +
S P K
S P 0 .1 m F
V
When AMP_EN enables the Power Amplifer, note that it
requires a certain time before it can output fully on the
OUTP pin. However, this delay time depends on the
value of C1. The C1 capacitor is connected between
VBIAS and VSS.
1 0 R
R
R
A M P 1
A u d In
C 1
Aud In: Audio input
B IA S
A M P 2
A M P _ E N
R
B IA S
A M P _ E N
O U T P
tR
Capacitor
tR
0.1mF
1mF
4.7mF
10mF
2.2V
15ms
30ms
90ms
185ms
3V
15ms
30ms
90ms
185ms
4
15ms
30ms
90ms
185ms
Voltage
Rev. 1.10
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December 12, 2012
HT86Axx/HT86ARxx
Turn On: audio signal standby (1/2VDD) ® enable amplifier ® wait tR for amplifier ready ® audio output
For battery based applications, power consumption is a
key issue, therefore the amplifier should be turned off
when in the standby state. In order to eliminate any
speaker sound bursts while turning the amplifier on, the
application circuit, which will incorporate a capacitance
value of C1, should be adjusted in accordance with the
speaker s audio frequency response. A greater value of
C1 will improve the noise burst while turning on the amplifier. The recommended operation sequence is:
Turn Off: audio signal finished ® disable amplifier ®
wait tR for amplifier off ® audio signal off
If the application is not powered by batteries and there is
no problem with amplifier On/Off issues, a capacitor
value of 0.1mF for C1 is recommended.
SP+/SP-
tR
tR
AMP_EN
Analog to Digital Converter
The following diagram shows the overall internal structure of the A/D converter, together with its associated
registers.
The need to interface to real world analog signals is a
common requirement for many electronic systems.
However, to properly process these signals by a
microcontroller, they must first be converted into digital
signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the
need for external components is reduced significantly
with the corresponding follow-on benefits of lower costs
and reduced component space requirements.
A/D Converter Data Registers - ADRL, ADRH
The devices have a 12-bit A/D converter, two registers
are required, a high byte register, known as ADRH , and
a low byte register, known as ADRL. After the conversion process takes place, these registers can be directly
read by the microcontroller to obtain the digitized conversion value. They use two A/D Converter Data Registers, note that only the high byte register ADRH utilises
its full 8-bit contents. The low byte register ADRL utilises only 4 of its 8-bit contents as it contains only the
lower 4 bit of the 12-bit converted value.
A/D Overview
The devices contain a 4-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals
and convert these signals directly into either a 12-bit digital value.
C lo c k D iv id e R a tio
A D C
fO
S o u rc e
S C
¸ 2 ~
¸ 3 2
V
A C S R
P C 0
P C 1
P C 2
P C 3
/A N
/A N
/A N
/A N
0
D D
A /D
r e fe r e n c e v o lta g e
1
2
P C R 0 ~ P C R 2
P in C o n fig u r a tio n
B its
A D R L
A D C
3
A C S 0 ~ A C S 1
C h a n n e l S e le c t
B its
S T A R T
R e g is te r
A D R H
E O C
A /D D a ta
R e g is te r s
A D C R
R e g is te r
S ta rt a n d E n d o f
C o n v e r s io n B its
A/D Converter Structure
Rev. 1.10
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December 12, 2012
HT86Axx/HT86ARxx
digital conversion cycle will be initiated. When the
START bit is brought from low to high but not low again,
the EOC bit in the ADCR register will be set high and the
analog to digital converter will be reset. It is the START
bit that is used to control the overall on/off operation of
the internal analog to digital converter.
In the following table, D0~D11 are the A/D conversion
data result bits.
Register
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
ADRL
D3
D2
D1
D0
¾
¾
¾
¾
ADRH
D11 D10 D9
D8
D7
D6
D5
D4
The EOC bit in the ADCR register is used to indicate
when the analog to digital conversion process is complete. This bit will be automatically cleared to zero by the
microcontroller after a conversion cycle has ended. In
addition, the corresponding A/D interrupt request flag
will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. This A/D internal interrupt signal
will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal
interrupt is disabled, the microcontroller can be used to
poll the EOC bit in the ADCR register to check whether it
has been cleared as an alternative method of detecting
the end of an A/D conversion cycle.
A/D Data Register
A/D Converter Control Register - ADCR
To control the function and operation of the A/D converter, a control register known as ADCR is provided.
This 8-bit register defines functions such as the selection of which analog channel is connected to the internal
A/D converter, which pins are used as analog inputs and
which are used as normal I/Os as well as controlling the
start function and monitoring the A/D converter end of
conversion status.
One section of this register contains the bits
ACS1~ACS0 which define the channel number. As each
of the devices contains only one actual analog to digital
converter circuit, each of the individual 4 analog inputs
must be routed to the converter. It is the function of the
ACS1~ACS0 bits in the ADCR register to determine
which analog channel is actually connected to the internal A/D converter.
A/D Converter Clock Source Register - ACSR
The clock source for the A/D converter, which originates
from the system clock fOSC, is first divided by a division
ratio, the value of which is determined by the ADCS1
and ADCS0 bits in the ACSR register.
Although the A/D clock source is determined by the system clock fOSC, and by bits ADCS1 and ADCS0, there
are some limitations on the maximum A/D clock source
speed that can be selected. Refer to the following table.
The ADCR control register also contains the
PCR2~PCR0 bits which determine which pins on Port C
are used as analog inputs for the A/D converter and
which pins are to be used as normal I/O pins. Note that if
the PCR2~PCR0 bits are all set to zero, then all the Port
C pins will be setup as normal I/Os and the internal A/D
converter circuitry will be powered off to reduce the
power consumption.
The START bit in the ADCR register is used to start and
reset the A/D converter. When the microcontroller sets
this bit from low to high and then low again, an analog to
b 7
S T A R T E O C B
P C R 2
P C R 1
P C R 0
A C S 1
b 0
A C S 0
ACS1
ACS0
Analog Channel
0
0
AN0
0
1
AN1
1
0
AN2
1
1
AN3
ACS Table: A/D Channel Select Table
A D C R
R e g is te r
S e le c t A /D c h a n n e l
T h e d e ta il r e fe r e n c e A C S ta b le
N o t im p le m e n te d r e a d a s " 0 "
P o r t C A /D c h a n n e l c o n fig u r a tio n s
T h e d e ta il r e fe r e n c e P C R ta b le
E n d o f A /D c o n v e r s io n fla g
1 : n o t e n d o f A /D c o n v e r s io n - A /D c o n v e r s io n w a itin g o r in p r o g r e s s
0 : e n d o f A /D c o n v e r s io n - A /D c o n v e r s io n e n d e d
S ta r t th e A /D c o n v e r s io n
0 ® 1 ® 0 : S ta rt
0 ® 1 : R e s e t A /D c o n v e rte r a n d s e t E O C B to "1 "
ADCR Register
Rev. 1.10
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December 12, 2012
HT86Axx/HT86ARxx
b 7
T E S T
b 0
A D C S 1 A D C S 0
A C S R
R e g is te r
S e le c t A /D c o n v e r te r c lo
A D C S 0
A D C S 1
: fO S
0
0
: fO S
1
0
0
1
: fO S
1
1
: N o
c k s o u rc e
/2
C
/8
C
/3 2
t im p le m e n te d
C
N o t im p le m e n te d , r e a d a s " 0 "
F o r te s t m o d e u s e o n ly
ACSR Register
PCR2
PCR1
PCR0
3
2
1
0
0
0
0
PC3
PC2
PC1
PC0
0
0
1
PC3
PC2
PC1
AN0
0
1
0
PC3
PC2
AN1
AN0
0
1
1
PC3
AN2
AN1
AN0
1
0
0
AN3
AN2
AN1
AN0
PCR Table: Port A/D Channel Configuration Table
A/D Clock Period (tAD)
fOSC
ADCS1, ADCS0=01
(fOSC/2)
ADCS1, ADCS0=10
(fOSC/8)
ADCS1, ADCS0=00
(fOSC/32)
ADCS1, ADCS0=11
4MHz
500ns
2ms
8ms
¾
6MHz
333ns
1.3ms
5.3ms
¾
8MHz
250ns
1ms
4ms
¾
A/D Clock Period Examples
A/D Input Pins
Initialising the A/D Converter
All of the A/D analog input pins are pin-shared with the
I/O pins on Port C. Bits PCR2~PCR0 in the ACSR registers, not configuration options, determine whether the
input pins are setup as normal Port C input/output pins
or whether they are setup as analog inputs. In this way,
pins can be changed under program control to change
their function from normal I/O operation to analog inputs
and vice versa. Pull-high resistors, which are setup
through configuration options, apply to the input pins
only when they are used as normal I/O pins, if setup as
A/D inputs the pull-high resistors will be automatically
disconnected. Note that it is not necessary to first setup
the A/D pin as an input in the PBC port control register to
enable the A/D input, when the PCR2~PCR0 bits enable an A/D input, the status of the port control register
will be overridden.
The internal A/D converter must be initialised in a special way. Each time the Port C A/D channel selection bits
are modified by the program, the A/D converter must be
re-initialised. If the A/D converter is not initialized after
the channel selection bits are changed, the EOCB flag
may have an undefined value, which may produce a
false end of conversion signal. To initialize the A/D converter after the channel selection bits have changed,
then, within a time frame of one to ten instruction cycles,
the START bit in the ADCR register must first be set high
and then immediately cleared to zero. This will ensure
that the EOCB flag is correctly set to a high condition.
Summary of A/D Conversion Steps
The following summarizes the individual steps that
should be executed in order to implement an A/D conversion process.
The VDD power supply pin is used as the A/D converter
reference voltage, and as such analog inputs must not
be allowed to exceed this value. Appropriate measures
should also be taken to ensure that the VDD pin remains
as stable and noise free as possible.
Rev. 1.10
· Step 1
Select the required A/D conversion clock by correctly
programming bits ADCS1 and ADCS0 in the ACSR
register.
45
December 12, 2012
HT86Axx/HT86ARxx
· Step 2
· Step 5
Select which channel is to be connected to the internal
A/D converter by correctly programming the
ACS1~ACS0 bits which are also contained in the
ADCR register.
To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR register
can be polled. The conversion process is complete
when this bit goes low. When this occurs the A/D data
registers ADRL and ADRH can be read to obtain the
conversion value.
· Step 3
Select which pins on Port C are to be used as A/D inputs and configure them as A/D input pins by correctly
programming the PCR2~PCR0 bits in the ADCR register. Note that this step can be combined with Step 2
into ADCR registers programming operation.
The following timing diagram shows graphically the various stages involved in an analog to digital conversion
process and its associated timing.
· Step 4
The analog to digital conversion process can now be
initialised by setting the START bit in the ADCR register from ²0² to ²1² and then to ²0² again. Note that this
bit should have been originally set to ²0².
S T A R T b it s e t h ig h w ith in o n e to te n in s tr u c tio n c y c le s a fte r th e P C R 0 ~ P C R 2 b its c h a n g e s ta te
S T A R T
E O C B
A /D s a m p lin g tim e
3 2 tA D
P C R 2 ~
P C R 0
0 0 0 B
A /D s a m p lin g tim e
3 2 tA D
A /D s a m p lin g tim e
3 2 tA D
0 1 1 B
1 0 0 B
0 0 0 B
1 . P C p o rt s e tu p a s I/O s
2 . A /D c o n v e r te r is p o w e r e d o ff
to r e d u c e p o w e r c o n s u m p tio n
A C S 1 ~
A C S 0
0 0 0 B
P o w e r-o n
R e s e t
0 1 0 B
0 0 0 B
0 0 1 B
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
1 : D e fin e P C c o n fig u r a tio n
2 : S e le c t a n a lo g c h a n n e l
A /D
tA D C
c o n v e r s io n tim e
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
A /D
tA D C
c o n v e r s io n tim e
D o n 't c a r e
E n d o f A /D
c o n v e r s io n
A /D
tA D C
c o n v e r s io n tim e
A/D Conversion Timing
Rev. 1.10
46
December 12, 2012
HT86Axx/HT86ARxx
SPI Serial Interface
The device includes a single SPI Serial Interfaces. The
SPI interface is a full duplex serial data link, originally
designed by Motorola, which allows multiple devices
connected to the same SPI bus to communicate with
each other. The devices communicate using a master/slave technique where only the single master device
can initiate a data transfer. A simple four line signal bus
is used for all communication. The four SPI lines are
shared with I/O pins PD0~PD3, the function of which is
chosen using a configuration option.
SPI Interface Communication
Four lines are used for SPI communication known as
SDI - Serial Data Input, SDO - Serial Data Output, SCK Serial Clock and SCS - Slave Select. Note that the condition of the Slave Select line is conditioned by the
CSEN bit in the SBCR control register. If the CSEN bit is
high then the SCS line is active while if the bit is low then
the SCS line will be in a floating condition. The following
timing diagram depicts the basic timing protocol of the
SPI bus.
S C S
S C K
S D I
S D O
S B C R
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
C K S
M 1
M 0
S B E N
M L S
C S E N
W C O L
T R F
0
1
1
0
0
0
0
0
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
S B D R
U
U
U
U
U
U
U
U
D A T A R E G IS T E R
D E F A U L T
S B D R
D E F A U L T
S B C R
: S E R IA L B U S
C O N T R O L R E G IS T E R
: S E R IA L B U S
N o te : "U " m e a n s u n c h a n g e d .
D a ta B u s
S B D R
( R e c e iv e d D a ta R e g is te r )
D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0
M
S D O
U
X
B u ffe r
S B E N
M L S
M
In te r n a l B a u d R a te C lo c k
S C K
a n d , s ta rt
E N
a n d , s ta rt
C lo c k P o la r ity
U
X
M
S D O
S D I
U
X
T R F
C 0 C 1 C 2
M a s te r o r S la v e
A N D
In te r n a l B u s y F la g
S B E N
a n d , s ta rt
E N
W r ite S B D R
W r ite S B D R
S B E N
W C O L F la g
E n a b le /D is a b le
W r ite S B D R
S C S
M a s te r o r S la v e
S B E N
C S E N
SPI Block Diagram
Rev. 1.10
47
December 12, 2012
HT86Axx/HT86ARxx
SPI Registers
SPI Bus Enable/Disable
There are two registers associated with the SPI Interface. These are the SBCR register which is the control
register and the SBDR which is the data register. The
SBCR register is used to setup the required setup parameters for the SPI bus and also used to store associated operating flags, while the SBDR register is used for
data storage.
To enable the SPI bus and CSEN=1, the SCK, SDI,
SDO and SCS lines should all be zero, then wait for data
to be written to the SBDR (TXRX bufffer) register. For
the Master Mode, after data has been written to the
SBDR (TXRX buffer) register then transmission or reception will start automatically. When all the data has
been transferred the TRF bit should be set. For the
Slave Mode, when clock pulses are received on SCK,
data in the TXRX buffer will be shifted out or data on SDI
will be shifted in.
After Power on, the contents of the SBDR register will be
in an unknown condition while the SBCR register will default to the condition below:
To Disable the SPI bus SCK, SDI, SDO, SCS floating.
CKS M1 M0 SBEN MLS CSEN WCOL TRF
0
1
1
0
0
0
0
0
SPI Operation
All communication is carried out using the 4-line interface for both Master or Slave Mode. The timing diagram
shows the basic operation of the bus.
Note that data written to the SBDR register will only be
written to the TXRX buffer, whereas data read from the
SBDR register will actual be read from the register.
b 7
C K S
b 0
M 1
M 0
S B E N
M L S
C S E N W C O L T R F
S B C R
R e g is te r
T r a n s m itt/R e c e iv e F la g
0 : N o t c o m p le te
1 : T r a n s m is s io n /r e c e p tio n c o m p le te
W r ite C o llis io n B it
0 : C o llis io n fr e e
1 : C o llis io n d e te c te d
S e le c tio n S ig n a l E n a b le /D is a b le B it
0 : S C S flo a tin g
1 : E n a b le
M S B /L S B F ir s t B it
0 : L S B s h ift fir s t
1 : M S B s h ift fir s t
S e r ia l B
0 : D is a b
1 : E n a b
D e p e
u s E n a b le /D is a b le B it
le
le
n d e n t u p o n C S E N b it
M a s te r /S la
M 1
M 0
0
0
0
1
1
0
1
1
v e /B a u d R a te B its
M a s
M a s
M a s
S la v
te r,
te r,
te r,
e m
b a u d ra te : fS
b a u d ra te : fS
b a u d ra te : fS
o d e
IO
IO
IO
/4
/1 6
C lo c k S o u r c e S e le c t B it
0 : f S IO = f S Y S / 4
1 : f S IO = f S Y S
SPI Interface Control Register
S B E N = 1 , C S E N = 0 a n d w r ite d a ta to S B D R ( if p u ll- h ig h e d )
S C S
S B E N = C S E N = 1 a n d w r ite d a ta to S B D R
S C K
S D I
S D O
D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7
D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7
S C K
SPI Bus Timing
Rev. 1.10
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December 12, 2012
HT86Axx/HT86ARxx
Step 2. Setup the M0 and M1 bits to 00 to select the
Slave Mode. The CKS bit is don¢t care.
Step 3. Setup the CSEN bit and setup the MLS bit to
choose if the data is MSB or LSB first,
this must be same as the Master device.
Step 4. Setup the SBEN bit in the SBCR control
register to enable the SPI interface.
Step 5. For write operations: write data to the SBCR
register, which will actually place the data into
the TXRX register, then wait for the master
clock and SCS signal. After this goto step 6.
For read operations: the data transferred in
on the SDI line will be stored in the TXRX
buffer until all the data has been received
at which point it will be latched into the SBDR
register.
Step 6. Check the WCOL bit, if set high then a
collision error has occurred so return to step5.
If equal to zero then go to the following step.
Step 7. Check the TRF bit or wait for an SBI serial bus.
Step 8. Read data from the SBDR register.
Step 9. Clear TRF
Step10. Goto step 5
The CSEN bit in the SBCR register controls the overall
function of the SPI interface. Setting this bit high, will enable the SPI interface by allowing the SCS line to be active, which can then be used to control the SPI interface.
If the CSEN bit is low, the SPI interface will be disabled
and the SCS line will be in a floating condition and can
therefore not be used for control of the SPI interface.
The SBEN bit in the SBCR register must also be high
which will place the SDI line in a floating condition and
the SDO line high. If in Master Mode the SCK line will be
either high or low depending upon the clock polarity configuration option. If in Slave Mode the SCK line will be in
a floating condition. If SBEN is low then the bus will be
disabled and SCS, SDI, SDO and SCK will all be in a
floating condition.
In the Master Mode the Master will always generate the
clock signal. The clock and data transmission will be initiated after data has been written to the SBDR register.
In the Slave Mode, the clock signal will be received from
an external master device for both data transmission or
reception. The following sequences show the order to
be followed for data transfer in both Master and Slave
Mode:
SPI Configuration Options
Several configuration options exist for the SPI Interface
function which must be setup during device programming. The first is a configuration to select the PD0~PD3
pins to be used as the SPI interface pins. Another option
is to enable the operation of the WCOL, write collision
bit, in the SBCR register. Another option exists to select
the clock polarity of the SCK line. A configuration option
also exists to disable or enable the operation of the
CSEN bit in the SBCR register. If the configuration option disables the CSEN bit then this bit cannot be used
to affect overall control of the SPI Interface.
· Master Mode
Step 1. Select the clock source using the CKS bit in
the SBCR control register
Step 2. Setup the M0 and M1 bits in the SBCR control
register to select the Master Mode and the
required Baud rate. Values of 00, 01 or 10 can
be selected.
Step 3. Setup the CSEN bit and setup the MLS bit to
choose if the data is MSB or LSB first,
this must be same as the Slave device.
Step 4. Setup the SBEN bit in the SBCR control
register to enable the SPI interface.
Step 5. For write operations: write the data to the
SBDR register, which will actually place the
data into the TXRX buffer. Then use the SCK
and SCS lines to output the data.
Goto to step6.For read operations: the data
transferred in on the SDI line will be stored
in the TXRX buffer until all the data has been
received at which point it will be latched into
the SBDR register.
Error Detection
The WCOL bit in the SBCR register is provided to indicate errors during data transfer. The bit is set by the Serial Interface but must be cleared by the application
program. This bit indicates a data collision has occurred
which happens if a write to the SBDR register takes
place during a data transfer operation and will prevent
the write operation from continuing. The bit will be set
high by the Serial Interface but has to be cleared by the
user application program. The overall function of the
WCOL bit can be disabled or enabled by a configuration
option.
Step 6. Check the WCOL bit, if set high then a
collision error has occurred so return to step5.
If equal to zero then go to the following step.
Step 7. Check the TRF bit or wait for an SBI serial bus.
Step 8. Read data from the SBDR register.
Programming Considerations
Step 9. Clear TRF.
When the device is placed into the Power Down Mode
note that data reception and transmission will continue.
The TRF bit is used to generate an interrupt when the
data has been transferred or received.
Step10. Goto step 5.
· Slave Mode
Step 1. The CKS bit has a don¢t care value in the
slave mode.
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Low Voltage Detect Function
A low voltage detect function is implemented within the microcontroller. The LVD function is controlled using the LVDC
register and configuration options. To enable the LVD function, both the LVD configuration option should be enabled
and the LVEN bit should be set high. After setting the LVEN bit high, the circuit requires about 100ms to stabilise. After
this time has elapsed, the LVFG bit can be monitored to look for low voltage conditions.
L V E N
L V D
O n /O ff
B it
L V D
F u n c tio n
L V D E n a b le
C o n fig u r a tio n O p tio n
L V S 0 /L V S 1 B it
L V D V o lta g e L e v e l
C o fig u r a tio n O p tio n
L V F G
L V D
V o lta g e L e v e l
M U X
L V D V o lta g e L e v e l
S o u r c e S e le c t
LVD Block Diagram
The LVS0 and LVS1 bits are used to define the LVD voltage threshold level, however configuration options can also be
used to define this voltage. A configuration option is used to decide whether these two register bits or the configuration
option is used to define the LVD voltage threshold level. As the low voltage detector circuitry will consume a certain
amount of power, the LVEN bit can be reset to zero to turn off the LVD internal circuitry to reduce power consumption.
b 7
L V F G
L V E N
L V S 1
b 0
L V S 0
L V D C
R e g is te r
L V D v o lta g e s e le c t
L V D
L V S 0
L V S 1
2
0
0
2
1
0
2
0
1
2
1
1
V o lta g e
.2 V
.3 V
.4 V
.5 V
N o t im p le m e n te d , r e a d a s " 0 "
L o w V o lta g e D e te c t E n a b le
1 : e n a b le
0 : d is a b le
L o w V o lta g e D e te c t L e v e l
1 : L B IN p in v o lta g e is le s s th a n
0 : L B IN v o lta g e is n o t le s s th a n
N o t im p le m e n te d , r e a s a s " 0 "
Low Voltage Detect Control Register - LVDC
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Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development
tools. As these options are programmed into the device using the hardware programming tools, once they are selected
they cannot be changed later by the application software.
No.
Options
I/O Options
1
PA0~PA7: wake-up enable or disable (bit option)
2
PA0~PA7: pull-high enable or disable (bit option)
3
PB0~PB7: pull-high enable or disable (bit option)
4
PC0~PC7: pull-high enable or disable (bit option)
5
PD0~PD7: pull-high enable or disable (bit option)
6
PE0~PE7: pull-high enable or disable (bit option)
7
PD pin shared function select: select PD3~PD0 as I/O pins or as serial interface function
Oscillation Option
8
OSC type selection: RC or crystal
9
RTC: enable or disable
Interrupt Option
10
INT Triggering edge: Falling or both
Watchdog Options
11
WDT: enable or disable
12
WDT clock source: WDROSC or T1
13
CLRWDT instructions: 1 or 2 instructions
Low Voltage Reset Option
14
LVR select: enable or disable
Low Voltage Detect Option
15
LVD voltage: 2.2V~2.5V
16
LVD select: enable or disable
17
LVD voltage level control select: Register bits or configuration option
Serial interface Option
18
Serial interface CPOL: falling edge or rising edge
19
Serial interface WCOL: enable or disable
20
Serial interface CSEN: enable or disable
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Application Circuits
V
D D
1 0 W
V D D M
V D D A 1
V
V D D A
4 7 m F
0 .1 m F
O S C 2
O S C 1
D D
V D D
1 0 0 m F
R
P A 0 ~ P A 7
O S C
P B 0 ~ P B 7
1 0 0 k W
P C 0 ~ P C 7
P D 0 ~ P D 7
R E S
P E 0 ~ P E 7
0 .1 m F
V
A U D _ IN
D D
0 .1 m F
A U D _ O U T
5 0 k W
IN T
V B IA S
1 0 m F
V S S
V S S A
V S S A 1
V S S M
S P K
S P +
S P -
H T 8 6 A 3 6 /H T 8 6 A 7 2 /H T 8 6 A R 7 2
V
D D
1 0 W
V D D M
V D D A
V
V D D A 1
4 7 m F
0 .1 m F
O S C 2
O S C 1
D D
V D D
1 0 0 m F
4 M H z ~
8 M H z
P A 0 ~ P A 7
P B 0 ~ P B 7
1 0 0 k W
P C 0 ~ P C 7
P D 0 ~ P D 7
R E S
P E 0 ~ P E 7
0 .1 m F
V
0 .1 m F
A U D _ IN
D D
A U D _ O U T
5 0 k W
IN T
V B IA S
1 0 m F
V S S
V S S A
V S S A 1
V S S M
S P +
S P -
S P K
H T 8 6 A 3 6 /H T 8 6 A 7 2 /H T 8 6 A R 7 2
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Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
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Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rev. 1.10
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
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Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
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Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
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CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
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CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
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INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
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OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
Rev. 1.10
60
December 12, 2012
HT86Axx/HT86ARxx
RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
Rev. 1.10
61
December 12, 2012
HT86Axx/HT86ARxx
SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
Rev. 1.10
62
December 12, 2012
HT86Axx/HT86ARxx
SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
Rev. 1.10
63
December 12, 2012
HT86Axx/HT86ARxx
SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 1.10
64
December 12, 2012
HT86Axx/HT86ARxx
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.10
65
December 12, 2012
HT86Axx/HT86ARxx
Package Information
Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website (http://www.holtek.com.tw/english/literature/package.pdf) for
the latest version of the package information.
44-pin LQFP (10mm´10mm) (FP2.0mm) Outline Dimensions
H
C
D
G
2 3
3 3
I
3 4
2 2
L
F
A
B
E
1 2
4 4
K
a
J
1
Symbol
A
Dimensions in inch
Min.
Nom.
Max.
0.469
¾
0.476
B
0.390
¾
0.398
C
0.469
¾
0.476
D
0.390
¾
0.398
E
¾
0.031
¾
F
¾
0.012
¾
G
0.053
¾
0.057
H
¾
¾
0.063
I
¾
0.004
¾
J
0.018
¾
0.030
K
0.004
¾
0.008
a
0°
¾
7°
Symbol
A
Rev. 1.10
1 1
Dimensions in mm
Min.
Nom.
Max.
11.90
¾
12.10
B
9.90
¾
10.10
C
11.90
¾
12.10
D
9.90
¾
10.10
E
¾
0.80
¾
F
¾
0.30
¾
G
1.35
¾
1.45
H
¾
¾
1.60
I
¾
0.10
¾
J
0.45
¾
0.75
K
0.10
¾
0.20
a
0°
¾
7°
66
December 12, 2012
HT86Axx/HT86ARxx
64-pin LQFP (10mm´10mm) Outline Dimensions
C
D
4 8
G
3 3
H
I
3 2
4 9
F
A
B
E
6 4
1 7
K
a
J
1 6
1
Symbol
Nom.
Max.
A
0.469
¾
0.476
B
0.390
¾
0.398
C
0.469
¾
0.476
D
0.390
¾
0.398
E
¾
0.020
¾
F
¾
0.008
¾
G
0.053
¾
0.057
H
¾
¾
0.063
I
¾
0.004
¾
J
0.018
¾
0.030
K
0.004
¾
0.008
a
0°
¾
7°
Symbol
Rev. 1.10
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
11.90
¾
12.10
B
9.90
¾
10.10
C
11.90
¾
12.10
D
9.90
¾
10.10
E
¾
0.50
¾
F
¾
0.20
¾
G
1.35
¾
1.45
H
¾
¾
1.60
I
¾
0.10
¾
J
0.45
¾
0.75
K
0.1
¾
0.2
a
0°
¾
7°
67
December 12, 2012
HT86Axx/HT86ARxx
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor (China) Inc.
Building No. 10, Xinzhu Court, (No. 1 Headquarters), 4 Cuizhu Road, Songshan Lake, Dongguan, China 523808
Tel: 86-769-2626-1300
Fax: 86-769-2626-1311
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2012 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.10
68
December 12, 2012