CS5371
CS5372
Low-power, High-performance ∆Σ Modulators
Features & Description
Description
∆Σ Architecture
z Clock-jitter-tolerant Architecture
z Input Voltage: 5 Vpp Fully Differential
z High Dynamic Range
The CS5371 and CS5372 are one- and two-channel,
high dynamic range, fourth-order ∆Σ modulators intended for geophysical and sonar applications. Used in
combination with the CS5376A or CS5378 digital filters,
a unique high-resolution A/D measurement system
results.
z Fourth-order
127 dB SNR @ 215 Hz BW (2 ms Output)
124 dB SNR @ 430 Hz BW (1 ms Output)
z Low
Total Harmonic Distortion
-118 dB THD Typical, -112 dB THD Maximum
z Low
Power Consumption
Normal Mode: 25 mW per Channel
Low-power Mode: 15 mW per Channel
z Small
Footprint, 24-pin SSOP Package
z Single- or Multi-channel System Support
1-channel System: CS5371
2-channel System: CS5372
3-channel System: CS5371 + CS5372
4-channel System: CS5372 + CS5372
z Single
or Dual Power Supply Configurations
The CS5371 and CS5372 have high dynamic range
(127 dB @ 215 Hz bandwidth) and low total harmonic
distortion (typically -118 dB THD), with very low power
consumption per channel. In normal mode
(LPWR=0, MCLK=2.048MHz), power consumption is
25 mW per channel, and in low-power mode
(LPWR=1, MCLK=1.024MHz), power consumption is
15 mW per channel. Each modulator can be independently powered down to 1 mW per channel, and by
halting the input clock, they will enter a micropower state
using only 10 µW per channel.
The modulators generate an oversampled serial bit
stream at 512 kbits per second when operated from a
clock frequency of 2.048 MHz. They are available in a
small 24-pin SSOP package, providing exceptional performance in a very small footprint.
VA+ = +5 V; VA- = 0 V;
VD = +3.3 V to +5 V
ORDERING INFORMATION
VA+ = +2.5 V;VA- = -2.5 V;VD = +3.3 V
See page 21.
VA+
INF+
INR+
INRINF-
VD
PWDN
VA+
MFLAG
4TH ORDER
∆−Σ MODULATOR
MDATA
CLOCK
GENERATOR
VREF+
VREF-
CS5371
VA-
http://www.cirrus.com
OFST LPWR
DGND
MCLK
MSYNC
VD
PWDN1
MFLAG1
INF1+
INR1+
INR1INF1-
TH
4 ORDER
∆−Σ MODULATOR
MDATA1
MCLK
MSYNC
CLOCK
GENERATOR
VREF+
VREFINF2+
INR2+
INR2INF2-
MFLAG2
4TH ORDER
∆−Σ MODULATOR
MDATA2
CS5372
VA-
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
PWDN2
OFST LPWR
DGND
OCT ‘05
DS255F3
CS5371 CS5372
TABLE OF CONTENTS
1. CHARACTERISTICS & SPECIFICATIONS................................................... 3
ANALOG CHARACTERISTICS .................................................................. 3
DIGITAL CHARACTERISTICS ................................................................... 5
ABSOLUTE MAXIMUM RATINGS ............................................................. 5
SWITCHING CHARACTERISTICS ............................................................ 6
2. GENERAL DESCRIPTION. ........................................................................... 7
3. MODULATOR PERFORMANCE ................................................................... 9
3.1. Full-scale Signal Performance ........................................................... 9
3.2. Noise Performance ............................................................................ 9
4. SIGNAL INPUTS ........................................................................................... 9
4.1. Differential Inputs - INR+/-, INF+/- ..................................................... 9
4.2. Anti-alias Filters ............................................................................... 10
4.3. Input Impedance .............................................................................. 10
4.4. Maximum Signal Levels ................................................................... 10
5. INPUT OFFSET ........................................................................................... 10
5.1. Offset Enable - OFST ...................................................................... 11
5.2. Offset Drift........................................................................................ 11
6. VOLTAGE REFERENCE INPUTS .............................................................. 11
6.1. Voltage Reference Configurations ................................................... 12
6.2. VREF Input Impedance.................................................................... 12
6.3. Gain Accuracy.................................................................................. 12
6.4. Gain Drift.......................................................................................... 12
7. DIGITAL FILTER INTERFACE ................................................................... 12
7.1. Modulator Clock - MCLK.................................................................. 13
7.2. Modulator Data - MDATA................................................................. 13
7.3. Modulator Sync - MSYNC................................................................ 13
7.4. Modulator Flag - MFLAG ................................................................. 13
8. POWER MODES ......................................................................................... 14
8.1. Normal Power Mode ........................................................................ 14
8.2. Low Power Mode - LPWR................................................................ 14
8.3. Power Down Mode - PWDN ............................................................ 14
8.4. Micro-power Mode ........................................................................... 14
9. POWER SUPPLY ........................................................................................ 14
9.1. Power Supply Configurations........................................................... 14
9.2. Power Supply Bypassing ................................................................. 14
9.3. SCR Latch-up Considerations ......................................................... 15
9.4. DC-DC Converter Considerations.................................................... 15
9.5. Power Supply Rejection................................................................... 15
10. PIN DESCRIPTION - CS5371 ..................................................................... 16
11. PIN DESCRIPTION - CS5372 ..................................................................... 18
12. PACKAGE DIMENSIONS ............................................................................ 20
13. ORDERING INFORMATION ....................................................................... 21
14. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION.. 21
15. REVISION HISTORY ................................................................................... 21
2
DS255F3
CS5371 CS5372
1. CHARACTERISTICS & SPECIFICATIONS
ANALOG CHARACTERISTICS Notes:TA = -40 C to +85 C; VA+ = 5V or 2.5V ± 5%; VA - = 0V or
-2.5V ± 5%; VD = 5V or 3.3V ± 5%; DGND = 0V; MCLK = 2.048 MHz; [(VREF+) - (VREF-)] = 2.5V;
Devices are connected as shown in Figure 3, the System Connection Diagram.
CS5371-BS / CS5372-BS
Parameter
Symbol
Specified Temperature Range
TA
Dynamic Performance
Dynamic Range
(Note 1) SNR
LPWR = 0
0 Hz to 1720 Hz
MCLK = 2.048 MHz
0 Hz to 860 Hz
0 Hz to 430 Hz
0 Hz to 215 Hz
0 Hz to 107.5 Hz
0 Hz to 53.75 Hz
0 Hz to 26.875 Hz
Dynamic Range
(Note 1) SNRLP
LPWR = 1
0 Hz to 1720 Hz
MCLK = 1.024 MHz
0 Hz to 860 Hz
0 Hz to 430 Hz
0 Hz to 215 Hz
0 Hz to 107.5 Hz
0 Hz to 53.75 Hz
0 Hz to 26.875 Hz
Total Harmonic Distortion
(Note 2)
THD
LPWR = 0; MCLK = 2.048 MHz
Total Harmonic Distortion
(Note 2) THDLP
LPWR = 1; MCLK = 1.024 MHz
DC Accuracy
Channel to Channel Gain Variation (Note 3) CGV
Full-scale Drift
(Notes 3 and 4) TCFS
Offset
(Note 3) VZSE
Offset after Calibration
(Note 5)
Offset Calibration Range
(Note 6)
Offset Drift
(Notes 3 and 4) TCZSE
Min
-40
Typ
-
Max
+85
Unit
C
121
-
109
121
124
127
130
133
136
-
dB
dB
dB
dB
dB
dB
dB
118
-
106
118
121
124
127
130
133
-118
-112
dB
dB
dB
dB
dB
dB
dB
dB
-
-114
-108
dB
-
1
5
1
±1
100
1
-
%
ppm/C
mV
µV
%F.S.
µV/C
Notes: 1. Dynamic Range defined as 20 log [ (RMS full scale) / (RMS idle noise) ]
2. Tested with full-scale input signal of 31.25 Hz; OWR = 1000 SPS; OFST = 1.
3. Specification is for the parameter over the specified temperature range for the CS5371/72 devices only
and does not include the effects of external components.
4. Specifications are guaranteed by design and/or characterization.
5. The offset after calibration specification applies to the effective offset voltage for a full-scale input to the
CS5371/72 modulator, but is measured from the output digital codes from the digital filter.
6. The CS5371/72 offset calibration is performed digitally and includes the full-scale range.
DS255F3
3
CS5371 CS5372
ANALOG CHARACTERISTICS (Continued)
Parameter
Specified Temperature Range
Symbol
Min
Typ
Max
Unit
TA
-40
-
+85
C
Input Characteristics
Input Signal Frequencies
(Note 7)
BW
DC
-
1720
Hz
Input Voltage Range
(Note 8)
VIN
-
-
5
Vp-p
Input Over-range Voltage Tolerance
(Note 8)
IOVR
5
-
-
%F.S.
(VA-)
+ 0.7V
-
(VA+)
- 1.7V
V
CMRR
-
90
-
dB
CXT
-
-120
-
dB
-
2.5
-
V
-
-
120
µA
-
5.0
0.2
3.0
0.2
7.0
0.3
4.5
0.3
mA
mA
mA
mA
-
1
10
-
mW
µW
-
25
1
10
-
mW
mW
µW
-
90
-
dB
Input Signal plus Common Mode
Common Mode Rejection Ratio
Channel Crosstalk (CS5372 only)
Voltage Reference Input
VREF
(VREF+) - (VREF-)
VREF Current
Power Supplies
DC Power Supply Currents
LPWR = 0; MCLK = 2.048 MHz
LPWR = 1; MCLK = 1.024 MHz
Power Down Modes
CS5371
CS5372
Power Supply Rejection
(Note 9 and 10)
Analog
Digital
Analog
Digital
PWDN = 1
PWDN = 1, MCLK = 0
VA
VD
VA
VD
PD
PWDN1 or PWDN2 = 1
PWDN1 = PWDN2 = 1
PWDN1 = PWDN2 = 1, MCLK = 0
(Note 11)
PSRR
Notes: 7. The upper bandwidth limit is determined by the digital filter. A simple single pole anti-alias filter with a 3 dB frequency at (MCLK / 256) should be placed in front of each channel.
8. The input voltage range is for the configuration depicted in Figure 3, the System Connection Diagram,
and applies to signal frequencies from DC to the stop-band frequency selected in the digital filter.
9. Per channel. All outputs unloaded. All digital inputs forced to VD or GND respectively.
10. In Low Power Mode LPWR = 1, the Master Clock MCLK is reduced to 1.024 MHz. This reduces the
oversampled signal bandwidth by a factor of 2.
11. Tested with a 50 Hz 100 mVpp sine wave applied separately to each supply.
4
DS255F3
CS5371 CS5372
DIGITAL CHARACTERISTICS Notes:TA = 25 C; VA+ = 5V or 2.5V ±5%; VA- = 0V or -2.5V ±5%;
VD = 5V or 3.3V ± 5%; DGND = 0V; All voltages with respect to DGND.
Parameter
Symbol
Min
Typ
Max
Unit
High-level Input Voltage
VIH
0.6 * VD
-
VD
V
Low-level Input Voltage
VIL
0.0
-
0.8
V
High-level Output Voltage
Iout = -5.0 mA
VOH
(VD) - 1.0
-
-
V
Low-level Output Voltage
Iout = 5.0 mA
VOL
-
-
0.4
V
Input Leakage Current
Iin
-
±1
±10
µA
3-state Leakage Current
IOZ
-
-
±10
µA
Digital Output Pin Capacitance
Cout
-
9
-
pF
ABSOLUTE MAXIMUM RATINGS Notes:DGND = 0 V
Parameter
Symbol
Min
Typ
Max
Unit
DC Power Supplies (Notes 12 and 13)
Positive Digital
Positive Analog
Negative Analog
VD
VA+
VA-
-0.3
-0.3
-3.3
-
+6.0
+6.0
+0.3
V
V
V
Input Current, Any Pin Except Supplies
(Note 14 and 15)
IIN
-
-
±10
mA
(Note 15)
IIN
-
-
±50
mA
IOUT
-
-
±25
mA
(Note 16)
PDN
-
-
500
mW
Analog Input Voltage
All Analog Pins
VINA
(VA-) - 0.5
-
(VA+) + 0.5
V
Digital Input Voltage
All Digital Pins
VIND
-0.5
-
(VD) + 0.5
V
Ambient Operating Temperature
TA
-40
-
85
°C
Storage Temperature
Tstg
-65
-
150
°C
Input Current, Supplies
Output Current
Power Dissipation
Notes: 12. VA+ and VA- must satisfy {(VA+) - (VA-)} < +6.8 V.
13. VD and VA- must satisfy {(VD) - (VA-)} < +7.6 V.
14. Includes continuous over-voltage conditions at the analog input (AIN) pins.
15. Transient current of up to 100 mA can be safely tolerated without SCR latch-up.
16. Total power dissipation, including all input and output currents.
DS255F3
5
CS5371 CS5372
SWITCHING CHARACTERISTICS Notes:TA = -40 C to +85 C; VA+ = +5V or +2.5V ± 5%; VA= 0V or -2.5V ± 5%; VD = +5V or +3.3V ± 5%; Digital Inputs: Logic 0 = 0V, Logic 1 = VD; CL = 50 pF
Parameter
Symbol
Min
Typ
Max
Unit
fc
0.1
2.048
2.2
MHz
40
-
60
%
MCLK Jitter (In-band or aliased in-band)
-
-
300
ps
MCLK Jitter (Out-of-band)
-
-
1
ns
MCLK Frequency
(Note 17)
MCLK Duty Cycle
Rise Times:
Any Digital Input
Any Digital Output
(Note 18)
trisein
triseout
-
50
50
100
ns
ns
Fall Times:
Any Digital Input
Any Digital Output
(Note 18)
tfallin
tfallout
-
50
50
100
ns
ns
(Note 19)
tmss
20
-
-
ns
MSYNC Hold Time after MCLK falling
tmsh
20
-
-
ns
MCLK rising to Valid MFLAG
tmfh
-
35
65
ns
MCLK rising to Valid MDATA
tmdv
-
60
90
ns
MSYNC Setup Time to MCLK falling
Notes: 17. If MCLK is removed, the CS5372 enters a micro power state.
18. Excludes MCLK input, MCLK should be driven with a signal having rise/fall times of 25 ns or faster.
19. MSYNC latched on MCLK falling edge, data output on next MCLK rising edge.
t risein
t riseout
t fallin
t fallout
0.9 * VD
0.9 * VD
0.1 * VD
0.1 * VD
Figure 1. Rise and Fall Times
MCLK
t mss
t msh
MSYNC
t mdv
MDATA
t mdv
VALID DATA
VALID DATA
t mfh
MFLAG
Figure 2. CS5372 Interface Timing
6
DS255F3
CS5371 CS5372
2. GENERAL DESCRIPTION.
Multi-channel System Support
The CS5371 and CS5372 are one- and two- channel fourth-order ∆Σ modulators, optimized for extremely high-resolution measurement of signals
between DC and 1600 Hz. They are designed to
be used with the CS5376A and CS5378 low-power
digital filters. Figure 3 on page 8 shows a fourchannel system connection diagram for two
CS5372 and one CS5376A.
Combining the CS5371 and CS5372 modulators
with a digital filter permits multiple system configurations:
High Performance
Differential Analog Signal Inputs
The CS5371/72 modulators have exceptional performance characteristics.
Modulator dynamic
range (SNR) is 127 dB over a 215 Hz bandwidth
(2 ms sampling), with total harmonic distortion
(THD) of -118 dB.
The CS5371/72 modulators have fully differential
analog inputs capable of measuring signals up to
5.0 V peak-to-peak when using a 2.5 V voltage reference. The inputs will tolerate a 5% over-range
voltage and continue operating at full specification.
Low Power Consumption
Digital Filter Interface
The CS5371/72 modulators have very low power
consumption. Power consumption is only 25 mW
per channel in normal mode (LPWR=0,
MCLK=2.048 MHz), and 15 mW per channel in low
power mode (LPWR=1, MCLK=1.024 MHz).
The CS5371/72 modulators are designed to operate with the CS5376A and CS5378 digital filters.
The digital filter generates the modulator clock and
synchronization signal inputs (MCLK and
MSYNC), while receiving the modulator data and
over-range flag outputs (MDATA and MFLAG).
The modulators produce an oversampled ∆Σ serial
bit stream at 512 kbits per second when operated
from a 2.048 MHz modulator clock.
An independently selectable power-down mode
(PWDN=1) can be used to disable a modulator and
reduces its power consumption to 1 mW. If MCLK
is then halted (MCLK=0), the modulator enters a
micropower state using only 10 µW per channel.
Small Package Size
The CS5371/72 modulators are available in a very
small 24-pin SSOP package approximately
8 mm x 8 mm in size. The CS5372 has two modulator channels per package to increase board layout density even further.
DS255F3
1 Channel - CS5371, CS5378
2 Channel - CS5372, CS5376A
3 Channel - CS5371, CS5372, CS5376A
4 Channel - CS5372, CS5372, CS5376A
Multiple Power Supply Configurations
The CS5371/72 modulators support flexible power
supply configurations. They can run from single or
dual supplies in the following configurations:
VA+ = +5V;
VA- = 0V;
VD = +3.3V to +5V
VA+ = +2.5V; VA- = -2.5V; VD = +3.3V
7
CS5371 CS5372
VD
VA+
100 µF
0.01 µF
INRI+
499 Ω
499 Ω
Channel 1
VA+
COG
0.02 µ F
X7R
INFI-
499 Ω
499 Ω
100 µF
VD
M F LAG1
INFI+
0.02 µ F
~
0.01 µF
MFLAG1
MDATA1
MDATA1
MFLAG2
MFLAG2
MDATA2
MDATA2
INRI-
CS5372
INR2+
499 Ω
499 Ω
MCLK
MSYNC
INF2+
Channel 2
0.02 µ F
~
COG
0.02 µ F
X7R
INF2-
499 Ω
499 Ω
INR2-
VA +
MCLK
MSYNC
OFST
GPIO4
LPWR
GPIO5
PWDN1
GPIO6
PWDN2
GPIO7
10 Ω
VREF
VREF+
100 µF
0.01µF
VA -
VREFVA-
DGND
CS5376A
10 Ω
VA+
VREF+
100 µF
VD
0.01µF
VREF-
INRI+
499 Ω
MCLK
499 Ω
Channel 3
INFI+
0.02 µ F
~
COG
MSYNC
0.02 µ F
X7R
OFST
INFI-
499 Ω
499 Ω
LPWR
PWDN1
INRI-
PWDN2
499 Ω
Channel 4
INF2+
0.02 µ F
~
CS5372
INR2+
499 Ω
COG
0.02 µ F
X7R
INF2-
499 Ω
499 Ω
MFLAG1
MFLAG3
MDATA1
MDATA3
MFLAG2
MFLAG4
MDATA2
MDATA4
INR2VA-
DGND
VA 100 µF
0.01 µF
Figure 3. System Connection Diagram
8
DS255F3
CS5371 CS5372
3. MODULATOR PERFORMANCE
Figures 4 and 5 illustrate the spectral performance
of the CS5371/72 modulators when combined with
the CS5376A or CS5378 digital filter. The plots
were created from ten averaged 1024 point FFTs.
3.1.
Full-scale Signal Performance
Figure 4 illustrates the full-scale signal performance of the CS5371/72 modulators and digital filter using a 31.25 Hz input signal and a 1000 SPS
output word rate. The outstanding full-scale signal
characteristics of the CS5371/72 modulators are
shown, with no harmonic components exceeding 120 dB. Analysis of this data set yields a signal-tonoise ratio (SNR) of 124.0 dB and a signal-to-distortion ratio (SDR) of 119.0 dB. Note that the fullscale signal peak in Figure 4 shows a slightly reduced amplitude due to spectral smearing associated with the FFT windowing function, and is a
purely digital phenomenon.
3.2.
Noise Performance
Figure 5 illustrates the noise performance of the
CS5371/72 modulators and digital filter using a
31.25 Hz -24 dB input signal at a 1000 SPS output
word rate. The outstanding noise characteristics of
the CS5371/72 modulators are shown, with the averaged noise components consistently below the
-150 dB level. Analysis of this data set yields a dynamic range of 124.7 dB. Note that the 0.7 dB
variation between the signal-to-noise calculation in
Figure 4 and the dynamic range calculation in Figure 5 is not modulator dependent and results from
jitter in the test signal generator when producing a
full-scale output, as evidenced by the skirt surrounding the signal peak below the -140 dB level in
Figure 4.
4. SIGNAL INPUTS
The CS5371/72 modulators use a switched capacitor architecture for the analog signal inputs, which
has increased jitter tolerance compared with continuous time signal input stages.
4.1.
The analog signal inputs are differential and use
four pins: INR+, INR-, INF+, and INF-. Two inputs,
INR+ and INF+, are connected to the positive half
of the differential signal, while two inputs, INR- and
INF-, are connected to the negative half. The INR+
and INR- pins are switched capacitor ‘rough
charge’ inputs that pre-charge the internal sampling capacitor before it is connected to the INF+
and INF- fine input pins.
The full-scale analog signal span is defined by the
voltage applied across the VREF+ and VREFpins. A 2.5 volt reference input sets full-scale signals as 5 volts peak-to-peak, fully differential. Differential inputs increase the dynamic range of
0
0
-20
-20
S/N = 124.0 dB
S/D = 119.0 dB
-40
Dynamic Range = 124.7 dB
-40
-60
-60
-80
-80
dB
dB
Differential Inputs - INR+/-, INF+/-
-100
-100
-120
-120
-140
-140
-160
-160
-180
-180
-200
-200
0
50
100
150
200
250
300
350
400
450
Hz
Figure 4. 1024 Point FFT plot with a 31.25 Hz
input at Full-scale, ten averages
DS255F3
500
0
50
100
150
200
250
Hz
300
350
400
450
500
Figure 5. 1024 Point FFT plot with a 31.25 Hz
input at -24 dB, ten averages
9
CS5371 CS5372
small signals, reducing the gain requirements for
input amplifier stages by a factor of two relative to
single ended analog inputs.
4.2.
Anti-alias Filters
The CS5371/72 modulator inputs must be bandwidth limited to ensure modulator loop stability and
to prevent aliased high-frequency signals. The
modulators are 4th order and so are conditionally
stable, and can be adversely affected by high amplitude out-of-band signals. Also, aliasing effects
degrade modulator performance if the analog inputs are not bandwidth limited since out-of-band
signals can appear in the measurement bandwidth. The use of a simple single pole low-pass
anti-alias filter on the differential inputs ensures
out-of-band signals are eliminated.
Anti-alias filtering may be accomplished actively in
an amplifier stage ahead of the CS5371/72 modulator, or passively using an RC filter across the differential rough and fine analog inputs. An RC filter
is recommended, even when using an amplifier
stage, as it minimizes the ‘charge kick’ that the
driving amplifier sees as switched capacitor sampling is performed.
The -3 dB corner of the input anti-alias filter should
be set to the internal modulator sampling clock divided by 64. The modulator sampling clock is a division by 4 of the modulator clock, MCLK. With
MCLK=2.048 MHz the modulator sampling clock is
512 kHz, requiring an input filter with a -3 dB corner at 8 kHz.
MCLK Frequency = 2.048 MHz
Sampling Frequency = MCLK / 4 = 512 kHz
-3 dB Filter Corner = Sample Freq / 64 = 8 kHz
RC filter = 8 kHz = 1 / [ 2π * (2 * Rdiff) * Cdiff ]
It should be noted that when using low power
mode (LPWR=1 and MCLK=1.024 MHz) the modulator sampling clock is 256 kHz, so the -3 dB filter
corner should be scaled down to 4 kHz.
MCLK Frequency = 1.024 MHz
Sampling Frequency = MCLK / 4 = 256 kHz
-3 dB Filter Corner = Sample Freq / 64 = 4 kHz
RC filter = 4 kHz = 1 / [ 2π * (2 * Rdiff) * Cdiff ]
10
Figure 3 illustrates the CS5372/CS5376A system
connections with input anti-alias filter components.
Filter components on the rough and fine pins
should be identical values for optimum performance, with the capacitor values a minimum of
0.02 µF. The rough input can use either X7R or
C0G capacitors, while the fine input requires C0G
type capacitors for optimal linearity. Using X7R capacitors on the fine inputs will degrade signal to
distortion performance up to 8 dB.
4.3.
Input Impedance
Due to the dynamic switched-capacitor input architecture, the input current required from the analog
signal source and thus the input impedance of the
analog input pins changes any time MCLK is
changed. The input impedance of the rough
charge inputs, INR+ and INR-, is [1 / (f * C)] where
f is the modulator clock frequency, MCLK, and C is
the internal sampling capacitor. A 2.048 MHz
modulator clock yields a rough input impedance of
approximately [1 / (2.048 MHz)*(20 pF)], or about
24 kΩ.
Internal to the modulator the rough charge inputs
pre-charge the sampling capacitor used by the fine
inputs, therefore the input current to the fine inputs
is very low and the effective input impedance is orders of magnitude above the impedance of the
rough inputs.
4.4.
Maximum Signal Levels
The CS5371/72 modulators are 4th order and are
therefore conditionally stable, and may go into an
oscillatory condition if the analog inputs over-range
beyond full scale by more than 5%. If an unstable
condition is detected, the modulators collapse to a
1st order system until loop stability is achieved.
During this time, the MFLAG pin transitions from
low to high signaling the digital filter to set an error
bit in the digital output status word. The analog input signal must be reduced to within the full-scale
range of the converter for at least 32 MCLK cycles
for the modulators to recover from an unstable
condition.
5. INPUT OFFSET
The CS5371/72 modulators are ∆Σ type and so
can produce ‘idle tones’ in the passband when the
DS255F3
CS5371 CS5372
input signal is a steady state DC signal within
±50 mV of the common mode input voltage. Idle
tones result from patterns in the output bitstream
and appear in the measurement spectrum about
-135 dB down from full scale.
Because offset drift is not linear with temperature,
an exact drift rate per °C cannot be specified. The
CS5371/72 modulators will exhibit approximately
5 ppm/°C of offset drift operating with an MCLK of
2.048 MHz.
Idle tones can be eliminated by adding differential
DC offset to the modulator inputs. The added offset should be applied differentially to the inputs,
common mode offsets do not affect idle tones.
6. VOLTAGE REFERENCE INPUTS
5.1.
Offset Enable - OFST
If the analog inputs are near the common mode
voltage when no signal is present, the OFST pin
can be used to eliminate idle tones. When
OFST=1, -50 mV of differential offset is added to
the modulator analog inputs to push the idle tones
out of the measurement bandwidth. Care should
be taken that when OFST is active, offset voltages
generated by external circuitry do not negate the
internally added offset.
5.2.
Offset Drift
Offset drift characteristics vary from part to part
and with changes in the power supply voltages. If
the CS5371/72 is used in precision DC measurement applications where offset drift is to be minimized, the power supplies should be well
regulated.
For the lowest offset drift, the CS5371/72 modulators should operate with an MCLK of 2.048 MHz.
The offset drift rate is inversely proportional to
clock frequency, with slower modulator clock rates
exhibiting more offset drift. Operating from an
MCLK of 1.024 MHz results in twice the offset drift
rate compared to an MCLK of 2.048 MHz.
DS255F3
The CS5371/72 modulators are designed to operate with a 2.5 V voltage reference applied across
the VREF+ and VREF- pins to set the full-scale signal range of the analog inputs. A 2.5 V voltage reference results in the highest dynamic range and
best signal-to-noise performance, though smaller
reference voltages may be used. When the
CS5371/72 modulators are operated with a 2.5 V
reference, the analog inputs measure full-scale
signals of 5 volts peak-to-peak fully differential.
In a single supply power configuration the voltage
reference output should be connected to the
VREF+ pin with the VREF- pin connected to
ground. In a dual supply power configuration the
voltage reference should be powered from the VA+
and VA- supplies, with the modulator VREF+ pin
connected to the voltage reference output and the
VREF- pin connected to VA-. Because most 2.5 V
voltage references require a power supply voltage
greater than 3 V to operate, when powering the
voltage reference from dual supplies the reference
voltage into the VREF+ pin should be defined relative to the VA- supply.
The selected voltage reference should produce
less than 1 µVrms of noise in the measurement
bandwidth on the VREF+ pin. The digital filter output word rate selection determines the bandwidth
11
CS5371 CS5372
For a 2.5 V reference, the Linear Technology
LT1019-2.5 voltage reference yields low enough
noise if the output is filtered with a low pass RC filter as shown in Figure 6. The filtered version in
Figure 6 is acceptable for most spectral measurement applications, but a buffered version with lower source impedance may be preferred for DC
measurement applications.
cy when using the higher source impedance configuration of Figure 6. The VREF+ pin input
impedance and the external low-pass filter resistor
create a voltage divider for the output reference
voltage, reducing the effective voltage reference
input. If gain error is to be minimized, especially
when MCLK is to be changed, the voltage reference should have a low output impedance to minimize the effect of the resistive voltage divider. A
buffered voltage reference configuration offers
lower output impedance and more stable gain
characteristics.
6.2.
6.4.
over which voltage reference noise affects the
CS5371/72 modulator dynamic range.
6.1.
Voltage Reference Configurations
VREF Input Impedance
The switched-capacitor input architecture of the
VREF+ pin causes the input current required from
the voltage reference to change any time MCLK is
changed. The input impedance of the voltage reference input is calculated similar to the analog signal input impedance as [1 / (f * C)] where f is the
modulator clock frequency, MCLK, and C is the internal sampling capacitor. A 2.048 MHz MCLK
yields a voltage reference input impedance of approximately [1 / (2.048 MHz)*(20 pF)], or about
24 kΩ.
6.3.
Gain Accuracy
Gain accuracy of the CS5371/72 modulators is affected by variations of the voltage reference input.
A change in the voltage reference input impedance
due to a change in MCLK could affect gain accura-
+VA
10 µF
Gain Drift
Gain drift of the CS5371/72 modulators due to temperature is around 5 ppm/°C, and does not include
the temperature drift characteristics of the external
voltage reference. Gain drift is not affected by the
modulator sample rate or by power supply variations.
7. DIGITAL FILTER INTERFACE
The CS5371/72 modulators are designed to operate with the CS5376A and CS5378 digital filters.
The digital filter generates the modulator clock and
synchronization signal inputs (MCLK and
MSYNC), while receiving the modulator data and
over-range flag outputs (MDATA and MFLAG).
The modulators produce an oversampled ∆Σ serial
0.1 µF
10 Ω
To VREF+
2.5 REF
0.1 µF
-VA
10 µF
+ 100µF
To VREF -
0.1 µF
Figure 6. 2.5 Voltage Reference
12
DS255F3
CS5371 CS5372
bit stream at 512 kbits per second when operated
from a 2.048 MHz modulator clock.
average, a ‘1’ value in 86 of every 100 output data
bits.
7.1.
When operated with the CS5376A or CS5378 digital filter, the full-scale 24-bit output codes range
from 0x5D1C41 to 0xA2EAAE with the internal
OFST disabled.
Modulator Clock - MCLK
For proper operation, the CS5371/72 modulators
must be provided with a CMOS compatible clock
on the MCLK pin. MCLK is internally divided by
four to generate the modulator sampling clock.
MCLK must have less than 300 ps of in-band jitter
to maintain full performance specifications.
When used with the CS5376A or CS5378 digital filter, MCLK is automatically generated and is typically 2.048 MHz or 1.024 MHz. MCLK can be
generated by other means, using a crystal oscillator for example, and can run any rate between
100 kHz and 2.2 MHz. If MCLK is disabled, the
modulators are automatically placed into a micropower state. They are equipped with loss of clock
detection circuitry to force power down if MCLK is
removed.
The choice of MCLK frequency affects the performance of the CS5371/72 modulators. They exhibit
the best dynamic range (SNR) performance with
faster MCLK rates because of increased oversampling of the analog input signal. The modulators
exhibit the best total harmonic distortion (THD)
performance with slower MCLK rates because
slower sampling allows more time to settle the analog input signal.
7.2.
Modulator Data - MDATA
The CS5371/72 modulators output a ∆Σ serial bitstream to the MDATA pin, with a one’s density proportional to the amplitude of the analog input signal
and a bit rate determined by the modulator sampling clock. The modulator sampling clock is a divide by four of MCLK, so for a 2.048 MHz MCLK
the modulator sampling clock and MDATA output
bit rate will be 512 kHz.
The MDATA output has a one’s density defined as
nominal 50% for no signal input, 86% for positive
full scale, and 14% for negative full scale. It has a
maximum positive over-range capability to 93%
and a maximum negative over-range capability to
7%. The one’s density of the MDATA output is defined as the ratio of ‘1’ bits to total bits in the serial
bitstream output, i.e. an 86% one’s density has, on
Modulator Input
Signal
> + (VREF + 5%)
Digital Filter
Output Code
OFST=0
OFST=1
Error Flag Possible
+VREF
5D1C41
5B3A71
0V
000000
FE21D8
-VREF
A2EAAE
A108DE
> - (VREF + 5%)
Error Flag Possible
Table 1. Output coding for the CS5371/72 and digital
filter combination
Note that for a full-scale input signal, 5 Vpp with
VREF=2.5 V, the CS5371/72 and CS5376A/78
chipset does not output a maximum 24-bit 2’s complement digital code of 0x7FFFFF, but instead a
lower scaled value to allow over-range capability.
7.3.
Modulator Sync - MSYNC
To synchronize the analog sampling instant and
timing of the digital output bitstream, the
CS5371/72 modulators use an MSYNC signal.
When using the CS5376A or CS5378 digital filter,
MSYNC is automatically generated from a SYNC
signal input from the external system.
The MSYNC input is rising edge triggered and resets the internal MCLK counter-divider so the analog sampling instant occurs during a consistent
MCLK phase. It also sets the MDATA output timing so the bitstream can be properly sampled by
the digital filter input.
7.4.
Modulator Flag - MFLAG
The CS5371/72 modulators are 4th order ∆Σ and
are therefore conditionally stable. The modulators
may go into an oscillatory condition if the analog inputs are over-ranged more than 5% past either
positive or negative fullscale.
If an unstable condition is detected, the modulators
collapse to a 1st order system until loop stability is
DS255F3
13
CS5371 CS5372
achieved. During this time, the MFLAG pin transitions from low to high to signal an error condition.
The analog input signal must be reduced to within
the full-scale range for at least 32 MCLK cycles for
the modulator to recover from an unstable condition.
The MFLAG output connects to a dedicated input
on the digital filter, causing an error bit to be set in
the status portion of the digital output data word
when detected.
PWDN on the CS5371 and PWDN1, PWDN2 on
the CS5372. Note that when the modulators are
powered down and MCLK is active, the internal
clock generator is still drawing minimal currents.
8.4.
Micro-power Mode
Standby power consumption of the modulators can
be minimized by placing them into a micro-power
mode, PWDN=1 and MCLK=0. Micro-power mode
requires setting the PWDN pin and halting MCLK
to remove the clock generator input current. Micropower mode consumes only 10 µW of power.
8. POWER MODES
Four power modes are available when using the
CS5371/72 modulators. Normal power and low
power modes are operational modes, power down
and micro-power modes are non-operational
standby modes.
8.1.
Normal Power Mode
The normal operational mode for the modulators,
LPWR=0 and MCLK=2.048 MHz, provides the
best performance with power consumption of
25 mW per channel. This power mode is recommended when maximum conversion accuracy is
required.
8.2.
Low Power Mode - LPWR
The modulators have a low-power operational
mode, LPWR=1 and MCLK=1.024 MHz, that reduces power consumption to 15 mW per channel
at the expense of 3 dB of dynamic range. This operational mode is recommended when minimizing
power is more important than maximizing dynamic
range.
9. POWER SUPPLY
The CS5371/72 modulators have one positive analog power supply pin, VA+, one negative analog
power supply pin, VA-, one digital power supply
pin, VD, and one digital ground pin, DGND. The
analog and digital circuitry is separated internally
to enhance performance, therefore power must be
supplied to all three supply pins and the digital
ground pin must be connected to system ground.
9.1.
Power Supply Configurations
The CS5371/72 analog supplies can be powered
by a single +5 V supply and analog ground, or by
dual supplies of ± 2.5 V. When using dual supplies, the positive and negative analog power supplies must satisfy the following conditions:
(VA+) - (VA-) < 6.8 volts
(VD) - (VA-) < 7.6 volts
These conditions permit several power supply configurations.
VA+ = +5V; VA- = 0V;
VD+ = +3.3V to +5V
When operated with LPWR=1, the modulator sampling clock (MCLK / 4) must be restricted to rates
of 256 kHz or less, which requires MCLK to run at
1.024 MHz or less. Operating in low power mode
with modulator sample rates greater than 256 kHz
will significantly degrade total harmonic distortion
performance.
When used with the CS5376A or CS5378 digital filter the maximum voltage differential between the
modulator digital supply, VD, and the CS5376A/78
I/O supply, VDD2 or VDDPAD, must be 0.3V or
less.
8.3.
9.2.
Power Down Mode - PWDN
The modulators have a power down mode,
PWDN=1 and MCLK=Active, that disables the operation of the selected modulator channel and reduces its power consumption to 1 mW. Each
modulator has an independent power down pin,
14
VA+ = +2.5V;VA- = -2.5V; VD+ = +3.3V
Power Supply Bypassing
The analog and digital supply pins, VA+, VA-, and
VD, should be decoupled to system ground with
0.01 µF and 10 µF capacitors, or with a single
0.1 µF capacitor. Bypass capacitors can be X7R,
tantalum, or any other dielectric types.
DS255F3
CS5371 CS5372
9.3.
SCR Latch-up Considerations
The VA- pin is tied to the CS5371/72 substrate and
should always be connected to the most negative
supply voltage to ensure SCR latch-up does not
occur. In general, latch-up may occur when any
pin voltage (including the analog inputs) is 0.7V or
more below VA-, or 7.6V or more above VA-.
Analog inputs INR+/- and INF+/- should be voltage
limited to ensure signals don’t exceed the (VA-)0.7V or (VA+)+7.6V requirement. Either the inputs
should be clamped to the VA+ and VA- rails using
reversed biased Schottky diodes (BAT85 or similar), or the current into the analog inputs should be
limited to less than 10mA. By current limiting the
analog inputs, the internal ESD diodes on the analog input pads will clamp the input signal to the
proper level. Input currents greater than 10mA will
overdrive the internal diodes, so external components are required.
When using dual analog power supplies, it is recommended to connect the VA- power supply pin to
system ground (DGND) using a reversed biased
Schottky diode. This configuration clamps the VA-
DS255F3
voltage a maximum of 0.3V above ground to ensure SCR latch-up does not occur during power
up. If the VA+ power supply ramps before the VAsupply, the VA- voltage could be pulled above
ground through the CS5371/72. If the VA- supply
is unintentionally pulled 0.7 V above the DGND
pin, SCR latch-up can occur.
9.4.
DC-DC Converter Considerations
Many measurement systems are battery powered
and utilize DC-DC converters to generate the necessary supply voltages for the system. To minimize the effects of interference, it is desirable to
operate the DC-DC converter at a frequency which
is rejected by the digital filter.
9.5.
Power Supply Rejection
Power supply rejection of the CS5371/72 modulators is frequency dependent. The digital filter rejects power supply noise for frequencies above the
filter corner frequency at 130 dB or greater. For
frequencies between DC and the digital filter corner frequency, power supply rejection is nearly
constant at 90 dB.
15
CS5371 CS5372
10. PIN DESCRIPTION - CS5371
Rough Non-Inverting Input
INR+
1
24
PWDN
Power-down Enable
Fine Non-Inverting Input
INF+
2
23
LPWR
Low Power Mode Select
Fine Inverting Input
INF-
3
22
MFLAG
Modulator Flag Output
Rough Inverting Input
INR-
4
21
MDATA
Modulator Data Output
Positive Voltage Reference Input
VREF+
5
20
MSYNC
Modulator Sync Input
Negative Voltage Reference Input
VREF-
6
19
MCLK
Modulator Clock Input
Negative Analog Power Supply
VA-
7
18
VD
Positive Digital Power Supply
Positive Analog Power Supply
VA+
8
17
DGND
Digital Ground
No Internal Connection
NC
9
16
NC
No Internal Connection
No Internal Connection
NC
10
15
NC
No Internal Connection
No Internal Connection
NC
11
14
OFST
Offset Mode Select
No Internal Connection
NC
12
13
VD
Positive Digital Power Supply
Power Supplies
_
VA+
Positive Analog Power Supply, pin 8
Positive supply voltage.
VA-
_
Negative Analog Power Supply, pin 7
Negative supply voltage.
VD
_
Positive Digital Power Supply, pin 13, 18
Positive supply voltage.
_
DGND
Digital Ground, pin 17
Analog Inputs
INR+
_
Rough Non-Inverting Input, pin 1
Rough non-inverting analog input. The rough input settles non-linear currents to improve
linearity on the fine input and reduce harmonic distortion.
INR-
_
Rough Inverting Input, pin 4
Rough inverting analog input. The rough input settles non-linear currents to improve linearity
on the fine input and reduce harmonic distortion.
INF+
_
Fine Non-Inverting Input, pin 2
Fine non-inverting analog input.
16
DS255F3
CS5371 CS5372
INF-
_
Fine Inverting Input, pin 3
Fine inverting analog input.
_
VREF+
Positive Voltage Reference Input, pin 5
Input for an external +2.5 V voltage reference relative to VREF-.
_
VREF-
Negative Voltage Reference Input, pin 6
This pin should be tied to VA-.
Digital Inputs
_
MCLK
Modulator Clock Input, pin 19
A CMOS compatible clock input for the modulator internal master clock, nominally 2.048 MHz
with an amplitude equal to the VD digital power supply.
_
MSYNC
Modulator Sync Input, pin 20
A low to high transition resets the internal clock phasing of the modulator. This assures the
sampling instant and modulator data output are synchronous to the external system.
OFST
_
Offset Mode Select, pin 14
When high, adds approximately -50 mV of offset to the analog inputs to guarantee any ∆Σ idle
tones are removed. When low, no offset is added.
_
LPWR
Low Power Mode Select, pin 23
When set high with MCLK operating at 1.024 MHz, modulator power dissipation is reduced to
15 mW per channel.
PWDN
_
Power-down Mode, pin 24
When high, the modulator is in power-down mode and consumes 1 mW. Halting MCLK while
in power down mode reduces modulator power dissipation to 10 µW.
Digital Outputs
MDATA
_
Modulator Data Output, pin 21
Modulator data is output as a 1-bit serial data stream at 512 kHz with an MCLK input of
2.048 MHz. Modulator data is output at 256 kHz with an MCLK input of 1.024 MHz.
MFLAG
_
Modulator Flag Output, pin 22
A high level output indicates the modulator is unstable due to an over-range on the analog
inputs.
DS255F3
17
CS5371 CS5372
11. PIN DESCRIPTION - CS5372
Ch. 1 Rough Non-Inverting Input
INR1+
1
24
PWDN1
Ch. 1 Power-down Enable
Ch. 1 Fine Non-Inverting Input
INF1+
2
23
LPWR
Low Power Mode Select
Ch. 1 Fine Inverting Input
INF1-
3
22
MFLAG1
Ch. 1 Modulator Flag Output
Ch. 1 Rough Inverting Input
INR1-
4
21
MDATA1
Ch. 1 Modulator Data Output
Positive Voltage Reference Input
VREF+
5
20
MSYNC
Modulator Sync Input
Negative Voltage Reference Input
VREF-
6
19
MCLK
Modulator Clock Input
Negative Analog Power Supply
VA-
7
18
VD
Positive Digital Power Supply
Positive Analog Power Supply
VA+
8
17
DGND
Digital Ground
Ch. 2 Rough Inverting Input
INR2-
9
16
MDATA2
Ch. 2 Modulator Data Output
Ch. 2 Fine Inverting Input
INF2-
10
15
MFLAG2
Ch. 2 Modulator Flag Output
Ch. 2 Fine Non-Inverting Input
INF2+
11
14
OFST
Offset Mode Select
Ch. 2 Rough Non-Inverting Input
INR2+
12
13
PWDN2
Ch. 2 Power-down Enable
Power Supplies
_
VA+
Positive Analog Power Supply, pin 8
Positive supply voltage.
VA-
_
Negative Analog Power Supply, pin 7
Negative supply voltage.
VD
_
Positive Digital Power Supply, pin 18
Positive supply voltage.
DGND
_
Digital Ground, pin 17
Analog Inputs
_
INR1+, INR2+
Channel 1 & 2 Rough Non-Inverting Inputs, pin 1, 12
Rough non-inverting analog inputs. The rough inputs settle non-linear currents to improve
linearity on the fine inputs and reduce harmonic distortion.
INR1-, INR2-
_
Channel 1 & 2 Rough Inverting Inputs, pin 4, 9
Rough inverting analog inputs. The rough inputs settle non-linear currents to improve linearity
on the fine inputs and reduce harmonic distortion.
INF1+, INF2+
_
Channel 1 & 2 Fine Non-Inverting Input, pin 2, 11
Fine non-inverting analog inputs.
18
DS255F3
CS5371 CS5372
INF1-, INF2-
_
Channel 1 & 2 Fine Inverting Input, pin 3, 10
Fine inverting analog inputs.
_
VREF+
Positive Voltage Reference Input, pin 5
Input for an external +2.5 V voltage reference relative to VREF-.
VREF-
_
Negative Voltage Reference Input, pin 6
This pin should be tied to VA-.
Digital Inputs
MCLK
_
Modulator Clock Input, pin 19
A CMOS compatible clock input for the modulator internal master clock, nominally 2.048 MHz
with an amplitude equal to the VD digital power supply.
MSYNC
_
Modulator Sync Input, pin 20
A low to high transition resets the internal clock phasing of the modulator. This assures the
sampling instant and modulator data output are synchronous to the external system.
OFST
_
Offset Mode Select, pin 14
When high, adds approximately -50 mV of offset to the analog inputs to guarantee any ∆Σ idle
tones are removed. When low, no offset is added.
LPWR
_
Low Power Mode Select, pin 23
When set high with MCLK operating at 1.024 MHz, modulator power dissipation is reduced to
15 mW per channel.
PWDN1, PWDN2
_
Channel 1 & 2 Power-down Mode, pin 24, 13
When high, the modulator is in power down mode and consumes 1 mW. Halting MCLK while
in power down mode reduces modulator power dissipation to 10 µW.
Digital Outputs
MDATA1, MDATA2
_
Modulator Data Output, pin 21, 16
Modulator data is output as a 1-bit serial data stream at 512 kHz with an MCLK input of
2.048 MHz. Modulator data is output at 256 kHz with an MCLK input of 1.024 MHz.
MFLAG1, MFLAG2
_
Modulator Flag, pin 22, 15
A high level output indicates the modulator is unstable due to an over-range on the analog
inputs.
DS255F3
19
CS5371 CS5372
12.PACKAGE DIMENSIONS
24 PIN SSOP PACKAGE DRAWING
N
D
E11
A2
E
b2
e
SIDE VIEW
A
A1
L
END VIEW
SEATING
PLANE
1 2 3
TOP VIEW
INCHES
DIM
A
A1
A2
b
D
E
E1
e
L
∝
MIN
-0.002
0.064
0.009
0.311
0.291
0.197
0.024
0.025
0°
MAX
0.084
0.010
0.074
0.015
0.335
0.323
0.220
0.027
0.040
8°
MILLIMETERS
MIN
MAX
-2.13
0.05
0.25
1.62
1.88
0.22
0.38
7.90
8.50
7.40
8.20
5.00
5.60
0.61
0.69
0.63
1.03
0°
8°
NOTE
2,3
1
1
Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not
reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
20
DS255F3
CS5371 CS5372
13.ORDERING INFORMATION
Model
Temperature
Package
-40 to +85 °C
24-pin SSOP
CS5371-BS
CS5371-BSZ (lead free)
CS5372-BS
CS5372-BSZ (lead free)
14.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model Number
Peak Reflow Temp
MSL Rating*
Max Floor Life
CS5371-BS
240 °C
2
365 Days
CS5371-BSZ (lead free)
260 °C
3
7 Days
CS5372-BS
240 °C
2
365 Days
CS5372-BSZ (lead free)
260 °C
3
7 Days
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
DS255F3
21
CS5371 CS5372
15.REVISION HISTORY
Revision
Date
Changes
PP2
AUG 2001
Preliminary release, updated with most-current characterization data.
F1
SEP 2005
Fix data sheet errata.
F2
SEP 2005
Corrected Table 1 on Page 13: When OFST=0 the 0V input is 0x000000, when
OFST=1 the 0V input is 0xFE21D8.
F3
OCT 2005
Corrected typical and maximum low-power THD on Page 3.
Corrected maximum input signal frequency on Page 4.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
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22
DS255F3