LTC2635 Quad 12-/10-/8-Bit I2C VOUT DACs with 10ppm/°C Reference Features n n n n n n n n n n n Description Integrated Precision Reference 2.5V Full-Scale 10ppm/°C (LTC2635-L) 4.096V Full-Scale 10ppm/°C (LTC2635-H) Maximum INL Error: ±2.5 LSB (LTC2635-12) Power-On-Reset to Zero-Scale/Mid-Scale/Hi-Z Low Noise: 0.75mVP-P 0.1Hz to 200kHz Guaranteed Monotonic Over –40°C to 125°C Automotive Temperature Range Selectable Internal or External Reference 2.7V to 5.5V Supply Range (LTC2635-L) Ultralow Crosstalk Between DACs (3nV•s) Low Power: 0.6mA at 3V Double-Buffered Data Latches Small 16-Pin 3mm × 3mm QFN and 10-Lead MSOP Packages Applications n n n n n Mobile Communications Process Control and Industrial Automation Power Supply Margining Portable Equipment Automotive The LTC®2635 is a family of quad 12-, 10-, and 8-bit voltage-output DACs with an integrated, high-accuracy, low-drift reference in a 16-pin QFN or a 10-lead MSOP package. It has rail-to-rail output buffers and is guaranteed monotonic. The LTC2635-L has a full-scale output of 2.5V, and operates from a single 2.7V to 5.5V supply. The LTC2635-H has a full-scale output of 4.096V, and operates from a 4.5V to 5.5V supply. Each DAC can also operate with an external reference, which sets the fullscale output to the external reference voltage. These DACs communicate via a 2-wire I2C-compatible serial interface. The LTC2635 operates in both the standard mode (clock rate of 100kHz) and the fast mode (clock rate of 400kHz). The LTC2635 incorporates a power-on reset circuit. Options are available for reset to zero-scale, reset to mid-scale in internal reference mode, reset to mid-scale in external reference mode, or reset with all DAC outputs in a high-impedance state after power-up. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5396245, 5859606, 6891433, 6937178, 7414561. Block Diagram Integral Nonlinerity INTERNAL REFERENCE GND SWITCH REF 2 VCC 1 VCC = 3V INTERNAL REF. REGISTER REGISTER REGISTER DAC A REGISTER VOUTA DAC D VREF (LDAC) DECODE CA0 (CA1) (CA2) I2C ADDRESS DECODE ( ) QFN PACKAGE ONLY REGISTER REGISTER REGISTER DAC B REGISTER VREF VOUTB VOUTD DAC C I C INTERFACE 0 VOUTC –1 POWER-ON RESET –2 SCL 2 INL (LSB) VREF (REFLO) 0 1024 2048 CODE 3072 4095 2635 TA01 SDA 2635 BD 2635fb LTC2635 Absolute Maximum Ratings (Notes 1, 2) Supply Voltage (VCC).................................... –0.3V to 6V SCL, SDA, REFLO, LDAC............................... –0.3V to 6V VOUTA-D, CA0, CA1, CA2....... –0.3V to Min (VCC + 0.3V, 6V) REF..................................... –0.3V to Min (VCC + 0.3V, 6V) Operating Temperature Range LTC2635C................................................. 0°C to 70°C LTC2635H (Note 3)............................. –40°C to 125°C Maximum Junction Temperature .......................... 150°C Storage Temperature Range.................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) MS Package....................................................... 300°C Pin Configuration REFLO GND DNC VCC TOP VIEW TOP VIEW 16 15 14 13 12 VOUTD VOUTA 1 VOUTB 2 11 VOUTC 17 GND LDAC 3 10 REF CA0 4 6 7 8 SCL DNC CA2 SDA 9 5 CA1 UD PACKAGE 16-LEAD (3mm s 3mm) PLASTIC QFN VCC 1 VOUTA 2 VOUTB 3 CA0 4 SCL 5 11 GND 10 9 8 7 6 GND VOUTD VOUTC REF SDA MSE PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 150°C, θJA = 35°C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB TJMAX = 150°C, θJA = 68°C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB 2635fb LTC2635 Order Information LTC2635 C UD –L Z 12 #TR PBF LEAD FREE DESIGNATOR PBF = Lead Free TAPE AND REEL TR = 2,500-Piece Tape and Reel RESOLUTION 12 = 12-Bit 10 = 10-Bit 8 = 8-Bit POWER-0N RESET MI = Reset to Mid-Scale in Internal Reference Mode MX = Reset to Mid-Scale in External Reference Mode (LMX Only) MO = Reset to Mid-Scale in Internal Reference Mode, DAC Outputs Hi-Z (LMO Only) Z = Reset to Zero-Scale in Internal Reference Mode FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE L = 2.5V H = 4.096V PACKAGE TYPE UD = 16-Pin QFN MSE = 10-Lead MSOP TEMPERATURE GRADE C = Commercial Temperature Range (0°C to 70°C) H = Automotive Temperature Range (–40°C to 125°C) PRODUCT PART NUMBER Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2635fb LTC2635 Product Selection Guide PART MARKING* POWER-ON RESET TO CODE POWER-ON REFERENCE MODE RESOLUTION VCC MAXIMUM INL PART NUMBER QFN MSOP VFS WITH INTERNAL REFERENCE LTC2635-LMI12 LTC2635-LMI10 LTC2635-LMI8 LDZB LDZJ LDZR LTDZY LTFBG LTFBP 2.5V • (4095/4096) 2.5V • (1023/1024) 2.5V • (255/256) Mid-Scale Mid-Scale Mid-Scale Internal Internal Internal 12-Bit 10-Bit 8-Bit 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V ±2.5LSB ±1LSB ±0.5LSB LTC2635-LMX12 LTC2635-LMX10 LTC2635-LMX8 LDYZ LDZH LDZQ LTDZX LTFBF LTFBN 2.5V • (4095/4096) 2.5V • (1023/1024) 2.5V • (255/256) Mid-Scale Mid-Scale Mid-Scale External External External 12-Bit 10-Bit 8-Bit 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V ±2.5LSB ±1LSB ±0.5LSB LTC2635-LZ12 LTC2635-LZ10 LTC2635-LZ8 LDYY LDZG LDZP LTDZW LTFBD LTFBM 2.5V • (4095/4096) 2.5V • (1023/1024) 2.5V • (255/256) Zero-Scale Zero-Scale Zero-Scale Internal Internal Internal 12-Bit 10-Bit 8-Bit 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V ±2.5LSB ±1LSB ±0.5LSB LTC2635-LMO12** LTC2635-LMO10** LTC2635-LMO8** LFBT LFBV LFBW LTFBX LTFBY LTFBZ 2.5V • (4095/4096) 2.5V • (1023/1024) 2.5V • (255/256) High Impedance High Impedance High Impedance Internal Internal Internal 12-Bit 10-Bit 8-Bit 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V ±2.5LSB ±1LSB ±0.5LSB LTC2635-HMI12 LTC2635-HMI10 LTC2635-HMI8 LDZF LDZN LDZV LTFBC LTFBK LTFBS 4.096V • (4095/4096) 4.096V • (1023/1024) 4.096V • (255/256) Mid-Scale Mid-Scale Mid-Scale Internal Internal Internal 12-Bit 10-Bit 8-Bit 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V ±2.5LSB ±1LSB ±0.5LSB LTC2635-HZ12 LTC2635-HZ10 LTC2635-HZ8 LDZC LDZK LDZS LTDZZ LTFBH LTFBQ 4.096V • (4095/4096) 4.096V • (1023/1024) 4.096V • (255/256) Zero-Scale Zero-Scale Zero-Scale Internal Internal Internal 12-Bit 10-Bit 8-Bit 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V ±2.5LSB ±1LSB ±0.5LSB *Above options are available in a 16-pin QFN package (LTC2635xUD) or 10-lead MSOP package (LTC2635xMSE). **Contact Linear Technology for other Hi-Z options. 2635fb LTC2635 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2635-LMI12/-LMI10/-LMI8/-LMX12/-LMX10/-LMX8/-LZ12/-LZ10/-LZ8/-LMO12/-LMO10/-LM08 (VFS = 2.5V) LTC2635-8 SYMBOL PARAMETER CONDITIONS MIN TYP LTC2635-10 MAX MIN TYP LTC2635-12 MAX MIN TYP MAX UNITS DC Performance Resolution l 8 8 10 12 VCC = 3V, Internal Ref. (Note 4) l l INL Differential Nonlinearity VCC = 3V, Internal Ref. (Note 4) Integral Nonlinearity VCC = 3V, Internal Ref. (Note 4) l ±0.05 ±0.5 ±0.2 ±1 ZSE Zero-Scale Error VCC = 3V, Internal Ref., Code=0 l 0.5 5 0.5 VOS Offset Error VCC = 3V, Internal Ref. (Note 5) l ±0.5 ±5 ±0.5 VOSTC VOS Temperature Coefficient VCC = 3V, Internal Ref. GE Gain Error VCC = 3V, Internal Ref. GETC Gain Temperature Coefficient VCC = 3V, Internal Ref. (Note 10) C-Grade H-Grade Monotonicity DNL Load Regulation ROUT DC Output Impedance Internal Ref., Mid-Scale, VCC = 3V ± 10%, –5mA ≤ IOUT ≤ 5mA VCC = 5V±10%, –10mA ≤ IOUT ≤ 10mA Internal Ref., Mid-Scale, VCC = 3V ± 10%, –5mA ≤ IOUT ≤ 5mA VCC = 5V±10%, –10mA ≤ IOUT ≤ 10mA 10 ±0.2 l Bits ±0.5 ±1 LSB ±1 ±2.5 LSB 5 0.5 5 mV ±5 ±0.5 ±5 mV ±10 ±0.8 ±0.2 ±10 ±0.8 ±0.2 10 10 10 µV/°C ±0.8 10 10 10 %FSR ppm/°C ppm/°C l 0.009 0.016 0.035 0.064 0.14 0.256 LSB/mA l 0.009 0.016 0.035 0.064 0.14 0.256 LSB/mA l 0.09 0.156 0.09 0.156 0.09 0.156 Ω l 0.09 0.156 0.09 0.156 0.09 0.156 Ω SYMBOL PARAMETER CONDITIONS VOUT DAC Output Span External Reference Internal Reference PSR Power Supply Rejection VCC = 3V ± 10% or 5V ± 10% ISC Short Circuit Output Current (Note 6) Sinking Sourcing VFS = VCC = 5.5V Zero-Scale; VOUT Shorted to VCC Full-Scale; VOUT Shorted to GND DAC ISD 12 ±0.5 ±10 Bits MIN TYP MAX UNITS 0 to VREF 0 to 2.5 V V –80 dB l l 27 –28 48 –48 mA mA DAC Output Current in High Impedance Mode MO Options Only Sinking Sourcing l l 0.05 –0.001 2 –0.1 µA µA Power Supply VCC Positive Supply Voltage For Specified Performance l 5.5 V ICC Supply Current (Note 7) VCC = 3V, VREF = 2.5V, External Reference VCC = 3V, Internal Reference VCC = 5V VREF = 2.5V, External Reference VCC = 5V, Internal Reference l l l l 2.7 0.5 0.6 0.6 0.7 0.7 0.8 0.8 0.9 mA mA mA mA ISD Supply Current in Power-Down Mode (Note 7) VCC = 5V, C-Grade VCC = 5V, H-Grade l l 1 1 20 30 µA µA 2635fb LTC2635 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2635-LMI12/-LMI10/-LMI8/-LMX12/-LMX10/-LMX8/-LZ12/-LZ10/-LZ8/-LMO12/-LMO10/-LM08 (VFS = 2.5V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCC V 200 kΩ Reference Input Input Voltage Range l 1 Resistance l 120 Capacitance IREF Reference Current, Power-Down Mode 160 14 DAC Powered Down l pF 0.005 1.5 µA 1.25 1.26 V Reference Output Output Voltage l 1.24 Reference Temperature Coefficient ±10 ppm/°C Output Impedance 0.5 kΩ Capacitive Load Driving 10 µF 2.5 mA Short Circuit Current VCC = 5.5V, REF Shorted to GND VIL Low Level Input Voltage (SDA and SCL) (Note 14) l –0.5 VIH High Level Input Voltage (SDA and SCL) (Note 11) l 0.7VCC VIL(CAn) Low Level Input Voltage on CAn (n = 0, 1,2) See Test Circuit 1 l VIH(CAn) High Level Input Voltage on CAn (n = 0, 1,2) See Test Circuit 1 l RINH Resistance from CAn (n = 0, 1,2) to VCC to Set CAn = VCC See Test Circuit 2 l 10 kΩ RINL Resistance from CAn (n = 0, 1,2) to GND to Set CAn = GND See Test Circuit 2 l 10 kΩ RINF Resistance from CAn (n = 0, 1,2) to VCC or GND to Set CAn = Float See Test Circuit 2 l 2 VOL Low Level Output Voltage Sink Current = 3mA l 0 0.4 V tOF Output Fall Time VO = VIH(MIN) to VO = VIL(MAX), CB = 10pF to 400pF (Note 12) l 20 + 0.1CB 250 ns tSP Pulse Width of Spikes Suppressed by Input Filter l 0 50 ns IIN Input Leakage 0.1VCC ≤ VIN ≤ 0.9VCC l 1 µA CIN I/O Pin Capacitance (Note 8) l 10 pF CB Capacitive Load for Each Bus Line l 400 pF CCAn External Capacitive Load on Address Pin CAn (n = 0, 1,2) l 10 pF Digital I/O 0.3VCC V V 0.15VCC 0.85VCC V V MΩ 2635fb LTC2635 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2635-LMI12/-LMI10/-LMI8/-LMX12/-LMX10/-LMX8/-LZ12/-LZ10/-LZ8/-LMO12/-LMO10/-LM08 (VFS = 2.5V) SYMBOL PARAMETER CONDITIONS Settling Time VCC = 3V (Note 9) ±0.39% (±1LSB at 8 Bits) ±0.098% (±1LSB at 10 Bits) ±0.024% (±1LSB at 12 Bits) MIN TYP MAX UNITS AC Performance tS 3.5 4.1 4.4 Voltage Output Slew Rate 1 Capacitive Load Driving en µs µs µs V/µs 500 pF 2.1 nV • s Glitch Impulse At Mid-Scale Transition DAC-to-DAC Crosstalk 1 DAC Held at FS, 1 DAC Switched 0 to FS 2.6 nV • s Multiplying Bandwidth External Reference 320 kHz Output Voltage Noise Density At f = 1kHz, External Reference At f = 10kHz, External Reference At f = 1kHz, Internal Reference At f = 10kHz, Internal Reference 180 160 200 180 nV/√Hz nV/√Hz nV/√Hz nV/√Hz Output Voltage Noise 0.1Hz to 10Hz, External Reference 0.1Hz to 10Hz, Internal Reference 0.1Hz to 200kHz, External Reference 0.1Hz to 200kHz, Internal Reference CREF = 0.1µF 35 40 680 730 µVP-P µVP-P µVP-P µVP-P TIMING Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V. (See Figure 1) (Note 13) LTC2635-LMI12/-LMI10/-LMI8/-LMX12/-LMX10/-LMX8/-LZ12/-LZ10/-LZ8/-LMO12/-LMO10/-LM08 (VFS = 2.5V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fSCL SCL Clock Frequency l 0 400 kHz tHD(STA) Hold Time (Repeated) Start Condition l 0.6 µs tLOW Low Period of the SCL Clock Pin l 1.3 µs tHIGH High Period of the SCL Clock Pin l 0.6 µs tSU(STA) Set-Up Time for a Repeated Start Condition l 0.6 µs tHD(DAT) Data Hold Time l 0 0.9 µs tSU(DAT) Data Set-Up Time l 100 tr Rise Time of Both SDA and SCL Signals (Note 12) l 20 + 0.1CB 300 ns ns tf Fall Time of Both SDA and SCL Signals (Note 12) l 20 + 0.1CB 300 ns tSU(STO) Set-Up Time for Stop Condition l 0.6 µs tBUF Bus Free Time Between a Stop and Start Condition l 1.3 µs t1 Falling Edge of 9th Clock of the 3rd Input Byte to LDAC l 400 ns LDAC Low Pulse Width l 20 ns t2 High or Low Transition 2635fb LTC2635 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2635-HMI12/-HMI10/-HMI8/-HZ12/-HZ10/-HZ8 (VFS = 4.096V) LTC2635-8 SYMBOL PARAMETER CONDITIONS MIN TYP LTC2635-10 MAX MIN TYP LTC2635-12 MAX MIN TYP MAX UNITS DC Performance l 8 10 12 Bits VCC = 5V, Internal Ref. (Note 4) l 8 10 12 Bits DNL Differential Nonlinearity VCC = 5V, Internal Ref. (Note 4) l INL Integral Nonlinearity VCC = 5V, Internal Ref. (Note 4) l 0.5 5 0.5 5 0.5 5 mV ±0.5 ±5 ±0.5 ±5 ±0.5 ±5 mV Resolution Monotonicity ±0.5 ±0.05 ±0.5 ±0.5 ±0.2 ±1 ±1 ±1 LSB ±2.5 LSB ZSE Zero-Scale Error VCC = 5V, Internal Ref., Code=0 l VOS Offset Error VCC = 5V, Internal Ref. (Note 5) l VOSTC VOS Temperature Coefficient VCC = 5V, Internal Reference GE Gain Error VCC = 5V, Internal Reference GETC Gain Temperature Coefficient VCC = 5V, Internal Ref. (Note 10) C-Grade H-Grade Load Regulation Internal Reference, Mid-Scale, VCC = 5V ± 10%, –10mA ≤ IOUT ≤ 10mA l 0.006 0.01 0.022 0.04 0.09 0.16 LSB/mA DC Output Internal Reference, Mid-Scale, VCC = 5V ± 10%, –10mA ≤ IOUT ≤ 10mA l 0.09 0.156 0.09 0.156 0.09 0.156 Ω ROUT ±10 l ±0.2 ±10 ±0.8 ±0.2 ±10 ±0.8 ±0.2 10 10 10 10 SYMBOL PARAMETER CONDITIONS VOUT DAC Output Span External Reference Internal Reference PSR Power Supply Rejection VCC = 5V±10% ISC Short Circuit Output Current (Note 6) Sinking Sourcing VFS = VCC = 5.5V Zero-Scale; VOUT Shorted to VCC Full-Scale; VOUT Shorted to GND l l VCC Positive Supply Voltage For Specified Performance l ICC Supply Current (Note 7) VCC = 3V, VREF = 4.096V, External Reference VCC = 3V, Internal Reference l l ISD Supply Current in Power-Down Mode (Note 7) VCC = 5V, C-Grade VCC = 5V, H-Grade l l µV/°C ±0.8 10 10 MIN TYP %FSR ppm/°C ppm/°C MAX UNITS 0 to VREF 0 to 4.096 V V –80 dB 27 –28 48 –48 mA mA 5.5 V 0.6 0.7 0.8 0.9 mA mA 1 1 20 30 µA µA Power Supply 4.5 2635fb LTC2635 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2635-HMI12/-HMI10/-HMI8/-HZ12/-HZ10/-HZ8 (VFS = 4.096V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCC V 200 kΩ Reference Input Input Voltage Range l 1 Resistance l 120 Capacitance IREF Reference Current, Power-Down Mode 160 14 DAC Powered Down l pF 0.005 1.5 µA 2.048 2.064 V Reference Output Output Voltage l 2.032 Reference Temperature Coefficient ±10 ppm/°C Output Impedance 0.5 kΩ Capacitive Load Driving 10 µF 4 mA Short Circuit Current VCC = 5.5V, REF Shorted to GND VIL Low Level Input Voltage (SDA and SCL) (Note 14) l –0.5 VIH High Level Input Voltage (SDA and SCL) (Note 11) l 0.7VCC VIL(CAn) Low Level Input Voltage on CAn (n = 0, 1,2) See Test Circuit 1 l VIH(CAn) High Level Input Voltage on CAn (n = 0, 1,2) See Test Circuit 1 l RINH Resistance from CAn (n = 0, 1,2) to VCC to Set CAn = VCC See Test Circuit 2 l 10 kΩ RINL Resistance from CAn (n = 0, 1,2) to GND to Set CAn = GND See Test Circuit 2 l 10 kΩ RINF Resistance from CAn (n = 0, 1,2) to VCC or GND to Set CAn = Float See Test Circuit 2 l 2 VOL Low Level Output Voltage Sink Current = 3mA l 0 0.4 V tOF Output Fall Time VO = VIH(MIN) to VO = VIL(MAX), CB = 10pF to 400pF (Note 12) l 20 + 0.1CB 250 ns tSP Pulse Width of Spikes Suppressed by Input Filter l 0 50 ns IIN Input Leakage 0.1VCC ≤ VIN ≤ 0.9VCC l 1 µA CIN I/O Pin Capacitance (Note 8) l 10 pF CB Capacitive Load for Each Bus Line l 400 pF CCAn External Capacitive Load on Address Pin CAn (n=0, 1,2) l 10 pF Digital I/O 0.3VCC V V 0.15VCC 0.85VCC V V MΩ 2635fb LTC2635 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2635-HMI12/-HMI10/-HMI8/-HZ12/-HZ10/-HZ8 (VFS = 4.096V) SYMBOL PARAMETER CONDITIONS Settling Time VCC = 5V (Note 9) ±0.39% (±1LSB at 8 Bits) ±0.098% (±1LSB at 10 Bits) ±0.024% (±1LSB at 12 Bits) MIN TYP MAX UNITS AC Performance tS 3.9 4.3 5 Voltage Output Slew Rate 1 Capacitive Load Driving en µs µs µs V/µs 500 pF Glitch Impulse At Mid-Scale Transition 3 nV • s DAC-to-DAC Crosstalk 1 DAC Held at FS, 1 DAC Switched 0 to FS Multiplying Bandwidth External Reference 320 3 nV • s kHz Output Voltage Noise Density At f = 1kHz, External Reference At f = 10kHz, External Reference At f = 1kHz, Internal Reference At f = 10kHz, Internal Reference 180 160 250 230 nV/√Hz nV/√Hz nV/√Hz nV/√Hz Output Voltage Noise 0.1Hz to 10Hz, External Reference 0.1Hz to 10Hz, Internal Reference 0.1Hz to 200kHz, External Reference 0.1Hz to 200kHz, Internal Reference CREF = 0.1µF 35 50 680 750 µVP-P µVP-P µVP-P µVP-P TIMING Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V. (See Figure 1) (Note 13) LTC2635-HMI12/-HMI10/-HMI8/-HZ12/-HZ10/-HZ8 (VFS = 4.096V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fSCL SCL Clock Frequency l 0 400 kHz tHD(STA) Hold Time (Repeated) Start Condition l 0.6 µs tLOW Low Period of the SCL Clock Pin l 1.3 µs tHIGH High Period of the SCL Clock Pin l 0.6 µs tSU(STA) Set-Up Time for a Repeated Start Condition l 0.6 µs tHD(DAT) Data Hold Time l 0 0.9 µs tSU(DAT) Data Set-Up Time l 100 tr Rise Time of Both SDA and SCL Signals (Note 12) l 20+0.1CB 300 ns ns tf Fall Time of Both SDA and SCL Signals (Note 12) l 20+0.1CB 300 ns tSU(STO) Set-Up Time for Stop Condition l 0.6 µs tBUF Bus Free Time Between a Stop and Start Condition l 1.3 µs t1 Falling Edge of 9th Clock of the 3rd Input Byte to LDAC l 400 ns LDAC Low Pulse Width l 20 ns t2 High or Low Transition 2635fb 10 LTC2635 Electrical Characteristics Note 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2. All voltages are with respect to GND. Note 3. High temperatures degrade operating lifetimes. Operating lifetime is derated at temperatures greater than 105°C. Operating at temperatures above 90°C and with VCC > 4V requires VCC slew rates to be no greater than 73mV/ms. Note 4. Linearity and monotonicity are defined from code kL to code 2N – 1, where N is the resolution and kL is given by kL = 0.016 • (2N/ VFS), rounded to the nearest whole code. For VFS = 2.5V and N = 12, kL = 26 and linearity is defined from code 26 to code 4,095. For VFS = 4.096V and N = 12, kL = 16 and linearity is defined from code 16 to code 4,095. Note 7. Digital inputs at 0V or VCC. Note 8. Guaranteed by design and not production tested. Note 9. Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. Load is 2kΩ in parallel with 100pF to GND. Note 10. Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. Note 11. Maximum VIH = VCC(MAX) + 0.5V. Note 12. CB = capacitance of one bus line in pF. Note 13. All values refer to VIH = VIH(MIN) and VIL = VIL(MAX) levels. Note 14. Minimum VIL exceeds the Absolute Maximum rating. This condition won’t damage the IC, but could degrade performance. Note 5. Inferred from measurement at code 16 (LTC2635-12), code 4 (LTC2635-10) or code 1 (LTC2635-8), and at full-scale. Note 6. This IC includes current limiting that is intended to protect the device during momentary overload conditions. Junction temperature can exceed the rated maximum during current limiting. Continuous operation above the specified maximum operating junction temperature may impair device reliability. 2635fb 11 LTC2635 Typical Performance Characteristics TA = 25°C, unless otherwise noted. LTC2635-L12 (Internal Reference, VFS = 2.5V) Integral Nonlinearity (INL) 1.0 Differential Nonlinearity (DNL) 1.0 VCC = 3V 0.5 DNL (LSB) INL (LSB) 0.5 0 –0.5 –1.0 VCC = 3V 0 –0.5 1024 0 2048 CODE 3072 –1.0 4095 1024 0 2048 CODE 3072 2635 G01 INL vs Temperature 1.0 DNL (LSB) INL (LSB) 0 –1.0 –50 –25 25 50 75 100 125 150 TEMPERATURE (°C) DNL (POS) 0 DNL (NEG) –1.0 –50 –25 0 1.240 –50 –25 25 50 75 100 125 150 TEMPERATURE (°C) 0 2635 G04 Settling to ±1 LSB Rising 25 50 75 100 125 150 TEMPERATURE (°C) 2635 G05 Settling to ±1 LSB Falling 9th CLOCK OF 3rd DATA BYTE 3/4 SCALE TO 1/4 SCALE STEP VCC = 3V, VFS = 2.5V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS VOUT 1 LSB/DIV 4.4µs 3.3µs VOUT 1 LSB/DIV 1.250 1.245 2635 G03 SCL 5V/DIV VCC = 3V 1.255 –0.5 INL (NEG) 0 1.260 VCC = 3V 0.5 INL (POS) –0.5 Reference Output Voltage vs Temperature DNL vs Temperature VCC = 3V 0.5 2635 G02 VREF (V) 1.0 4095 1/4 SCALE TO 3/4 SCALE STEP VCC = 3V, VFS = 2.5V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 2µs/DIV 2635 G06 SCL 5V/DIV 9th CLOCK OF 3rd DATA BYTE 2µs/DIV 2635 G07 2635fb 12 LTC2635 Typical Performance Characteristics TA = 25°C, unless otherwise noted. LTC2635-H12 (Internal Reference, VFS = 4.096V) Integral Nonlinearity (INL) 1.0 Differential Nonlinearity (DNL) 1.0 VCC = 5V 0.5 DNL (LSB) INL (LSB) 0.5 0 –0.5 –1.0 VCC = 5V 0 –0.5 1024 0 2048 CODE 3072 –1.0 4095 0 1024 2048 CODE 3072 2635 G08 INL vs Temperature 1.0 VCC = 5V INL (POS) 2.068 VCC = 5V 0.5 0 INL (NEG) –0.5 –1.0 –50 –25 Reference Output Voltage vs Temperature DNL (POS) 0 DNL (NEG) –0.5 0 25 50 75 100 125 150 TEMPERATURE (°C) –1.0 –50 –25 0 2.028 –50 –25 25 50 75 100 125 150 TEMPERATURE (°C) 0 2635 G11 Settling to ±1 LSB Rising 25 50 75 100 125 150 TEMPERATURE (°C) 2635 G12 Settling to ±1 LSB Falling 3/4 SCALE TO 1/4 SCALE STEP VCC = 5V, VFS = 4.095V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 9th CLOCK OF 3rd DATA BYTE VOUT 1 LSB/DIV 3.9µs VOUT 1 LSB/DIV 2.048 2.038 2635 G10 SCL 5V/DIV VCC = 5V 2.058 VREF (V) INL (LSB) 0.5 2635 G09 DNL vs Temperature DNL (LSB) 1.0 4095 5µs 1/4 SCALE TO 3/4 SCALE STEP VCC = 5V, VFS = 4.095V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 2µs/DIV 2635 G13 SCL 5V/DIV 9th CLOCK OF 3rd DATA BYTE 2µs/DIV 2635 G14 2635fb 13 LTC2635 Typical Performance Characteristics TA = 25°C, unless otherwise noted. LTC2635-10 Integral Nonlinearity (INL) 1.0 Differential Nonlinearity (DNL) 1.0 VCC = 3V VFS = 2.5V INTERNAL REF 0.5 DNL (LSB) INL (LSB) 0.5 0 –0.5 –1.0 VCC = 3V VFS = 2.5V INTERNAL REF 0 –0.5 256 0 512 CODE 768 –1.0 1023 256 0 512 CODE 768 2635 G15 1023 2635 G16 LTC2635-8 Integral Nonlinearity (INL) 0.50 Differential Nonlinearity (DNL) 0.50 VCC = 3V VFS = 2.5V INTERNAL REF 0.25 DNL (LSB) INL (LSB) 0.25 0 –0.25 –0.50 VCC = 3V VFS = 2.5V INTERNAL REF 0 –0.25 0 64 128 CODE 192 –0.50 255 64 0 128 CODE 2635 G17 192 255 2635 G18 LTC2635 8 6 Current Limiting 0.20 VCC = 5V (LTC2635-H) VCC = 5V (LTC2635-L) VCC = 3V (LTC2635-L) 0.15 0.10 2 ΔVOUT (V) ΔVOUT (mV) 4 0 –2 –4 VCC = 5V (LTC2635-H) VCC = 5V (LTC2635-L) VCC = 3V (LTC2635-L) 2 0.05 0 –0.05 –0.01 –6 INTERNAL REF. CODE = MID-SCALE –8 –10 –30 Offset Error vs Temperature 3 OFFSET ERROR (mV) Load Regulation 10 –20 –10 0 10 IOUT (mA) 20 30 2635 G19 –0.15 –0.20 –30 INTERNAL REF. CODE = MID-SCALE –20 –10 0 10 IOUT (mA) 20 30 2635 G20 1 0 –1 –2 –3 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2635 G21 2635fb 14 LTC2635 Typical Performance Characteristics TA = 25°C, unless otherwise noted. LTC2635 Large-Signal Response Mid-Scale Glitch Impulse Power-On Reset Glitch LTC2635-L 9th CLOCK OF 3rd DATA BYTE SCL 5V/DIV VOUT 0.5V/DIV VCC 2V/DIV LTC2635-H12, VCC = 5V 3nV • s TYP VOUT 5mV/DIV ZERO SCALE VOUT 5mV/DIV LTC2635-L12, VCC = 3V 2.1nV • s TYP VFS = VCC = 5V 1/4 SCALE to 3/4 SCALE 2µs/DIV 2µs/DIV 2635 G23 200µs/DIV 2635 G22 2635 G24 Headroom at Rails vs Output Current Exiting Power-Down to Mid-Scale 5.0 VCC = 5V INTERNAL REFERENCE 5V SOURCING 4.5 4.0 3V (LTC2635-L) SOURCING 3.0 VCC 2V/DIV 9th CLOCK OF 3rd DATA BYTE LTC2635-H 2.5 2.0 1.5 DACs A-C IN POWER-DOWN MODE 0 1 2 3 LTC2635-H 4 5 6 IOUT (mA) 7 8 9 5µs/DIV 10 2635 G26 2635 G27 Exiting Power-Down for Hi-Z Option SWEEP SDA, SCL BETWEEN 0V AND VCC 1.4 9th CLOCK OF 3rd DATA BYTE SCL 5V/DIV 1.2 VCC = 5V 1.0 0.8 0 1 2 3 LOGIC VOLTAGE (V) HIGH-IMPEDANCE (POWER-DOWN) MODE DAC OUTPUT SET TO MID-SCALE VOUT 500mV/DIV VCC = 3V (LTC2635-L) 0.6 0.4 200µs/DIV 2635 G25 Supply Current vs Logic Voltage 1.6 LTC2635-L VOUT 0.5V/DIV 3V (LTC2635-L) SINKING 0.5 0 VOUT 0.5V/DIV 5V SINKING 1.0 ICC(mA) VOUT (V) 3.5 SCL 5V/DIV Power-On Reset to Mid-Scale 4 5 2635 G28 2µs/DIV 2635 G29 LTC2635-LMO, VCC = 3V DAC OUTPUT DRIVEN BY 1V SOURCE THROUGH 15k RESISTOR 2635fb 15 LTC2635 Typical Performance Characteristics TA = 25°C, unless otherwise noted. LTC2635 Noise Voltage vs Frequency 500 0 NOISE VOLTAGE (nV/√Hz) –2 –4 –8 –10 –12 VCC = 5V VREF(DC) = 2V VREF(AC) = 0.2VP-P CODE = FULL-SCALE –14 –16 –18 1k 10k 100k FREQUENCY (Hz) VCC = 5V CODE = MID-SCALE INTERNAL REF VCC = 5.5V 0.8 GAIN ERROR OF 4 CHANNELS 0.6 300 LTC2635-H 200 LTC2635-L 100 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 1M 0 100 2635 G31 1k 10k 100k FREQUENCY (Hz) –1.0 1M 1 1.5 2 2.5 3 3.5 4 4.5 REFERENCE VOLTAGE (V) 0.1Hz to 10Hz Voltage Noise 5 5.5 2635 G33 2634 G32 DAC-to-DAC Crosstalk (Dynamic) Gain Error vs Temperature 1.0 VCC = 5V, VFS = 2.5V CODE = MID-SCALE INTERNAL REF SCL 5V/DIV 9th CLOCK OF 3rd DATA BYTE GAIN ERROR (%FSR) dB –6 400 Gain Error vs Reference Input 1.0 GAIN ERROR (%FSR) Mulitplying Bandwidth 2 1 DAC SWITCH 0-FS 2V/DIV 10µV/DIV VOUT 2mV/DIV LTC2635-H12, VCC = 5V 3nV • s TYPICAL CREF = 0.1µF 2µs/DIV 1s/DIV 2635 G34 2635 G35 0.5 0 –0.5 –1.0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2635 G36 2635fb 16 LTC2635 Pin Functions (MSOP/QFN) VCC (Pin 1/Pin 16): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V (LTC2635-L) or 4.5V ≤ VCC ≤ 5.5V (LTC2635-H). Bypass to GND with a 0.1µF capacitor. VOUTA to VOUTD (Pins 2, 3, 8, 9/Pins 1, 2, 11, 12): DAC Analog Voltage Outputs. LDAC (Pin 3, QFN Only): Asynchronous DAC Update. A falling edge on this input after four bytes (slave address byte plus three data bytes) have been written into the part immediately updates the DAC registers with the contents of the input registers (similar to a software update). A low on this input without a complete 32-bit (four bytes including the slave address) data write transfer to the part does not update the DAC output. A low on the LDAC pin powers up the DACs. A software power down command is ignored if LDAC is low. CA0 (Pin 4/Pin 4): Chip Address Bit 0. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (see Tables 1 and 2). SCL (Pin 5/Pin 5): Serial Clock Input Pin. Data is shifted into the SDA pin at the rising edges of the clock. This high-impedance pin requires a pull-up resistor or current source to VCC. SDA (Pin 6/Pin 8): Serial Data Bidirectional Pin. Data is shifted into the SDA pin and acknowledged by the SDA pin. This pin is high impedance while data is shifted in. Open drain N-channel output during acknowledgment. SDA requires a pull-up resistor or current source to VCC. REF (Pin 7/Pin 10): Reference Voltage Input or Output. When External Reference mode is selected, REF is an input (1V ≤ VREF ≤ VCC) where the voltage supplied sets the full-scale DAC output voltage. When Internal Reference is selected, the 10ppm/°C 1.25V (LTC2635-L) or 2.048V (LTC2635-H) internal reference (half full-scale) is available at the pin. This output may be bypassed to GND with up to 10µF, and must be buffered when driving an external DC load current. DNC (Pins 6, 15, QFN Only): Do Not Connect These Pins. CA2 (Pin 7, QFN Only): Chip Address Bit 2. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (see Table 1). CA1 (Pin 9, QFN Only): Chip Address Bit 1. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (see Table 1). GND (Pin 10, Exposed Pad Pin 11/Pin 14, Exposed Pad Pin 17): Ground. Must be soldered to PCB ground. REFLO (Pin 13, QFN Only): Reference Low Pin. The voltage at this pin sets the zero-scale voltage of all DACs. This pin must be tied to GND. 2635fb 17 LTC2635 Block Diagram INTERNAL REFERENCE GND SWITCH REF VREF VCC REGISTER REGISTER DAC A REGISTER VOUTA REGISTER (REFLO) DAC D VREF (LDAC) DECODE CA0 (CA1) (CA2) I2C ADDRESS DECODE ( ) QFN PACKAGE ONLY REGISTER REGISTER REGISTER DAC B REGISTER VREF VOUTB VOUTD DAC C VOUTC POWER-ON RESET SCL I2C INTERFACE SDA 2635 BD 2635fb 18 LTC2635 TEST CIRCUITS Test Circuits for I2C Digital I/O (See Electrical Characteristics) Test Circuit 1 Test Circuit 2 VDD 100Ω CAn RINH/RINL/RINF CAn VIH(CAn)/VIL(CAn) 2635 TC01 2635 TC02 GND TIMING Diagrams SDA tf tLOW tSU(DAT) tr tHD(STA) tr tSP tBUF tr SCL tHD(STA) S tHD(DAT) tHIGH tSU(STA) Sr ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS tSU(STO) P S 2635 F01 Figure 1. I2C Timing 2635fb 19 LTC2635 TIMING Diagrams SLAVE ADDRESS 1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE START SDA A6 A5 A4 A3 A2 A1 A0 W ACK C3 C2 C1 C0 A3 A2 A1 A0 ACK SCL 1 2 3 4 5 6 7 8 2 3 5 6 7 8 9 1 4 9 ACK 1 2 3 4 5 6 7 8 9 1 2 3 4 X X X X ACK 5 6 7 8 9 t1 t2 LDAC 2635 F02a Figure 2a. Typical LTC2635 Write Transaction 9TH CLOCK OF 3RD DATA BYTE SCL t1 LDAC 2635 F02b Figure 2b. LTC2635 LDAC Timing (QFN Package Only) 2635fb 20 LTC2635 OPERATION The LTC2635 is a family of quad voltage output DACs in 16-pin QFN and 10-lead MSOP packages. Each DAC can operate rail-to-rail using an external reference, or with its full-scale voltage set by an integrated reference. Eighteen combinations of accuracy (12-, 10-, and 8-bit), power-on reset value (zero-scale, mid-scale in internal reference mode, or mid-scale in external reference mode), DAC power-down output load (high impedance or 200kΩ), and full-scale voltage (2.5V or 4.096V) are available. The LTC2635 is controlled using a 2-wire I2C interface. Power-On Reset The LTC2635-HZ/-LZ clear the output to zero-scale when power is first applied, making system initialization consistent and repeatable. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC2635 contains circuitry to reduce the power-on glitch: the analog output typically rises less than 5mV above zeroscale during power on. In general, the glitch amplitude decreases as the power supply ramp time is increased. See “Power-On Reset Glitch” in the Typical Performance Characteristics section. The LTC2635-HMI/-LMI/-LMX provide an alternative reset, setting the output to mid-scale when power is first applied. The LTC2635-LMI and LTC2635-HMI power up in internal reference mode, with the output set to a mid-scale voltage of 1.25V and 2.048V, respectively. The LTC2635-LMX power-up in external reference mode, with the output set to mid-scale of the external reference. The LTC2635-LMO powers up in internal reference mode with all the DAC channels placed in the high-impedance state (powered-down). Input and DAC registers are set to the mid-scale code, and only the internal reference is powered up, causing supply current to be typically 100µA upon power up. Default reference mode selection is described in the Reference Modes section. Power Supply Sequencing The voltage at REF (Pin 10 – QFN, Pin 7 – MSOP) must be kept within the range –0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum Ratings). Particular care should be taken to observe these limits during power supply turnon and turn-off sequences, when the voltage at VCC is in transition. Transfer Function The digital-to-analog transfer function is k VOUT(IDEAL) = ( VREF – VREFLO ) + VREFLO 2N where k is the decimal equivalent of the binary DAC input code, N is the resolution, and VREF is either 2.5V (LTC2635LMI/-LMX/-LMO/-LZ) or 4.096V (LTC2635-HMI/-HZ) when in Internal Reference mode, and the voltage at REF when in External Reference mode. I2C Serial Interface The LTC2635 communicates with a host using the standard 2-wire I2C interface. The timing diagrams (Figures 1 and 2) show the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. The value of these pull-up resistors is dependent on the power supply and can be obtained from the I2C specifications. For an I2C bus operating in the fast mode, an active pull-up will be necessary if the bus capacitance is greater than 200pF. The LTC2635 is a receive-only (slave) device. The master can write to the LTC2635. The LTC2635 will not acknowledge (NAK) a read request from the master. START (S) and STOP (P) Conditions When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a communication to a slave device by transmitting a START condition. A START condition is generated by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP condition. A STOP condition is generated by transitioning SDA from low to high while SCL is high. The bus is then free for communication with another I2C device. 2635fb 21 LTC2635 OPERATION Acknowledge Table 1. Slave Address Map (QFN Package) The Acknowledge (ACK) signal is used for handshaking between the master and the slave. An ACK (active LOW) generated by the slave lets the master know that the latest byte of information was properly received. The ACK related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the ACK clock pulse. The slave-receiver must pull down the SDA bus line during the ACK clock pulse so that it remains a stable LOW during the HIGH period of this clock pulse. The LTC2635 responds to a write by a master in this manner but does not acknowledge a read operation; in that case, SDA is retained HIGH during the period of the ACK clock pulse. CA2 CA1 GND GND Chip Address The state of pins CA0, CA1 and CA2 (CA1 and CA2 are only available on the QFN package) determines the slave address of the part. These pins can be each set to any one of three states: VCC, GND or float. This results in 27 (QFN Package) or 3 (MSOP Package) selectable addresses for the part. The slave address assignments are shown in Tables 1 and 2. In addition to the address selected by the address pins, the part also responds to a global address. This address allows a common write to all LTC2635 parts to be accomplished using one 3-byte write transaction on the I2C bus. The global address, listed at the end of Tables 1 and 2, is a 7-bit hardwired address not selectable by CA0, CA1 or CA2. If another address is required, please consult the factory. The maximum capacitive load allowed on the address pins (CA0, CA1 and CA2) is 10pF, as these pins are driven during address detection to determine if they are floating. CA0 A6 A5 A4 A3 A2 A1 A0 GND GND 0 0 1 0 0 0 0 GND FLOAT 0 0 1 0 0 0 1 GND GND VCC 0 0 1 0 0 1 0 GND FLOAT GND 0 0 1 0 0 1 1 GND FLOAT FLOAT 0 1 0 0 0 0 0 GND FLOAT VCC 0 1 0 0 0 0 1 GND VCC GND 0 1 0 0 0 1 0 GND VCC FLOAT 0 1 0 0 0 1 1 GND VCC VCC 0 1 1 0 0 0 0 FLOAT GND GND 0 1 1 0 0 0 1 FLOAT GND FLOAT 0 1 1 0 0 1 0 FLOAT GND VCC 0 1 1 0 0 1 1 FLOAT FLOAT GND 1 0 0 0 0 0 0 FLOAT FLOAT FLOAT 1 0 0 0 0 0 1 FLOAT FLOAT VCC 1 0 0 0 0 1 0 FLOAT VCC GND 1 0 0 0 0 1 1 FLOAT VCC FLOAT 1 0 1 0 0 0 0 FLOAT VCC VCC 1 0 1 0 0 0 1 VCC GND GND 1 0 1 0 0 1 0 VCC GND FLOAT 1 0 1 0 0 1 1 VCC GND VCC 1 1 0 0 0 0 0 VCC FLOAT GND 1 1 0 0 0 0 1 VCC FLOAT FLOAT 1 1 0 0 0 1 0 VCC FLOAT VCC 1 1 0 0 0 1 1 VCC VCC GND 1 1 1 0 0 0 0 VCC VCC FLOAT 1 1 1 0 0 0 1 VCC VCC VCC GLOBAL ADDRESS 1 1 1 0 0 1 0 1 1 1 0 0 1 1 Table 2. Slave Address Map (MSOP Package) CA0 A6 A5 A4 A3 A2 A1 A0 GND 0 0 1 0 0 0 0 FLOAT 0 0 1 0 0 0 1 VCC 0 0 1 0 0 1 0 GLOBAL ADDRESS 1 1 1 0 0 1 1 2635fb 22 LTC2635 OPERATION Write Word Protocol The master initiates communication with the LTC2635 with a START condition and a 7-bit slave address followed by the Write bit (W) = 0. The LTC2635 acknowledges by pulling the SDA pin low at the 9th clock if the 7-bit slave address matches the address of the part (set by CA0, CA1 or CA2) or the global address. The master then transmits three bytes of data. The LTC2635 acknowledges each byte of data by pulling the SDA line low at the 9th clock of each data byte transmission. After receiving three complete bytes of data, the LTC2635 executes the command specified in the 24-bit input word. If more than three data bytes are transmitted after a valid 7-bit slave address, the LTC2635 does not acknowledge (NAK) the extra bytes of data (SDA is high during the 9th clock). The format of the three data bytes is shown in Figure 3. The first byte of the input word consists of the 4-bit command, followed by the 4-bit DAC address. The next two bytes contain the 16-bit data word, which consists of the 12-, 10- or 8-bit input code, MSB to LSB, followed by 4, 6 or 8 don’t-care bits (LTC2635-12, -10 and -8, respectively). A typical LTC2635 write transaction is shown in Figure 4. The command bit assignments (C3-C0) and address (A3A0) assignments are shown in Tables 3 and 4. The first four commands in the table consist of write and update operations. A write operation loads a 16-bit data word from the 32-bit shift register into the input register. In an update operation, the data word is copied from the input register to the DAC register. Once copied into the DAC register, the data word becomes the active 12-, 10-, or 8-bit input code, and is converted to an analog voltage at the DAC output. Write to and Update combines the first two commands. The Update operation also powers up the DAC if it had been in power-down mode. The data path and registers are shown in the Block Diagram. Table 3. Command Codes COMMAND* C3 C2 C1 C0 0 0 0 0 Write to Input Register n 0 0 0 1 Update (Power Up) DAC Register n 0 0 1 0 Write to Input Register n, Update (Power Up) All 0 0 1 1 Write to and Update (Power Up) DAC Register n 0 1 0 0 Power Down n 0 1 0 1 Power Down Chip (All DAC’s and Reference) 0 1 1 0 Select Internal Reference (Power Up Reference) 0 1 1 1 Select External Reference (Power Down Internal Reference) 1 1 1 1 No Operation *Command codes not shown are reserved and should not be used. Table 4. Address Codes ADDRESS (n)* A3 A2 A1 A0 0 0 0 0 DAC A 0 0 0 1 DAC B 0 0 1 0 DAC C 0 0 1 1 DAC D 1 1 1 1 ALL DACs * Address codes not shown are reserved and should not be used. Reference Modes For applications where an accurate external reference is either not available, or not desirable due to limited space, the LTC2635 has a user-selectable, integrated reference. The integrated reference voltage is internally amplified by 2x to provide the full-scale DAC output voltage range. The LTC2635-LMI/-LMX/-LMO/-LZ provides a full-scale output of 2.5V. The LTC2635-HMI/-HZ provides a full-scale output of 4.096V. The internal reference can be useful in applications where the supply voltage is poorly regulated. Internal Reference mode can be selected by using command 0110b, and is the power-on default for LTC2635-HZ/-LZ, as well as for LTC2635-HMI/-LMI/-LMO. 2635fb 23 LTC2635 OPERATION Write Word Protocol for LTC2635 S W SLAVE ADDRESS ACK 1ST DATA BYTE ACK 2ND DATA BYTE ACK 3RD DATA BYTE ACK P D1 D0 INPUT WORD Input Word (LTC2635-12) C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 1ST DATA BYTE D8 D7 D6 D5 D4 D3 D2 2ND DATA BYTE X X X X X X X X X X 3RD DATA BYTE Input Word (LTC2635-10) C3 C2 C1 C0 A3 A2 A1 A0 D9 D8 D7 1ST DATA BYTE D6 D5 D4 D3 D2 D1 D0 X 2ND DATA BYTE X X 3RD DATA BYTE Input Word (LTC2635-8) C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 1ST DATA BYTE D4 D3 D2 D1 D0 2ND DATA BYTE X X X X X 3RD DATA BYTE 2635 F03 Figure 3. Command and Data Input Format The 10ppm/°C, 1.25V (LTC2635-LMI/-LMX/-LMO/-LZ) or 2.048V (LTC2635-HMI/-HZ) internal reference is available at the REF pin. Adding bypass capacitance to the REF pin will improve noise performance; and up to 10µF can be driven without oscillation. This output must be buffered when driving an external DC load current. Alternatively, the DAC can operate in External Reference mode using command 0111b. In this mode, an input voltage supplied externally to the REF pin provides the reference (1V ≤ VREF ≤ VCC) and the supply current is reduced. The external reference voltage supplied sets the full-scale DAC output voltage. External Reference mode is the power-on default for LTC2635-LMX. The reference mode of LTC2635-HZ/-LZ/-HMI/-LMI/-LMO (Internal Reference power-on default), can be changed by software command after power up. The same is true for LTC2635-LMX (External Reference power-on default). Power-Down Mode For power-constrained applications, power-down mode can be used to reduce the supply current whenever less than four DAC outputs are needed. When in power-down, the buffer amplifiers, bias circuits, and integrated reference circuits are disabled, and draw essentially zero current. The DAC amplifier outputs are put into a high-impedance state, and the output pins are passively pulled to ground through individual 200k resistors (LTC2635-LMI/-LMX/ -LZ/-HMI/-HZ). For the LTC2635-LMO options, the output pins are not passively pulled to ground, but are also placed in a high-impedance state (open-circuited state) during power-down, typically drawing less than 0.1µA. The LTC2635-LMO options power-up with all DAC outputs in this high-impedance state. They remain that way until given a software or hardware update command. For all LTC2635 options, input- and DAC-register contents are not disturbed during power-down. 2635fb 24 LTC2635 Operation Any channel or combination of channels can be put into power-down mode by using command 0100b in combination with the appropriate DAC address, (n). The supply current is reduced approximately 20% for each DAC powered down. The integrated reference is automatically powered down when external reference is selected using command 0111b. In addition, all the DAC channels and the integrated reference together can be put into power-down mode using Power Down Chip command 0101b. When the integrated reference is in power-down mode, the REF pin becomes high impedance (typically > 1GΩ). For all powerdown commands the 16-bit data word is ignored. Normal operation resumes after executing any command that includes a DAC update, (as shown in Table 1) or pulling the asynchronous LDAC pin low (QFN package only). The selected DAC is powered up as its voltage output is updated. When a DAC which is in a powered-down state is powered up and updated, normal settling is delayed. If less than four DACs are in a powered-down state prior to the update command, the power-up delay time is 10µs. However, if all four DACs and the integrated reference are powered down, then the main bias generation circuit block has been automatically shut down in addition to the DAC amplifiers and reference buffers. In this case, the power up delay time is 12µs. The power-up of the integrated reference depends on the command that powered it down. If the reference is powered down using the Select External Reference Command (0111b), then it can only be powered back up using Select Internal Reference Command (0110b). However, if the reference was powered down using Power Down Chip Command (0101b), then in addition to Select Internal Reference Command (0110b), any command (in software or using the LDAC pin) that powers up the DACs will also power up the integrated reference. Voltage Output The LTC2635’s integrated rail-to-rail amplifier has guaranteed load regulation when sourcing or sinking up to 10mA at 5V, and 5mA at 3V. Load regulation is a measure of the amplifier’s ability to maintain the rated voltage accuracy over a wide range of load current. The measured change in output voltage per change in forced load current is expressed in LSB/mA. DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to Ω. The amplifier’s DC output impedance is 0.1Ω when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 50Ω typical channel resistance of the output devices (e.g., when sinking 1mA, the minimum output voltage is 50Ω • 1mA, or 50mV). See the graph Headroom at Rails vs. Output Current in the Typical Performance Characteristics section. The amplifier is stable driving capacitive loads of up to 500pF. Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Since the analog output of the DAC cannot go below ground, it may limit for the lowest codes as shown in Figure 5b. Similarly, limiting can occur near full-scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC, as shown in Figure 5c. No full-scale limiting can occur if VREF is less than VCC – FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. Board Layout The PC board should have separate areas for the analog and digital sections of the circuit. A single, solid ground plane should be used, with analog and digital signals carefully routed over separate areas of the plane. This keeps digital signals away from sensitive analog signals and minimizes the interaction between digital ground currents and the analog section of the ground plane. The resistance from the LTC2635 GND pin to the ground plane should be as low as possible. Resistance here will add directly to the effective DC output impedance of the device (typically 0.1Ω). Note that the LTC2635 is no more susceptible to 2635fb 25 LTC2635 OPERATION this effect than any other parts of this type; on the contrary, it allows layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. analog ground, digital ground, and power ground. When the LTC2635 is sinking large currents, this current flows out the ground pin and directly to the power ground trace without affecting the analog ground plane voltage. Another technique for minimizing errors is to use a separate power ground return trace on another board layer. The trace should run between the point where the power supply is connected to the board and the DAC ground pin. Thus the DAC ground pin becomes the common point for It is sometimes necessary to interrupt the ground plane to confine digital ground currents to the digital portion of the plane. When doing this, make the gap in the plane only as long as it needs to be to serve its purpose and ensure that no traces cross over the gap. SLAVE ADDRESS COMMAND/ADDRESS MS DATA A6 A5 A4 A3 A2 A1 A0 W C3 C2 C1 C0 A3 A2 A1 A0 SDA A6 A5 A4 A3 A2 A1 A0 W ACK C3 C2 C1 C0 A3 A2 A1 A0 ACK SCL 1 2 3 4 5 6 7 8 2 3 5 6 7 8 LS DATA D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X STOP START 9 1 4 9 ACK 1 2 3 4 5 6 7 8 9 ACK 1 2 3 4 5 6 VOUT 7 8 9 FULL-SCALE VOLTAGE ZERO-SCALE VOLTAGE X = DON’T CARE 2635 F04 Figure 4. Typical LTC2635 Input Waveform—Programming DAC Output for Full-Scale 2635fb 26 LTC2635 Operation VREF = VCC POSITIVE FSE VREF = VCC OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE OUTPUT VOLTAGE 0V NEGATIVE OFFSET 2635 F05 (c) 0 2,048 INPUT CODE 4,095 (a) 0V INPUT CODE (b) Figure 5. Effects of Rail-to-Rail On a DAC Transfer Curve (Shown for 12 Bits). (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero (c) Effect of Positive Full-Scale Error for Codes Near Full-Scale 2635fb 27 LTC2635 APPLICATION INFORMATION Voltage Margining Application with LTC3850 (1.2V ±5%) –LTC2635– LMO Option Only 0.1µF VIN 6.5V TO 14V 4.7µF 2.2Ω 100k 0.1µF INTVCC PGOOD VIN ILIM TG1 10k 0.1µF BOOST1 FREQ 2.2µH 0.008Ω VOUT 1.2V ±5% SW1 1nF LTC3850EUF 3.32k BG1 PGND ITH1 500kHz 1nF TK/SS1 10k 1nF RUN1 MODE/PLLIN 100pF 10Ω SENSE+ 10Ω SENSE– 10nF VFB1 SGND 15pF 5V VOUT 1.26V 1.2V 1.14V DAC D OUTPUT 0.5V 0.8V 1.1V DAC CODE 819 1311 1802 7 VCC REF 0.1µF 63.4k 2635 TA02 20k 1 LTC2635CMSE-LMOI2 2 DAC A 9 DAC D 10k 15k 0.22µF 3 TO I2C BUS 4 5 6 DAC B CAO 8 DAC C GND 10 SCL SDA 2635 TA02 2635fb 28 LTC2635 Package Description UD Package 16-Lead Plastic QFN (3mm × 3mm) (Reference LTC DWG # 05-08-1691) 0.70 p0.05 3.50 p 0.05 1.45 p 0.05 2.10 p 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 p0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 p 0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD PIN 1 NOTCH R = 0.20 TYP OR 0.25 s 45o CHAMFER R = 0.115 TYP 0.75 p 0.05 15 PIN 1 TOP MARK (NOTE 6) 16 0.40 p 0.10 1 1.45 p 0.10 (4-SIDES) 2 (UD16) QFN 0904 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 p 0.05 0.50 BSC 2635fb 29 LTC2635 Package Description MSE Package 10-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1664 Rev D) BOTTOM VIEW OF EXPOSED PAD OPTION 1.88 p 0.102 (.074 p .004) 5.23 (.206) MIN 0.889 p 0.127 (.035 p .005) 1.68 p 0.102 (.066 p .004) 1 0.05 REF 10 3.00 p 0.102 (.118 p .004) (NOTE 3) DETAIL “B” CORNER TAIL IS PART OF DETAIL “B” THE LEADFRAME FEATURE. FOR REFERENCE ONLY NO MEASUREMENT PURPOSE 10 9 8 7 6 DETAIL “A” 0o – 6o TYP 1 2 3 4 5 GAUGE PLANE 0.53 p 0.152 (.021 p .006) DETAIL “A” 0.18 (.007) 0.497 p 0.076 (.0196 p .003) REF 3.00 p 0.102 (.118 p .004) (NOTE 4) 4.90 p 0.152 (.193 p .006) 0.254 (.010) 0.29 REF 1.68 (.066) 3.20 – 3.45 (.126 – .136) 0.50 0.305 p 0.038 (.0197) (.0120 p .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 1.88 (.074) SEATING PLANE 0.86 (.034) REF 1.10 (.043) MAX 0.17 – 0.27 (.007 – .011) TYP 0.50 (.0197) BSC NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 6. EXPOSED PAD DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED 0.254mm (.010") PER SIDE. 0.1016 p 0.0508 (.004 p .002) MSOP (MSE) 0210 REV D 2635fb 30 LTC2635 Revision History REV DATE DESCRIPTION PAGE NUMBER A 12/09 Revise QFN pin names 2, 17 Minor text edit in Operations section 21, 24 B 06/10 Revised Note 3 in the Electrical Characteristics section 11 Added Typical Application drawing and revised Related Parts List 32 2635fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 31 LTC2635 Typical APPLICATION Voltage Margining Application with LTC3850 (1.2V ±5%) –LTC2635– LMO Option Only 0.1µF VIN 6.5V TO 14V 4.7µF 2.2Ω 100k 0.1µF INTVCC PGOOD VIN ILIM TG1 0.1µF 10k FREQ BOOST1 2.2µH 0.008Ω VOUT 1.2V ±5% SW1 3.32k 1nF BG1 LTC3850EUF PGND ITH1 SENSE+ MODE/PLLIN SENSE– 10Ω RUN1 1nF 10k 500kHz 100pF TK/SS1 10nF 1nF 10Ω VFB1 SGND 15pF 5V 7 0.1µF VOUT 1.26V 1.2V 1.14V DAC D OUTPUT 0.5V 0.8V 1.1V REF 2 DAC CODE 819 1311 1802 LTC2635CMSE-LMOI2 DAC A VCC 63.4k 1 2635 TA02 9 DAC D 10k 15k 20k 0.22µF 3 TO I2C BUS 4 5 6 DAC B CAO 8 DAC C GND 10 SCL SDA 2635 TA03 Related Parts PART NUMBER LTC2654/LTC2655 DESCRIPTION Quad 16-/12 Bit, SPI/I2C VOUT DACs with 10ppm/°C Maximum Reference LTC2609/LTC2619/ Quad 16-/14-/12-Bit VOUT DACs with I2C Interface LTC2629 LTC2604/LTC2614/ Quad 16-/14-/12-Bit, SPI VOUT DACs with External Reference LTC2624 LTC2634 Quad 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference LTC2656/LTC2657 LTC2636/LTC2637 LTC2630/LTC2631 LTC2640 LTC1664 Octal 16-/12 Bit, SPI/I2C VOUT DACs with 10ppm/°C Maximum Reference Octal 12-/10-/8-Bit, SPI/I2C VOUT DACs with 10ppm/°C Reference Single 12-/10-/8-Bit, SPI/ I2C VOUT DACs with 10ppm/°C Reference Single 12-/10-/8-Bit, SPI VOUT DACs with 10ppm/°C Reference Quad 10-Bit, Serial VOUT DAC COMMENTS ±4LSB INL Maximum at 16 Bits and ±2mV Offset Error, Rail-to-Rail Output, 20-Lead 4mm × 4mm QFN and 16-Lead Narrow SSOP Packages 250µA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output with Separate VREF Pins for Each DAC 250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, 16-Lead SSOP Package 125µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode, Rail-to-Rail Output, 16-Pin 3mm × 3mm QFN and 10-Lead MSOP Packages ±4LSB INL Maximum at 16 Bits and ±2mV Offset Error, Rail-to-Rail Output, 20-Lead 4mm × 5mm QFN and 16-Lead TSSOP Packages 125µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode, Rail-to-Rail Output, 14-Lead 4mm × 3mm DFN and 16-Lead MSOP Packages 180µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, Rail-to-Rail Output, SC70 (LTC2630)/ThinSOT™ (LTC2631) Packages 180µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode, Rail-to-Rail Output, ThinSOT Package VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output, 16-Pin Narrow SSOP 2635fb 32 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LT 0610 REV B • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2009