Davicom DM9106EP 10/100 mbps 3-port ethernet switch controller with pci interface Datasheet

DAVICOM Semiconductor, Inc.
DM9106
10/100 Mbps 3-port Ethernet Switch Controller
with PCI Interface
DATA SHEET
Preliminary
Version: DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
1.
GENERAL DESCRIPTION............................................................................................... 8
2.
BLOCK DIAGRAM........................................................................................................... 8
3.
FEATURES ...................................................................................................................... 9
4.
PIN CONFIGURATION : 128 PIN LQFP........................................................................ 10
5.
PIN DESCRIPTION ........................................................................................................ 11
5.1 PCI BUS INTERFACE ...................................................................................................................................... 11
5.2 P2 MII / RMII / REVERSE MII INTERFACES ...................................................................................................... 12
5.2.1 MII Interfaces ....................................................................................................................................... 12
5.2.2 RMII Interfaces..................................................................................................................................... 13
5.2.3 Reverse MII Interfaces......................................................................................................................... 13
5.3 EEPROM INTERFACES ................................................................................................................................. 13
5.4 LED PINS ..................................................................................................................................................... 14
5.5 CLOCK INTERFACE ........................................................................................................................................ 14
5.6 NETWORK INTERFACE.................................................................................................................................... 14
5.7 MISCELLANEOUS PINS ................................................................................................................................... 15
5.8 POWER PINS ................................................................................................................................................. 15
5.9 STRAP PINS TABLE ........................................................................................................................................ 16
5.9.1 Strap pin in 3-port mode ...................................................................................................................... 16
DESCRIPTION ...................................................................................................................................................... 16
5.9.2 strap pin in 2-port mode....................................................................................................................... 17
DESCRIPTION ...................................................................................................................................................... 17
6.
REGISTER SET ............................................................................................................. 18
6.1 PCI CONFIGURATION REGISTERS ................................................................................................................... 18
6.1.1 Identification ID (xxxxxx00H - PCIID) .................................................................................................. 19
6.1.2 Command & Status (xxxxxx04H - PCICS) .......................................................................................... 19
6.1.3 Revision ID (xxxxxx08H - PCIRV) ....................................................................................................... 20
6.1.4 Miscellaneous Function (xxxxxx0cH - PCILT) ..................................................................................... 21
6.1.5 I/O Base Address (xxxxxx10H - PCIIO)............................................................................................... 21
2
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
6.1.6 Memory Mapped Base Address (xxxxxx14H - PCIMEM).................................................................... 21
6.1.7 Subsystem Identification (xxxxxx2cH - PCISID).................................................................................. 22
6.1.8 Capabilities Pointer (xxxxxx34H - Cap _Ptr) ....................................................................................... 22
6.1.9 Interrupt & Latency Configuration (xxxxxx3cH - PCIINT) .................................................................... 22
6.1.10 Device Specific Configuration Register (xxxxxx40H- PCIUSR) ........................................................ 22
6.1.11 Power Management Register (xxxxxx50H~PCIPMR) ....................................................................... 23
6.1.12 Power Management Control/Status (xxxxxx54H~PMCSR)............................................................... 24
6.2 PCI CONTROL AND STATUS REGISTERS (CR) ................................................................................................ 25
6.2.1 System Control Register (CR0) ........................................................................................................... 26
6.2.2 Transmit Descriptor Poll Demand (CR1) ............................................................................................. 26
6.2.3 Receive Descriptor Poll Demand (CR2) .............................................................................................. 26
6.2.4 Receive Descriptor Base Address (CR3) ............................................................................................ 27
6.2.5 Transmit Descriptor Base Address (CR4) ........................................................................................... 27
6.2.6 Network Status Report Register (CR5) ............................................................................................... 27
6.2.7 Network Operation Mode Register (CR6)............................................................................................ 29
6.2.8 Interrupt Mask Register (CR7)............................................................................................................. 31
6.2.9 Reserved (CR8) ................................................................................................................................... 32
6.2.10 Management Access Register (CR9) ................................................................................................ 32
6.2.11 Reserved (CR10) ............................................................................................................................... 33
6.2.12 Reserved (CR11) ............................................................................................................................... 33
6.2.13 Reserved (CR12) ............................................................................................................................... 33
6.2.14 (Reserved CR13) ............................................................................................................................... 33
6.2.15 (Reserved CR14) ............................................................................................................................... 33
6.2.16 Checksum Offload Control Register (CR15) ..................................................................................... 33
6.12.17 Switch Control Register (CR16)....................................................................................................... 33
6.2.18 Per Port Index Register (CR17)......................................................................................................... 34
6.2.19 Per Port Control Register (CR18) ...................................................................................................... 34
6.2.20 Per Port Status Data Register (CR19) ............................................................................................ 37
6.2.21 Per Port VLAN Tag Byte Register (CR20)......................................................................................... 39
6.2.22 Per Port MIB counter Index Register (CR21).................................................................................. 40
6.2.23 MIB counter Data Register (CR22).................................................................................................... 41
6.2.24 VLAN priority Map Register (CR23)................................................................................................... 41
6.2.25 Ethernet Address Data 1,2 Register (CR22,CR23)...................................................................... 42
6.2.26 Port-based VLAN mapping table register 0 (CR24) .......................................................................... 42
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
3
DM9106
3-port switch with PCI Interface
6.2.27 Port-based VLAN mapping table register 1 (CR25) .......................................................................... 43
6.2.28 Port-based VLAN mapping table register 2 (CR26) .......................................................................... 43
6.2.29 Port-based VLAN mapping table register 3 (CR27) .......................................................................... 43
6.2.30 TOS Priority Map Register 0 (CR28) ................................................................................................. 43
6.2.31 TOS Priority Map Register 1 (CR29) ................................................................................................. 44
6.2.32 TOS Priority Map Register 2 (CR30) ................................................................................................. 44
6.2.33 TOS Priority Map Register 3 (CR31) ................................................................................................. 45
6.3 DESCRIPTOR LIST .......................................................................................................................................... 45
6.3.1 Receive Descriptor Format .................................................................................................................. 45
6.3.1.1 Receive Status Register (RDES0) ................................................................................................. 46
6.3.1.2 Receive Descriptor Control and Buffer Size Register (RDES1) .................................................... 46
6.3.1.3 Buffer Starting Address Register (RDES2) .................................................................................... 46
6.3.1.4 Next descriptor Address Register (RDES3)................................................................................... 46
6.3.2 Transmit Descriptor Format ................................................................................................................. 47
6.3.2.1 Transmit Status Register (TDES0)................................................................................................. 47
6.3.2.2 Transmit buffer control and buffer size Register (TDES1)............................................................. 47
6.3.2.3 Next descriptor Address Register (TDES3) ................................................................................... 48
7.
PCI MODE EEPROM FORMAT ..................................................................................... 49
8.
PHY REGISTERS .......................................................................................................... 52
8.1 BASIC MODE CONTROL REGISTER (BMCR) – 00H......................................................................................... 53
8.2 BASIC MODE STATUS REGISTER (BMSR) – 01H............................................................................................ 54
8.3 PHY ID IDENTIFIER REGISTER #1 (PHYID1) – 02H ........................................................................................ 55
8.4 PHY ID IDENTIFIER REGISTER #2 (PHYID2) – 03H ........................................................................................ 55
8.5 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (ANAR) – 04H .................................................................... 56
8.6 AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (ANLPAR) – 05H ...................................................... 57
8.7 AUTO-NEGOTIATION EXPANSION REGISTER (ANER)- 06H .............................................................................. 58
8.8 DAVICOM SPECIFIED CONFIGURATION REGISTER (DSCR) – 10H ................................................................. 58
8.9 DAVICOM SPECIFIED CONFIGURATION AND STATUS REGISTER (DSCSR) – 11H ........................................... 60
8.10 10BASE-T CONFIGURATION/STATUS (10BTCSR) – 12H ............................................................................ 61
8.11 POWER DOWN CONTROL REGISTER (PWDOR) – 13H.................................................................................. 62
8.12 (SPECIFIED CONFIG) REGISTER – 14H .......................................................................................................... 62
8.13 DAVICOM SPECIFIED RECEIVE ERROR COUNTER REGISTER (RECR) – 16H................................................ 63
8.14 DAVICOM SPECIFIED DISCONNECT COUNTER REGISTER (DISCR) – 17H.................................................... 63
4
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
9.
FUNCTIONAL DESCRIPTION....................................................................................... 64
9.1 PCI BUS BUFFER MANAGEMENT .................................................................................................................... 64
9.1.1. Overview ............................................................................................................................................. 64
9.1.2. Data Structure and Descriptor List...................................................................................................... 64
9.1.3. Buffer Management : Ring Structure Method ..................................................................................... 64
9.1.4. Buffer Management : Chain Structure Method ................................................................................... 64
9.1.5. Descriptor List: Buffer Descriptor Format ........................................................................................... 65
9.1.2. Transmit Data Buffer Processing........................................................................................................ 72
9.2 SWITCH FUNCTION:........................................................................................................................................ 73
9.2.1 Address Learning................................................................................................................................. 73
9.2.2 Address Aging...................................................................................................................................... 73
9.2.3 Packet Forwarding ............................................................................................................................... 73
9.2.4 Inter-Packet Gap (IPG) ........................................................................................................................ 73
9.2.5 Back-off Algorithm................................................................................................................................ 73
9.2.6 Late Collision ....................................................................................................................................... 73
9.2.7 Half Duplex Flow Control ..................................................................................................................... 73
9.2.8 Full Duplex Flow Control...................................................................................................................... 73
9.2.9 Partition Mode...................................................................................................................................... 73
9.2.10 Broadcast Storm Filtering .................................................................................................................. 74
9.2.11 Bandwidth Control ............................................................................................................................. 74
9.2.12 Port Monitoring Support..................................................................................................................... 74
9.2.13 VLAN Support .................................................................................................................................... 75
9.2.13.1 Port-Based VLAN ........................................................................................................................... 75
9.2.13.2 802.1Q-Based VLAN ...................................................................................................................... 75
9.2.13.3 Tag/Untag ....................................................................................................................................... 75
9.2.14 Priority Support .................................................................................................................................. 76
9.2.14.1 Port-Based Priority.......................................................................................................................... 76
9.2.14.2 802.1p-Based Priority ..................................................................................................................... 76
9.2.14.3 DiffServ-Based Priority ................................................................................................................... 76
9.3 MII INTERFACE .............................................................................................................................................. 77
9.3.1 MII data interface ................................................................................................................................. 77
9.3.2 MII Serial Management........................................................................................................................ 77
9.3.3 Serial Management Interface............................................................................................................... 78
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
5
DM9106
3-port switch with PCI Interface
9.3.4 Management Interface - Read Frame Structure.................................................................................. 78
9.3.5 Management Interface - Write Frame Structure .................................................................................. 78
9.4 INTERNAL PHY FUNCTIONS ............................................................................................................................ 79
9.4.1 100Base-TX Operation ........................................................................................................................ 79
9.4.1.1 4B5B Encoder................................................................................................................................... 79
9.4.1.2 Scrambler.......................................................................................................................................... 79
9.4.1.3 Parallel to Serial Converter............................................................................................................... 79
9.4.1.4 NRZ to NRZI Encoder....................................................................................................................... 79
9.4.1.5 MLT-3 Converter............................................................................................................................... 79
9.4.1.6 MLT-3 Driver ..................................................................................................................................... 79
9.4.1.7 4B5B Code Group ............................................................................................................................ 80
9.4.2 100Base-TX Receiver.......................................................................................................................... 81
9.4.2.1 Signal Detect..................................................................................................................................... 81
9.4.2.2 Adaptive Equalization ....................................................................................................................... 81
9.4.2.3 MLT-3 to NRZI Decoder ................................................................................................................... 81
9.4.2.4 Clock Recovery Module.................................................................................................................... 81
9.4.2.5 NRZI to NRZ ..................................................................................................................................... 81
9.4.2.6 Serial to Parallel................................................................................................................................ 81
9.4.2.7 Descrambler...................................................................................................................................... 81
9.4.2.8 Code Group Alignment ..................................................................................................................... 82
9.4.2.9 4B5B Decoder................................................................................................................................... 82
9.4.3 10Base-T Operation ............................................................................................................................ 82
9.4.4 Collision Detection ............................................................................................................................... 82
9.4.5 Carrier Sense....................................................................................................................................... 82
9.4.6 Auto-Negotiation .................................................................................................................................. 82
9.5 AUTO MDIX HP AUTO-MDIX FUNCTIONAL DESCRIPTION ............................................................................... 82
10. DC AND AC ELECTRICAL CHARACTERISTICS......................................................... 84
10.1 ABSOLUTE MAXIMUM RATINGS .................................................................................................................. 84
10.2
OPERATING CONDITIONS ........................................................................................................................ 84
10.3
DC ELECTRICAL CHARACTERISTICS........................................................................................................ 85
10.3 AC CHARACTERISTICS ................................................................................................................................. 86
10.3.1 PCI Clock Specifications Timing........................................................................................................ 86
10.3.2 Power On Reset Timing..................................................................................................................... 86
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Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
10.3.3 Other PCI Signals Timing Diagram.................................................................................................... 87
10.3.4 Port 2 MII Interface Transmit Timing ................................................................................................. 88
10.3.5 Port 2 MII Interface Receive Timing .................................................................................................. 88
10.3.6 MII Management Interface Timing ..................................................................................................... 89
10.3.7 EEPROM timing................................................................................................................................. 90
11. PACKAGE INFORMATION ........................................................................................... 91
12. ORDERING INFORMATION .......................................................................................... 92
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
7
DM9106
3-port switch with PCI Interface
1. General Description
The DM9106 is a fully integrated, high performance, and cost-effective fast Ethernet switch controller with
one general PCI bus interface, two ports 10M/100Mbps PHY, and one port MII or RMII interface.
The general PCI bus connects directly to internal host MAC with 32-bit data registers and internal memory. The host
MAC has the similar functions as other 10/100Mbps PHY or MII does. This makes the DM9106 act as an extended four ports
switch and to shorten the latency from PCI port to destination port.
The internal memory of the DM9106 supports up to 1K uni-cast MAC address table, and provides to three
ports’ and PCI port’s transmit and receive buffers. For efficient memory usage algorithm, if application only uses
two ports solution, the another disabled port’s memory resource can be shared to other two ports and PCI port.
Each port of the DM9106 provides four priority transmit queues, that can be defined by port-based, 802.1p
VLAN, or IP packet ToS field automatically, to fit the various bandwidth and latency requirement of data, voice,
and video applications. Each port also supports ingress and/or egress rate control to provide proper bandwidth.
And up to 16 groups of 802.1Q VLAN with Tag/Un-tag functions are supported to provide efficient packet
forwarding.
The TCP/UDP/IPv4 checksum generation and checking functions are also provided by PCI port to offload the
processor computing loading. Besides the packet transmit and receive functions, the PCI port also provides
various registers to control and get status of the DM9106 functional operation. Each port, including the PCI port,
provides the MIB counters and loop-back capability and the build in memory self test (BIST) for system and
board level diagnostic.
The integrated two ports PHY are compliant with IEEE 802.3u standards. The MII interface provides the
flexibility to connect Ethernet PHY, and it can be configured as Reversed MII interface for SoC with MII
interface. An alternative interface, the RMII interface, is also provided to connect the lower pin count Ethernet
PHY or SoC with RMII interface.
2. Block Diagram
Port 0
MDI/MDIX
Port 1
MDI/MDIX
10/100M
PHY
10/100M
MAC
10/100M
PHY
10/100M
MAC
Port 2
MII / RMII
PCI BUS
Switch
Fabric
Switch
Engine
Switch
Controller
Memory
Management
10/100M
MAC
Processor
Interface
HOST
MAC
Control
Registers
8
Memory
BIST
Embedded
Memory
MIB
Counters
EEPROM
Interface
EEPROM
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
3. Features
‰
‰
‰
‰
‰
‰
‰
‰
‰
‰
‰
‰
‰
‰
‰
‰
‰
‰
‰
‰
‰
Ethernet Switch with two 10/100Mb PHY, one MII/RMII, and PCI bus interface
Support Reverse-MII
PCI bus master architecture
EEPROM interface for power up configurations
Support TCP/UDP/IPv4 checksum offload
Support HP Auto-MDIX
Support IEEE 802.3x Flow Control in Full-duplex mode
Support Back Pressure Flow Control in Half-duplex mode
Per port support 4 priority queues by Port-based, 802.1P QoS, and IP TOS priority
Support 802.1Q VLAN up-to 16 VLAN group
Support VLAN ID tag/untag options
Per port support bandwidth, ingress and egress rate control
Support Broadcast Storming filter function
Support Store and Forward switching approach
Support up-to 1K Uni-cast MAC addresses
Support MIB counters for diagnostic
Support IGMP Snooping v1, v2
EEPROM 93C46 or 93C56 auto detection
PCI bus driving capability adjustable
Port 2 TXD/TXE driving capability adjustable
128-pin LQFP 1.8V internal core, 3.3V I/O with 5V tolerant
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
9
DM9106
3-port switch with PCI Interface
VCNTL
TX1-
TX1+
AVDDI
TEST3
TEST2
TEST1
VCC3
RXD2_0
RXD2_1
RXD2_2
RXD2_3
RXDV2
GND
RXC2
RXER2
COL2
CRS2
83
81
80
79
78
77
76
74
73
71
70
69
68
67
66
65
72
AGND
AGND
84
75
RX1+
86
85
82
AVDD3
RX1-
88
87
TX0-
TX0+
AVDDI
89
90
RX0+
AGND
AGND
AVDD3
RX094
91
BGRES
95
97
98
64
TXC2
VREF
63
TXE2
AVDD3
99
62
VCC3
VCC3
100
61
TXD2_0
X1
101
60
TXD2_1
X2
102
59
TXD2_2
GND
103
58
TXD2_3
57
VCCI
LNK1_LED
104
SPD1_LED
105
FDX1_LED
106
LNK0_LED
107
SPD0_LED
108
109
FDX0_LED
WOL
56
MDIO
55
MDC
54
GND
53
PWRST#
52
EECS
51
50
EECK
49
EEDI
48
VCC3
47
AD0
46
AD1
45
GND
44
AD2
43
AD3
42
41
AD4
40
39
VCC3
AD6
38
AD7
AD8
110
PME#
111
INT#
112
RST#
113
PCICLK
114
ISOLATE#
115
SCLK
116
GNT#
117
REQ#
118
AD31
119
120
VCCI
AD30
AD29
121
AD28
123
DM9106
122
EEDO
AD5
26
27
28
29
30
31
32
AD15
GND
AD14
AD13
AD12
AD11
VCC3
25
24
VCCI
CBE1#
23
PAR
18
VCC3
22
17
SERR#
16
DEVSEL#
21
15
IRDY#
TRDY#
GND
14
FRAME#
19
13
CBE2#
20
12
STOP#
11
AD16
PERR#
10
GND
VCC3
AD23
IDSEL
9
AD10
AD18
33
AD17
AD9
128
8
34
AD19
127
7
GND
AD25
AD24
AD20
35
6
126
5
CBE0#
AD26
AD22
36
AD21
125
3
4
124
GND
1
2
AD27
37
CBE3#
10
93
92
BGRESG
96
4. Pin Configuration : 128 pin LQFP
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
5. Pin Description
I = Input, O = Output, I/O = Input / Output, O/D = Open Drain, P = Power, PD=internal pull-low (about 50K Ohm)
# = asserted Low
5.1 PCI Bus interface
Pin No.
Pin Name
I/O
Description
2
IDSEL
I
14
FRAME#
I/O
15
IRDY#
I/O
16
TRDY#
I/O
17
DEVSEL#
I/O
19
STOP#
I/O
20
PERR#
I/O
22
SERR#
I/O
23
PAR
I/O
1,13,25,36
C/BE3#
C/BE2#
C/BE1#
C/BE0#
I/O
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
Initialization Device Select
This signal is asserted high during the Configuration Space
read/write access.
Cycle Frame
This signal is driven low by the DM9106 master mode to
indicate the beginning and duration of a bus transaction.
Initiator Ready
This signal is driven low when the master is ready to complete
the current data phase of the transaction. A data phase is
completed on any clock when both IRDY# and TRDY# are
sampled asserted.
Target Ready
This signal is driven low when the target is ready to complete
the current data phase of the transaction. During a read, it
indicates that valid data is asserted. During a write, it indicates
that the target is prepared to accept data.
Device Select
The DM9106 asserts the signal low when it recognizes its
target address after FRAME# is asserted. As a bus master, the
DM9106 will sample this signal which insures its destination
address of the data transfer is recognized by a target.
Stop
This signal is asserted low by the target device to request the
master device to stop the current transaction.
Parity Error
The DM9106 as a master or slave will assert this signal low to
indicate a parity error on any incoming data.
System Error
This signal is asserted low when address parity is detected with
enabled PCICS bit31 (detected parity error.) The system error
asserts two clock cycles after the falling address if an address
parity error is detected.
Parity
This signal indicates even parity across AD0~AD31 and
C/BE0#~C/BE3# including the PAR pin. This signal is an
output for the master and an input for the slave device. It is
stable and valid one clock after the address phase.
Bus Command/Byte Enable
During the address phase, these signals define the bus
command or the type of bus transaction that will take place.
During the data phase these pins indicate which byte lanes
contain valid data. C/BE0# applies to bit7-0 and C/BE3#
applies to bit31-24.
11
DM9106
3-port switch with PCI Interface
AD31~AD0
I/O
110
WOL
O
111
PME#
O/D
112
INT#
O/D
113
RST#
I
114
PCICLK
I
115
ISOLATE#
I
117
GNT#
I
118
REQ#
O
119,121,122,123,124,126,127,128,
3,5,6,7,8,9,10,12,
26,28,29,30,31,33,34,37,
38,39,41,42,43,44,46,47
Address & Data
These are multiplexed address and data bus signals. As a bus
master, the DM9106 will drive address during the first bus
phase. During subsequent phases, the DM9106 will either
read or write data expecting the target to increment its address
pointer. As a target, the DM9106 will decode each address on
the bus and respond if it is the target being addressed.
Issue a wake up signal when wake up event occurred.
Power Management Event.
The DM9106 drives it low to indicate that a power
management event has occurred.
Interrupt Request
This signal will be asserted low when an interrupted condition
as defined in CR5 is set, and the corresponding mask bit in
CR7 is set.
System Reset
When this signal is low, the DM9106 performs the internal
system reset to its initial state.
PCI system clock
PCI bus clock that provides timing for DM9106 related to PCI
bus transactions.
Isolate
This pin is used to isolate the DM9106 from the PCI bus.
Bus Grant
This signal is asserted low to indicate that DM9106 has been
granted ownership of the bus by the central arbiter.
Bus Request
The DM9106 will assert this signal low to request the
ownership of the bus.
5.2 P2 MII / RMII / Reverse MII Interfaces
5.2.1 MII Interfaces
Pin No.
12
Pin Name
I/O
55
56
58,59,60,61
MDC
MDIO
TXD2_3~0
O,PD
I/O
O,PD
63
64
65
66
67
68
70
71,72,73,74
TXE2
TXC2
CRS2
COL2
RXER2
RXC2
RXDV2
RXD2_3~0
O,PD
I/O
I/O
I/O
I
I
I
I
Description
MII Serial Management Data Clock
MII Serial Management Data
Port 2 MII Transmit Data
4-bit nibble data outputs (synchronous to the TXC2)
Port 2 MII Transmit Enable
Port 2 MII Transmit Clock.
Port 2 MII Carrier Sense
Port 2 MII Collision Detect.
Port 2 MII Receive Error
Port 2 MII Receive Clock
Port 2 MII Receive Data Valid
Port 2 MII Receive Data
4-bit nibble data input (synchronous to RXC2)
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
5.2.2 RMII Interfaces
Pin No.
55
56
58,59
60,61
63
64
65
66
67
68
70
71,72
73,74
Pin Name
I/O
MDC
MDIO
TXD2_3~2
TXD2_1~0
TXE2
TXC2
CRS2
COL2
RXER2
RXC2
RXDV2
RXD2_3~2
RXD2_1~0
O,PD
I/O
O
O,PD
O,PD
O
I
I
I
I
I
I
I
5.2.3 Reverse MII Interfaces
Pin No.
Pin Name
I/O
55
56
58,59,60,61
MDC
MDIO
TXD2_3~0
O,PD
I/O
O,PD
63
64
65
TXE2
TXC2
CRS2
O,PD
O
O
66
COL2
O
67
68
70
71,72,73,74
RXER2
RXC2
RXDV2
RXD2_3~0
I
I
I
I
Pin Name
I/O
49
50
EEDI
EEDO
I,PD
O,PD
51
EECK
O,PD
52
EECS
O,PD
5.3 EEPROM Interfaces
Pin No.
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
Description
MII Serial Management Data Clock
MII Serial Management Data
Reserved
RMII Transmit Data
RMII Transmit Enable.
Reserved
RMII CRS_DV
Reserved, tie to ground in application.
Reserved, tie to ground in application.
50MHz reference clock.
Reserved, tie to ground in application.
Reserved, tie to ground in application.
RMII Receive Data.
Description
Reserved
Reserved
Port 2 MII Transmit Data
4-bit nibble data outputs (synchronous to the TXC2)
Port 2 MII Transmit Enable
25MHz clock output
Port 2 carrier sense output when TXE2 or RXDV2
asserted.
Port 2 collision output when TXE2 and RXDV2
asserted.
Port 2 MII Receive Error
Port 2 MII Receive Clock
Port 2 MII Receive Data Valid
Port 2 MII Receive Data
4-bit nibble data input (synchronous to RXC2)
Description
EEPROM Data In
EEPROM Data Out
This pin is used serially to write op-codes, addresses and
data into the EEPROM.
EEPROM Serial Clock
This pin is used as the clock for the EEPROM data transfer.
EEPROM Chip Selection.
13
DM9106
3-port switch with PCI Interface
5.4 LED Pins
Pin No.
Pin Name
I/O
Description
104
LNK1_LED
O/D
105
SPD1_LED
106
FDX1_LED
107
LNK0_LED
108
SPD0_LED
109
FDX0_LED
Port 1 Link / Active LED
It is the combined LED of link and carrier sense signal
of the internal PHY1
Port 1 Speed LED
Its low output indicates that the internal PHY1 is
operated in 100M/S, or it is floating for the 10M mode of
the internal PHY1
Port 1 Full-duplex LED
Its low output indicates that the internal PHY1 is
operated in full-duplex mode, or it is floating for the
half-duplex mode of the internal PHY1
Port 0 Link / Active LED
It is the combined LED of link and carrier sense signal
of the internal PHY0
Port 0 Speed LED
Its low output indicates that the internal PHY0 is
operated in 100M/S, or it is floating for the 10M mode of
the internal PHY0
Port 0 Full-duplex LED
Its low output indicates that the internal PHY0 is
operated in full-duplex mode, or it is floating for the
half-duplex mode of the internal PHY0
5.5 Clock Interface
Pin No.
O/D
O/D
O/D
O/D
Pin Name
I/O
X1
X2
SCLK
I
O
I
Pin Name
I/O
80,81
TX1+/-
I/O
84,85
RX1+/-
I/O
88,89
TX0+/-
I/O
92,93
RX0+/-
I/O
101
102
116
5.6 Network Interface
Pin No.
14
O/D
Description
Crystal 25MHz In
Crystal 25MHz Out
External system clock source
If strap pin EECS is pulled high, this pin is used for
DM9106 system clock. The frequency range is
between 20MHz and 100MHz depend on application.
Description
Port 1 TP TX
These two pins are the Twisted Pair transmit in MDI
mode or receive in MDIX mode.
Port 1 TP RX
These two pins are the Twisted Pair receive in MDI
mode or transmit in MDIX mode.
Port 0 TP TX
These two pins are the Twisted Pair transmit in MDI
mode or receive in MDIX mode.
Port 0 TP RX
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
95
BGRES
I/O
96
97
98
BGGND
VCNTL
VREF
P
I/O
O
Pin Name
I/O
53
PWRST#
I
76
77
TEST1
TEST2
78
TEST3
5.7 Miscellaneous Pins
Pin No.
5.8 Power Pins
Pin No.
4,18,32,40,48,62,75,100
24,57,120
11,21,27,35,45,
54,69,103,125
86,94,99
79,87
82,83,90,91
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
These two pins are the Twisted Pair receive in MDI
mode or transmit in MDIX mode.
Bandgap Pin
Connect a 1.4K resistor to BGGND in application.
Bandgap Ground
1.8V Voltage control
Voltage Reference
Connect a 0.1u capacitor to ground in application.
Description
Power on Reset
Low active with minimum 1ms
I,PD Tie to high in application
I,PD 0: 3-port mode
All ports are active in this mode.
1: 2-port mode
Only 2 ports are active in this mode. Port 1 or port 2
can be disabled by strap TXEN2. In this mode, the
memory resource is shared by PCI bus port and the
other 2 ports.
I,PD Tie to ground in application
Pin Name
I/O
Description
VCC3
VCCI
GND
P
P
P
Digital 3.3V
Internal 1.8V core power
Digital GND
AVDD3
AVDDI
AGND
P
P
P
Analog 3.3V power
Analog 1.8V power
Analog GND
15
DM9106
3-port switch with PCI Interface
5.9 Strap pins table
1: pull-high 1K~10K, 0: default floating.
5.9.1 Strap pin in 3-port mode
Pin No.
52
50
58
59
60,51
61
63,56
16
Pin Name
Description
Source of System Clock
0: system clock is internal 50MHz clock
1: use SCLK pin as system clock
EEDO
When Port 2 in force status mode
0: Port 2 in 100Mbps
1: Port 2 in 10Mbps
TXD2_3
When Port 2 in force status mode
0: link ON
1: link OFF
TXD2_2
0: Port 2 status from external PHY
1: Port 2 status in force mode
TXD2_1,EECK 00: Port 2 is MII mode (Default)
01: Port 2 is in reverse MII mode
10: Port 2 is in RMII mode and memory BIST disabled
11: Reserved
TXD2_0
When Port 2 in force status mod
0: Port 2 in full duplex mode
1: Port 2 in half duplex mode
TXEN2,MDC Reserved
EECS
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
5.9.2 strap pin in 2-port mode
Pin No.
52
50
58
59
60,51
61
63
56
Pin Name
Description
Source of System Clock
0: system clock is internal 50MHz clock
1: use SCLK pin as system clock
EEDO
When Port 2 in force status mode
0: Port 2 in 100Mbps
1: Port 2 in 10Mbps
TXD2_3
When Port 2 in force status mode
0: link ON
1: link OFF
TXD2_2
0: Port 2 status from external PHY
1: Port 2 status in force mode
TXD2_1,EECK 00: Port 2 is MII mode (Default)
01: Port 2 is in reverse MII mode
10: Port 2 is in RMII mode and memory BIST disabled
11: Reserved
TXD2_0
When Port 2 in force status mode
0: Port 2 in full duplex mode
1: Port 2 in half duplex mode
TXEN2
0: port 2 disabled
1: port 1 disabled
MDC
reserved
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
EECS
17
DM9106
3-port switch with PCI Interface
6. Register Set
6.1 PCI Configuration Registers
The definitions of PCI Configuration Registers are based on
the PCI specification revision 2.2 and it provides the
initialization and configuration information to operate the PCI
interface in the DM9106. All registers can be accessed with
byte, word, or double word mode. As defined in PCI
specification 2.1, read accesses to reserve or
unimplemented registers will return a value of “0.” These
registers are to be described in the following sections.
The default value of PCI configuration registers after reset.
Description
Identifier
Address Offset
Value of Reset
Identification
PCIID
00H
1282H
Command & Status
PCICS
04H
02100000H*
Revision
PCIRV
08H
02000021H
Miscellaneous
PCILT
0CH
BIOS determine
I/O Base Address
PCIIO
10H
System allocate
Memory Base Address
PCIMEM
14H
System allocate
Reserved
-------18H - 28H
00000000H
Subsystem Identification
PCISID
2CH
load from EEPROM
Reserved
-------30H
00000000H
Capabilities Pointer
Cap _Ptr
34H
00000050H
Reserved
-------38H
00000000H
Interrupt & Latency
PCIINT
3CH
System allocate bit7~0
Device Specific Configuration Register
PCIUSR
40H
00000000H**
Power Management Register
PCIPMR
50H
C0310001H**
Power Management Control & Status
PMCSR
54H
00000100H
* It is written to 02100007H by most BIOS.
** It may be changed from EEPROM in application.
Key to Default
In the register description that follows, the default column
takes the form <Reset Value>
Where:
<Reset Value>:
1
Bit set to logic one
0
Bit set to logic zero
X
No default value
18
<Access Type>:
RO = Read only
RW = Read/Write
R/C: means Read / Write & Write "1" for Clear.
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
6.1.1 Identification ID (xxxxxx00H - PCIID)
Bit
0:15
Default
1282H
Type
RO
Description
This field identifies the manufacturer of the device. Unique and fixed number for
Davicom is 1282H.
6.1.2 Command & Status (xxxxxx04H - PCICS)
Bit
31
Default
0
Type
R/C
30
0
R/C
29
0
R/C
28
0
R/C
27
0
R/C
26:25
01
R/C
24
0
R/C
23
0
RO
22
21
20
0
0
1
RO
RO
RO
19:10
0
RO
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
Description
Detected Parity Error
The DM9106 samples the AD[0:31], C/BE[0:3]#, and the PAR signal to
check parity and to set parity errors. In slave mode, the parity check falls
on command phase and data valid phase (IRDY# and TRDY# both
active). In master mode, the DM9106 will check each data phase, during
a memory read cycle, for parity error. During a memory write cycle, if an
error occurs, the PERR# signal will be driven by the target. This bit is set
by the DM9106 and cleared by writing "1". There is no effect by writing "0"
Signal For System Error
This bit is set when the SERR# signal is driven by the DM9106. This
system error occurs when an address parity is detected under the
condition that bit 8 and bit 6 in command register below are set
Master Abort Detected
This bit is set when the DM9106 terminates a master cycle with the
master-abort bus transaction
Target Abort Detected
This bit is set when the DM9106 terminates a master cycle due to a
target-abort signal from other targets
Send Target Abort (0 for No Implementation)
The DM9106 will never assert the target-abort sequence
DEVSEL Timing (01 Select Medium Timing)
Medium timing of DEVSEL# means the DM9106 will assert DEVSEL#
signal two clocks after FRAME# is sample “asserted”
Data Parity Error Detected
This bit will take effect only when operating as a master and when a Parity
Error Response Bit in command configuration register is set. It is set under
two conditions:
(i) PERR# asserted by the DM9106 in memory data read error
(ii) PERR# sent from the target due to memory data write error
Slave Mode Fast Back-To-Back Capable (0 for No Support)
This bit is always reads "1" to indicate that the DM9106 is capable of
accepting fast back-to-back transaction as a slave mode device
User-Definable Feature Supported (0 for No Support)
66 MHz (0 for No Capability)
New Capability
This bit indicates whether this function implements a list of extended
capabilities.
Reserved
19
DM9106
3-port switch with PCI Interface
9
0
RO
8
0
RW
7
6
0
0
RO
RW
5
4
0
0
RO
RO
3
2
0
1
RO
RW
1
1
RW
0
1
RW
Master Mode Fast Back-To-Back (0 for No Support)
The DM9106 does not support master mode fast back-to-back capability
and will not generate fast back-to-back cycles
SERR# Driver Enable/Disable
This bit controls the assertion of SERR# signal output. The SERR# output
will be asserted on detection of an address parity error and if both this bit
and bit 6 are set
Address/Data Stepping (0 for No Stepping)
Parity Error Response Enable/Disable
Setting this bit will enable the DM9106 to assert PERR# on the detection
of a data parity error and to assert SERR# for reporting address parity
error
VGA Palette Snooping (0 for No Support)
Memory Write and Invalid (0 for No Implementation)
The DM9106 only generates memory write cycle
Special Cycles (0 for No Implementation)
Master Device Capability Enable/Disable
When this bit is set, DM9106 has the ability of master mode operation
Memory Space Access Enable/Disable
This bit controls the ability of memory space access. The memory access
includes memory mapped I/O access and Boot ROM access. As the
system boots up, this bit will be enabled by BIOS for Boot ROM memory
access. While in normal operation, using memory mapped I/O access,
this bit should be set by driver before memory access cycles
I/O Space Access Enable/Disable
This bit controls the ability of I/O space access. It will be set by BIOS after
power on
6.1.3 Revision ID (xxxxxx08H - PCIRV)
20
Bit
31:8
Default
020000H
Type
RO
7:4
0002
RO
3:0
0001
RO
Description
Class Code (020000H)
This is the standard code for Ethernet LAN controller
Revision Major Number
This is the silicon-major revision number that will increase for the subsequent
versions of the DM9106
Revision Minor Number
This is the silicon-minor revision number that will increase for the subsequent
versions of the DM9106
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
6.1.4 Miscellaneous Function (xxxxxx0cH - PCILT)
Bit
31:24
23:16
15:8
Default
00H
00H
00H
Type
RO
RO
RW
7:0
00H
RO
Description
Built In Self Test ( 00H means No Implementation)
Header Type ( 00H means single function with Predefined Header Type ).
Latency Timer For The Bus Master
The latency timer is guaranteed by the system and measured by clock cycles.
When the FRAME# is asserted at the beginning of a master period by the
DM9106, the value will be copied into a counter and start counting down. If the
FRAME# is de-asserted prior to count expiration, this value is meaningless. When
the count expires before GNT# is de-asserted, the master transaction will be
terminated as soon as the GNT# is removed
While GNT# signal is removed and the counter is non-zero, the DM9106 will
continue with its data transfers until the count expires. The system host will read
MIN_GNT and MAX_LAT registers to determine the latency requirement for the
device and then initialize the latency timer with an appropriate value
The reset value of Latency Timer is determined by BIOS
Cache Line Size For Memory Read Mode Selection ( 00H means No
Implementation For Use)
6.1.5 I/O Base Address (xxxxxx10H - PCIIO)
Bit
31:7
Default
Undefined
Type
RW
6:1
000000
RO
0
1
RO
Description
PCI I/O Base Address
This is the base address value for I/O accesses cycles. It will be compared to
AD[31:7] in the address phase of bus command cycle for the I/O resource access
PCI I/O Range Indication
It indicates that the minimum I/O resource size is 80h
I/O Space Or Memory Space Base Indicator
Determines that the register maps into the I/O space ( = 1 Indicates I/O Base)
6.1.6 Memory Mapped Base Address (xxxxxx14H - PCIMEM)
Bit
31:7
Default
Undefined
Type
R/W
6:1
000000
RO
0
0
RO
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
Description
PCI Memory Base Address
This is the base address value for memory accesses cycles. It will be compared to
the AD [31:7] in the address phase of bus command cycle for the Memory resource
access
PCI Memory Range Indication
It indicates that the minimum memory resource size is 80h
I/O Space Or Memory Space Base Indicator
Determines that the register maps into the memory space( = 0 Indicates Memory
Base)
21
DM9106
3-port switch with PCI Interface
6.1.7 Subsystem Identification (xxxxxx2cH - PCISID)
Bit
31:16
Default
XXXXH
Type
RO
15:0
XXXXH
RO
Description
Subsystem ID
It can be loaded from EEPROM word 1
Subsystem Vendor ID
It can be loaded from EEPROM word 0
6.1.8 Capabilities Pointer (xxxxxx34H - Cap _Ptr)
Bit
31:8
7:0
Default
000000H
01010000
Type
RO
RO
Description
Reserved
Capability Pointer
The Cap_ Ptr provides an offset (default is 50H) into the function’s PCI
Configuration Space for the location of the first term in the Capabilities Linked List.
The Cap_ Ptr offset is double word aligned so the two least significant bits are
always “0”s
6.1.9 Interrupt & Latency Configuration (xxxxxx3cH - PCIINT)
Bit
31:24
23:16
Default
28H
14H
Type
RO
RO
15:8
7:0
01H
XXH
RO
RW
Description
Maximum Latency Timer that can be sustained.
Minimum Grant
Minimum Length of a Burst Period.
Interrupt Pin read as 01H to indicate INTA#
Interrupt Line that Is routed to the Interrupt Controller
The value depends on system software.
6.1.10 Device Specific Configuration Register (xxxxxx40H- PCIUSR)
Bit
31:30
29
28
27
26
Default
0
0
0
0
0
Type
RO
RW
RO
RW
RO
25
24
0
0
RO
RO
23:16
15:8
7:0
00H
00H
00H
RO
RW
RO
22
Description
Reserved Bits Read As 0
When set, enables port 0 or 1 Link Status Change Wake up Event
Reserved Bit Read As 0
When set, enables Magic Packet Wake up Event
When set, indicates the port 0 or 1 Link Change and the Link Status Change Event
occurred
Reserved Bit Read As 0
When set, indicates the Magic Packet is received and the Magic packet Event
occurred
Reserved Bits Read As 0
Device Specific
Reserved Bits Read As 0
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
6.1.11 Power Management Register (xxxxxx50H~PCIPMR)
Bit
31:27
Default
11000
Type
RO
26:25
00
RO
24:22
011
RO
21
0
RO
20
19
0
0
RO
RO
18:16
010
RO
15:8
00H
RO
7:0
01H
RO
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
Description
PME_ Support
This field indicates that the power states in which the function may assert PME#. A
value of 0 for any bit indicates that the function is not capable of asserting the PME#
signal while in that power state
bit27 Æ PME# support D0
bit28 Æ PME# support D1
bit29 Æ PME# support D2
bit30 Æ PME# support D3(hot)
bit31 Æ PME# support D3(cold)
DM9106’s bit31~27=11000 indicates PME# can be asserted from D3(hot) &
D3(cold)
These bits can be load from EEPROM word 7 bit [7:3]
Reserved
These two bits can be load from EEPROM word 7 bit [1:0]
Aux_ Current
This field reports the 3.3Vaux auxiliary current requirement for the PCI function.
The default value of this field is 011 means 160mA and it can be loaded from
EEPROM word 4 bit [15:13] if EEPROM word 4 bit [9] is 1
Reserved
This bit can be load from EEPROM word 7 bit [2]
Reserved
PME# Clock
“0” indicates that no PCI clock is required for the function to generate PME#
Version
A default value of 010 indicates that this function complies with the Revision 1.1 of
the PCI Power Management Interface Specification
This value can be loaded from EEPROM word 4 bit [12:10] if EEPROM word 4 bit
[9] is 1
Next Item Pointer
The offset into the function’s PCI Configuration Space pointing to the location of
next item in the function’s capability list is “00H”
Capability Identifier
When “01H” indicates the linked list item as being the PCI Power Management
Registers
23
DM9106
3-port switch with PCI Interface
6.1.12 Power Management Control/Status (xxxxxx54H~PMCSR)
24
Bit
31:16
15
Default
0000H
0
Type
RO
RW/C
14:9
000000
RO
8
1
RW
7:2
1:0
000000
00
RO
RW
Description
Reserved
PME_ Status
This bit is set when the function would normally assert the PME# signal
independent of the state of the PME_ En bit. Writing a “1” to this bit will clear it.
This bit defaults to “0” if the function does not support PME# generation from D3
(cold).If the function supports PME# from D3 (cold) then this bit is sticky and must
be explicitly cleared by the operating system whenever the operating system is
initially loaded.
Reserved
It means that the DM9106 does not support reporting power consumption.
PME_ En
Write “1” to enables the function to assert PME#, write “0” to disable PME#
assertion
This bit defaults to “0” if the function does not support PME# generation from D3
(cold)
If the function supports PME# from D3(cold) then this bit is sticky and must be
explicitly cleared by the operating system each time the operating system is
initially loaded.
Reserved
This two bits field is both used to determine the current power state of a function
and to set the function into a new power state. The definitions given below
00: D0
11: D3 (hot)
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
6.2 PCI Control and Status Registers (CR)
The DM9106 implements 32 control and status registers,
which can be accessed by the host. These CRs are double
long word aligned. All CRs are set to their default values by
Register
Description
CR0
CR1
CR2
CR3
CR4
CR5
CR6
CR7
CR8
CR9
CR10
CR11
CR12
CR13
CR14
CR15
CR16
CR17
CR18
CR19
CR20
CR21
CR22
CR23
CR24-27
CR28-31
For register bank 1
CR18
CR19
CR20
CR21
CR22
CR23
CR24
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
hardware or software reset unless otherwise specified. All
Control and Status Registers with their definitions and offset
from IO or memory Base Address are shown below:
System Control Register
Transmit Descriptor Poll Demand
Receive Descriptor Poll Demand
Receive Descriptor Base Address Register
Transmit Descriptor Base Address Register
Network Status Report Register
Network Operation Mode Register
Interrupt Mask Register
Reserved
External Management Access Register
Reserved
Reserved
Reserved
Reserved
Reserved
Watchdog And Jabber Timer Register
SWITCH Control Register
Per Port Index Register
Per Port Control Register
Per Port Status Data Register
Per Port VLAN Tag Byte Register
Per Port MIB counter Index Register
MIB counter Data Register
VLAN priority Map Register
Port-based VLAN mapping table registers x 4
TOS Priority Map Register x 4
Offset from CSR
Base Address
00H
08H
10H
18H
20H
28H
30H
38H
40H
48H
50H
58H
60H
68H
70H
78H
80H
88H
90H
98H
A0H
A8H
B0H
B8H
C0H-D8H
E0H-F8H
Default value
after reset
DE000000H
FFFFFFFFH
FFFFFFFFH
00000000H
00000000H
FC000000H
02040000H
FFFE0000H
00000000H
000083F0H
FFFFFFFFH
FFFE0000H
FFFFFFXXH
XXXXXX00H
Unpredictable
00000000H
00000000H
00000000H
00000000H
00000000H
00000001H
00000000H
00000000H
0000FA50H
0F0F0F0FH
XXXXXXXXH
Port Security Register
IGMP Snooping 1 Register
IGMP Snooping 2 Register
Ethernet Address Control Status Register
Ethernet Address Data 1 Register
Ethernet Address Data 2 Register
PCI/port 2 Driving Capability Register
90H
98H
A0H
A8H
B0H
B8H
C0H
00000000H
00000000H
00000000H
00000001H
00000000H
00000000H
00000000H
25
DM9106
3-port switch with PCI Interface
Key to Default
In the register description that follows, the default column
takes the form:
<Reset Value>, <Access Type>
Where:
<Reset Value>:
1
Bit set to logic one
0
Bit set to logic zero
X
No default value
<Access Type>:
RO = Read only
RW = Read/Write
RW/C = Read/Write and Clear
WO = Write only
RO/C = Read only and cleared after read.
Reserved bits are shaded and should be written with 0.
Reserved bits are undefined on read access.
6.2.1 System Control Register (CR0)
Bit
31:24
25:22
21
Name
RESERVED
RESERVED
MRM
Default
DEH,RO
00,RO
0,RW
20
19:1
0
RESERVED
RESERVED
SR
0,RW
0,RO
0,RW
Description
Reserved
Reserved
Memory Read Multiple
When set, the DM9106 will use memory read multiple command (C/BE3~0 1100)
when it initialize the memory read burst transaction as a master device
When reset, it will use memory read command (C/BE3 ~ 0 = 0110) for the same
master operation
Reserved
Reserved
Software Reset
When set, the DM9106 will make a internal reset cycle. All consequent action to
DM9106 should wait at least 32 PCI clock cycles for its self-cleared.
6.2.2 Transmit Descriptor Poll Demand (CR1)
Bit
31:0
Name
TDP
Default
FFFFFFFF
H
,WO
Description
Transmit Descriptor Polling Command
Writing any value to this port will force DM9106 to poll the transmit descriptor. If
the acting descriptor is not available, transmit process will return to suspend state.
If the descriptor shows buffer available, transmit process will begin the data
transfer.
6.2.3 Receive Descriptor Poll Demand (CR2)
Bit
31:0
26
Name
RDP
Default
FFFFFFF
FH
,WO
Description
Receive Descriptor Polling Command
Writing any value to this port will force DM9106 to poll the receive descriptor. If the
acting descriptor is not available, receive process will return to suspend state.
If the descriptor shows buffer available, receive process will begin the data transfer.
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
6.2.4 Receive Descriptor Base Address (CR3)
Bit
Name
Default
Description
31:0
RDBA
0000000 Receive Descriptor Base Address
0H,
This register defines base address of receive descriptor-chain. The receive
RW
descriptor- polling command, after CR3 is set, will make DM9106 to fetch the
descriptor at the Base-Address.
This is a working register, so the value of reading is unpredictable.
6.2.5 Transmit Descriptor Base Address (CR4)
Bit
Name
Default
Description
31:0
TDBA
0000000 Transmit Descriptor Base Address
0H,RW
This register defines base address of transmit descriptor-chain. The transmit
descriptor- polling command after CR4 is set to make DM9106 fetch the descriptor
at the Base-Address.
This is a working register, so the value of reading is unpredictable.
6.2.6 Network Status Report Register (CR5)
Note: Bits [13:0] can be cleared by written 1 to them respectively.
Bit
Name
Default
Description
31:26 RESERVED 000000,RO Reserved
25:23
SBEB
000,RO System Bus Error Bits
These bits are read only and used to indicate the type of system bus fatal error. Valid
only when System Bus Error is set. The mapping bits are shown below
22:20
TXPS
000,RO
19:17
RXPS
000,RO
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
Bit25
Bit24
Bit23
Bus Error Type
0
0
0
Parity error
0
0
1
Master abort
0
1
0
Slave abort
0
1
1
Reserved
1
X
X
Reserved
Transmit Process State
These bits are read only and used to indicate the state of transmit process
The mapping table is shown below
Bit22 Bit21 Bit20
Process State
0
0
0
Transmit process stopped
0
0
1
Fetch transmit descriptor
0
1
0
Move Setup Frame from the host memory
0
1
1
Move data from host memory to transmit FIFO
1
0
0
Close descriptor by clearing owner bit of descriptor
1
0
1
Waiting end of transmit
1
1
0
Transmit end and Close descriptor by writing status
1
1
1
Transmit process suspend
Receive Process State
These bits are read only and used to indicate the state of receive process. The
mapping table is shown below
Bit19 Bit18 Bit17
Process State
0
0
0
Receive process stopped
0
0
1
Fetch receive descriptor
0
1
0
Wait for receive packet under buffer available
27
DM9106
3-port switch with PCI Interface
0
1
1
1
1
16
NIS
0,RW
15
AIS
0,RW
14
13
RESERVED
SBE
0,RW
0,RW
12
LINKS
0,RO
11
10:9
8
RESERVED
RESERVED
RXPS
0,RO
0,RO
0,RW
7
RXDU
0,RW
6
RXCI
0,RW
5
TXFU
0,RW
4
3
2
RESERVED
RESERVED
TXDU
0,RO
0,RO
0,RW
1
TXPS
0,RW
0
TXCI
0,RW
28
1
0
0
1
1
1
0
1
0
1
Move data from receive FIFO to host memory
Close descriptor by clearing owner bit of descriptor
Close descriptor by writing status
Receive process suspended due to buffer unavailable
Purge the current frame from received FIFO
because of the unavailable received buffer
Normal Interrupt Summary
Normal interrupt includes any of the three conditions:
CR5<0> – TXCI: Transmit Complete Interrupt
CR5<2> – TXDU: Transmit Buffer Unavailable
CR5<6> – RXCI: Receive Complete Interrupt
Abnormal Interrupt Summary
Abnormal interrupt includes any interrupt condition as shown below, excluding
Normal Interrupt conditions. They are TXPS (bit1), TXFU (bit5), RXDU (bit7), RXPS
(bit8), SBE (bit13).
Reserved
System Bus Error
The PCI system bus errors will set this bit. The type of system bus error is shown in
CR5<25:23>.
Link Change Status
This bit is set to indicate that the link status changed in port 0 or 1 PHYceiver
Reserved
Reserved
Receive Process Stopped
This bit is set to indicate that the receive process enters the stopped state.
Receive Buffer Unavailable
This bit is set when the DM9106 fetches the next receive descriptor that is still owned
by the host. Receive process will be suspended until a new frame enters or the
receive polling command is set.
Receive Complete Interrupt
This bit is set when a received frame is fully moved into host memory and receive
status has been written to descriptor. Receive process is still running and continues to
fetch next descriptor.
Transmit FIFO Underrun
This bit is set when transmit FIFO has underrun condition during the packet
transmission. It may happen due to the heavy load on bus, cause transmit buffer
unavailable before end of packet. In this case, transmit process is placed in the
suspend state and underrun error TDES0<1> is set.
Reserved
Reserved
Transmit Buffer Unavailable
This bit is set when the DM9106 fetches the next transmit descriptor that is still owned
by the host. Transmit process will be suspended until the transmission polling
command is set.
Transmit Process Stopped
This bit is set to indicate transmit process enters the stopped state.
Transmit Complete Interrupt
This bit is set when a frame is fully transmitted and transmit status has been written to
descriptor (the TDES1<31> is also asserted). Transmit process is still running and
continues to fetch next descriptor.
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
6.2.7 Network Operation Mode Register (CR6)
Bit
31
30:29
28:25
Name
RESERVED
RESERVED
RESERVED
Default
0,RO
0,RO
0001,RO
24:23
22
21
20
19
18
17
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
MII_CNTL
00,RO
0,RO
0,RO
0,RW
0,RW
0,RO
0,RW
16
1PKT
0,RW
15:14
13
RESERVED
TXSC
0,RO
0,RW
12
11:10
RESERVED
LBM
0,RO
0,RW
Description
Reserved
Reserved
0001: normal mode
0011: memory test mode (CR13/14 enable)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MII Management Pin Control
Set this bit to enable CR9 bit 16~19 to control MII management pin (MDC,MDIO)
One Packet Mode
When this bit is set, only one packet is stored at TX FIFO
Reserved
Transmit Start/Stop Command
When set, the transmit process will begin by fetching the transmit descriptor for
available packet data to be transmitted (running state). If the fetched descriptor is
owned by the host, transmit process will enter the suspend state and transmit buffer
unavailable (CR5<2>) is set. Otherwise it will begin to move data from host to
FIFO and transmit out after reaching threshold value.
When reset, the transmit process is placed in the stopped state after completing the
transmission of the current frame.
Reserved
Loop-back Mode
These bits decide two loop-back modes, MAC and PHY, besides normal
operation. These loop-back modes expect transmitted data back to receive path
and ignore collision detection.
Bit11
0
0
1
9
8
7
RESERVED
RESERVED
PAM
0,RO
0,RO
0,RW
6
PM
0,RW
5
RESERVED
0,RO
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
Bit10
0
1
X
Loop-back Mode
Normal
Internal loop-back
Reserved
Reserved
Reserved
Pass All Multicast
When set, any packet with a multicast destination address is received by the
DM9106. The packet with a physical address will also be filtered based on the
filter mode setting
Promiscuous Mode
When set, any incoming valid frame is received by the DM9106, and no matter
what the destination address is. The DM9106 is initialized to this mode after reset
operation.
Reserved
29
DM9106
3-port switch with PCI Interface
4
IAFM
0,RO
Inverse Address Filtering Mode
It is set to indicate the DM9106 operate in a Inverse Filtering Mode. This is a
only bit and mapped from the setup frame together with CR6<2>, CR6<0>
setting. That is it is valid only during perfect filtering mode.
3
PBF
0,RW
Pass Bad Frame
When set, the DM9106 is indicated to receive the bad frames including
runt packets, truncated frames caused by the FIFO overflow.
The bad frame also has to pass the address filtering if the
DM9106 is not set in promiscuous mode.
2
HOFM
0,RO
Hash-only Filter Mode
This is a read-only bit and mapped from the set-up frame together with
bit4,0 of CR6.It is set to indicate the DM9106 operate in a Hash-only
Filtering Mode.
1
RXRC
0,RW
Receive Start/Stop Command
When set, the receive process will begin by fetching the receive descriptor
for available buffer to store the new-coming packet (placed in the running
state). If the fetched descriptor is owned by the host (no descriptor is
owned by the DM9106), the receive process will enter the suspend state
and receive buffer unavailable CR5<7> sets. Otherwise it runs to wait for
the packet’s income. When reset, the receive process is placed in the
stopped state after completing the reception of the current frame.
0
HPFM
0,RO
Hash/Perfect Filter Mode
This is a read only bit and mapped from the setup frame together with
CR6<4>, CR6<2>. When reset, the DM9106 does a perfect address filter
of incoming frames according to the addresses specified in the setup
frame. When set, the DM9106 does a imperfect address filtering for the
incoming frame with a multicast address according to the hash table
specified in the setup frame. The filtering mode (perfect/imperfect) for the
frame with a physical address will depend on CR6<2>.
30
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
6.2.8 Interrupt Mask Register (CR7)
Bit
16
Name
NISE
Default
0,RW
15
AISE
0,RW
14
13
RESERVED
SBEE
0,RW
0,RW
LINKE
0,RW
11
10:9
8
RESERVED
RESERVED
RXPSE
0,RW
0,RO
0,RW
7
RXDUE
0,RW
6
RXCIE
0,RW
5
TXFUE
0,RW
4
3
2
RESERVED
RESERVED
TXDUE
0,RO
0,RO
0,RW
1
TXPSE
0,RW
0
TXCIE
0,RW
12
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
Description
Normal Interrupt Summary Enable
This bit is set to enable the interrupt for Normal Interrupt Summary.
Normal interrupt includes three conditions:
CR5<0> – TXCI: Transmit Complete Interrupt
CR5<2> – TXDU: Transmit Buffer Unavailable
CR5<6> – RXCI: Receive Complete Interrupt
Abnormal Interrupt Summary Enable
This bit is set to enable the interrupt for Abnormal Interrupt Summary.
Abnormal interrupt includes all interrupt conditions as shown below, excluding
Normal Interrupt conditions. They are TXPS(bit1), TXFU(bit5), RXDU(bit7),
RXPS(bit8), SBE(bit13).
Reserved
System Bus Error Enable
When set together with CR7<15>, CR5<13>, it enables the interrupt for System
Bus Error. The type of system bus error is shown in CR5<24:23>.
Link Change Interrupt Enable
When this bit and CR7<16>, CR5<12> are set together, it will enable the interrupt
of link status changed from port 0 or 1 PHYceiver.
Reserved
Reserved
Receive Process Stopped Enable
When set together with CR7<15> and CR5<8>. This bit is set to enable the
interrupt of receive process stopped condition.
Receive Buffer Unavailable Enable
When this bit and CR7<15>, CR5<7> are set together, it will enable the interrupt of
receive buffer unavailable condition.
Receive Complete Interrupt Enable
When this bit and CR7<16>, CR5<6> are set together, it will enable the interrupt of
receive process complete condition.
Transmit FIFO Underrun Enable
When set together with CR7<15>, CR5<5>, it will enable the interrupt of transmit
FIFO underrun condition.
Reserved
Reserved
Transmit Buffer Unavailable Enable
When this bit and CR7<16>, CR5<2> are set together, the interrupt of transmit
buffer unavailable is enabled.
Transmit Process Stopped Enable
When this bit is set together with CR7<15> and CR5<1>, it will enable the interrupt
of the transmit process to stop.
Transmit Complete Interrupt Enable
When this bit and CR7<16>, CR5<0> are set, the transmit interrupt is enabled.
31
DM9106
3-port switch with PCI Interface
6.2.9 Reserved (CR8)
6.2.10 Management Access Register (CR9)
Bit
31:22
21
Name
RESERVED
LES
Default
0,RO
0,RO
20
RLM
0,RW
19
MDIN
0,RO
18
MRW
0,RW
17
MDOUT
0,RW
16
MDCLK
0,RW
15
14
13:12
11
RESERVED
RESERVED
RESERVED
ERS
1,RO
0,RO
0,RO
0,RW
10
EE_TYPE
0,RO
9:8
7:4
3
RESERVED
RESERVED
CRDOUT
011,RW
FH,RO
0,RW
2
CRDIN
0,RW
1
CRCLK
0,RW
0
CRCS
0,RW
32
Description
Reserved
Load EEPROM status
It is set to indicate the load of EEPROM is in progress.
Reload EEPROM
Set to reload the content of EEPROM.
MII Management Data_In
This is a read-only bit to indicate the MDIO input data, when bit 18 MRW is set.
MII Management Read/Write Mode Selection
This bit defines the Read/Write Mode for PHY MII management register access. 1
for read and 0 for write.
MII Management Data_Out
This bit is used to generate the output data signal for PHY MII management register
access.
MII Management Clock
This bit is used to generate the output clock signal for PHY MII management
register access.
Reserved.
Reserved.
Reserved.
EEPROM Selected
This bit is used to enable EEPROM access.
EEPROM type
0: 93C46
1: 93C56
Reserved
Reserved
Data_Out from EEPROM
This bit reflects the status of EEDI pin when the EEPROM access is enabled.
Data_In to EEPROM
This bit maps to EEDO pin when the EEPROM access is enabled.
Clock to EEPROM
This bit maps EECK pin when the EEPROM access is enabled
Chip_Select to EEPROM
This bit maps to EECS pin when the EEPROM access is enabled
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
6.2.11 Reserved (CR10)
6.2.12 Reserved (CR11)
6.2.13 Reserved (CR12)
6.2.14 (Reserved CR13)
6.2.15 (Reserved CR14)
6.2.16 Checksum Offload Control Register (CR15)
Bit
31
30
29
28
27
26:0
Name
TXSUMC
IPSUM
TCPSUM
UDPSUM
RXSUM
Reserved
Default
0,WO
0,WO
0,WO
0,WO
0,WO
0,RO
Description
in transmit, generate IP/TCP/UDP chksum depend-on TX desc. control
in transmit, generate IP chksum to all packets
in transmit, generate TCP chksum to all packets
in transmit, generate UDP chksum to all packets
In receiving, report IP/TCP/UDP checksum status to RDES0
Reserved
6.12.17 Switch Control Register (CR16)
Bit
31:16
15
Name
RESERVED
TOS6
Default
0,RW
0,RW
14
13
12
RESERVED
UNICAST
VIDFF
0,RO
0,RW
0,RW
11
VID1
0,RW
10
VID0
0,RW
9
8
PRI
VLAN
0,RW
0,RW
7
MEM_BIST
0,RO
6
5
RST_SW
RST_ANLG
0,RW
0,RW
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
Description
Reserved
Full ToS Using Enable
1: check most significant 6-bit of TOS
0: check most significant 3-bit only of TOS
Reserved
Unicast packet can across VLAN boundary
Replace VIDFF
If the received packet is a tagged VLAN with VID equal to “FFF”, its VLAN field is
replaced with VLAN tag defined in CR20 bit 15~0.
Replace VID01
If the received packet is a tagged VLAN with VID equal to “001”, its VLAN field is
replaced with VLAN tag defined in CR20 bit 15~0.
Replace VID0
If the received packet is a tagged VLAN with VID equal to “000”, its VLAN field is
replaced with VLAN tag defined in CR20 bit 15~0.
Replace priority field in the tag with value define in CR20 bit 15~13.
VLAN mode enable
1: 802.1Q base VLAN mode enable
0: port-base VLAN
Address Memory Test BIST Status
0: OK
1: Fail
Reset Switch Core and auto clear after 10us
Reset Analog PHY Core and auto clear after 10us
33
DM9106
3-port switch with PCI Interface
4:3
SNF_PORT
00,RW
2
CRC_DIS
PE0,RW
1:0
RESERVED
PE0,RW
Sniffer Port Number
Define the port number to act as the sniffer port
CRC Checking Disable
When set, the received CRC error packet also accept to receive memory
Reserved
6.2.18 Per Port Index Register (CR17)
Bit
31:8
8
Name
RESERVED
BANK_REG
Default
0,RO
0,RW
7:6
5
4:2
1:0
MONITOR
BLOCK
RESERVED
INDEX
00,RW
0,RW
0,RO
0,RW
Description
Reserved
0: CR18 ~ 31 is accessed with bank 0
1: CR18 ~ 31 is accessed with bank 1
Reserved, 00 in application.
1: for write CR20[31:16] BLOCK mode
Reserved
Port index for register CR17~22
Write the port number to this register before write/read register CR17~22.
Note that the processor port INDEX number is 3
6.2.19 Per Port Control Register (CR18)
If BANK_REG = 0:
Bit
Name
Default
Description
31
TAG_OUT
0,RW
Output Packet Tagging Enable
The transmitted packets contain VLAN tagged field
30
PRI_DIS
0,RO
Priority Queue Disable
Only one transmit queue is supported in this port.
29
WFQUE
0,RW
Weighted Fair Queuing
1: The priority weight for queue 3,2,1, and 0 is 8,4,2, and 1 respectively.
0: The queue 3 has the highest priority, and the next priorities are queue
2,1, and 0 respectively.
28
TOS_PRI
0,RW
Priority ToS over VLAN
If a IP packet with VLAN tag, the priority of this packet is decode from ToS
field.
27
TOS_OFF
0,RW
ToS Priority Classification Disable
The priority information from ToS field of IP packet is ignored.
26
PRI_OFF
0,RW
802.1 p Priority Classification Disable
The priority information from VLAN tag field is ignored.
25:24 P_PRI
0,RW
Port Base priority
The priority queue number in port base.
00= queue 0, 01=queue 1, 10=queue 2, 11=queue 3
34
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
23:20
BSTH
0,RW
19:16
BW CTRL
0,RW
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
Broadcast Storm Threshold
These bits define the bandwidth threshold that received broadcast packets over the
threshold are discarded
0000: no broadcast storm control
0001: 8K packets/sec
0010: 16K packets/sec
0011: 64K packets/sec
0100: 5%
0101: 10%
0110: 20%
0111: 30%
1000: 40%
1001: 50%
1010: 60%
1011: 70%
1100: 80%
1101: 90%
111X: no broadcast storm control
Received packet length counted. Bandwidth table below.
These bits define the bandwidth threshold that transmitted or received packets over
the threshold are discarded
000X: none
0000: none
0001: 64Kbps
0010: 128Kbps
0011: 256Kbps
0100: 512Kbps
0101: 1Mbps
0110: 2Mbps
0111: 4Mbps
1000: 8Mbps
1001: 16Mbps
1010: 32Mbps
1011: 48Mbps
1100: 64Mbps
1101: 72Mbps
1110: 80Mbps
1111: 88Mbps
35
DM9106
3-port switch with PCI Interface
15:12
INGRESS
0,RW
11:8
EGRESS
0,RW
7
6
5
FAST_LEV
PARTI_EN
NO_DIS_R
X
0,RW
0,RW
0,RW
4
FLOW_DIS
0,RW
3
BANDWIDT
H
0,RW
36
Ingress Rate Control
These bits define the bandwidth threshold that received packets over the threshold
are discarded.
0000: none
0001: 64Kbps
0010: 128Kbps
0011: 256Kbps
0100: 512Kbps
0101: 1Mbps
0110: 2Mbps
0111: 4Mbps
1000: 8Mbps
1001: 16Mbps
1010: 32Mbps
1011: 48Mbps
1100: 64Mbps
1101: 72Mbps
1110: 80Mbps
1111: 88Mbps
Egress Rate Control
These bits define the bandwidth threshold that transmitted packets over the
threshold are discarded.
0000: none
0001: 64Kbps
0010: 128Kbps
0011: 256Kbps
0100: 512Kbps
0101: 1Mbps
0110: 2Mbps
0111: 4Mbps
1000: 8Mbps
1001: 16Mbps
1010: 32Mbps
1011: 48Mbps
1100: 64Mbps
1101: 72Mbps
1110: 80Mbps
1111: 88Mbps
IGMP Snooping Fast Leave Enable
Enable Partition Detection
Not Discard RX Packets when Ingress Bandwidth Control
When received packets bandwidth reach Ingress bandwidth threshold, the
packets over the threshold are not discarded but with flow control.
Flow control in full duplex mode, or back pressure in half duplex mode
enable
0 – enable
1 – disable
Bandwidth Control
0: Control with Ingress and Egress separately in bit 15~12 and bit 11~8.
1: Control with Ingress or Egress in bit 19~16
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
2
BP_DIS
0,RW
1
MP_DIS
0,RW
0
MP_STORM
0,RW
Port Security Register (CR18)
If BANK_REG = 1:
Bit
Name
Default
31:6 RESERVED
0,RO
5:4
STPS
PH0,RW
3
2
RESERVED
PS_UNK
0,RO
PH0,RW
1:0
PS_EN
PH0,RW
Broadcast packet filter
0 – accept broadcast packets
1 – reject broadcast packets
Multicast packet filter
0 – accept multicast packets
1 – reject multicast packets
Broadcast Storm Control
0 – only broadcast packet
1 – also multicast packet
Description
Reserved
Spanning Tree Port Status
There are 4 port status for supporting Spanning Tree Protocol
00: Forwarding State, The port transmits and receives packets normally & learning
is enabled.
01: Disabled State, The port will not transmit and receive any packets & learning is
disabled.
10: Learning State, The port will only forward the packets that are to and from uP
port (span packets) & leaning is enabled.
11: Blocking/Listening State, The port will only forward the packets that are to and
from uP port (span packets) & leaning is disabled.
Reserved
Unknown source address handling when port security is enabled
0: Discard Unknown (Default)
1: Unknown to uP Port
Port Security Enable
00: Port Security Disable (Default)
01: First Lock
10: First Link Lock
11: Assign Lock
6.2.20 Per Port Status Data Register (CR19)
Bit
31
30
Name
LOOPBACK
MONI_TX
Default
0,RW
0,RW
29
MONI_RX
0,RW
28
DIS_BMP
27
26
RESERVED
TX_DIS
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
0,RW
0,RO
0,RW
Description
Loop-back mode
TX Packet Monitored
The transmitted packets are also forward to sniffer port.
RX Packet Monitored
The received packets are also forward to sniffer port
Broad/Multicast Not Monitored
The received broadcast or multicast packets are not forward to sniffer
port.
Reserved
Packet Transmit Disabled
All packets can not be forward to this port.
37
DM9106
3-port switch with PCI Interface
25
RX_DIS
0,RW
24
ADR_DIS
0,RW
23~6
5
4
RESERVED
LP_FCS
BIST
0,RO
0,RO
0,RO
3
2
RESERVED
SPEED2
0,RO
RO
1
FDX2
RO
0
LINK2
RO
Packet receive Disabled
All received packets are discarded.
Address Learning Disabled
The Source Address (SA) field of packet is not learned to address table.
Reserved
Link Partner Flow Control Enable Status
BIST status
1: SRAM BIST fail
0: SRAM BIST pass
Reserved
PHY Speed Status
0: 10Mbps, 1:100Mbps
PHY Duplex Status
0: half-duplex, 1:full-duplex
PHY Link Status
0: link fail, 1: link OK
IGMP Snooping 1 Register (CR19)
If BANK_REG = 1:
Bit
31:26
25:24
Name
RESERVED
RV
Default
0,RO
RW
23:16
QI
RW
15
SCP_PE
PH0,R
W
14:13
SCP_PRI
PH0,R
W
12:11
SCP_OTC
PH0,R
W
10:8
RPP
PH0,R
W
7
RESERVED
0,RO
38
Description
Reserved
Robustness Variable
Define Robustness Variable when Hardware-IGS is enabled.
00 = Reserved
01 = 1 times
10 = 2 times (Default)
11 = 3 times
Query Interval
Define Query Interval when Hardware-IGS is enabled
Snooping Control Packet Priority Enable
0: Disable
1: Enable
Snooping Control Packet Priority
00: Queue 0
01: Queue 1
10: Queue 2
11: Queue 3
Snooping Control Packet Output Tag Control
00: Unmodified
01: Always Tagged
10: Always Untagged
11: Reserved
Router Port Portmap
If User-defined IGMP Router Port Configuration is enabled, this 3-bit register is
used to define static router portmap, otherwise, this register is automatic
manipulation by IGMP snooping and read only.
Reserved
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
6:5
UIPMPC
PH0,R
W
4
UD_IGR
PH0,R
W
3
SIGS2UP
2
HIGS2UP
PH0,R
W
PH0,R
W
1
SIGS_EN
PH0,R
W
0
IGS_EN
PH0,R
W
Unregistered IP Multicast Packet Control
The IP multicast packet with a destination address which does not match any of
groups announced in earlier IGMP Membership Reports, i.e. not found in the IGMP
membership table.
00: As normal multicast packets
01: Dropped.
10: Force forward to processor port.
11: Forward to all ports except incoming & uP port.
User-defined IGMP Router Port Configuration Enable
0: Disable, the router portmap is automatic manipulation via IGMP snooping.
1: Enable, the router portmap is static defined by user.
IGMP Packet Forward to uP Port only when Software-IGS
IGMP Packet Forward to uP Port also when Hardware-IGS
0: IGMP packet doesn’t forwards to processor port when Hardware based IGMP
Snooping is enabled.
1: IGMP packet also forwards to processor port when Hardware based IGMP
Snooping is enabled.
Software-based IGMP Snooping Enable
0: Hardware based IGMP Snooping, without software intervention. (default)
1: Software based IGMP Snooping
IGMP Snooping Enable
0: Disable
1: Enable
6.2.21 Per Port VLAN Tag Byte Register (CR20)
Bit
31:28
Name
BLK_UKP
27:24
BLK_BP
0,RW
23:20
BLK_MP
0,RW
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
Default
0,RW
Description
Ports of Unknown Packet Be Blocked
The packets with DA field not found in address table are not forward to the
assigned ports.
These bits can be written if CR17.5=1
Ports of Broadcast Packet Be Blocked
The received broadcast packets are not forward to the assigned ports.
These bits can be written if CR17.5=1
Ports of Multicast Packet Be Blocked
The received multicast packets are not forward to the assigned ports.
These bits can be written if CR17.5=1
39
DM9106
3-port switch with PCI Interface
19:16
15:13
12
11:0
BLK_UP
PRI
CFI
VID118
0,RW
0,RW
0,RW
0,RW
Ports of Unicast Packet Be Blocked
The received unicast packets are not forward to the assigned ports.
Note that the assigned port definition: bit 0 for port 0, bit 1 for port 1, bit 2 for
port 2, and bit 3 for processor port.
These bits can be written if CR17.5=1
Port VLAN Tag [15:13]
Port VLAN Tag[12]
Port VLAN VID[11:0]
IGMP Snooping 2 Register (CR20)
If BANK_REG = 1:
Bit
31:2
2
Name
RESERVED
MLDS_OPT
Default
0,RO
PH0,RW
1
0
MLD2UP
MLDS_EN
PH0,RW
PH0,RW
Description
Reserved
MLD Snooping Option Enable
0: Disable
1: Enable
MLD Packet Forward to uP Port only.
MLD Snooping Enable
0: Disable
1: Enable
6.2.22 Per Port MIB counter Index Register (CR21)
Bit
31:8
7
Name
RESERVED
READY
Default
0,RO
0,RO
6:5
4:0
RESERVED
INDEX
0,RO
0,RW
40
Description
Reserved
MIB counter data is ready
When this register is written with INDEX data, this bit is cleared and the MIB counter
reading is in progress. After end of read MIB counter, the MIB data is loaded into
CR22, and this bit is set to indicate that the MIB data is ready, and then the MIB
data of this INDEX is cleared.
Reserved
MIB counter index
00H: RX Byte Counter
01H: RX Uni-cast Packet Counter
02H: RX Multi-cast Packet Counter
03H: RX Discard Packet Counter
04H: RX Error Packet Counter
05H: TX Byte Counter
06H: TX Uni-cast Packet Counter
07H: TX Multi-cast Packet Counter
08H: TX Discard Packet Counter
09H: TX Error Packet Counter
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
Ethernet Address Control Status Register (CR21)
If BANK_REG = 1:
Bit
31:8
7
6:5
Name
RESERVED
RESERVED
EAS
Default
0,RO
0,RO
P0,RO
4
3
RESERVED
TAB_INDEX
0,RO
PHY,RW
2:1
EAC
PH0,RW
0
Busy
P0,RO
Description
Reserved
Reserved
Ethernet Address Status
00: Command OK, Entry Non-exist
a. Create an new entry when command is write
b. Do nothing when command is delete
c. Entry not found when command is search
01: Command OK, Entry Exist
a. Overwrite the entry when command is write
b. Delete entry when command is delete
c. Entry found when command is search
1X: Command Error
Reserved
Table Index
0: Unicast Address Table
1: Multicast Address Table
Ethernet Address Command
00: Reserved
01: Write
10: Delete
11: Search
0: Available
1: Busy
6.2.23 MIB counter Data Register (CR22)
Bit
Name
Default
31:0
MIB_DATA
0,RO
MIB counter data
Description
6.2.24 VLAN priority Map Register (CR23)
Define the 3-bit of priority field VALN mapping to 2-bit priority queue number
Bit
31:12
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
Name
RESERVED
TAG7
TAG6
TAG5
TAG4
TAG3
TAG2
TAG1
TAG0
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
Default
0,RO
3,RW
3,RW
2,RW
2,RW
1,RW
1,RW
0,RW
0,RW
Description
Reserved
VLAN priority tag value = 07h
VLAN priority tag value = 06h
VLAN priority tag value = 05h
VLAN priority tag value = 04h
VLAN priority tag value = 03h
VLAN priority tag value = 02h
VLAN priority tag value = 01h
VLAN priority tag value = 00h
41
DM9106
3-port switch with PCI Interface
6.2.25 Ethernet Address Data 1,2 Register (CR22,CR23)
If BANK_REG = 1:
Ethernet Address Data Register (CR22)
Bit
Name
Default
Description
31:0
EAD31_0
0,RO
MAC Address bit 31~00
Ethernet Address Data Register (CR23)
Bit
Name
Default
Description
31:22
RESERVED
0,RO
Reserved
21
IGMPE
PH0,R 1: IGMP Entry
O
When reading multicast address table, this bit indicated the entry is IGMP entry or
not.
EA_STATIC
20
PH0,R 0: This entry is dynamic.
W
1: This entry is static, never age-out
When writing unicast address table, this bit can be used to set the entry as static or
dynamic. When reading unicast address table, it indicated the entry is static or
dynamic.
19:16
PORT
PH0,R Forwarding Port Number (0~3), when access Unicast Address Table.
W
Forwarding Port Mapping {uP, P2, P1, P0}, when access Multicast Address Table.
15:0
EAD47_32
0,RW
MAC Address bit 47~32
6.2.26 Port-based VLAN mapping table register 0 (CR24)
Define the port member in VLAN group
There are 16 VLAN groups that defined in (CR24) – (CR27)
Group 0 defined in CR24 Bit 3:0 , group 1 defined in CR24 Bit 11:8, … and group 15 defined in CR27 Bit 27:24.
.
Bit
Name
Default
Description
31:28
RESERVED
0,RO
Reserved
27:24
GROUP3
F,RW
Group 3 member:Port 3(uP),2~0
23:20
RESERVED
0,RO
Reserved
19:16
GROUP2
F,RW
Group 2 member:Port 3(uP) 2~0
15:12
RESERVED
0,RO
Reserved
11:8
GROUP1
F,RW
Group 1 member:Port 3(uP)2~0
7:4
RESERVED
0,RO
Reserved
3:0
GROUP0
F,RW
Group 0 member : Port 3(uP)2~0
PCI/Port 2 driving capability Register (CR24)
If BANK_REG = 1:
Bit
Name
Default
Description
31:15
RESERVED
0,RO
Reserved
Port 2 TXD/TXECurrent Driving/Sinking Capability
14:13
00: 2mA
P01,R
P2_CURR
01: 4mA (default)
W
10: 6mA
11: 8mA
RESERVED
0,RW
Reserved
12:7
42
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
6:5
4:0
PCI_CURR
P01,R
W
RESERVED
0,RW
PCI Bus Current Driving/Sinking Capability
00: 2mA
01: 4mA (default)
10: 6mA
11: 8mA
Reserved
6.2.27 Port-based VLAN mapping table register 1 (CR25)
Bit
31:28
27:24
23:20
19:16
15:12
11:8
7:4
3:0
Name
RESERVED
GROUP7
RESERVED
GROUP6
RESERVED
GROUP5
RESERVED
GROUP4
Default
0,RO
F,RW
0,RO
F,RW
0,RO
F,RW
0,RO
F,RW
Description
Reserved
Group 7 member:Port 3(uP)2~0
Reserved
Group 6 member:Port 3(uP)2~0
Reserved
Group 5 member:Port 3(uP)2~0
Reserved
Group 4 member : Port3(uP) 2~0
6.2.28 Port-based VLAN mapping table register 2 (CR26)
Bit
Name
Default
Description
31:28
RESERVED
0,RO
Reserved
27:24
GROUP11
F,RW
Group 11 member:Port 3(uP) 2~0
23:20
RESERVED
0,RO
Reserved
19:16
GROUP10
F,RW
Group 10 member:Port 3(uP) 2~0
15:12
RESERVED
0,RO
Reserved
11:8
GROUP9
F,RW
Group 9 member:Port 3(uP) 2~0
7:4
RESERVED
0,RO
Reserved
3:0
GROUP8
F,RW
Group 8 member : Port 3(uP) 2~0
6.2.29 Port-based VLAN mapping table register 3 (CR27)
Bit
Name
Default
Description
31:28
RESERVED
0,RO
Reserved
27:24
GROUP15
F,RW
Group 15 member:Port 3(uP) 2~0
23:20
RESERVED
0,RO
Reserved
19:16
GROUP14
F,RW
Group 14 member:Port 3(uP) 2~0
15:12
RESERVED
0,RO
Reserved
11:8
GROUP13
F,RW
Group 13 member:Port 3(uP) 2~0
7:4
RESERVED
0,RO
Reserved
3:0
GROUP12
F,RW
Group 12 member : Port 3(uP) 2~0
6.2.30 TOS Priority Map Register 0 (CR28)
Define the 6-bit or 3-bit of ToS field mapping to 2-bit priority queue number.
In 6-bit type, the CR16 bit 15 is “1”, CR28 bit [1:0] define the mapping for ToS value 0, CR28 bit [3:2] define the mapping for
ToS value 1, … and so on, till CR31 bit [31:30] define ToS value 63.
In 3-bit type, CR28 bit [1:0] define the mapping for ToS value 0, CR28 bit [3:2] define the mapping for ToS value 1, … and so
on, till CR28 bit [15:14] define ToS value 7.
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
43
DM9106
3-port switch with PCI Interface
Bit
31:30
29:28
27:26
25:24
23:22
21:20
19:18
17:16
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
Name
TOSF
TOSE
TOSD
TOSC
TOSB
TOSA
TOS9
TOS8
TOS7
TOS6
TOS5
TOS4
TOS3
TOS2
TOS1
TOS0
Default
0,RW
0,RW
0,RW
0,RW
0,RW
0,RW
0,RW
0,RW
0/3,RW
0/3,RW
0/2,RW
0/2,RW
0/1,RW
0,/1RW
0,RW
0,RW
Description
If bit 15 of CR16 =1 :TOS[7:2]=0Fh
If bit 15 of CR16 =1 :TOS[7:2]=0Eh
If bit 15 of CR16 =1 :TOS[7:2]=0Dh
If bit 15 of CR16 =1 :TOS[7:2]=0Ch
If bit 15 of CR16 =1 :TOS[7:2]=0Bh
If bit 15 of CR16 =1 :TOS[7:2]=0Ah
If bit 15 of CR16 =1 :TOS[7:2]=09h
If bit 15 of CR16 =1 :TOS[7:2]=08h
If bit 15 of CR16 =1 :TOS[7:2]=07h, otherwise TOS]7:5]=07h
If bit 15 of CR16 =1 :TOS[7:2]=06h, otherwise TOS]7:5]=06h
If bit 15 of CR16 =1 :TOS[7:2]=05h, otherwise TOS]7:5]=05h
If bit 15 of CR16 =1 :TOS[7:2]=04h, otherwise TOS]7:5]=04h
If bit 15 of CR16 =1 :TOS[7:2]=03h, otherwise TOS]7:5]=03h
If bit 15 of CR16 =1 :TOS[7:2]=02h, otherwise TOS]7:5]=02h
If bit 15 of CR16 =1 :TOS[7:2]=01h, otherwise TOS]7:5]=01h
If bit 15 of CR16 =1 :TOS[7:2]=00h, otherwise TOS]7:5]=00h
6.2.31 TOS Priority Map Register 1 (CR29)
Bit
31:30
29:28
27:26
25:24
23:22
21:20
19:18
17:16
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
Name
TOS1F
TOS1E
TOS1D
TOS1C
TOS1B
TOS1A
TOS19
TOS18
TOS17
TOS16
TOS15
TOS14
TOS13
TOS12
TOS11
TOS10
Default
1,RW
1,RW
1,RW
1,RW
1,RW
1,RW
1,RW
1,RW
1,RW
1,RW
1,RW
1,RW
1,RW
1,RW
1,RW
1,RW
Description
If bit 15 of CR16 =1 :TOS[7:2]=1Fh
If bit 15 of CR16 =1 :TOS[7:2]=1Eh
If bit 15 of CR16 =1 :TOS[7:2]=1Dh
If bit 15 of CR16 =1 :TOS[7:2]=1Ch
If bit 15 of CR16 =1 :TOS[7:2]=1Bh
If bit 15 of CR16 =1 :TOS[7:2]=1Ah
If bit 15 of CR16 =1 :TOS[7:2]=19h
If bit 15 of CR16 =1 :TOS[7:2]=18h
If bit 15 of CR16 =1 :TOS[7:2]=17h
If bit 15 of CR16 =1 :TOS[7:2]=16h
If bit 15 of CR16 =1 :TOS[7:2]=15h
If bit 15 of CR16 =1 :TOS[7:2]=14h
If bit 15 of CR16 =1 :TOS[7:2]=13h
If bit 15 of CR16 =1 :TOS[7:2]=12h
If bit 15 of CR16 =1 :TOS[7:2]=11h
If bit 15 of CR16 =1 :TOS[7:2]=10h
6.2.32 TOS Priority Map Register 2 (CR30)
Bit
Name
Default
Description
31:30
TOS2F
2,RW
If bit 15 of CR16 =1 :TOS[7:2]=2Fh
29:28
TOS2E
2,RW
If bit 15 of CR16 =1 :TOS[7:2]=2Eh
27:26
TOS2D
2,RW
If bit 15 of CR16 =1 :TOS[7:2]=2Dh
25:24
TOS2C
2,RW
If bit 15 of CR16 =1 :TOS[7:2]=2Ch
23:22
TOS2B
2,RW
If bit 15 of CR16 =1 :TOS[7:2]=2Bh
21:20
TOS2A
2,RW
If bit 15 of CR16 =1 :TOS[7:2]=2Ah
44
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
19:18
17:16
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
TOS29
TOS28
TOS27
TOS26
TOS25
TOS24
TOS23
TOS22
TOS21
TOS20
2,RW
2,RW
2,RW
2,RW
2,RW
2,RW
2,RW
2,RW
2,RW
2,RW
If bit 15 of CR16 =1 :TOS[7:2]=29h
If bit 15 of CR16 =1 :TOS[7:2]=28h
If bit 15 of CR16 =1 :TOS[7:2]=27h
If bit 15 of CR16 =1 :TOS[7:2]=26h
If bit 15 of CR16 =1 :TOS[7:2]=25h
If bit 15 of CR16 =1 :TOS[7:2]=24h
If bit 15 of CR16 =1 :TOS[7:2]=23h
If bit 15 of CR16 =1 :TOS[7:2]=22h
If bit 15 of CR16 =1 :TOS[7:2]=21h
If bit 15 of CR16 =1 :TOS[7:2]=20h
6.2.33 TOS Priority Map Register 3 (CR31)
Bit
Name
Default
Description
31:30
TOS3F
3,RW
If bit 15 of CR16 =1 :TOS[7:2]=3Fh
29:28
TOS3E
3,RW
If bit 15 of CR16 =1 :TOS[7:2]=3Eh
27:26
TOS3D
3,RW
If bit 15 of CR16 =1 :TOS[7:2]=3Dh
25:24
TOS3C
3,RW
If bit 15 of CR16 =1 :TOS[7:2]=3Ch
23:22
TOS3B
3,RW
If bit 15 of CR16 =1 :TOS[7:2]=3Bh
21:20
TOS3A
3,RW
If bit 15 of CR16 =1 :TOS[7:2]=3Ah
19:18
TOS39
3,RW
If bit 15 of CR16 =1 :TOS[7:2]=39h
17:16
TOS38
3,RW
If bit 15 of CR16 =1 :TOS[7:2]=38h
15:14
TOS37
3,RW
If bit 15 of CR16 =1 :TOS[7:2]=37h
13:12
TOS36
3,RW
If bit 15 of CR16 =1 :TOS[7:2]=36h
11:10
TOS35
3,RW
If bit 15 of CR16 =1 :TOS[7:2]=35h
9:8
TOS34
3,RW
If bit 15 of CR16 =1 :TOS[7:2]=34h
7:6
TOS33
3,RW
If bit 15 of CR16 =1 :TOS[7:2]=33h
5:4
TOS32
3,RW
If bit 15 of CR16 =1 :TOS[7:2]=32h
3:2
TOS31
3,RW
If bit 15 of CR16 =1 :TOS[7:2]=31h
1:0
TOS30
3,RW
If bit 15 of CR16 =1 :TOS[7:2]=30h
6.3 Descriptor List
Refer to Section 9.1 “PCI Bus Buffer Management” for the description of the descriptor list.
6.3.1 Receive Descriptor Format
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
45
DM9106
6.3.1.1 Receive Status Register (RDES0)
Bit
31
30
29:16
15
14
13
Name
OWN
RAU
FL
ES
DUE
IP_CSUM
Default
0,RO
0,RO
0,RO
0,RO
0,RO
0,RO
12
TCP_CSUM
0,RO
11:10
PKT_TYPE
0,RO
9
8
7:6
5
4
3
2
1
0
BD
ED
SRCP
FT
TCP
PLE
RESERVED
CRCE
RESERVED
0,RO
0,RO
0,RO
0,RO
0,RO
0,RO
0,RO
0,RO
0,RO
Description
Owner bit of received status
Received address unmatched
Frame Length
Error Summary
Descriptor Unavailable Error
IP chksum status
0: OK
1: Fail
TCP/UDP chksum status
0: OK
1: Fail
Received Frame TYPE
00: Reserved
01: IGMP packet
10: MLD packet
11: BPDU packet
Begin Descriptor
End Descriptor
Source Port Number if IGMP snooping enabled
Frame Type or IP packet
TCP packet
Physical Layer Error or UDP packet
Reserved
CRC Error
reserved
6.3.1.2 Receive Descriptor Control and Buffer Size Register (RDES1)
Bit
Name
Default
Description
31:25 RESERVED
0,RW
Reserved
24
CHAIN
0,RW
Chain Mode
Must be set to 1 in application
23:12 RESERVED
0,RW
Reserved
10:0
BL
0,RW
Buffer Length
6.3.1.3 Buffer Starting Address Register (RDES2)
Bit
Name
Default
Description
31:0
N_BUF
0,RW
Buffer start address, bit 1~0 should be set 0
6.3.1.4 Next descriptor Address Register (RDES3)
Bit
Name
Default
Description
31:0
N_ADR
0,RW
Next descriptor address, bit 2~0 should be set 0
Preliminary datasheet
DM9106-DS-P02
June 01, 2007
46
DM9106
3-port switch with PCI Interface
6.3.2 Transmit Descriptor Format
31
0
OWN
OWN
TDES0
Status
Control
bits
Buffer Length
TDES1
Buffer Address
TDES2
Next Descriptor Address
TDES3
6.3.2.1 Transmit Status Register (TDES0)
Bit
31
30:16
15
14:10
9
8
7
6:3
2
1
0
Name
OWN
RESERVED
ES
RESERVED
LC
EC
RESERVED
CC
RESERVED
FUE
DF
Default
0,RO
0,RO
0,RO
0,RO
0,RO
0,RO
0,RO
0,RO
0,RO
0,RO
0,RO
Description
Owner bit of transmit status
Reserved
Error Summary
Reserved
Late Collision
Excessive collision
Reserved
Collision Count
Reserved
FIFO Underrun Error
Deferred
6.3.2.2 Transmit buffer control and buffer size Register (TDES1)
Bit
31:11
30
29
28
27
26
25
24
Name
CI
ED
BD
FB1
SF
CAD
RESERVED
CHAIN
Default
0,RW
0,RW
0,RW
0,RW
0,RW
0,RW
0,RW
0,RW
23
22
21
20
19
18:11
10:0
RESERVED
FB0
IP
TCP
UDP
RESERVED
BL
0,RW
0,RW
0,RW
0,RW
0,RW
0,RW
0,RW
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
Description
Completion Interrupt
Ending Descriptor
Begin Descriptor
Filtering Mode Bit 1
Setup Frame
CRC Append Disable
Reserved
Chain Mode
Must be set to 1 in application
Reserved
Filtering Mode Bit 0
IP Packet Checksum Generation
TCP Packet Checksum Generation
UDP Packet Checksum Generation
Reserved
Buffer Length
47
DM9106
3-port switch with PCI Interface
Bit
31:0
Name
BUFADR
Default
0,RW
Description
Buffer start address bit 31:00
6.3.2.3 Next descriptor Address Register (TDES3)
Bit
31:0
48
Name
NADR
Default
0,RO
Description
Next descriptor address, bit 2~0 should be set 0.
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
7. PCI mode EEPROM Format
The first 48 words of Configuration EEPROM are loaded into the DM9106 after power-on-reset for the settings of the power
management, system ID and Ethernet address. The format of the EEPROM is as followed
name
Subsystem Vendor ID
Subsystem ID
RESERVED
Auto_ Load_ Control
PCI Vendor ID
Word offset
0
1
2~3
4
5
PCI Device ID
6
PMC
7
RESERVED
Ethernet Address
8~9
10~12
RESERVED
Control
13~15
16
Switch Control 1
17
Switch Control 2
18
Port 0 Control 1
19
Port 0 Control 2
20
Port 1 Control 1
21
Port 1 Control 2
22
Port 2 Control 1
23
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
Description
The content will be transferred into the PCI configuration space 2CH bit
15~0.
The content will be transferred into the PCI configuration space 2CH bit
31~16.
Reserved
Bit3~0: “1010” to enable auto-load of PCI Vendor_ ID & Device_ ID.
When Word[4] bit 3~0=”1010”, this word will be loaded to PCI
Configuration space address 0 bit 15~0
When Word[4] bit 3~0=”1010”, this word will be loaded to PCI
Configuration space address 0 bit 31~16
Bit2~0: Directly mapping to bit[21,26:25] of the PCIPMR
Bit7~3: Directly mapping to bit[31:27] of the PCIPMR.
Bit 15~8: Reserved
Reserved
Word 10 low byte for address 0
Word 10 high byte for address 1
Word 11 low byte for address 2
Word 11 high byte for address 3
Word 12 low byte for address 4
Word 12 high byte for address 5
Reserved
Bit 1:0=01: Accept setting of WORD 17,18
Bit 3:2=01: Accept setting of WORD 19~26
Bit 5:4=01: Accept setting of WORD 27~30
Bit 7:6=01: Accept setting of WORD 31
Bit 9:8=01: Accept setting of WORD 32~39
Bit 11:10=01: Accept setting of WORD 40~47
Bit 13:12 =01: Accept setting of WORD 49~52
Bit 15:14 Reserved
When word 16 bit 1:0 is “01”, after power on reset:
This word will be loaded to CR16 bit 15~0
When word 16 bit 1:0 is “01”, after power on reset:
This word will be loaded to CR16 bit 31~16
When word 16 bit 3:2 is “01”, after power on reset:
This word will be loaded to port 0 CR18 bit 15~0
When word 16 bit 3:2 is “01”, after power on reset:
This word will be loaded to port 0 CR18 bit 31~16
When word 16 bit 3:2 is “01”, after power on reset:
This word will be loaded to port 1 CR18 bit 15~0
When word 16 bit 3:2 is “01”, after power on reset:
This word will be loaded to port 1 CR18 bit 31~16
When word 16 bit 3:2 is “01”, after power on reset:
49
DM9106
3-port switch with PCI Interface
Port 2 Control 2
24
uP Port Control 1
25
uP Port Control 2
26
Port 0 VLAN Tag
27
Port 1 VLAN Tag
28
Port 2 VLAN Tag
29
uP Port VLAN Tag
30
VLAN Priority Map
31
Port VLAN Group
0,1
Port VLAN Group
2,3
Port VLAN Group
4,5
Port VLAN Group
6,7
Port VLAN Group
8,9
Port VLAN Group
10,11
Port VLAN Group
12,13
Port VLAN Group
14,15
ToS Priority Map 0
32
ToS Priority Map 1
41
ToS Priority Map 2
42
ToS Priority Map 3
43
ToS Priority Map 4
44
ToS Priority Map 5
45
ToS Priority Map 6
46
ToS Priority Map 7
47
50
33
34
35
36
37
38
39
40
This word will be loaded to port 2 CR18 bit 15~0
When word 16 bit 3:2 is “01”, after power on reset:
This word will be loaded to port 2 CR18 bit 31~16
When word 16 bit 3:2 is “01”, after power on reset:
This word will be loaded to port 3 CR18 bit 15~0
When word 16 bit 3:2 is “01”, after power on reset:
This word will be loaded to port 3 CR18 bit 31~16
When word 16 bit 5:4 is “01”, after power on reset:
This word will be loaded to port 0 CR20 bit 15~0
When word 16 bit 5:4 is “01”, after power on reset:
This word will be loaded to port 1 CR20 bit 15~0
When word 16 bit 5:4 is “01”, after power on reset:
This word will be loaded to port 2 CR20 bit 15~0
When word 16 bit 5:4 is “01”, after power on reset:
This word will be loaded to port 3 CR20 bit 15~0
When word 16 bit 7:6 is “01”, after power on reset:
This word will be loaded to CR23 bit 15~0
When word 16 bit 9:8 is “01”, after power on reset:
This word will be loaded to CR24 bit 15~0
When word 16 bit 9:8 is “01”, after power on reset:
This word will be loaded to CR24 bit 31~16
When word 16 bit 9:8 is “01”, after power on reset:
This word will be loaded to CR25 bit 15~0
When word 16 bit 9:8 is “01”, after power on reset:
This word will be loaded to CR25 bit 31~16
When word 16 bit 9:8 is “01”, after power on reset:
This word will be loaded to CR26 bit 15~0
When word 16 bit 9:8 is “01”, after power on reset:
This word will be loaded to CR26 bit 31~16
When word 16 bit 9:8 is “01”, after power on reset:
This word will be loaded to CR27 bit 15~0
When word 16 bit 9:8 is “01”, after power on reset:
This word will be loaded to CR27 bit 31~16
When word 16 bit 11:10 is “01”, after power on reset:
This word will be loaded to CR28 bit 15~0
When word 16 bit 11:10 is “01”, after power on reset:
This word will be loaded to CR28 bit 31~16
When word 16 bit 11:10 is “01”, after power on reset:
This word will be loaded to CR29 bit 15~0
When word 16 bit 11:10 is “01”, after power on reset:
This word will be loaded to CR29 bit 31~16
When word 16 bit 11:10 is “01”, after power on reset:
This word will be loaded to CR30 bit 15~0
When word 16 bit 11:10 is “01”, after power on reset:
This word will be loaded to CR30 bit 31~16
When word 16 bit 11:10 is “01”, after power on reset:
This word will be loaded to CR31 bit 15~0
When word 16 bit 11:10 is “01”, after power on reset:
This word will be loaded to CR31 bit 31~16
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
reserved
Port Security Control
48
49
Snooping Control 1
50
Snooping Control 2
51
Snooping Control 3
52
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
reserved
When word 16 bit 13:12 is “01”, after power on reset:
This word bit 2~0 will be loaded to port 0 bank 1 CR17 bit 2~0
This word bit 10~8 will be loaded to port 1 bank 1 CR17 bit 2~0
This word bit 18~16 will be loaded to port 2 bank 1 CR17 bit 2~0
When word 16 bit 13:12 is “01”, after power on reset:
This word will be loaded to bank 1 CR19 bit 15~0
When word 16 bit 13:12 is “01”, after power on reset:
This word will be loaded to bank 1 CR19 bit 31~16
When word 16 bit 13:12 is “01”, after power on reset:
This word bit 1~0 will be loaded to bank 1 CR20 bit 1~0
51
DM9106
3-port switch with PCI Interface
8. PHY Registers
MII Register Description
ADD Name
15
00H CONTR Reset
OL
0
01H STATUS T4
Cap.
0
02H PHYID1
0
03H PHYID2
1
14
Loop
back
0
TX FDX
Cap.
1
0
0
13
12
11
Speed Auto-N Power
select
Enable Down
1
1
0
TX HDX 10 FDX 10 HDX
Cap.
Cap.
Cap.
1
1
1
0
0
0
1
1
1
04H Auto-Neg. Next
Advertise Page
05H Link Part. LP
Ability
Next
Page
06H Auto-Neg.
Expansio
n
10H Specifie BP
d
4B5B
Config.
11H Specifie 100
FDX
d
Conf/Stat
12H
10T
Rsvd
Conf/Stat
FLP Rcv
Ack
LP
Ack
Remote
Fault
LP
RF
Reserved
Reserved
10
Isolate
0
9
8
Restart
Full
Auto-N Duplex
0
1
Reserved
7
Coll.
Test
0
6
5
Pream. Auto-N
Supr.
Compl.
0000
1
0
0
1
1
0
0
Model No.
01011
T4
TX FDX TX HDX 10 FDX 10 HDX
Adv
Adv
Adv
Adv
Adv
LP
LP
LP
LP
LP
T4
TX FDX TX HDX 10 FDX 10 HDX
0
0
FC
Adv
LP
FC
Reserved
BP
SCR
BP
BP_ADP Reserve
ALIGN
OK
dr
100
HDX
10
FDX
LP
Enable
HBE
Enable
13H PWDOR
TX
JAB
Enable
Pream.
Supr.
PHY ADDR [4:0]
PDchip
Extd
Cap.
1
1
New Pg LP AutoN
Rcv
Cap.
Sleep
mode
Remote
LoopOut
Auto-N. Monitor Bit [3:0]
Reserved
PD10DR PD100l
V
Reserved
0
Link Partner Protocol Selector Field
Reserve Reserve Force Reserve Reserve RPDCTR Reset
d
d
100LNK
d
d
-EN
St. Mch
Reserve
d
1
000_0000
Auto-N
Link
Jabber
Cap.
Status
Detect
1
0
0
0
0
0
Version No.
0000
Advertised Protocol Selector Field
Next Pg
Able
16H RCVER
17H DIS_conn
ect
2
LP Next
Pg Able
Reserved
14H Specified TSTSE1 TSTSE2 FORCE_ FORCE_
config
TXSD
FEF
Remote
Fault
0
0
3
Reserved
Pardet
Fault
10 HDX Reserve Reverse Reverse
d
d
d
SQUE
Enable
4
PDcrm
Polarity
Reverse
PDaeq
PDdrv
PDecli
PDeclo
PD10
MDIX_C AutoNeg Mdix_fix Mdix_do MonSel1 MonSel0 Reserve PD_valu
NTL
_dlpbk
Value
wn
d
e
Receiver Error Counter
Reversed
Disconnect_counter
Key to Default
In the register description that follows, the default
column takes the form:
<Reset Value>, <Access Type> / <Attribute(s)>
Where:
<Reset Value>:
1
Bit set to logic one
0
Bit set to logic zero
X
No default value
<Access Type>:
RO = Read only,
RW = Read/Write
<Attribute (s)>:
SC = Self clearing, P = Value permanently set
52
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
8.1 Basic Mode Control Register (BMCR) – 00H
Bit
15
Bit Name
Reset
14
Loopback
13
Speed selection
12
Auto-negotiation
enable
11
Power down
10
Isolate
9
Restart
Auto-negotiation
8
Duplex mode
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
Default
Description
0, RW/SC Reset
1=Software reset
0=Normal operation
This bit sets the status and controls the PHY registers to their
default states. This bit, which is self-clearing, will keep returning a
value of one until the reset process is completed
0, RW
Loopback
Loop-back control register
1 = Loop-back enabled
0 = Normal operation
When in 100Mbps operation mode, setting this bit may cause the
descrambler to lose synchronization and produce a 720ms "dead
time" before any valid data appears at the MII receive outputs
1, RW
Speed Select
1 = 100Mbps
0 = 10Mbps
Link speed may be selected either by this bit or by auto-negotiation.
When auto-negotiation is enabled and bit 12 is set, this bit will return
auto-negotiation selected medium type
1, RW
Auto-negotiation Enable
1 = Auto-negotiation is enabled, bit 8 and 13 will be in
auto-negotiation status
0, RW
Power Down
While in the power-down state, the PHY should respond to
management transactions. During the transition to power-down
state and while in the power-down state, the PHY should not
generate spurious signals on the MII
1=Power down
0=Normal operation
0,RW
Isolate
Force to 0 in application.
0,RW/SC Restart Auto-negotiation
1 = Restart auto-negotiation. Re-initiates the auto-negotiation
process. When auto-negotiation is disabled (bit 12 of this register
cleared), this bit has no function and it should be cleared. This bit is
self-clearing and it will keep returning to a value of 1 until
auto-negotiation is initiated by the DM9106. The operation of the
auto-negotiation process will not be affected by the management
entity that clears this bit
0 = Normal operation
1,RW
Duplex Mode
1 = Full duplex operation. Duplex selection is allowed when
Auto-negotiation is disabled (bit 12 of this register is cleared). With
auto-negotiation enabled, this bit reflects the duplex capability
selected by auto-negotiation
0 = Normal operation
53
DM9106
3-port switch with PCI Interface
7
Collision test
0,RW
6-0
Reserved
0,RO
Collision Test
1 = Collision test enabled. When set, this bit will cause the COL
signal to be asserted in response to the assertion of TX_EN in
internal MII interface.
0 = Normal operation
Reserved
Read as 0, ignore on write
8.2 Basic Mode Status Register (BMSR) – 01H
54
Bit
15
Bit Name
100BASE-T4
Default
0,RO/P
14
100BASE-TX
full-duplex
1,RO/P
13
100BASE-TX
half-duplex
1,RO/P
12
10BASE-T
full-duplex
1,RO/P
11
10BASE-T
half-duplex
1,RO/P
10-7
Reserved
0,RO
6
MF preamble
suppression
1,RO
5
Auto-negotiation
Complete
0,RO
4
Remote fault
0, RO
3
Auto-negotiation
ability
1,RO/P
2
Link status
0,RO
Description
100BASE-T4 Capable
1 = DM9106 is able to perform in 100BASE-T4 mode
0 = DM9106 is not able to perform in 100BASE-T4 mode
100BASE-TX Full Duplex Capable
1 = DM9106 is able to perform 100BASE-TX in full duplex mode
0 = DM9106 is not able to perform 100BASE-TX in full duplex mode
100BASE-TX Half Duplex Capable
1 = DM9106 is able to perform 100BASE-TX in half duplex mode
0 = DM9106 is not able to perform 100BASE-TX in half duplex
mode
10BASE-T Full Duplex Capable
1 = DM9106 is able to perform 10BASE-T in full duplex mode
0 = DM9106 is not able to perform 10BASE-TX in full duplex mode
10BASE-T Half Duplex Capable
1 = DM9106 is able to perform 10BASE-T in half duplex mode
0 = DM9106 is not able to perform 10BASE-T in half duplex mode
Reserved
Read as 0, ignore on write
MII Frame Preamble Suppression
1 = PHY will accept management frames with preamble suppressed
0 = PHY will not accept management frames with preamble
suppressed
Auto-negotiation Complete
1 = Auto-negotiation process completed
0 = Auto-negotiation process not completed
Remote Fault
1 = Remote fault condition detected (cleared on read or by a chip
reset). Fault criteria and detection method is DM9106
implementation specific. This bit will set after the RF bit in the
ANLPAR (bit 13, register address 05) is set
0 = No remote fault condition detected
Auto Configuration Ability
1 = DM9106 is able to perform auto-negotiation
0 = DM9106 is not able to perform auto-negotiation
Link Status
1 = Valid link is established (for either 10Mbps or 100Mbps
operation)
0 = Link is not established
The link status bit is implemented with a latching function, so that
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
1
Jabber detect
0, RO
0
Extended
capability
1,RO/P
the occurrence of a link failure condition causes the link status bit to
be cleared and remain cleared until it is read via the management
interface
Jabber Detect
1 = Jabber condition detected
0 = No jabber
This bit is implemented with a latching function. Jabber conditions
will set this bit unless it is cleared by a read to this register through a
management interface or a DM9106 reset. This bit works only in
10Mbps mode
Extended Capability
1 = Extended register capable
0 = Basic register capable only
8.3 PHY ID Identifier Register #1 (PHYID1) – 02H
The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9106. The Identifier consists
of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model
revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E.
Bit
15-0
Bit Name
OUI_MSB
Default
<0181h>
Description
OUI Most Significant Bits
This register stores bit 3 to 18 of the OUI (00606E) to bit 15 to 0 of
this register respectively. The most significant two bits of the OUI
are ignored (the IEEE standard refers to these as bit 1 and 2)
8.4 PHY ID Identifier Register #2 (PHYID2) – 03H
Bit
15-10
Bit Name
OUI_LSB
Default
<101110>,
RO/P
9-4
VNDR_MDL
<001011>,
RO/P
3-0
MDL_REV
<0000>,
RO/P
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
Description
OUI Least Significant Bits
Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this
register respectively
Vendor Model Number
Five bits of vendor model number mapped to bit 9 to 4 (most
significant bit to bit 9)
Model Revision Number
Five bits of vendor model revision number mapped to bit 3 to 0
(most significant bit to bit 4)
55
DM9106
3-port switch with PCI Interface
8.5 Auto-negotiation Advertisement Register (ANAR) – 04H
This register contains the advertised abilities of this DM9106 device as they will be transmitted to its link partner
during Auto-negotiation.
Bit
15
Bit Name
NP
14
ACK
13
RF
12-11
Reserved
10
FCS
9
T4
8
TX_FDX
7
TX_HDX
6
10_FDX
5
10_HDX
4-0
Selector
56
Default
0,RO/P
Description
Next page Indication
0 = No next page available
1 = Next page available
The DM9106 has no next page, so this bit is permanently set to 0
0,RO
Acknowledge
1 = Link partner ability data reception acknowledged
0 = Not acknowledged
The DM9106's auto-negotiation state machine will automatically
control this bit in the outgoing FLP bursts and set it at the
appropriate time during the auto-negotiation process. Software
should not attempt to write to this bit.
0, RW
Remote Fault
1 = Local device senses a fault condition
0 = No fault detected
X, RW
Reserved
Write as 0, ignore on read
0, RW
Flow Control Support
1 = Controller chip supports flow control ability
0 = Controller chip doesn’t support flow control ability
0, RO/P
100BASE-T4 Support
1 = 100BASE-T4 is supported by the local device
0 = 100BASE-T4 is not supported
The DM9106 does not support 100BASE-T4 so this bit is
permanently set to 0
1, RW
100BASE-TX Full Duplex Support
1 = 100BASE-TX full duplex is supported by the local device
0 = 100BASE-TX full duplex is not supported
1, RW
100BASE-TX Support
1 = 100BASE-TX half duplex is supported by the local device
0 = 100BASE-TX half duplex is not supported
1, RW
10BASE-T Full Duplex Support
1 = 10BASE-T full duplex is supported by the local device
0 = 10BASE-T full duplex is not supported
1, RW
10BASE-T Support
1 = 10BASE-T half duplex is supported by the local device
0 = 10BASE-T half duplex is not supported
<00001>, RW Protocol Selection Bits
These bits contain the binary encoded protocol selector supported
by this node
<00001> indicates that this device supports IEEE 802.3 CSMA/CD
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) – 05H
This register contains the advertised abilities of the link partner when received during Auto-negotiation.
Bit
15
Bit Name
NP
14
ACK
13
RF
12-11
Reserved
10
FCS
9
T4
8
TX_FDX
7
TX_HDX
6
10_FDX
5
10_HDX
4-0
Selector
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
Default
0, RO
Description
Next Page Indication
0 = Link partner, no next page available
1 = Link partner, next page available
0, RO
Acknowledge
1 = Link partner ability data reception acknowledged
0 = Not acknowledged
The DM9106's auto-negotiation state machine will automatically
control this bit from the incoming FLP bursts. Software should not
attempt to write to this bit
0, RO
Remote Fault
1 = Remote fault indicated by link partner
0 = No remote fault indicated by link partner
0, RO
Reserved
Read as 0, ignore on write
0, RO
Flow Control Support
1 = Controller chip supports flow control ability by link partner
0 = Controller chip doesn’t support flow control ability by link
partner
0, RO
100BASE-T4 Support
1 = 100BASE-T4 is supported by the link partner
0 = 100BASE-T4 is not supported by the link partner
0, RO
100BASE-TX Full Duplex Support
1 = 100BASE-TX full duplex is supported by the link partner
0 = 100BASE-TX full duplex is not supported by the link partner
0, RO
100BASE-TX Support
1 = 100BASE-TX half duplex is supported by the link partner
0 = 100BASE-TX half duplex is not supported by the link partner
0, RO
10BASE-T Full Duplex Support
1 = 10BASE-T full duplex is supported by the link partner
0 = 10BASE-T full duplex is not supported by the link partner
0, RO
10BASE-T Support
1 = 10BASE-T half duplex is supported by the link partner
0 = 10BASE-T half duplex is not supported by the link partner
<00000>, RO Protocol Selection Bits
Link partner’s binary encoded protocol selector
57
DM9106
3-port switch with PCI Interface
8.7 Auto-negotiation Expansion Register (ANER)- 06H
Bit
15-5
Bit Name
Reserved
Default
0, RO
4
PDF
0, RO/LH
3
LP_NP_ABLE
0, RO
2
NP_ABLE
0,RO/P
1
PAGE_RX
0, RO
0
LP_AN_ABLE
0, RO
Description
Reserved
Read as 0, ignore on write
Local Device Parallel Detection Fault
PDF = 1: A fault detected via parallel detection function.
PDF = 0: No fault detected via parallel detection function
Link Partner Next Page Able
LP_NP_ABLE = 1: Link partner, next page available
LP_NP_ABLE = 0: Link partner, no next page
Local Device Next Page Able
NP_ABLE = 1: DM9106, next page available
NP_ABLE = 0: DM9106, no next page
DM9106 does not support this function, so this bit is always 0
New Page Received
A new link code word page received. This bit will be automatically
cleared when the register (register 6) is read by management
Link Partner Auto-negotiation Able
A “1” in this bit indicates that the link partner supports
Auto-negotiation
8.8 DAVICOM Specified Configuration Register (DSCR) – 10H
58
Bit
15
Bit Name
BP_4B5B
Default
0,RW
14
BP_SCR
0, RW
13
BP_ALIGN
0, RW
12
BP_ADPOK
0, RW
11
Reserved
RW
10
TX
1, RW
9
Reserved
0, RO
Description
Bypass 4B5B Encoding and 5B4B Decoding
1 = 4B5B encoder and 5B4B decoder function bypassed
0 = Normal 4B5B and 5B4B operation
Bypass Scrambler/Descrambler Function
1 = Scrambler and descrambler function bypassed
0 = Normal scrambler and descrambler operation
Bypass Symbol Alignment Function
1 = Receive functions (descrambler, symbol alignment and symbol
decoding functions) bypassed. Transmit functions (symbol
encoder and scrambler) bypassed
0 = Normal operation
BYPASS ADPOK
Force signal detector (SD) active. This register is for debug only,
not release to customer
1=Forced SD is OK,
0=Normal operation
Reserved
Force to 0 in application
100BASE-TX Mode Control
1 = 100BASE-TX operation
0 = 100BASE-FX operation
Reserved
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
8
RMII_MODE
0, RW
RMII mode enable
7
F_LINK_100
0, RW
6
Reserved
0, RW
5
4
COL_LED
RPDCTR-EN
0, RW
1, RW
3
SMRST
0, RW
2
MFPSC
1, RW
1
SLEEP
0, RW
0
RLOUT
0, RW
Force Good Link in 100Mbps
0 = Normal 100Mbps operation
1 = Force 100Mbps good link status
This bit is useful for diagnostic purposes
Reserved
Force to 0 in application.
COL LED Control (valid in PHY test mode)
Reduced Power Down Control Enable
This bit is used to enable automatic reduced power down
0 = Disable automatic reduced power down
1 = Enable automatic reduced power down
Reset State Machine
When writes 1 to this bit, all state machines of PHY will be reset.
This bit is self-clear after reset is completed
MF Preamble Suppression Control
MII frame preamble suppression control bit
1 = MF preamble suppression bit on
0 = MF preamble suppression bit off
Sleep Mode
Writing a 1 to this bit will cause PHY entering the Sleep mode and
power down all circuit except oscillator and clock generator circuit.
When waking up from Sleep mode (write this bit to 0), the
configuration will go back to the state before sleep; but the state
machine will be reset
Remote Loopout Control
When this bit is set to 1, the received data will loop out to the
transmit channel. This is useful for bit error rate testing
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
59
DM9106
3-port switch with PCI Interface
8.9 DAVICOM Specified Configuration and Status Register (DSCSR) – 11H
60
Bit
15
Bit Name
100FDX
Default
1, RO
14
100HDX
1, RO
13
10FDX
1, RO
12
10HDX
1, RO
11
Reserved
0, RO
10
9
8-4
Reserved
Reserved
PHYADR[4
:0]
0,RW
0,RW
1, RW
3-0
ANMB[3:0]
0, RO
Description
100M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 100M full duplex mode. The
software can read bit [15:12] to see which mode is selected after
auto-negotiation. This bit is invalid when it is not in the auto-negotiation
mode
100M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 100M half duplex mode. The
software can read bit [15:12] to see which mode is selected after
auto-negotiation. This bit is invalid when it is not in the auto-negotiation
mode
10M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 10M Full Duplex mode. The
software can read bit [15:12] to see which mode is selected after
auto-negotiation. This bit is invalid when it is not in the auto-negotiation
mode
10M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 10M half duplex mode. The
software can read bit [15:12] to see which mode is selected after
auto-negotiation. This bit is invalid when it is not in the auto-negotiation
mode
Reserved
Read as 0, ignore on write
Reserved
Reserved
PHY Address Bit 4:0
The first PHY address bit transmitted or received is the MSB of the
address (bit 4). A station management entity connected to multiple PHY
entities must know the appropriate address of each PHY
Auto-negotiation Monitor Bits
These bits are for debug only. The auto-negotiation status will be written
to these bits.
B3 b2 b1 B0
0 0 0 0 In IDLE state
0 0 0 1 Ability match
0 0 1 0 Acknowledge match
0 0 1 1 Acknowledge match fail
0 1 0 0 Consistency match
0 1 0 1 Consistency match fail
0 1 1 0 Parallel detects signal_link_ready
0 1 1 1 Parallel detects signal_link_ready fail
1 0 0 0 Auto-negotiation completed successfully
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
8.10 10BASE-T Configuration/Status (10BTCSR) – 12H
Bit
15
Bit Name
Reserved
Default
0, RO
14
LP_EN
1, RW
13
HBE
1,RW
12
SQUELCH
1, RW
11
JABEN
1, RW
10
SERIAL
0, RW
9-1
Reserved
0, RO
0
POLR
0, RO
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
Description
Reserved
Read as 0, ignore on write
Link Pulse Enable
1 = Transmission of link pulses enabled
0 = Link pulses disabled, good link condition forced
This bit is valid only in 10Mbps operation
Heartbeat Enable
1 = Heartbeat function enabled
0 = Heartbeat function disabled
When the DM9106 is configured for full duplex operation, this bit will
be ignored (the collision/heartbeat function is invalid in full duplex
mode)
Squelch Enable
1 = Normal squelch
0 = Low squelch
Jabber Enable
Enables or disables the Jabber function when the DM9106 is in
10BASE-T full duplex or 10BASE-T transceiver Loopback mode
1 = Jabber function enabled
0 = Jabber function disabled
10M Serial Mode (valid in PHY test mode)
Force to 0, in application.
Reserved
Read as 0, ignore on write
Polarity Reversed
When this bit is set to 1, it indicates that the 10Mbps cable polarity is
reversed. This bit is automatically set and cleared by 10BASE-T
module
61
DM9106
3-port switch with PCI Interface
8.11 Power Down Control Register (PWDOR) – 13H
Bit
15-9
Bit Name
Reserved
Default
0, RO
Description
Reserved
Read as 0, ignore on write
8
PD10DRV
0, RW
Vendor power down control test
7
PD100DL
0, RW
Vendor power down control test
6
PDchip
0, RW
Vendor power down control test
5
PDcrm
0, RW
Vendor power down control test
4
PDaeq
0, RW
Vendor power down control test
3
PDdrv
0, RW
Vendor power down control test
2
PDedi
0, RW
Vendor power down control test
1
PDedo
0, RW
Vendor power down control test
0
PD10
0, RW
Vendor power down control test
* when selected, the power down value is control by Register 20.0
8.12 (Specified config) Register – 14H
Bit
15
14
13
12
11-8
7
6
5
4
3
2
1
0
62
Bit Name
TSTSE1
TSTSE2
FORCE_TXSD
Default
0,RW
0,RW
0,RW
Description
Vendor test select control
Vendor test select control
Force Signal Detect
1: force SD signal OK in 100M
0: normal SD signal.
FORCE_FEF
0,RW
Vendor test select control
Reserved
0, RO
Reserved
Read as 0, ignore on write
MDIX_CNTL
MDI/MDIX,RO The polarity of MDI/MDIX value
1: MDIX mode
0: MDI mode
AutoNeg_dpbk
0,RW
Auto-negotiation Loopback
1: test internal digital auto-negotiation Loopback
0: normal.
Mdix_fix Value
0, RW
MDIX_CNTL force value:
When Mdix_down = 1, MDIX_CNTL value depend on the register
value.
Mdix_down
0,RW
MDIX Down
Manual force MDI/MDIX.
0: Enable HP Auto-MDIX
1: Disable HP Auto-MDIX , MDIX_CNTL value depend on 20.5
MonSel1
0,RW
Vendor monitor select
MonSel0
0,RW
Vendor monitor select
Reserved
0,RW
Reserved
Force to 0, in application.
PD_value
0,RW
Power down control value
Decision the value of each field Register 19.
1: power down
0: normal
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
8.13 DAVICOM Specified Receive Error Counter Register (RECR) – 16H
Bit
15-0
Bit Name
Rcv_ Err_ Cnt
Default
0, RO
Description
Receive Error Counter
Receive error counter that increments upon detection of RXER.
Clean by read this register.
8.14 DAVICOM Specified Disconnect Counter Register (DISCR) – 17H
Bit
15-8
Bit Name
Reserved
Default
0, RO
7-0
Disconnect
Counter
0, RO
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
Description
Reserved
Disconnect Counter that increment upon detection of
disconnection. Clean by read this register.
63
DM9106
3-port switch with PCI Interface
9. Functional Description
9.1 PCI Bus Buffer Management
9.1.1. Overview
The data buffers for reception and transmission of
data reside in the host memory. They are directed
by the descriptor lists that are located in another
region of the host memory. All actions for the buffer
management are operated by the DM9106 in
conjunction with the driver. The data structures and
processing algorithms are described in the following
text.
9.1.2. Data Structure and Descriptor List
There are two types of buffers that reside in the
host memory, the transmit buffer and the receive
buffer. The buffers are composed of many
distributed regions in the host memory. They are
linked together and controlled by the descriptor lists
that reside in another region of the host memory.
own
control
The content of each descriptor includes pointer to
the buffer, count of the buffer, command and status
for the packet to be transmitted or received. Each
descriptor list starts from the address setting of CR3
(receive descriptor base address) and CR4
(transmit descriptor base address). The descriptor
lists have two types of structure, Ring structure and
Chain structure.
9.1.3. Buffer Management : Ring Structure
Method
As the Ring structure depicted below, the
descriptors are linked directly one after another.
The first and last descriptor on the list have the
necessary information for the DM9106 to return to
the beginning of the list after the bottom descriptor
is accessed. Each descriptor points to the two
buffer regions and one packet may cross many
descriptors boundaries.
status
buffer 2 length buffer 1 length
Buffer 1
buffer address 1
buffer address 2
Buffer 2
Descriptor 1
Buffer 1
Buffer 2
Descriptor N
9.1.4. Buffer Management : Chain Structure
Method
As the Chain structure depicted below, each
descriptor contains two pointers, one point to a
64
Packet N
single buffer and the other to the next descriptor
chained. The first descriptor is chained by the last
descriptor under host driver’s control. With this
structure, a descriptor can be allocated anywhere in
host memory and is chained to the next descriptor.
The Chain structure and the Ring structure may
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
combine to make the buffer structure more flexible.
status
own
control
not valid
Buffer 1
buffer 1 length
buffer address 1
next descriptor address
Buffer 1
Descriptor 1
Packet N
Descriptor N
9.1.5. Descriptor List: Buffer Descriptor Format
(a). Receive Descriptor Format
Each receive descriptor has four doubleword entries
and may be read or written by the host or the
DM9106. The descriptor format is shown below with
a detailed functional description.
31
0
OWN
OWN
RDES0
Status
Buffer 2 Length
Control bits
Buffer 1 Length
RDES1
Buffer Address 1
RDES2
Buffer Address 2
RDES3
Receive Descriptor Format
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
65
DM9106
3-port switch with PCI Interface
RDES0: Owner bit with receive status
31
30
OWN
AUN
29
28
27
26
25
24
23
22
21
20
19
18
14
ES
DUE
FL: Frame length indicating total byte count of
received packet.
13
12
LBOM
11
10
9
8
RF
MF
BD
ED
7
6
TLF
EFL LCS
5
FT
AUN: Received address unmatched.
4
3
RWT PLE
This word-wide content includes status of received
frame. They are loaded after the received buffer
that belongs to the corresponding descriptor is full.
All status bits are valid only when the last descriptor
( End Descriptor ) bit is set.
Bit 15: ES, Error Summary
It is set for the following error conditions :
Descriptor Unavailable Error (DUE =1),
Runt Frame (RF=1), Excessive Frame
Length (EFL=1), Late Collision Seen
(LCS=1), CRC error (CE=1), FIFO Overflow
error (FOE=1). Valid only when ED is set.
Bit 14: DUE, Descriptor Unavailable Error
It is set when the frame is truncated due to
the buffer
unavailable. It is valid only when ED is set.
Bit 13,12: LBOM, Loopback Operation Mode
These two bits show the received frame is
derived from
00 --- normal operation
01 --- internal loopback
10 --- external loopback
11 --- reserved
Bit 11: RF, Runt Frame
It is set to indicate the received frame
has the size
smaller than 64 bytes. Valid only when
ED is set
and FOE is reset.
Bit 10: MF, Multicast Frame
It is set to indicate the received frame
has a
66
16
Frame Length ( FL )
OWN: 1=owned by DM9106, 0=owned by host
This bit should be reset after packet
reception is completed. It will be set by the
host after received data are removed.
15
17
2
1
0
AE
CE
FOE
multicast address. Valid only when ED is
set.
Bit 9: BD, Begin Descriptor
This bit is set for the descriptor indicating
start of a
received frame.
Bit 8: ED, Ending Descriptor
This bit is set for the descriptor indicating
end of a
received frame.
Bit 7: EFL, Excessive Frame Length
It is set to indicate the received frame
length exceeds
1518 bytes. Valid only when ED is set.
Bit 6: LCS: Late Collision Seen
It is set to indicate a late collision found
during the frame reception. Valid only
when ED is set.
Bit 5: FT, Frame Type
It is set to indicate the received frame is the
Ethernet-type. It is reset to indicate the received
frame is the EEE802.3- type. Valid only when ED
is set
Bit 4: RWT, Receive Watchdog Time-Out
It is set to indicate the receive Watchdog
time-out
during the frame reception. CR5<9> will
also be set.
Valid only when ED is set.
Bit 3: PLE, Physical Layer Error
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
It is set to indicate a physical layer error
found during
the frame reception.
It is set to indicate the received frame
ends with a
CRC error. Valid only when ED is set.
Bit 2: AE, Alignment Error
It is set to indicate the received frame
ends with a
non-byte boundary.
Bit 0: FOE, FIFO Overflow Error
This bit is valid for Ending Descriptor is set.
(ED = 1)
It is set to indicate a FIFO Overflow error
happens during the frame reception.
Bit 1: CE, CRC Error
RDES1: Descriptor Status And Buffer Size
31
30
29
28
27
26
25
24
23
21 ~ 11
10 ~ 0
Buffer 2 Length
Buffer 1 Length
22
EOR CE
Bit 25: EOR, End of Ring
Set to indicate that the descriptor is
located on
the bottom of the descriptor list.
Bit 24: CE, Chain Enable
Set to indicate that the second address
is the
chained descriptor instead of the other
buffer.
Used as the indication of the Chain
structure.
Bit 21-11: Buffer 2 Length
Indicates the size of the second buffer. It
has no meaning in chain type descriptor.
Bit 10-0: Buffer 1 Length
Indicates the size of the first buffer in
Ring type structure and single buffer in
Chain type
structure.
RDES2: Buffer 1 Starting Address
Indicates the physical starting address of buffer 1.
31
0
Buffer Address 1
RDES3: Buffer 2 Starting Address
Indicates the physical starting address of buffer 2
under the Ring structure and that of the chained
31
descriptor under the Chain descriptor structure.
0
Buffer Address 2
(b). Transmit Descriptor Format
Each transmit descriptor has four doubleword
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
content and may be read or written by the host or
67
DM9106
3-port switch with PCI Interface
by the DM9106. The descriptor format are shown
below with detailed description.
31
0
OWN
Status
Control bits
TDES0
Buffer 2 Length
Buffer 1 Length
TDES1
Buffer Address 1
TDES2
Buffer Address 2
TDES3
Transmit Descriptor Format
TDES0 : Owner Bit With Transmit Status
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OWN
is filled with data and ready to be transmitted.
It will be reset by DM9106 after transmitting
the whole data buffer.
Bit 31: OWN,
1=owned by DM9106, 0=owned by host, this
bit should be set when the transmitting buffer
15
14
ES
TX
JT
13
12
11
10
9
8
7
LOC
NC
LC
EC
HF
6
5
4
CC
This word wide content includes status of transmitted
frame. They are loaded after the data buffer that
belongs to the corresponding descriptor is
transmitted.
Bit 15: ES, Error Summary
It is set for the following error conditions :
Transmit Jabber Time-out ( TXJT=1), Loss of
Carrier (LOC=1), No Carrier (NC=1), Late
Collision (LC=1), Excessive Collision (EC=1),
FIFO Underrun Error (FUE=1).
3
2
LF
1
FUE
0
DF
Bit 10: NC, No Carrier
It is set to indicate that no carrier signal from
transceiver is found. Not valid in internal
loopback mode.
Bit 9: LC, Late Collision
It is set to indicate a collision occurs after
the collision window of 64 bytes. Not valid if
FUE is set.
Bit 14: TXJT, Transmit Jabber Time Out
It is set to indicate the transmitted frame is
truncated due to the transmit jabber time out
condition. The transmit jabber time out
interrupt
CR5<3> is set.
Bit 8: EC, Excessive collision
It is set to indicate the transmission is
aborted due to 16 excessive collisions.
Bit 7: HF, Heartbeat Fail
It is set to indicate the Heartbeat check
failed after complete transmission. Not valid
if FUE is set. When TDES0<14> is set, this
bit is not valid.
Bit 11: LOC, Loss Of Carrier
It is set to indicate the loss of carrier during the
frame transmission. Not valid in internal
loopback mode.
Bits 6-3: CC, Collision Count
These bits shows the number of collision
before transmission. Not valid if excessive
collision bit is also set.
68
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
to a transmit FIFO underrun condition.
Bit 2: LF, Link test Fail
It is set to indicate the link test fails before the
frame transmission.
Bit 0: DF, Deferred
It is set to indicate the frame is deferred before
ready to transmit.
Bit 1: FUE, FIFO Underrun Error
It is set to indicate the transmission aborted due
TDES1 : Transmit buffer control and buffer size
31
30
29
28
27
26
25
24
CI
ED
BD FMB1 SETF CAD EOR CE
23
22
PD FMB0
21 ~ 11
Buffer 2 Length
Bit 31: CI, Completion Interrupt
It is set to enable the transmit interrupt after the
10 ~ 0
Buffer 1 Length
structure. When reset, it indicates the Ring
structure.
present frame has been transmitted. It is valid only Bit 23: PD, Padding Disable
This bit is set to disable the padding field for a
when TDES1<30> is set or when it is a setup
packet shorter than 64 bytes.
frame.
Bit 22: FMB0, Filtering Mode Bit 0
Bit 30: ED, Ending Descriptor
It is set to indicate the pointed buffer
contains the last segment of a frame.
Bit 29: BD, Begin Descriptor
It is set to indicate the pointed buffer
contains the first segment of a frame.
Bit 28: FMB1, Filtering Mode Bit 1
This bit is used with FMB0 to indicate the
filtering type when the present frame is a
setup frame.
Bit 27: SETF, Setup Frame
It is set to indicate the current frame is a
setup frame.
Bit 26: CAD, CRC Append Disable
It is set to disable the CRC appending at the
end of the transmitted frame. Valid only
when TDES1<29> is set.
This bit is used with FMB1 to indicate the filtering
type when the present frame is a setup frame.
FMB1
FMB0
Filtering Type
0
0
Perfect Filtering
0
1
Hash Filtering
1
1
0
1
Inverse Filtering
Hash-Only Filtering
Bits 21-11: Buffer 2 length
Indicates the size of second buffer. It has
no meaning with chain structure
descriptor type.
Bit 10-0: Buffer 1 length
Indicates the size of the first buffer in
Ring type structure and single buffer in
Chain type
structure.
Bit 25: EOR, End of Ring Descriptor
It is set to indicate the descriptor is located
on the bottom of the descriptor list.
Bit 24: CE, Chain Enable
This bit is set to indicate the second address
( TDES3 ) is the chained descriptor instead
of the other buffer. It is used as the indication
of the Chain
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
69
DM9106
TDES2 : Buffer 1 Starting Address indicates the physical starting address of buffer 1.
31
0
Buffer Address 1
BA1:
TDES3 : Buffer 2 Starting Address indicates the physical starting address of buffer 2 under the Ring structure.
31
0
Buffer Address 2
BA2:
Initialization Procedure
After hardware or software reset, the transmit and
receive processes are placed in the STOP state.
The DM9106 can accept the host commands to
start operation. The general procedure for
initialization is described below:
(1) Read/write suitable values for the PCI
configuration registers.
(2) Write CR3 and CR4 to provide the starting
address of each descriptor list.
(3) Write CR0 to set global host bus operation
parameters.
(4) Write CR7 to mask unnecessary interrupt
causes.
(5) Write CR6 to set global parameters and start
both the receive and transmit processes. The
receive and transmit processes will enter the
running state and attempt to acquire descriptors
from the respective descriptor lists.
(6) Wait for any interrupt.
Data Buffer Processing Algorithm
The data buffer processing algorithm is based on
the cooperation of the host and the DM9106. The
host sets CR3 ( receive descriptor base address )
and CR4 ( transmit descriptor base address ) for the
descriptor list initialization. The DM9106 will start
the data buffer transfer after the descriptor polling
and get the ownership. For detailed processing
procedure, please see below.
Preliminary datasheet
DM9106-DS-P02
June 01, 2007
1. Receive Data Buffer Processing
The DM9106 always attempts to acquire an extra
descriptor in anticipation of the incoming frames.
Any incoming frame size covers a few buffer
regions and descriptors. The following conditions
satisfy the descriptor acquisition attempt :
z
z
z
z
z
When start/stop receive sets immediately after
being placed in the running state.
When the DM9106 begins writing frame data to
a data buffer pointed to by the current
descriptor and the buffer ends before the frame
ends.
When the DM9106 completes the reception of
a frame and the current receive descriptor is
closed.
When the receive process is suspended due to
no free buffer for the DM9106 and a new frame
is received.
When the receive poll demand is issued.
After acquiring the free descriptor, the DM9106
processes the incoming frame and places it in
the acquired descriptor's data buffer. When the
whole received frame data has been
transferred, the DM9106 will write the status
information to the last descriptor. The same
process will repeat until it encounters a
descriptor flagged as being owned by the host.
If this occurs, the receive process enters the
suspended state and waits the host to service.
70
DM9106
Stop
State
Stop Receive Command or
Reset Command
Start Receive Command Or
Receive Poll Command
Descriptor
Access
New Frame Coming Or
Receive Poll Command
Receive Buffer
Unavailable
Buffer Full
Suspended
Buffer Available
( OWN bit = 1 )
FIFO Threshold
Reached
Datat
Transfer
Frame Fully
Received
Write
Status
Buffer not
Full
Receive Buffer Management State Transition
Preliminary datasheet
DM9106-DS-P02
June 01, 2007
71
DM9106
3-port switch with PCI Interface
9.1.2. Transmit Data Buffer Processing
the first frame, it immediately polls the transmit
descriptor list for the second frame. If the second
frame is valid, the transmit process copies the
frame before writing the status information of the
first frame.
When start/stop transmit command is set and the
DM9106 is in running state, the transmit process
polls the transmit descriptor list for frames requiring
transmission. When it completes a frame
transmission, the status related to the transmitted
frame will be written into the transmit descriptor. If
the DM9106 detects a descriptor flagged as owned
by the host and no transmit buffers are available,
the transmit process will be suspended. While in the
running state, the transmit process can
simultaneously acquire two frames. As the transmit
process completes copying
Both conditions below will make transmit process
be suspended : (i) The DM9106 detects a descriptor
owned by the host. ( ii ) A frame transmission is
aborted when a locally induced error is detected.
Under either condition, the host driver has to
service the condition before the DM9106 can
resume.
Stop State
Stop Transmit Command Or
Reset Command
Start Transmit Command Or
Transmit Poll Command
Descriptor
Access
Transmit Poll Command
Transmit Buffer Unavailable
( Owned By Host )
Buffer Empty
Suspended
Buffer Available
( OWN bit = 1 )
Under FIFO Threshold
Data
Transfer
Frame Fully Transmited
Write
Status
Buffer not Empty
Transmit Buffer Management State Transition
72
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
9.2 Switch function:
9.2.1 Address Learning
The DM9106 has a self-learning mechanism for
learning the MAC addresses of incoming packets in
real time. DM9106 stores MAC addresses, port
number and time stamp information in the
Hash-based Address Table. It can learn up to 1K
unicast address entry.
The switch engine updates address table with
new entry if incoming packet’s Source Address (SA)
does not exist and incoming packet is valid (non-error
and legal length).
Besides, DM9106 has an option to disable
address learning for individual port. This feature can
be set by bit 24 of register CR19
9.2.2 Address Aging
The time stamp information of address table is
used in the aging process. The switch engine
updates time stamp whenever the corresponding SA
receives. The switch engine would delete the entry if
its time stamp is not updated for a period of time.
The period can be programmed or disabled through
bit 0 & 1 of register CR16.
9.2.3 Packet Forwarding
The DM9106 forwards the incoming packet
according to following decision:
(1). If DA is Multicast/Broadcast, the packet is
forwarded to all ports, except to the port on which the
packet was received.
(2). Switch engine would look up address table
based on DA when incoming packets is UNICAST. If
the DA was not found in address table, the packet is
treated as a multicast packet and forward to other
ports. If the DA was found and its destination port
number is different to source port number, the packet
is forward to destination port.
(3). Switch engine also look up VLAN, Port
Monitor setting and other forwarding constraints for
the forwarding decision, more detail will discuss in
later sections.
The DM9106 will filter incoming packets under
following conditions:
(1). Error packets, including CRC errors,
alignment errors, illegal size errors.
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
(2). PAUSE packets.
(3). If incoming packet is UNICAST and its
destination port number is equal to source port
number.
9.2.4 Inter-Packet Gap (IPG)
IPG is the idle time between any two valid packets
at the same port. The typical number is 96 bits time.
In other word, the value is 9.6u sec for 10Mbps and
960n sec for 100Mbps.
9.2.5 Back-off Algorithm
The DM9106 implements the binary exponential
back-off algorithm in half-duplex mode compliant to
IEEE standard 802.3.
9.2.6 Late Collision
Late Collision is a type of collision. If a collision
error occurs after the first 512 bit times of data are
transmitted, the packet is dropped.
9.2.7 Half Duplex Flow Control
The DM9106 supports IEEE standard 802.3x flow
control frames on both transmit and receive sides.
On the receive side, The DM9106 will defer
transmitting next normal frames, if it receives a pause
frame from link partner.
On the transmit side, The DM9106 issues pause
frame with maximum pause time when internal
resources such as received buffers, transmit queue
and transmit descriptor ring are unavailable. Once
resources are available, The DM9106 sends out a
pause frame with zero pause time allows traffic to
resume immediately.
9.2.8 Full Duplex Flow Control
The DM9106 supports half-duplex backpressure.
The inducement is the same as full duplex mode.
When flow control is required, the DM9106 sends jam
pattern, thus forcing a collision.
The flow control ability can be set in bit 4 of
register CR18.
9.2.9 Partition Mode
The DM9106 provides a partition mode for each
73
DM9106
3-port switch with PCI Interface
port, see bit 6 of register CR18. The port enters
partition mode when more than 64 consecutive
collisions are occurred. In partition mode the port
continuous to transmit but it will not receive. The port
returned to normal operation mode when a good
packet is seen on the wire. The detail description of
partition mode represent following:
(1). Entering Partition State
A port will enter the Partition State when either of
the following conditions occurs:
z The port detects a collision on every one of 64
consecutive re-transmit attempts to the same packet.
z The port detects a single collision which occurs
for more than 512 bit times.
z Transmit defer timer time out, which indicates
the transmitting packet is deferred to long.
(2). While in Partition state:
The port will continue to transmit its pending
packet, regardless of the collision detection, and will
not allow the usual Back-off Algorithm. Additional
packets pending for transmission will be transmitted,
while ignoring the internal collision indication. This
frees up the port’s transmit buffers which would
otherwise be filled up at the expense of other ports
buffers. The assumption is that the partition is
signifying a system failure situation (bad
connection/cable/station), thus dropping packets is a
small price to pay vs. the cost of halting the switch
due to a buffer full condition.
(3). Exiting from Partition State
The Port exits from Partition State, following the
end of a successful packet transmission.
A
successful packet transmission is defined as no
collisions were detected on the first 512 bits of the
transmission.
9.2.10 Broadcast Storm Filtering
The DM9106 has an option to limit the traffic of
broadcast or multicast packets, to protect the switch
from lower bandwidth availability.
There are two type of broadcast storm control,
one is throttling broadcast packet only, the other
includes multicast. This feature can be set through bit
0 of register CR18.
The broadcast storm threshold can be
programmed by EEPROM or bit 23~20 of CR18, the
default setting is no broadcast storm protecting.
74
9.2.11 Bandwidth Control
The DM9106 supports two type of bandwidth
control for each port. One is the ingress and egress
bandwidth rate can be control separately, the other is
combined together, this function can be set through
bit 3 of register CR18. The bandwidth control is
disabled by default.
For separated bandwidth control mode, the
threshold rate is defined in bit 15~8 of register CR18.
For combined mode, it is defined in bit 19~16 of
register CR18.
The behavior of bandwidth control as below:
(1).For the ingress control, if flow control function
is enabled, Pause or Jam packet will be transmitted.
The ingress packets will be dropped if flow control is
disabled.
(2).For the egress control, the egress port will not
transmit any packets. On the other hand, the ingress
bandwidth of source port will be throttled that prevent
packets from forwarding.
(3).In combined mode, if the sum of ingress and
egress bandwidth over threshold, the bandwidth will
be throttled.
9.2.12 Port Monitoring Support
The DM9106 supports “Port Monitoring” function
on per port base, detail as below:
(1). Sniffer Port and Monitor Port
There is only one port can be selected as “sniffer
port” by bit 4~3 of register CR16, multiple ports can
be set as “receive monitor port” or “transmit monitor
port” in per-port bit 29 and 30 of register CR19
respectively.
(2).Receive monitor
All packets received on the “receive monitor port”
are send a copy to “sniffer port”. For example, port 0
is set as “receive monitor port” and port 3 is selected
as “sniffer port”. If a packet is received form port 0
and predestined to port 1 after forwarding decision,
the DM9106 will forward it to port 1 and port 3 in the
end.
(3).Transmit monitor
All packets transmitted on the “transmit monitor
port” are send a copy to “sniffer port”. For example,
port 1 is set as “transmit monitor port” and port 3 is
selected as “sniffer port”. If a packet is received from
port 0 and predestined to port 1 after forwarding
decision, the DM9106 will forward it to port 1 and port
3 in the end.
(4).Exception
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
The DM9106 has an optional setting that
broadcast/multicast packets are not monitored (see
bit 28 of register CR19). It’s useful to avoid
unnecessary bandwidth.
9.2.13 VLAN Support
9.2.13.1 Port-Based VLAN
The DM9106 supports port-based VLAN as
default, up to 16 groups. Each port has a default VID
Dest.
Src.
Dest.
Src.
called PVID (Port VID, see bit 11~0 of register CR20).
The DM9106 used LSB 4-bytes of PVID as index and
mapped to register CR24~27, to define the VLAN
groups.
9.2.13.2 802.1Q-Based VLAN
Regarding IEEE 802.1Q standard, Tag-based
VLAN uses an extra tag to identify the VLAN
membership of a frame across VLAN-aware
switch/router. A tagged frame is four bytes longer
than an untagged frame and contains two bytes of
TPID (Tag Protocol Identifier) and two bytes of TCI
(Tag Control Information).
Length/Type
TPID
TCI
Data
Length / Type
Standard frame
Data
Tagged frame
0x8100
2 bytes
Priority
3 bits
The DM9106 also supports 16 802.1Q-based
VLAN groups, as specified in bit 8 of register CR16.
It’s obvious that the tagged packets can be assigned
to several different VLANs which are determined
according to the VID inside the VLAN Tag. Therefore,
the operation is similar to port-based VLAN. The
DM9106 used LSB 4-bytes VID of received packet
with VLAN tag and VLAN Group Mapping Register
(CR24~CR27) to configure the VLAN partition. If the
destination port of received packet is not same VLAN
group with received port, it will be discarded.
9.2.13.3 Tag/Untag
User can define each port as Tag port or Un-tag
port by bit 31 of register CR18 in 802.1Q-based
VLAN mode. The operation of Tag and Un-tag can
explain as below conditions:
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
CFI
1 bits
VID
12 bits
(1). Receive untagged packet and forward to
Un-tag port.
Received packet will forward to destination port
without modification.
(2). Receive tagged packet and forward to Un-tag
port.
The DM9106 will remove the tag from the
packet and recalculate CRC before sending it out.
(3). Receive untagged packet and forward to Tag
port.
The DM9106 will insert the PVID tag when an
untagged packet enters the port, and recalculate
CRC before delivering it.
(4). Receive tagged packet and forward to Tag
port.
Received packet will forward to destination port
without modification.
75
DM9106
3-port switch with PCI Interface
9.2.14 Priority Support
The DM9106 supports Quality of Service (QoS)
mechanism for multimedia communication such as
VoIP and video conferencing.
The DM9106 provides three priority classifications:
Port-based, 802.1p-based and DiffServ-based priority.
See next section for more detail. The DM9106 offers
four level queues for transmit on per-port based.
The DM9106 provides two packet scheduling
algorithms: Weighted Fair Queuing and Strict Priority
Queuing. Weighted Fair Queuing (WFQ) based on
their priority and queue weight. Queues with larger
weights get more service than smaller. This
mechanism can get highly efficient bandwidth and
smooth the traffic. Strict Priority Queuing (SPQ)
based on priority only. The Packet on the highest
priority queue is transmitted first. The next
highest-priority queue is work until last queue empties,
and so on. This feature can be set in bit 29 of register
CR18.
transmit queue. This value can be set in bit 24 and 25
of register CR18.
9.2.14.2 802.1p-Based Priority
802.1p priority can be disabled by bit 26 of
register CR18, it is enabled by default.
The DM9106 extracts 3-bit priority field from
received packet with 802.1p VLAN tag, and maps this
field against VLAN Priority Map Register CR23 to
determine which transmit queue is designated. The
VLAN Priority Map is programmable.
9.2.14.3 DiffServ-Based Priority
DiffServ based priority uses the most significant
6-bit of the ToS field in standard IPv4 header, and
maps this field against ToS Priority Map Registers
(C0h~CFh) to determine which transmit queue is
designated. The ToS Priority Map is programmable
too. In addition, User can only refer to most
significant 3-bit of the ToS field optionally, see bit 15
of register CR16.
9.2.14.1 Port-Based Priority
Port based priority is the simplest scheme and as
default. Each port has a 2-bit priority value as index
for splitting ingress packets to the corresponding
76
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
9.3 MII Interface
9.3.1 MII data interface
The DM9106 port 2 provides a Media Independent
Interface (MII) as defined in the IEEE 802.3u
standard (Clause 22).
The MII consists of a nibble wide receive data bus,
a nibble wide transmit data bus, and control signals to
facilitate data transfers between the DM9106 port 2
and external device (a PHY or a MAC in reverse MII).
• TXD2 (transmit data) is a nibble (4 bits) of
data that are driven by the DM9106 synchronously
with respect to TXC2. For each TXC2 period, which
TXE2 is asserted, TXD2 (3:0) are accepted for
transmission by the external device.
• TXC2 (transmit clock) from the external
device is a continuous clock that provides the timing
reference for the transfer of the TXE2, TXD2. The
DM9106 can drive 25MHz clock if it is configured to
reversed MII mode.
• TXE2 (transmit enable) from the DM9106 port
2 MAC indicates that nibbles are being presented on
the MII for transmission to the external device.
• RXD2 (receive data) is a nibble (4 bits) of data
that are sampled by the DM9106 port 2 MAC
synchronously with respect to RXC2. For each RXC2
period which RXDV2 is asserted, RXD2 (3:0) are
transferred from the external device to the DM9106
port 2 MAC reconciliation sublayer.
• RXC2 (receive clock) from external device to
the DM9106 port 2 MAC reconciliation sublayer is a
continuous clock that provides the timing reference
for the transfer of the RXDV2, RXD2, and RXER2
signals.
• RXDV2 (receive data valid) input from the
external device to indicates that the external device is
presenting recovered and decoded nibbles to the
DM9106 port 2 MAC reconciliation sublayer. To
interpret a receive frame correctly by the
reconciliation sublayer, RXDV2 must encompass the
frame, starting no later than the Start-of-Frame
delimiter and excluding any End-Stream delimiter.
• RXER2 (receive error) input from the external
device is synchronously with respect to RXC2.
RXER2 will be asserted for 1 or more clock periods to
indicate to the reconciliation sublayer that an error
was detected somewhere in the frame being
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
transmitted from the external device to the DM9106
port 2 MAC.
• CRS2 (carrier sense) is asserted by the
external device when either the transmit or receive
medium is non-idle, and de-asserted by the external
device when the transmit and receive medium are
idle. The CRS2 can also in output mode when the
DM9106 port 2 is configured to reversed MII mode.
• COL2 (collision detection) is asserted by the
external device, when both the transmit and receive
medium is non-idle, and de-asserted by the external
device when the either transmit or receive medium
are idle. The COL2 can also in output mode when the
DM9106 port 2 is configured to reversed MII mode.
9.3.2 MII Serial Management
The MII serial management interface consists of a
data interface, basic register set in DM9106 port 0
and 1, and a serial management interface to the
register set. Through this interface it is possible to
control and configure multiple PHY devices, include
internal two ports, get status and error information,
and determine the type and capabilities of the
attached PHY device(s). The DM9106 default is
polling 3 ports basic registers 0,1,4, and 5 to get the
link, duplex, and speed status automatically.
Alternatively, the DM9106 can be programmed to
read or write any registers of 3 ports by section
6.8~11 CSR B,C,D,and E.
The DM9106 management functions correspond
to MII specification for IEEE 802.3u-1995 (Clause 22)
for registers 0 through 6 with vendor-specific registers
16,17, 18, 21, 22, 23 and 24~27.
In read/write operation, the management data
frame is 64-bits long and starts with 32 contiguous
logic one bits (preamble) synchronization clock cycles
on MDC. The Start of Frame Delimiter (SFD) is
indicated by a <01> pattern followed by the operation
code (OP):<10> indicates Read operation and <01>
indicates Write operation. For read operation, a 2-bit
turnaround (TA) filing between Register Address field
and Data field is provided for MDIO to avoid
contention. Following the turnaround time, 16-bit data
is read from or written onto management registers.
77
DM9106
3-port switch with PCI Interface
9.3.3 Serial Management Interface
The serial control interface uses a simple
two-wired serial interface to obtain and control the
status of the physical layer through the MII interface.
The serial control interface consists of MDC
(Management Data Clock), and MDI/O (Management
Data Input/Output) signals.
The MDIO pin is bi-directional and may be shared
by up to 32 devices.
9.3.4 Management Interface - Read Frame Structure
MDC
MDIO Read
32 "1"s
Idle
0
Preamble
1
SFD
1
0
A4
Op Code
A3
A0
PHY Address
R4
R3
R0
Register Address
0
Z
D15
//
D14
Turn Around
//
D1
D0
Data
Read
Write
Idle
9.3.5 Management Interface - Write Frame Structure
MDC
MDIO Write
32 "1"s
Idle
78
Preamble
0
1
SFD
0
1
Op Code
A4
A3
PHY Address
A0
R4
R3
R0
Register Address
Write
1
0
Turn Around
D15
D14
Data
D1
D0
Idle
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
9.4 Internal PHY functions
9.4.1 100Base-TX Operation
The transmitter section contains the following
functional blocks:
- 4B5B Encoder
- Scrambler
- Parallel to Serial Converter
- NRZ to NRZI Converter
- NRZI to MLT-3
- MLT-3 Driver
By scrambling the data, the total energy presented to
the cable is randomly distributed over a wide
frequency range. Without the scrambler, energy
levels on the cable could peak beyond FCC
limitations at frequencies related to the repeated 5B
sequences, like the continuous transmission of IDLE
symbols. The scrambler output is combined with the
NRZ 5B data from the code-group encoder via an
XOR logic function. The result is a scrambled data
stream with sufficient randomization to decrease
radiated emissions at critical frequencies.
9.4.1.3 Parallel to Serial Converter
9.4.1.1 4B5B Encoder
The 4B5B encoder converts 4-bit (4B) nibble data
generated by the MAC Reconciliation Layer into a
5-bit (5B) code group for transmission, see reference
Table 1. This conversion is required for control and
packet data to be combined in code groups. The
4B5B encoder substitutes the first 8 bits of the MAC
preamble with a J/K code-group pair (11000 10001)
upon transmit. The 4B5B encoder continues to
replace subsequent 4B preamble and data nibbles
with corresponding 5B code-groups. At the end of the
transmit packet, upon the deassertion of the Transmit
Enable signal from the MAC Reconciliation layer, the
4B5B encoder injects the T/R code-group pair (01101
00111) indicating the end of frame. After the T/R
code-group pair, the 4B5B encoder continuously
injects IDLEs into the transmit data stream until
Transmit Enable is asserted and the next transmit
packet is detected.
9.4.1.2 Scrambler
The scrambler is required to control the radiated
emissions (EMI) by spreading the transmit energy
across the frequency spectrum at the media
connector and on the twisted pair cable in
100Base-TX operation.
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
The Parallel to Serial Converter receives parallel 5B
scrambled data from the scrambler, and serializes it
(converts it from a parallel to a serial data stream).
The serialized data stream is then presented to the
NRZ to NRZI encoder block
9.4.1.4 NRZ to NRZI Encoder
After the transmit data stream has been scrambled
and serialized, the data must be NRZI encoded for
compatibility with the TP-PMD standard, for 100Base
-TX transmission over Category-5 unshielded twisted
pair cable.
9.4.1.5 MLT-3 Converter
The MLT-3 conversion is accomplished by converting
the data stream output, from the NRZI encoder into
two binary data streams, with alternately phased logic
one event.
9.4.1.6 MLT-3 Driver
The two binary data streams created at the MLT-3
converter are fed to the twisted pair output driver,
which converts these streams to current sources and
alternately drives either side of the transmit
transformer’s primary winding, resulting in a minimal
current MLT-3 signal.
79
DM9106
3-port switch with PCI Interface
9.4.1.7 4B5B Code Group
Symbol
Meaning
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data A
Data B
Data C
Data D
Data E
Data F
4B code
3210
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
5B Code
43210
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
I
J
K
T
R
H
Idle
SFD (1)
SFD (2)
ESD (1)
ESD (2)
Error
undefined
0101
0101
undefined
undefined
undefined
11111
11000
10001
01101
00111
00100
V
V
V
V
V
V
V
V
V
V
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
00000
00001
00010
00011
00101
00110
01000
01100
10000
11001
Table 1
80
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
9.4.2 100Base-TX Receiver
The 100Base-TX receiver contains several function
blocks that convert the scrambled 125Mb/s serial
data to synchronous 4-bit nibble data.
The receive section contains the following functional
blocks:
- Signal Detect
- Digital Adaptive Equalization
- MLT-3 to Binary Decoder
- Clock Recovery Module
- NRZI to NRZ Decoder
- Serial to Parallel
- Descrambler
- Code Group Alignment
- 4B5B Decoder
9.4.2.1 Signal Detect
The signal detect function meets the specifications
mandated by the ANSI XT12 TP-PMD 100Base-TX
standards for both voltage thresholds and timing
parameters.
9.4.2.2 Adaptive Equalization
When transmitting data over copper twisted pair
cable at high speed, attenuation based on frequency
becomes a concern. In high speed twisted pair
signaling, the frequency content of the transmitted
signal can vary greatly during normal operation based
on the randomness of the scrambled data stream.
This variation in signal attenuation, caused by
frequency variations, must be compensated for to
ensure the integrity of the received data. In order to
ensure quality transmission when employing MLT-3
encoding, the compensation must be able to adapt to
various cable lengths and cable types depending on
the installed environment. The selection of long cable
lengths for a given implementation requires
significant compensation, which will be over-killed in
a situation that includes shorter, less attenuating
cable lengths. Conversely, the selection of short or
intermediate
cable
lengths
requiring
less
compensation will cause serious under-compensation
for longer length cables. Therefore, the compensation
or equalization must be adaptive to ensure proper
conditioning of the received signal independent of the
cable length.
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
9.4.2.3 MLT-3 to NRZI Decoder
The DM9106 decodes the MLT-3 information from
the Digital Adaptive Equalizer into NRZI data.
9.4.2.4 Clock Recovery Module
The Clock Recovery Module accepts NRZI data from
the MLT-3 to NRZI decoder. The Clock Recovery
Module locks onto the data stream and extracts the
125Mhz reference clock. The extracted and
synchronized clock and data are presented to the
NRZI to NRZ decoder.
9.4.2.5 NRZI to NRZ
The transmit data stream is required to be NRZI
encoded for compatibility with the TP-PMD standard
for 100Base-TX transmission over Category-5
unshielded twisted pair cable. This conversion
process must be reversed on the receive end. The
NRZI to NRZ decoder, receives the NRZI data stream
from the Clock Recovery Module and converts it to a
NRZ data stream to be presented to the Serial to
Parallel conversion block.
9.4.2.6 Serial to Parallel
The Serial to Parallel Converter receives a serial data
stream from the NRZI to NRZ converter. It converts
the data stream to parallel data to be presented to the
descrambler.
9.4.2.7 Descrambler
Because of the scrambling process requires to
control the radiated emissions of transmit data
streams, the receiver must descramble the receive
data streams. The descrambler receives scrambled
parallel data streams from the Serial to Parallel
converter, and it descrambles the data streams, and
presents the data streams to the Code Group
alignment block.
81
DM9106
3-port switch with PCI Interface
9.4.2.8 Code Group Alignment
The Code Group Alignment block receives un-aligned
5B data from the descrambler and converts it into 5B
code group data. Code Group Alignment occurs after
the J/K is detected, and subsequent data is aligned
on a fixed boundary.
9.4.2.9 4B5B Decoder
The 4B5B Decoder functions as a look-up table that
translates incoming 5B code groups into 4B (Nibble)
data. When receiving a frame, the first 2 5-bit code
groups receive the start-of-frame delimiter (J/K
symbols). The J/K symbol pair is stripped and two
nibbles of preamble pattern are substituted. The last
two code groups are the end-of-frame delimiter (T/R
Symbols).
The T/R symbol pair is also stripped from the nibble,
presented to the Reconciliation layer.
9.4.3 10Base-T Operation
The 10Base-T transceiver is IEEE 802.3u compliant.
When the DM9106 is operating in 10Base-T mode,
the coding scheme is Manchester. Data processed
for transmit is presented in nibble format, converted
to a serial bit stream, then the Manchester encoded.
When receiving, the bit stream, encoded by the
Manchester, is decoded and converted into nibble
format.
9.4.4 Collision Detection
For half-duplex operation, a collision is detected
when the transmit and receive channels are active
simultaneously. Collision detection is disabled in full
duplex operation.
9.4.5 Carrier Sense
Carrier Sense (CRS) is asserted in half-duplex
operation during transmission or reception of data.
During full-duplex mode, CRS is asserted only during
receive operations.
82
9.4.6 Auto-Negotiation
The objective of Auto-negotiation is to provide a
means to exchange information between linked
devices and to automatically configure both devices
to take maximum advantage of their abilities. It is
important to note that Auto-negotiation does not test
the characteristics of the linked segment. The
Auto-Negotiation function provides a means for a
device to advertise supported modes of operation to
a remote link partner, acknowledge the receipt and
understanding of common modes of operation, and to
reject un-shared modes of operation. This allows
devices on both ends of a segment to establish a link
at the best common mode of operation. If more than
one common mode exists between the two devices, a
mechanism is provided to allow the devices to
resolve to a single mode of operation using a
predetermined priority resolution function.
Auto-negotiation also provides a parallel detection
function for devices that do not support the
Auto-negotiation feature. During Parallel detection
there is no exchange of information of configuration.
Instead, the receive signal is examined. If it is
discovered that the signal matches a technology,
which the receiving device supports, a connection will
be automatically established using that technology.
This allows devices not to support Auto-negotiation
but support a common mode of operation to establish
a link.
9.5 Auto MDIX HP Auto-MDIX Functional
Description
The DM9106 supports the automatic detect cable
connection type, MDI/MDIX (straight through/cross
over). A manual configuration by register bit for MDI
or MDIX is still accepted.
When set to automatic, the polarity of MDI/MDIX
controlled timing is generated by a 16-bits LFSR. The
switching cycle time is located from 200ms to 420ms.
The polarity control is always switch until detect
received signal. After selected MDI or MDIX,
This feature is able to detect the required cable
connection type.( straight through or crossed over )
and make correction automatically
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
RX + /- from DM9106
RX+/- to RJ45
TX + /- from DM9106
TX+/- to RJ45
* MDI : __________
* MDIX : - - - - - - - - -
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
83
DM9106
3-port switch with PCI Interface
10. DC and AC Electrical Characteristics
10.1 Absolute Maximum Ratings
Symbol
Parameter
VCC3
3.3V Supply Voltage
VCCI
1.8V core power supply
AVDD3
Analog power supply 3.3V
AVDDI
Analog power supply 1.8V
VIN
DC Input Voltage (VIN)
Storage Temperature range
TSTG
Ambient Temperature
TA
Lead Temperature
LT
(TL,soldering,10 sec.).
10.2 Operating Conditions
Symbol
Parameter
VCC3
3.3V Supply Voltage
VCCI
1.8V core power supply
AVDD3
Analog power supply 3.3V
AVDDI
Analog power supply 1.8V
PD
100BASE-TX
(Power
Dissipation)
10BASE-TX
Auto-negotiation or cable off
84
Min.
3.135
1.71
3.135
1.71
-0.5
-65
0
-
Min.
3.135
1.71
3.135
1.71
-
Typ.
3.30
1.80
3.30
1.80
230
70
140
250
Max.
3.6
1.95
3.6
1.95
5.5
+150
+70
+260
Max.
3.465
1.89
3.465
1.89
-
Unit
V
V
V
V
V
°C
°C
°C
Unit
V
V
V
V
mA
mA
mA
mA
360
mA
30
170
40
mA
mA
mA
Conditions
Lead-free Device
Conditions
1.8V only
3.3V only
TX idle, 1.8V only
50% utilization,
1.8V only
100% utilization,
1.8V only
3.3V only
1.8V only
3.3V only
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
10.3 DC Electrical Characteristics
Symbol
Inputs
VIL
VIH
IIL
IIH
Outputs
VOL
VOH
Receiver
VICM
Parameter
Min.
Typ.
Input Low Voltage
Input High Voltage
Input Low Leakage Current
Input High Leakage Current
2.0
-1
-
Output Low Voltage
Output High Voltage
RX+/RX- Common Mode Input
Voltage
Transmitter
VTD100 100TX+/- Differential Output
Voltage
VTD10 10TX+/- Differential Output Voltage
ITD100 100TX+/- Differential Output
Current
ITD10
10TX+/- Differential Output Current
Max.
Unit
Conditions
-
0.8
1
V
V
uA
uA
Vcond1
Vcond1
VIN = 0.0V, Vcond1
VIN = 3.3V, Vcond1
2.4
-
0.4
-
V
V
IOL = 4mA
IOH = -4mA
-
1.8
-
V
100 Ω Termination
Across
1.9
2.0
2.1
V
Peak to Peak
4.0
5
5.6
│19│
│20│
│21│
V
mA
Peak to Peak
Absolute Value
│40│
│50│
│56│
mA
Absolute Value
Note: Vcond1 = VCC3 = 3.3V, VCCI = 1.8V, AVDD3 = 3.3V, AVDDI = 1.8V.
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
85
DM9106
3-port switch with PCI Interface
10.3 AC characteristics
10.3.1 PCI Clock Specifications Timing
T1
2.0V
T2
0.8V
T3
T4
T5
Symbol
T1
T2
T3
T4
T5
Parameter
PCI_CLK High Time
PCI_CLK Low Time
PCI_CLK Rising Time
PCI_CLK Falling Time
Cycle Time
Min.
12
12
-
Typ.
-
Max.
4
4
Unit
ns
ns
ns
ns
Conditions
-
25
30
-
ns
-
10.3.2 Power On Reset Timing
T1
PWRST#
Strap pins
T2
Symbol
T1
T2
86
Parameter
PWRST# Low Period
Strap pin hold time with PWRST#
Min.
1
40
Typ.
-
Max.
-
Unit
ms
ns
Conditions
-
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
10.3.3 Other PCI Signals Timing Diagram
2.5V
CLK
T1
Output
T2
T3
Input
T5
T4
Symbol
T1
T2
T3
T4
T5
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
Parameter
Clk-To-Signal Valid Delay
Float-To-Active Delay From Clk
Active-To-Float Delay From Clk
Input Signal Valid Setup Time Before Clk
Input Signal Hold Time From Clk
Min.
2
2
7
0
Typ.
-
Max.
13
28
-
Unit
ns
ns
ns
ns
ns
Conditions
Cload = 50 pF
-
87
DM9106
3-port switch with PCI Interface
10.3.4 Port 2 MII Interface Transmit Timing
TXC2
TXE2
T1
T2
TXD2_3~0
Symbol
Parameter
T1
TXE2,TXD2_3~0 Setup Time
T2
TXE2,TXD2_3~0 Hold Time
Min.
Typ.
32
8
Max.
Unit
ns
ns
Max.
Unit
ns
ns
10.3.5 Port 2 MII Interface Receive Timing
RXC2
RXER2,RXDV2
T1
T2
RXD2_3~0
Symbol
Parameter
T1
RXER2, RXDV2,RXD2_3~0 Setup Time
T2
RXER2, RXDV2,RXD2_3~0 Hold Time
88
Min.
5
5
Typ.
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
10.3.6 MII Management Interface Timing
T1
MDC
T2
MDIO (drived by DM9106)
T3
T4
MDIO (drived by exetrnal MII)
T5
Symbol
T1
T2
T3
T4
T5
Parameter
MDC Frequency
MDIO by DM9106 Setup Time
MDIO by DM9106 Hold Time
MDIO by External MII Setup Time
MDIO by External MII Hold Time
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
Min.
40
40
Typ.
0.52
955
960
Max.
Unit
MHz
ns
ns
ns
ns
89
DM9106
3-port switch with PCI Interface
10.3.7 EEPROM timing
T1
T2
EECS
T3
EECK
T4
EEDO
T6
T5
EEDI
T7
Symbol
T1
T2
T3
T4
T5
T6
T7
90
Parameter
EECS Setup Time
EECS Hold Time
EECK Frequency
EEDO Setup Time
EEDO Hold Time
EEDI Setup Time
EEDI Hold Time
Min.
8
8
Typ.
480
2080
0.38
460
2100
Max.
Unit
ns
ns
MHz
ns
ns
ns
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
DM9106
3-port switch with PCI Interface
11. Package Information
128 Pins LQFP Package Outline Information:
Dimension in mm
Dimension in inch
Min
Nom
Max
Min
Nom
Max
A
1.60
0.063
A1
0.05
0.002
A2
1.35
1.40
1.45
0.053
0.055
0.057
b
0.13
0.18
0.23
0.005
0.007
0.009
b1
0.13
0.16
0.19
0.005
0.006
0.007
c
0.09
0.20
0.004
0.008
c1
0.09
0.16
0.004
0.006
D
15.85
16.00
16.15
0.624
0.630
0.636
D1
13.90
14.00
14.10
0.547
0.551
0.555
E
15.85
16.00
16.15
0.624
0.630
0.636
E1
13.90
14.00
14.10
0.547
0.551
0.555
e
0.40 BSC
0.016 BSC
L
0.45
0.60
0.75
0.018
0.024
0.030
L1
1.00 REF
0.039 REF
R1
0.08
0.003
R2
0.08
0.20
0.003
0.008
S
0.20
0.008
o
o
o
o
o
o
θ
0
3.5
7
0
3.5
7
o
o
θ1
0
0
o
o
θ2
12 TYP
12 TYP
o
o
θ3
12 TYP
12 TYP
1. Dimension D1 and E1 do not include resin fin.
2. All dimensions are base on metric system.
3. General appearance spec should base on its final visual inspection spec.
Symbol
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
91
DM9106
3-port switch with PCI Interface
reference purposes only.
12. Ordering Information
Part Number
DM9106EP
Pin Count
128
Package
LQFP
(Pb-free)
Disclaimer
The information appearing in this publication is
believed to be accurate. Integrated circuits sold by
DAVICOM Semiconductor are covered by the
warranty and patent indemnification provisions
stipulated in the terms of sale only. DAVICOM makes
no warranty, express, statutory, implied or by
description regarding the information in this
publication or regarding the information in this
publication or regarding the freedom of the described
chip(s) from patent infringement.
FURTHER,
DAVICOM
MAKES
NO
WARRANTY
OF
MERCHANTABILITY OR FITNESS FOR ANY
PURPOSE. DAVICOM reserves the right to halt
production or alter the specifications and prices at
any time without notice. Accordingly, the reader is
cautioned to verify that the data sheets and other
information in this publication are current before
placing orders. Products described herein are
intended for use in normal commercial applications.
Applications involving unusual environmental or
reliability requirements, e.g. military equipment or
medical life support equipment, are specifically not
recommended without additional processing by
DAVICOM for such applications. Please note that
application circuits illustrated in this document are for
DAVICOM’s terms and conditions printed on the
order acknowledgment govern all sales by DAVICOM.
DAVICOM will not be bound by any terms
inconsistent with these unless DAVICOM agrees
otherwise in writing. Acceptance of the buyer’s orders
shall be based on these terms.
Company Overview
DAVICOM Semiconductor Inc. develops and
manufactures integrated circuits for integration into
data communication products. Our mission is to
design and produce IC products that are the
industry’s best value for Data, Audio, Video, and
Internet/Intranet applications. To achieve this goal,
we have built an organization that is able to develop
chipsets in response to the evolving technology
requirements of our customers while still delivering
products that meet their cost requirements.
Products
We offer only products that satisfy high performance
requirements and which are compatible with major
hardware and software standards. Our currently
available and soon to be released products are based
on our proprietary designs and deliver high quality,
high performance chipsets that comply with modem
communication standards and Ethernet networking
standards.
Contact Windows
For additional information about DAVICOM products, contact the Sales department at:
Headquarters
Hsin-chu Office:
No.6 Li-Hsin Rd. VI,
Science-based Park,
Hsin-chu City, Taiwan, R.O.C.
TEL: + 886-3-5798797
FAX: + 886-3-5646929
MAIL: [email protected]
HTTP: http://www.davicom.com.tw
WARNING
Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near the limits of
the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and function.
92
Preliminary datasheet
DM9106-DS-P01
July 9, 2009