Numonyx M25P10-AVMB6T/Y 1 mbit, serial flash memory, 50 mhz spi bus interface Datasheet

M25P10-A
1 Mbit, serial Flash memory, 50 MHz SPI bus interface
Features
■
1 Mbit of Flash memory
■
Page Program (up to 256 bytes) in 1.4 ms
(typical)
■
Sector Erase (256 Kbit) in 0.65 s (typical)
■
Bulk Erase (1 Mbit) in 1.7 s (typical)
■
2.3 to 3.6 V single supply voltage
■
SPI bus compatible serial interface
■
50 MHz Clock rate (maximum)
■
Deep Power-down mode 1 µA (typical)
■
Electronic signatures
– JEDEC standard two-byte signature
(2011h)
– RES instruction, one-byte signature (10h),
for backward compatibility
■
More than 20 years’ data retention
■
Packages
– ECOPACK® (RoHS compliant)
SO8 (MN)
150 mil width
VFQFPN8 (MP)
(MLP8)
UFDFPN8 (MB)
2 x 3 mm
December 2007
Rev 11
1/51
www.numonyx.com
1
Contents
M25P10-A
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6
Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2
Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3
Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 11
4.4
Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 11
4.5
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.6
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.7
Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3
Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.5
2/51
6.4.1
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4.2
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4.3
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4.4
SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
M25P10-A
Contents
6.6
Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.7
Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . 25
6.8
Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.9
Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.10
Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.11
Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.12
Release from Deep Power-down and Read Electronic Signature (RES) . 31
7
Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
11
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3/51
List of tables
M25P10-A
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
4/51
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Data retention and endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
DC characteristics (device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
DC characteristics (device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Instruction times (device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Instruction times (device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
AC characteristics (25 MHz operation, device grade 6 or 3) . . . . . . . . . . . . . . . . . . . . . . . 40
AC characteristics (40 MHz operation, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
AC characteristics (50 MHz operation, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
SO8 narrow – 8-lead plastic small outline, 150 mils body width,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead,
2 x 3 mm package mechanical data47
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
M25P10-A
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SO, VFQFPN and UFDFPN8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 19
Read Status Register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . 21
Write Status Register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 24
Read Data Bytes at Higher Speed (FAST_READ) instruction sequence
and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14. Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. Sector Erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16. Bulk Erase (BE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 17. Deep Power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) instruction
sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 19. Release from Deep Power-down (RES) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 32
Figure 20. Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 21. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 22. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 23. Write Protect Setup and Hold timing during WRSR when SRWD=1 . . . . . . . . . . . . . . . . . 43
Figure 24. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 25. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 26. SO8 narrow – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . 45
Figure 27. VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 28. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead,
2 x 3 mm package outline47
5/51
Description
1
M25P10-A
Description
The M25P10-A is a 1 Mbit (128 Kbit x 8) serial Flash memory, with advanced write
protection mechanisms, accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program
instruction.
The memory is organized as 4 sectors, each containing 128 pages. Each page is 256 bytes
wide. Thus, the whole memory can be viewed as consisting of 512 pages, or 131,072 bytes.
The whole memory can be erased using the Bulk Erase instruction, or a sector at a time,
using the Sector Erase instruction.
Figure 1.
Logic diagram
VCC
D
Q
C
S
M25P10-A
W
HOLD
VSS
AI05760
Table 1.
Signal names
Signal name
6/51
Function
Direction
C
Serial Clock
Input
D
Serial Data input
Input
Q
Serial Data output
Output
S
Chip Select
Input
W
Write Protect
Input
HOLD
Hold
Input
VCC
Supply voltage
VSS
Ground
M25P10-A
Description
Figure 2.
SO, VFQFPN and UFDFPN8 connections
M25P10-A
S
Q
W
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
C
D
AI05761B
1. There is an exposed die paddle on the underside of the MLP8 packages. This is pulled, internally, to VSS,
and must not be allowed to be connected to any other voltage or signal line on the PCB.
2. See Package mechanical section for package dimensions, and how to identify pin-1.
7/51
Signal descriptions
2
Signal descriptions
2.1
Serial Data output (Q)
M25P10-A
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
2.2
Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C).
2.3
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data output (Q) changes after the falling edge of Serial Clock (C).
2.4
Chip Select (S)
When this input signal is High, the device is deselected and Serial Data output (Q) is at high
impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress,
the device will be in the Standby mode (this is not the Deep Power-down mode). Driving
Chip Select (S) Low selects the device, placing it in the Active Power mode.
After power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
2.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data
input (D) and Serial Clock (C) are Don’t care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
2.6
Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against program or erase instructions (as specified by the values in the BP1 and
BP0 bits of the Status Register).
8/51
M25P10-A
3
SPI modes
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
●
CPOL=0, CPHA=0
●
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 4, is the clock polarity when the
bus master is in Standby mode and not transferring data:
Figure 3.
●
C remains at 0 for (CPOL=0, CPHA=0)
●
C remains at 1 for (CPOL=1, CPHA=1)
Bus master and memory devices on the SPI bus
VSS
VCC
R
SDO
SPI interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
VCC
C Q D
SPI Bus Master
SPI memory
device
R
CS3
CS2
VCC
C Q D
VSS
VCC
C Q D
VSS
SPI memory
device
R
VSS
SPI memory
device
R
CS1
S
W
HOLD
S
W
HOLD
S
W
HOLD
AI12836b
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 3 shows an example of three devices connected to an MCU, on an SPI bus. Only one
device is selected at a time, so only one device drives the Serial Data output (Q) line at a
time, the other devices are high impedance. Resistors R (represented in Figure 3) ensure
that the M25P10-A is not selected if the Bus Master leaves the S line in the high impedance
state. As the Bus Master may enter a state where all inputs/outputs are in high impedance
at the same time (for example, when the Bus Master is reset), the clock line (C) must be
connected to an external pull-down resistor so that, when all inputs/outputs become high
impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and
C do not become High at the same time, and so, that the tSHCH requirement is met). The
typical value of R is 100 kΩ, assuming that the time constant R*Cp (Cp = parasitic
capacitance of the bus line) is shorter than the time during which the Bus Master leaves the
SPI bus in high impedance.
9/51
SPI modes
M25P10-A
Example: Cp = 50 pF, that is R*Cp = 5 µs <=> the application must ensure that the Bus
Master never leaves the SPI bus in the high impedance state for a time period shorter than
5 µs.
Figure 4.
SPI modes supported
CPOL CPHA
0
0
C
1
1
C
D
Q
MSB
MSB
AI01438B
10/51
M25P10-A
Operating features
4
Operating features
4.1
Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one
byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is
followed by the internal Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be
programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive
addresses on the same page of memory.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes (see Page Program (PP)
and Table 16: Instruction times (device grade 6)).
4.2
Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be
applied, the bytes of memory need to have been erased to all 1s (FFh). This can be
achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the
entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of
duration tSE or tBE).
The Erase instruction must be preceded by a Write Enable (WREN) instruction.
4.3
Polling during a Write, Program or Erase cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase
(SE or BE) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, or tBE). The
Write In Progress (WIP) bit is provided in the Status Register so that the application program
can monitor its value, polling it to establish when the previous Write cycle, Program cycle or
Erase cycle is complete.
4.4
Active Power, Standby Power and Deep Power-down modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode.
When Chip Select (S) is High, the device is deselected, but could remain in the Active Power
mode until all internal cycles have completed (Program, Erase, Write Status Register). The
device then goes in to the Standby Power mode. The device consumption drops to ICC1.
The Deep Power-down mode is entered when the specific instruction (the Deep Powerdown (DP) instruction) is executed. The device consumption drops further to ICC2. The
device remains in this mode until another specific instruction (the Release from Deep
Power-down and Read Electronic Signature (RES) instruction) is executed.
While in the Deep Power-down mode, the device ignores all write, program and erase
instructions (see Deep Power-down (DP)). This can be used as an extra software protection
mechanism, when the device is not in active use, to protect the device from inadvertent
write, program or erase instructions.
11/51
Operating features
4.5
M25P10-A
Status Register
The Status Register contains a number of status and control bits, as shown in Table 6, that
can be read or set (as appropriate) by specific instructions. For a detailed description of the
Status Register bits, see Section 6.4: Read Status Register (RDSR).
4.6
Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25P10-A features the following data protection mechanisms:
●
Power On Reset and an internal timer (tPUW) can provide protection against inadvertent
changes while the power supply is outside the operating specification.
●
Program, Erase and Write Status Register instructions are checked that they consist of
a number of clock pulses that is a multiple of eight, before they are accepted for
execution.
●
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
12/51
Power-up
–
Write Disable (WRDI) instruction completion
–
Write Status Register (WRSR) instruction completion
–
Page Program (PP) instruction completion
–
Sector Erase (SE) instruction completion
–
Bulk Erase (BE) instruction completion
●
The Block Protect (BP1, BP0) bits allow part of the memory to be configured as readonly. This is the Software Protected mode (SPM).
●
The Write Protect (W) signal, in co-operation with the Status Register Write Disable
(SRWD) bit, allows the Block Protect (BP1, BP0) bits and Status Register Write Disable
(SRWD) bit to be write-protected. This is the Hardware Protected mode (HPM).
●
In addition to the low power consumption feature, the Deep Power-down mode offers
extra software protection, as all write, program and erase instructions are ignored.
M25P10-A
Operating features
Table 2.
Protected area sizes
Status
Register
content
Memory content
BP1
bit
BP0
bit
0
0
none
All sectors(1) (four sectors: 0, 1, 2 and 3)
0
1
Upper quarter (sector 3)
Lower three-quarters (three sectors: 0 to 2)
1
0
Upper half (two sectors: 2 and 3)
Lower half (sectors 0 and 1)
1
1
All sectors (four sectors: 0, 1, 2 and 3) none
Protected area
Unprotected area
1. The device is ready to accept a Bulk Erase instruction if, and only if, both Block Protect (BP1, BP0) bits are
0.
4.7
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence. However, taking this signal Low does not terminate any
Write Status Register, Program or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (S) Low.
The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low (as shown in Figure 5).
The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition
starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes
Low. (This is shown in Figure 5).
During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data
input (D) and Serial Clock (C) are Don’t care.
Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration
of the Hold condition. This is to ensure that the state of the internal logic remains unchanged
from the moment of entering the Hold condition.
If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of
resetting the internal logic of the device. To restart communication with the device, it is
necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents
the device from going back to the Hold condition.
13/51
Operating features
Figure 5.
M25P10-A
Hold condition activation
C
HOLD
Hold
condition
(standard use)
Hold
condition
(non-standard use)
AI02029D
14/51
M25P10-A
Memory organization
The memory is organized as:
●
131,072 bytes (8 bits each)
●
4 sectors (256 Kbits, 32768 bytes each)
●
512 pages (256 bytes each).
Each page can be individually programmed (bits are programmed from 1 to 0). The device is
sector or bulk erasable (bits are erased from 0 to 1) but not page erasable.
Table 3.
Memory organization
Sector
Figure 6.
Address range
3
18000h
1FFFFh
2
10000h
17FFFh
1
08000h
0FFFFh
0
00000h
07FFFh
Block diagram
HOLD
W
High Voltage
Generator
Control Logic
S
C
D
I/O Shift Register
Q
Address Register
and Counter
Status
Register
256 byte
Data Buffer
1FFFFh
18000h
Y Decoder
5
Memory organization
10000h
08000h
00000h
000FFh
256 bytes (page size)
X Decoder
15/51
Instructions
6
M25P10-A
Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit
first.
Serial Data input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select
(S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most
significant bit first, on Serial Data input (D), each bit being latched on the rising edges of
Serial Clock (C).
The instruction set is listed in Table 4.
Every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
Chip Select (S) must be driven High after the last bit of the instruction sequence has been
shifted in.
In the case of a Read Data Bytes (READ), Read Data Bytes at higher speed (FAST_READ),
Read Identification (RDID), Read Status Register (RDSR) or Release from Deep Powerdown, and Read Electronic Signature (RES) instruction, the shifted-in instruction sequence
is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the
data-out sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status
Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP)
instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the
instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when
the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of
eight.
All attempts to access the memory array during a Write Status Register cycle, Program
cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program
cycle or Erase cycle continues unaffected.
16/51
M25P10-A
Instructions
Table 4.
Instruction set
Instruction
One-byte instruction Address Dummy
code
bytes
bytes
Description
Data
bytes
WREN
Write Enable
0000 0110
06h
0
0
0
WRDI
Write Disable
0000 0100
04h
0
0
0
Read Identification
1001 1111
9Fh
0
0
1 to 3
RDSR
Read Status Register
0000 0101
05h
0
0
1 to ∞
WRSR
Write Status Register
0000 0001
01h
0
0
1
READ
Read Data Bytes
0000 0011
03h
3
0
1 to ∞
Read Data Bytes at Higher
Speed
0000 1011
0Bh
3
1
1 to ∞
PP
Page Program
0000 0010
02h
3
0
1 to 256
SE
Sector Erase
1101 1000
D8h
3
0
0
BE
Bulk Erase
1100 0111
C7h
0
0
0
DP
Deep Power-down
1011 1001
B9h
0
0
0
Release from Deep Powerdown, and Read Electronic
Signature
0
3
1 to ∞
1010 1011
ABh
0
0
0
RDID
(1)
FAST_READ
RES
Release from Deep Powerdown
1. The Read Identification (RDID) instruction is available in products with process technology code X and Y
(see application note AN1995).
6.1
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 7) sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector
Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
Figure 7.
Write Enable (WREN) instruction sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI02281E
17/51
Instructions
6.2
M25P10-A
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 8) resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under the following conditions:
●
Power-up
●
Write Disable (WRDI) instruction completion
●
Write Status Register (WRSR) instruction completion
●
Page Program (PP) instruction completion
●
Sector Erase (SE) instruction completion
●
Bulk Erase (BE) instruction completion
Figure 8.
Write Disable (WRDI) instruction sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI03750D
18/51
M25P10-A
6.3
Instructions
Read Identification (RDID)
The Read Identification (RDID) instruction is available in products with process technology
code X and Y.
The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be
read, followed by two bytes of device identification. The manufacturer identification is
assigned by JEDEC, and has the value 20h for Numonyx. The device identification is
assigned by the device manufacturer, and indicates the memory type in the first byte (20h),
and the memory capacity of the device in the second byte (11h).
Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is
not decoded, and has no effect on the cycle that is in progress.
The Read Identification (RDID) instruction should not be issued while the device is in Deep
Power-down mode.
The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code
for the instruction is shifted in. This is followed by the 24-bit device identification, stored in
the memory, being shifted out on Serial Data output (Q), each bit being shifted out during
the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 9.
The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at
any time during data output.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in
the Standby Power mode, the device waits to be selected, so that it can receive, decode and
execute instructions.
Table 5.
Read identification (RDID) data-out sequence
Device identification
Manufacturer identification
20h
Figure 9.
Memory type
Memory capacity
20h
11h
Read Identification (RDID) instruction sequence and data-out sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
28 29 30 31
C
Instruction
D
Manufacturer Identification
Device Identification
High Impedance
Q
15 14 13
MSB
3
2
1
0
MSB
AI06809b
19/51
Instructions
6.4
M25P10-A
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Program, Erase or Write Status
Register cycle is in progress. When one of these cycles is in progress, it is recommended to
check the Write In Progress (WIP) bit before sending a new instruction to the device. It is
also possible to read the Status Register continuously, as shown in Figure 10.
Table 6.
Status Register format
b7
SRWD
b0
0
0
0
BP1
BP0
WEL
WIP
Status Register Write Protect
Block Protect bits
Write Enable Latch bit
Write In Progress bit
The status and control bits of the Status Register are as follows:
6.4.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to ‘1’, such a cycle is in progress, when reset to
‘0’ no such cycle is in progress.
6.4.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to ‘1’ the internal Write Enable Latch is set, when set to ‘0’ the internal Write
Enable Latch is reset and no Write Status Register, Program or Erase instruction is
accepted.
6.4.3
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against program and erase instructions. These bits are written with the
Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1,
BP0) bits is set to ‘1’, the relevant memory area (as defined in Table 2) becomes protected
against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect (BP1,
BP0) bits can be written provided that the Hardware Protected mode has not been set. The
Bulk Erase (BE) instruction is executed if, and only if, both Block Protect (BP1, BP0) bits are
0.
6.4.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to ‘1’, and Write Protect (W) is driven Low). In this mode, the
20/51
M25P10-A
Instructions
non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the
Write Status Register (WRSR) instruction is no longer accepted for execution.
Figure 10. Read Status Register (RDSR) instruction sequence and data-out
sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
D
Status Register Out
Status Register Out
High Impedance
Q
7
MSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
AI02031E
21/51
Instructions
6.5
M25P10-A
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded and
executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on Serial Data input (D).
The instruction sequence is shown in Figure 11.
The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the
Status Register. b6, b5 and b4 are always read as 0.
Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.
If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select
(S) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is
initiated. While the Write Status Register cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the
Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as readonly, as defined in Table 2. The Write Status Register (WRSR) instruction also allows the
user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the
Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect
(W) signal allow the device to be put in the Hardware Protected mode (HPM). The Write
Status Register (WRSR) instruction is not executed once the Hardware Protected mode
(HPM) is entered.
The protection features of the device are summarized in Table 7.
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W) is driven High or Low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to ‘1’, two
cases need to be considered, depending on the state of Write Protect (W):
22/51
●
If Write Protect (W) is driven High, it is possible to write to the Status Register provided
that the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction
●
If Write Protect (W) is driven Low, it is not possible to write to the Status Register even
if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN)
instruction. (Attempts to write to the Status Register are rejected, and are not accepted
for execution). As a consequence, all the data bytes in the memory area that are
software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register,
are also hardware protected against data modification.
M25P10-A
Instructions
Regardless of the order of the two events, the Hardware Protected mode (HPM) can be
entered:
●
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)
Low
●
or by driving Write Protect (W) Low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected mode (HPM) once entered is to pull Write
Protect (W) High.
If Write Protect (W) is permanently tied High, the Hardware Protected mode (HPM) can
never be activated, and only the Software Protected mode (SPM), using the Block Protect
(BP1, BP0) bits of the Status Register, can be used.
Figure 11. Write Status Register (WRSR) instruction sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
Status
Register In
7
D
High Impedance
6
5
4
3
2
1
0
MSB
Q
AI02282D
Table 7.
Protection modes
Memory content
W
SRWD
signal
bit
1
0
0
0
1
1
0
1
Mode
Write protection of the
Status Register
Protected area(1)
Unprotected
area(1)
Status Register is writable (if
Software the WREN instruction has set
protected the WEL bit)
(SPM) The values in the SRWD, BP1
and BP0 bits can be changed
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program
and Sector Erase
instructions
Status Register is hardware
Hardware write protected
protected The values in the SRWD, BP1
(HPM) and BP0 bits cannot be
changed
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program
and Sector Erase
instructions
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2.
23/51
Instructions
6.6
M25P10-A
Read Data Bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that
address, is shifted out on Serial Data output (Q), each bit being shifted out, at a maximum
frequency fR, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 12.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ)
instruction, while an Erase, Program or Write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
Figure 12. Read Data Bytes (READ) instruction sequence and data-out sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-bit address
23 22 21
D
3
2
1
0
MSB
Data Out 1
High Impedance
Q
7
6
5
4
3
2
Data Out 2
1
0
7
MSB
AI03748D
1. Address bits A23 to A17 are Don’t care.
24/51
M25P10-A
6.7
Instructions
Read Data Bytes at Higher Speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).
Then the memory contents, at that address, is shifted out on Serial Data output (Q), each bit
being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 13.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ)
instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving
Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any
Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in
progress.
Figure 13. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence
and data-out sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
C
Instruction
24-bit address
23 22 21
D
3
2
1
0
High Impedance
Q
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Dummy byte
D
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
7
Q
MSB
6
5
4
3
2
1
0
7
MSB
6
5
4
3
2
1
0
7
MSB
AI04006
1. Address bits A23 to A17 are Don’t care.
25/51
Instructions
6.8
M25P10-A
Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory
(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable (WREN) instruction has been
decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by
the instruction code, three address bytes and at least one data byte on Serial Data input (D).
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes
beyond the end of the current page are programmed from the start address of the same
page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 14.
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less
than 256 Data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes (see Table 16: Instruction
times (device grade 6)).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect
(BP1, BP0) bits (see Table 3 and Table 2) is not executed.
26/51
M25P10-A
Instructions
Figure 14. Page Program (PP) instruction sequence
S
0
1
2
3
4
5
6
7
8
28 29 30 31 32 33 34 35 36 37 38 39
9 10
C
Instruction
24-bit address
23 22 21
D
3
2
Data byte 1
1
0
7
6
5
4
3
2
1
0
MSB
MSB
2078
2079
2077
2076
2075
2074
2073
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2072
S
1
0
C
Data byte 2
D
7
6
MSB
5
4
3
2
Data byte 3
1
0
7
MSB
6
5
4
3
2
Data byte 256
1
0
7
6
5
4
3
2
MSB
AI04082B
1. Address bits A23 to A17 are Don’t care.
27/51
Instructions
6.9
M25P10-A
Sector Erase (SE)
The Sector Erase (SE) instruction sets to ‘1’ (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded, the device sets the Write
Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address bytes on Serial Data input (D). Any address inside the
sector (see Table 3) is a valid address for the Sector Erase (SE) instruction. Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 15.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is
initiated. While the Sector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect
(BP1, BP0) bits (see Table 3 and Table 2) is not executed.
Figure 15. Sector Erase (SE) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
29 30 31
C
Instruction
D
24-bit address
23 22
2
1
0
MSB
AI03751D
1. Address bits A23 to A17 are Don’t care.
28/51
M25P10-A
6.10
Instructions
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to ‘1’ (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in Figure 16.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S)
is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the
Bulk Erase cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk
Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Bulk Erase (BE) instruction is executed only if both Block Protect (BP1, BP0) bits are 0.
The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected.
Figure 16. Bulk Erase (BE) instruction sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
AI03752D
29/51
Instructions
6.11
M25P10-A
Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction is the only way to put the device in the
lowest consumption mode (the Deep Power-down mode). It can also be used as a software
protection mechanism, while the device is not in active use, as in this mode, the device
ignores all write, program and erase instructions.
Driving Chip Select (S) High deselects the device, and puts the device in the Standby mode
(if there is no internal cycle currently in progress). But this mode is not the Deep Powerdown mode. The Deep Power-down mode can only be entered by executing the Deep
Power-down (DP) instruction, to reduce the standby current (from ICC1 to ICC2, as specified
in Table 14).
To take the device out of Deep Power-down mode, the Release from Deep Power-down and
Read Electronic Signature (RES) instruction must be issued. No other instruction must be
issued while the device is in Deep Power-down mode.
The Release from Deep Power-down, and Read Electronic Signature (RES) instruction and
the Read Identification (RDID) instruction also allow the electronic signature of the device to
be output on Serial Data output (Q).
The Deep Power-down mode automatically stops at power-down, and the device always
powers-up in the Standby mode.
The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed
by the instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 17.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as
Chip Select (S) is driven High, it requires a delay of tDP before the supply current is reduced
to ICC2 and the Deep Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 17. Deep Power-down (DP) instruction sequence
S
0
1
2
3
4
5
6
7
tDP
C
Instruction
D
Standby mode
Deep Power-down mode
AI03753D
30/51
M25P10-A
6.12
Instructions
Release from Deep Power-down and Read Electronic
Signature (RES)
To take the device out of Deep Power-down mode, the Release from Deep Power-down and
Read Electronic Signature (RES) instruction must be issued. No other instruction must be
issued while the device is in Deep Power-down mode.
The instruction can also be used to read, on Serial Data output (Q), the 8-bit electronic
signature, whose value for the M25P10-A is 10h.
Except while an Erase, Program or Write Status Register cycle is in progress, the Release
from Deep Power-down and Read Electronic Signature (RES) instruction always provides
access to the 8-bit electronic signature of the device, and can be applied even if the Deep
Power-down mode has not been entered.
Any release from Deep Power-down and Read Electronic Signature (RES) instruction while
an Erase, Program or Write Status Register cycle is in progress, is not decoded, and has no
effect on the cycle that is in progress.
The device is first selected by driving Chip Select (S) Low. The instruction code is followed
by 3 dummy bytes, each bit being latched-in on Serial Data input (D) during the rising edge
of Serial Clock (C). Then, the 8-bit electronic signature, stored in the memory, is shifted out
on Serial Data output (Q), each bit being shifted out during the falling edge of Serial Clock
(C).
The instruction sequence is shown in Figure 18.
The Release from Deep Power-down and Read Electronic Signature (RES) instruction is
terminated by driving Chip Select (S) High after the electronic signature has been read at
least once. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is
driven Low, cause the electronic signature to be output repeatedly.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. If the
device was not previously in the Deep Power-down mode, the transition to the Standby
Power mode is immediate. If the device was previously in the Deep Power-down mode,
though, the transition to the Standby Power mode is delayed by tRES2, and Chip Select (S)
must remain High for at least tRES2(max), as specified in Table 18. Once in the Standby
Power mode, the device waits to be selected, so that it can receive, decode and execute
instructions.
Driving Chip Select (S) High after the 8-bit instruction byte has been received by the device,
but before the whole of the 8-bit electronic signature has been transmitted for the first time
(as shown in Figure 19), still ensures that the device is put into Standby Power mode. If the
device was not previously in the Deep Power-down mode, the transition to the Standby
Power mode is immediate. If the device was previously in the Deep Power-down mode,
though, the transition to the Standby Power mode is delayed by tRES1, and Chip Select (S)
must remain High for at least tRES1(max), as specified in Table 18. Once in the Standby
Power mode, the device waits to be selected, so that it can receive, decode and execute
instructions.
31/51
Instructions
M25P10-A
Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) instruction
sequence and data-out sequence
S
0
1
2
3
4
5
6
7
8
28 29 30 31 32 33 34 35 36 37 38
9 10
C
Instruction
tRES2
3 Dummy bytes
23 22 21
D
3
2
1
0
MSB
Electronic Signature Out
High Impedance
7
Q
6
5
4
3
2
1
0
MSB
Deep Power-down mode
Standby mode
AI04047C
1. The value of the 8-bit electronic signature, for the M25P10-A, is 10h.
Figure 19. Release from Deep Power-down (RES) instruction sequence
S
0
1
2
3
4
5
6
7
tRES1
C
Instruction
D
High Impedance
Q
Deep Power-down mode
Standby mode
AI04078B
32/51
M25P10-A
7
Power-up and power-down
Power-up and power-down
At power-up and power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on VCC) until VCC reaches the correct value:
●
VCC(min) at power-up, and then for a further delay of tVSL
●
VSS at power-down
A safe configuration is provided in Section 3: SPI modes.
To avoid data corruption and inadvertent write operations during power-up, a Power On
Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less
than the Power On Reset (POR) threshold voltage, VWI – all operations are disabled, and
the device does not respond to any instruction.
Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Sector Erase
(SE), Bulk Erase (BE) and Write Status Register (WRSR) instructions until a time delay of
tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the
correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min).
No Write Status Register, Program or Erase instructions should be sent until the later of:
●
tPUW after VCC passed the VWI threshold
●
tVSL after VCC passed the VCC(min) level
These values are specified in Table 8.
If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be
selected for read instructions even if the tPUW delay is not yet fully elapsed.
At power-up, the device is in the following state:
●
The device is in the Standby mode (not the Deep Power-down mode).
●
The Write Enable Latch (WEL) bit is reset.
●
The Write In Progress (WIP) bit is reset.
Normal precautions must be taken for supply rail decoupling, to stabilize the VCC supply.
Each device in a system should have the VCC rail decoupled by a suitable capacitor close to
the package pins. (Generally, this capacitor is of the order of 0.1 µF).
At power-down, when VCC drops from the operating voltage, to below the Power On Reset
(POR) threshold voltage, VWI, all operations are disabled and the device does not respond
to any instruction (the designer needs to be aware that if a power-down occurs while a
Write, Program or Erase cycle is in progress, some data corruption can result).
33/51
Power-up and power-down
M25P10-A
Figure 20. Power-up timing
VCC
VCC(max)
Program, Erase and Write commands are rejected by the device
Chip selection not allowed
VCC(min)
tVSL
Reset state
of the
device
Read access allowed
Device fully
accessible
VWI
tPUW
time
AI04009C
Table 8.
Power-up timing and VWI threshold
Symbol
Parameter
Max
Unit
tVSL(1)
VCC(min) to S low
10
tPUW(1)
Time delay to write instruction
1
10
ms
VWI(1)
Write Inhibit voltage (device grade 6)
1
2
V
VWI(1)
Write Inhibit voltage (device grade 3)
1
2.2
V
1. These parameters are characterized only.
34/51
Min
µs
M25P10-A
8
Initial delivery state
Initial delivery state
The device is delivered with the memory array erased: all bits are set to ‘1’ (each byte
contains FFh). The Status Register contains 00h (all Status Register bits are 0).
9
Maximum rating
Stressing the device above the rating listed in Table 9: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the Numonyx SURE Program
and other relevant quality documents.
Table 9.
Absolute maximum ratings
Symbol
Parameter
TSTG
Storage temperature
TLEAD
Lead temperature during soldering
Min
Max
Unit
–65
150
°C
see (1)
VIO
Input and output voltage (with respect to ground)
–0.6
VCC + 0.6
V
VCC
Supply voltage
–0.6
4.0
V
–2000
2000
V
VESD
Electrostatic discharge voltage (Human Body
model)(2)
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the Numonyx
ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances
(RoHS) 2002/95/EU.
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω).
35/51
DC and AC parameters
10
M25P10-A
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 10.
Operating conditions
Symbol
VCC
TA
Parameter
Min
Supply voltage
2.3
(1)
Max
Unit
3.6
V
Ambient operating temperature (device grade 6)
–40
85
Ambient operating temperature (device grade 3)
–40
125
°C
1. Only in products with process technology code Y. In products with process technology code X, Vcc(min) is
2.7 V.
Table 11.
Data retention and endurance
Parameter
Condition
Min
Max
Erase/Program
cycles
Device grade 6
100,000
Device grade 3
10,000
Data retention
at 55 °C
Table 12.
cycles per sector
CL
20
years
AC measurement conditions
Symbol
Parameter
Min
Max
Load capacitance
30
Input rise and fall times
Unit
pF
5
ns
Input pulse voltages
0.2VCC to 0.8VCC
V
Input timing reference voltages
0.3VCC to 0.7VCC
V
VCC / 2
V
Output timing reference voltages
1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 21. AC measurement I/O waveform
Input levels
0.8VCC
0.2VCC
Input and output
timing reference levels
0.7VCC
0.5VCC
0.3VCC
AI07455
36/51
Unit
M25P10-A
DC and AC parameters
Table 13.
Symbol
Capacitance
Parameter
Test condition
COUT
Output capacitance (Q)
CIN
Input capacitance (other pins)
Min
Max
Unit
VOUT = 0 V
8
pF
VIN = 0 V
6
pF
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 25 MHz.
Table 14.
Symbol
DC characteristics (device grade 6)
Parameter
Test condition (in addition to
those in Table 10)
Min
Max
Unit
ILI
Input Leakage current
±2
µA
ILO
Output Leakage current
±2
µA
ICC1
Standby current
S = VCC, VIN = VSS or VCC
50
µA
ICC2
Deep Power-down current
S = VCC, VIN = VSS or VCC
5
µA
C = 0.1VCC / 0.9.VCC at 50 MHz,
Q = open
8
mA
C = 0.1VCC / 0.9.VCC at 25 MHz,
Q = open
4
mA
ICC3
Operating current (READ)
ICC4
Operating current (PP)
S = VCC
15
mA
ICC5
Operating current (WRSR)
S = VCC
15
mA
ICC6
Operating current (SE)
S = VCC
15
mA
ICC7
Operating current (BE)
S = VCC
15
mA
VIL
Input Low voltage
–0.5
0.3VCC
V
VIH
Input High voltage
0.7VCC
VCC+0.4
V
VOL
Output Low voltage
IOL = 1.6 mA
0.4
V
VOH
Output High voltage
IOH = –100 µA
VCC–0.2
V
37/51
DC and AC parameters
Table 15.
M25P10-A
DC characteristics (device grade 3)(1)
Symbol
Test condition (in addition to
those in Table 10)
Parameter
Min(2)
Max(2)
Unit
ILI
Input Leakage current
±2
µA
ILO
Output Leakage current
±2
µA
ICC1
Standby current
S = VCC, VIN = VSS or VCC
100
µA
ICC2
Deep Power-down current
S = VCC, VIN = VSS or VCC
50
µA
C = 0.1VCC / 0.9.VCC at 25 MHz,
Q = open
8
mA
C = 0.1VCC / 0.9.VCC at 20 MHz,
Q = open
4
mA
ICC3
Operating current (READ)
ICC4
Operating current (PP)
S = VCC
15
mA
ICC5
Operating current (WRSR)
S = VCC
15
mA
ICC6
Operating current (SE)
S = VCC
15
mA
ICC7
Operating current (BE)
S = VCC
15
mA
VIL
Input Low voltage
–0.5
0.3VCC
V
VIH
Input High voltage
0.7VCC
VCC+0.4
V
VOL
Output Low voltage
IOL = 1.6 mA
0.4
V
VOH
Output High voltage
IOH = –100 μA
VCC–0.2
V
1. Only for products with process technology code X.
2. Preliminary data.
Table 16.
Instruction times (device grade 6)
Test conditions specified in Table 10 and Table 12
Symbol
tW
Alt.
Parameter
Write Status Register cycle time
Page Program cycle time (256 bytes)
tPP
(1)
Page Program cycle time (n bytes)
Min
Typ
Max
Unit
5
15
ms
0.4+
n*1/256(2)
5
ms
1.4
tSE
Sector Erase cycle time
0.65
3
s
tBE
Bulk Erase cycle time
1.7
6
s
1. When using the Page Program (PP) instruction to program consecutive bytes, optimized timings are
obtained with one sequence including all the bytes versus several sequences of only a few bytes. (1 ≤n ≤
256).
2. tPP=2μs+8μs*[int(n-1)/2+1]+4μs*[int(n-1)/2]+2μs, in products with process technology code X and Y.
38/51
M25P10-A
DC and AC parameters
Table 17.
Instruction times (device grade 3)(1)
Test conditions specified in Table 10 and Table 12
Symbol
Alt.
tW
Parameter
Write Status Register cycle time
Page Program cycle time (256 bytes)
tPP(4)
Page Program cycle time (n bytes)
tSE
Sector Erase cycle time
tBE
Bulk Erase cycle time
Min
Typ(2)(3)
Max(3)
Unit
8
15
ms
0.4+
n*1.1/256
5
ms
1
3
s
4.5
10
s
1.5
1. Only for products with process technology code X.
2. At 85 °C.
3. Preliminary data.
4. When using the Page Program (PP) instruction to program consecutive bytes, optimized timings are
obtained with one sequence including all the bytes versus several sequences of only a few bytes. (1 ≤n ≤
256).
39/51
DC and AC parameters
Table 18.
M25P10-A
AC characteristics (25 MHz operation, device grade 6 or 3)
Test conditions specified in Table 10 and Table 12
Symbol
Alt.
fC
fC
fR
Parameter
Min
Typ
Max
Unit
Clock frequency for the following
instructions: FAST_READ, PP, SE, BE, DP,
RES, WREN, WRDI, RDSR, WRSR
D.C.
25
MHz
Clock frequency for READ instructions
D.C.
20
MHz
tCH(1)
tCLH
Clock High time
18
ns
tCL(1)
tCLL
Clock Low time
18
ns
0.1
V/ns
0.1
V/ns
S Active Setup time (relative to C)
10
ns
S Not Active Hold time (relative to C)
10
ns
tCLCH(2)
tCHCL(2)
tSLCH
(3)
Clock Rise time
Clock Fall
tCSS
tCHSL
time(3)
(peak to peak)
(peak to peak)
tDVCH
tDSU
Data In Setup time
5
ns
tCHDX
tDH
Data In Hold time
5
ns
tCHSH
S Active Hold time (relative to C)
10
ns
tSHCH
S Not Active Setup time (relative to C)
10
ns
tCSH
S Deselect time
100
ns
tDIS
Output Disable time
15
ns
Clock Low to Output Valid
15
ns
tSHSL
tSHQZ
(2)
tCLQV
tV
tCLQX
tHO
Output Hold time
0
ns
tHLCH
HOLD Setup time (relative to C)
10
ns
tCHHH
HOLD Hold time (relative to C)
10
ns
tHHCH
HOLD Setup time (relative to C)
10
ns
tCHHL
HOLD Hold time (relative to C)
10
ns
tHHQX(2)
tHLQZ(2)
tWHSL(4)
tSHWL(4)
tDP(2)
tLZ
HOLD to Output Low-Z
15
ns
tHZ
HOLD to Output High-Z
20
ns
Write Protect Setup time
20
ns
Write Protect Hold time
100
ns
S High to Deep Power-down mode
tRES1(2)
S High to Standby mode without Read
Electronic Signature
tRES2(2)
S High to Standby mode with Read
Electronic Signature
3
µs
3 or 30(5)
µs
1.8 or 30(5)
µs
1. tCH + tCL must be greater than or equal to 1/ fC.
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’.
5. It is 30 µs in devices produced with the ‘X’ and ‘Y’ process technology (grade 3 devices are only produced
using the ‘X’ process technology). Details of how to find the process letter on the device marking are given
in the application note AN1995.
40/51
M25P10-A
DC and AC parameters
Table 19.
AC characteristics (40 MHz operation, device grade 6)
40 MHz available for products marked since week 20 of 2004, only(1)
Test conditions specified in Table 10 and Table 12
Symbol
Alt.
fC
fC
fR
Min
Typ
Max
Unit
Clock frequency for the following instructions:
FAST_READ, PP, SE, BE, DP, RES, WREN,
WRDI, RDSR, WRSR
D.C.
40
MHz
Clock frequency for READ instructions
D.C.
20
MHz
(2)
tCLH
Clock High time
11
ns
(2)
tCLL
Clock Low time
11
ns
0.1
V/ns
0.1
V/ns
5
ns
5
ns
tCH
tCL
Parameter
tCLCH(3)
tCHCL(3)
tSLCH
(4)
Clock Rise time
Clock Fall
time(4)
(peak to peak)
(peak to peak)
tCSS S Active Setup time (relative to C)
tCHSL
S Not Active Hold time (relative to C)
tDVCH
tDSU Data In Setup time
2
ns
tCHDX
tDH
Data In Hold time
5
ns
tCHSH
S Active Hold time (relative to C)
5
ns
tSHCH
S Not Active Setup time (relative to C)
5
ns
100
ns
tSHSL
tCSH S Deselect time
tSHQZ(3)
tDIS
tCLQV
tV
tCLQX
tHO
Output Disable time
9
ns
Clock Low to Output Valid
9
ns
Output Hold time
0
ns
tHLCH
HOLD Setup time (relative to C)
5
ns
tCHHH
HOLD Hold time (relative to C)
5
ns
tHHCH
HOLD Setup time (relative to C)
5
ns
tCHHL
HOLD Hold time (relative to C)
5
ns
tHHQX(3)
tHLQZ(3)
tWHSL(5)
tSHWL(5)
tDP(3)
tLZ
HOLD to Output Low-Z
9
ns
tHZ
HOLD to Output High-Z
9
ns
Write Protect Setup time
20
ns
Write Protect Hold time
100
ns
S High to Deep Power-down mode
tRES1(3)
S High to Standby mode without Read
Electronic Signature
tRES2(3)
S High to Standby mode with Read Electronic
Signature
3
µs
3 or 30(6)
µs
1.8 or 30(6)
µs
1. Details of how to find the date of marking are given in application note, AN1995.
2. tCH + tCL must be greater than or equal to 1/ fC.
3. Value guaranteed by characterization, not 100% tested in production.
4. Expressed as a slew-rate.
5. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’.
6. It is 30 µs in devices produced with the ‘X’ and ‘Y’ process technology codes. Details of how to find the
process letter on the device marking are given in the application note AN1995.
41/51
DC and AC parameters
Table 20.
M25P10-A
AC characteristics (50 MHz operation, device grade 6)
50 MHz available only in products with process technology code Y(1)(2)
Test conditions specified in Table 10 and Table 12
Symbol
fC
Alt.
Parameter
Min
fC
Clock frequency(1) for the following instructions:
FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI,
RDID, RDSR, WRSR
Clock frequency for READ instructions
fR
Typ
Max
Unit
D.C.
50
MHz
D.C.
25
MHz
tCH(3)
tCL(3)
tCLCH(4)
tCHCL(4)
tCLH
Clock High time
9
ns
tCLL
Clock Low time
9
ns
0.1
V/ns
0.1
V/ns
tSLCH
tCSS
S Active Setup time (relative to C)
5
ns
S Not Active Hold time (relative to C)
5
ns
Clock Rise time
(5)
(5)
Clock Fall time
tCHSL
(peak to peak)
(peak to peak)
tDVCH
tDSU
Data In Setup time
2
ns
tCHDX
tDH
Data In Hold time
5
ns
tCHSH
S Active Hold time (relative to C)
5
ns
tSHCH
S Not Active Setup time (relative to C)
5
ns
100
ns
tSHSL
tCSH
S Deselect time
tSHQZ(4)
tDIS
Output Disable time
8
ns
tCLQV
tV
Clock Low to Output Valid
8
ns
tCLQX
tHO
Output Hold time
0
ns
tHLCH
HOLD Setup time (relative to C)
5
ns
tCHHH
HOLD Hold time (relative to C)
5
ns
tHHCH
HOLD Setup time (relative to C)
5
ns
tCHHL
HOLD Hold time (relative to C)
5
ns
tHHQX(4)
tHLQZ(4)
tWHSL(6)
tSHWL(6)
tDP(4)
tLZ
HOLD to Output Low-Z
8
ns
tHZ
HOLD to Output High-Z
8
ns
Write Protect Setup time
20
ns
Write Protect Hold time
100
ns
S High to Deep Power-down mode
3
μs
tRES1(4)
S High to Standby mode without Read Electronic
Signature
30
μs
tRES2(4)
S High to Standby mode with Read Electronic
Signature
30
μs
1. Details of how to find the process on the device marking are given in application note AN1995.
2. 50 MHz operation is also available in products with process technology code X, but with a reduced supply
voltage range (2.7 to 3.6 V).
3. tCH + tCL must be greater than or equal to 1/ fC.
4. Value guaranteed by characterization, not 100% tested in production.
5. Expressed as a slew-rate.
6. Only applicable as a constraint for a WRSR instruction when SRWD is set at ‘1’.
42/51
M25P10-A
DC and AC parameters
Figure 22. Serial input timing
tSHSL
S
tCHSL
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCHDX
D
Q
MSB IN
tCLCH
LSB IN
High Impedance
AI01447C
Figure 23. Write Protect Setup and Hold timing during WRSR when SRWD=1
W
tSHWL
tWHSL
S
C
D
High Impedance
Q
AI07439
43/51
DC and AC parameters
M25P10-A
Figure 24. Hold timing
S
tHLCH
tCHHL
tHHCH
C
tCHHH
tHLQZ
tHHQX
Q
D
HOLD
AI02032
Figure 25. Output timing
S
tCH
C
tCLQV
tCLQX
tCLQV
tCL
tSHQZ
tCLQX
LSB OUT
Q
tQLQH
tQHQL
D
ADDR.
LSB IN
AI01449e
44/51
M25P10-A
11
Package mechanical
Package mechanical
In order to meet environmental requirements, Numonyx offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
Figure 26. SO8 narrow – 8-lead plastic small outline, 150 mils body width, package
outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
GAUGE PLANE
D
k
8
E1
E
1
L
A1
L1
SO-A
1. Drawing is not to scale.
2. The ‘1’ that appears in the top view of the package shows the position of pin 1.
Table 21.
SO8 narrow – 8-lead plastic small outline, 150 mils body width,
package mechanical data
millimeters
inches
Symbol
Typ
A
A1
A2
b
c
ccc
D
E
E1
e
h
k
L
L1
Min
0.10
1.25
0.28
0.17
4.90
6.00
3.90
1.27
1.04
4.80
5.80
3.80
–
0.25
0°
0.40
Max
Typ
1.75
0.25
0.48
0.23
0.10
5.00
6.20
4.00
–
0.50
8°
1.27
Min
0.004
0.049
0.011
0.007
0.193
0.236
0.154
0.050
0.189
0.228
0.150
–
0.010
0°
0.016
Max
0.069
0.010
0.019
0.009
0.004
0.197
0.244
0.157
–
0.020
8°
0.050
0.041
45/51
Package mechanical
M25P10-A
Figure 27. VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead,
package outline
D
D1
E E1
E2
e
b
D2
θ
A
A2
L
A1 A3
VFQFPN-01
1. Drawing is not to scale.
2. The circle in the top view of the package indicates the position of pin 1.
Table 22.
VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead,
package mechanical data
millimeter
inches
Symbol
Typ
A
0.85
A1
0.00
Max
Typ
1.00
0.033
0.05
A2
0.65
0.026
A3
0.20
0.008
b
0.40
D
6.00
0.236
D1
5.75
0.226
D2
3.40
E
5.00
0.197
E1
4.75
0.187
E2
4.00
e
1.27
L
0.60
θ
46/51
Min
0.35
3.20
3.80
0.48
3.60
4.20
0.016
0.134
0.157
Min
Max
0.039
0.000
0.002
0.014
0.019
0.126
0.142
0.150
0.165
0.020
0.029
0.050
0.50
0.75
12°
0.024
12°
M25P10-A
Package mechanical
Figure 28. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead,
2 x 3 mm package outline
e
D
b
L1
L3
E
E2
L
A
D2
ddd
A1
UFDFPN-01
1. Drawing is not to scale.
Table 23.
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead,
2 x 3 mm package mechanical data
millimeters
inches
Symbol
Typ
Min
Max
Typ
Min
Max
A
0.55
0.45
0.60
0.022
0.018
0.024
A1
0.02
0.00
0.05
0.001
0.000
0.002
b(1)
0.25
0.20
0.30
0.010
0.008
0.012
D
2.00
1.90
2.10
0.079
0.075
0.083
D2
1.60
1.50
1.70
0.063
0.059
0.067
(2)
0.08
ddd
0.003
E
3.00
2.90
3.10
0.118
0.114
0.122
E2
0.20
0.10
0.30
0.008
0.004
0.012
e
0.50
-
-
0.020
-
-
L
0.45
0.40
0.50
0.018
0.016
0.020
L1
L3
0.15
0.30
0.006
0.012
1. Dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.
47/51
Part numbering
12
M25P10-A
Part numbering
Table 24.
Ordering information scheme
Example:
M25P10-A
V MN 6
T
P /X
Device type
M25P
Device function
10-A = 1 Mbit (128 Kbit x 8)
Operating voltage
V = VCC = 2.3 to 3.6 V
Package
MN = SO8 (150 mil width)
MP = VFQFPN8 (MLP8)
MB = UFDFPN8 (MLP8)
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
3(1) = Device tested with high reliability certified flow(2).
Automotive temperature range (–40 to 125 °C)
Option
blank = Standard packing
T = Tape & reel packing
Plating technology
blank = Standard SnPb plating
P or G = ECOPACK® (RoHS compliant)
Process(3)
/X = T7Y
/Y = T7Y redesigned(4)
1. Device grade 3 available in an SO8 ECOPACK® (RoHS compliant) package.
2. Numonyx strongly recommends the use of the Automotive Grade devices for use in an automotive
environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801.
Please ask your nearest Numonyx Sales Office for a copy.
3. The process letter (/X) is specified in the ordering information of grade 3 devices only.
For grade 6 devices, the process letter does not appear in the ordering information, it only appears on the
device package (marking) and on the shipment box. Please contact your nearest Numonyx Sales Office.
For more information on how to identify products by the process identification letter, please refer to
AN1995: Serial Flash memory device marking.
4. Only available for grade 6 devices.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest Numonyx Sales Office.
48/51
M25P10-A
13
Revision history
Revision history
Table 25.
Document revision history
Date
Revision
25-Feb-2001
1.0
Document written.
12-Sep-2002
1.1
VFQFPN8 package (MLP8) added. Clarification of descriptions of
entering Standby Power mode from Deep Power-down mode, and of
terminating an instruction sequence or data-out sequence.
13-Dec-2002
1.2
Typical Page Program time improved. Write Protect setup and hold times
specified, for applications that switch Write Protect to exit the Hardware
Protection mode immediately before a WRSR, and to enter the Hardware
Protection mode again immediately after.
21-Feb-2003
1.3
Erroneous address ranges corrected in memory organization table.
2.0
Table of contents, warning about exposed paddle on MLP8, and Pb-free
options added.
40 MHz AC characteristics table included as well as 25 MHz. ICC3(max),
tSE(typ) and tBE(typ) values improved. Change of naming for VDFPN8
package.
3.0
Devices with Process technology Code X added (Read Identification
(RDID) and Table 20: AC characteristics (50 MHz operation, device grade
6)) added.
SO8 narrow package specifications updated.
Notes 1 and 2 removed from Table 24: Ordering information scheme.
Note 1 to Table 9: Absolute maximum ratings changed, note 2 removed
and TLEAD values removed.
Small text changes. End timing line of tSHQZ modified in Figure 25: Output
timing.
01-Apr-2005
4.0
Read Identification (RDID), Deep Power-down (DP) and Release from
Deep Power-down and Read Electronic Signature (RES) instructions,
and Active Power, Standby Power and Deep Power-down modes
paragraph clarified.
01-Aug-2005
5.0
Updated Page Program (PP) instructions in Page Programming, Page
Program (PP) and Table 16: Instruction times (device grade 6).
24-Nov-2003
08-Mar-2005
14-Apr-2006
6
Changes
All packages are ECOPACK® compliant. Grade 3 information added (see
Table 10, Table 11, Table 15, Table 17, Table 18 and Table 24).
Figure 3: Bus master and memory devices on the SPI bus modified and
Note 2 added.
Table 11: Data retention and endurance added.
40MHz frequency condition modified for ICC3 in Table 14: DC
characteristics (device grade 6).
Table 14: DC characteristics (device grade 6) shows preliminary data.
MLP package renamed as VFQFPN and specifications updated (see
silhouette on first page, Figure 27 and Table 22). Note 2 added below
Figure 26 and Note 2 added below Figure 27. VWI parameter for device
grade 3 added to Table 8: Power-up timing and VWI threshold.
/X Process added to Table 24: Ordering information scheme.
49/51
Revision history
Table 25.
Date
Document revision history (continued)
Revision
Changes
7
tRES1 and tRES2 parameter timings changed for devices produced with the
“X” process technology in Table 18 and Table 19.
SO8 narrow package specifications updated (see Figure 26 and
Table 21).
8
Changed the minimum value for supply voltage.
Added TLEAD and changed maximum value for VIO in Table 9: Absolute
maximum ratings.
Updated Section 3: SPI modes and modified Figure 3: Bus master and
memory devices on the SPI bus.
Note 1 to Table 13: Capacitance changed.
Note 2 below Table 16: Instruction times (device grade 6) added.
Changed test condition for ICC3 in Table 14 and fR in Table 20.
23-Aug-2007
9
Removed “low voltage” from the title. Small text changes.
Typical values for Sector Erase and Bulk Erase modified.
UFDFPN8 package (MLP8) added.
Added the reference to a new process technology (code “Y”).
Added notes below Table 10: Operating conditions, Table 15: DC
characteristics (device grade 3), and Table 17: Instruction times (device
grade 3).
/Y process added to Table 24: Ordering information scheme.
18-Oct-2007
10
Code of the UFDFPN8 package modified.
Small text changes.
10-Dec-2007
11
Applied Numonyx branding.
05-Jun-2006
06-Jul-2007
50/51
M25P10-A
M25P10-A
Please Read Carefully:
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NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
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applications.
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Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
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these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
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visiting Numonyx's website at http://www.numonyx.com.
Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.
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Copyright © 11/5/7, Numonyx, B.V., All Rights Reserved.
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